Flip-flops, shift registers, and active-matrix display devices

Flip-flop, shift register, and active matrix display device

The present invention generally relates to flip-flops, shift registers including multi-stage flip-flops, and/or active matrix display devices using shift registers in scan signal line drive circuits or data signal line drive circuits .

The scanning line driving circuit and the data signal line driving circuit of the active matrix display device are used to drive the pixel rows and columns arranged in a matrix. The scanning line drive circuit and the data signal line drive circuit use shift registers to drive the gate line and the source line in a predetermined sequence. Multi-stage flip-flops connected to each other realize the shift register.

The structure of the conventional flip-flop constituting the shift register will be explained below. The following flip-flop system settings-reset flip-flop (hereinafter referred to as "RS flip-flop"), as shown in Figure 17, it has a control terminal GB, an input terminal CK, a reset terminal RB, and an output terminal OUT .

Figure 18 illustrates the structure of the RS flip-flop. The RS flip-flop shown in FIG. 18 includes an inverter circuit 101, in which the p-type transistor Mp1 and the n-type transistor Mn1 (hereafter Mp and Mn respectively represent p-type and n-type transistors) will be connected to the power supply Vdd (High potential) and Vss (low potential) in series. The control terminal GB is connected to the input side of the inverter circuit 101, that is, to the gates of Mp1 and Mn1.

A CMOS analog switch ASW and Mp3 are connected in series between the power supply VDD and the input terminal CK, wherein the CMOS analog switch ASW includes Mn2 and Mp2 connected in parallel with each other. In the analog switch ASW, the gate of Mn2 is connected to the output of the inverter circuit 101 (the junction between the source of Mp1 and the drain of Mn1), and the gate of Mp2 is connected to the control terminal GB. The gate of Mp3 is connected to the reset terminal RB.

Supplying VDD to the gate of Mn2 in the analog switch ASW will connect the source and drain of Mn2, and when VSS is powered, the source and drain of Mn2 will be disconnected. On the other hand, the gate of Mp2 that supplies VSS will be connected to the source and drain of Mp2, and when the gate of Mp2 is connected to VDD, the source and drain of Mp2 will be disconnected. Through these operations of Mn2 and Mp2, the analog switch ASW can control the supply of the input signal CK.

Between the power supply VDD and VSS, the RS flip-flop includes an inverter circuit 102 and an inverter circuit 103. The inverter circuit 102 includes Mp4 and Mn4, and the inverter circuit 103 includes Mp5 and Mn5. The inverter circuit 102 and the inverter circuit 103 connect their inputs and outputs to each other (the input of the inverter circuit 102 is connected to the output of the inverter circuit 103, and the output of the inverter 102 is connected to the inverter 103 input) together to form a lock circuit. Between Mn4 of the inverter circuit 102 and the power supply VSS is Mn6, the gate of which is connected to the reset terminal RB.

The junction between Mp3 and the analog switch ASW is connected to the output of the inverter circuit 102 (the junction between the source of Mp4 and the drain of Mn4). (The junction of Mp3 and the analog switch ASW and the output of the inverter circuit 102 have the potential of node A) The output 103 of the inverter circuit (the junction between the source of Mp5 and the drain of Mn5) is connected to the output terminal OUT .

In the RS flip-flop, the inverter circuit 101, Mp3, and the analog switch ASW implement the gate area. The inverter circuit 102, the inverter circuit 103, and Mn6 implement a queuing area. The gate area is a functional area. According to the control signal supplied separately from the input signal, the externally supplied input signal is sent to the subsequent lock area. The lock area is a functional area for input signals supplied by the lock gate area.

The operation of the RS flip-flop shown in FIG. 18 will be explained with reference to the figure below.

The timing diagram of FIG. 19 assumes that the control signal GB, the clock signal CK, and the reset signal RB are respectively input to the control terminal GB, the input terminal CK, and the reset terminal RB of the RS flip-flop.

First, when the control signal GB drops to the low level (VSS) at time t1, the output of the inverter circuit 101 will become VDD, and VDD will be supplied to the gate of Mn2 in the analog switch ASW. Here, here, the gate of Mp2 in the analog switch ASW will receive VSS (control signal GB).

As a result, the analog switch ASW is closed, and the input signal is supplied to the node A. Here, the reset signal RB is at a high level (VDD) and Mp3 is off. Therefore, the node A has the potential of the input signal CK.

The high level (VDD) reset signal RB is also supplied to the gate of Mn6. As Mn6 is turned on, Mn4 and Mp4 can operate as the inverter circuit 102. The potential of the node A is the input of the inverter circuit 103. Therefore, in this state, the output 103 of the inverter circuit 103-the output signal OUT of the RS flip-flop-is at the low level (VSS). When the potential at the junction between the input of the inverter circuit 102 and the output of the output circuit 103 is regarded as the potential of the node B, the potential of the node B will also be at a low level. Here, the potential of the output signal OUT is locked by the inverter circuit 102 and the inverter circuit 103.

When the clock signal CK becomes the low level (VSS) at time t2, the potential of the node A becomes (VSS) the low level. The potential of node B and the output signal OUT become high level (VDD).

When the control signal GB becomes the high level (VDD) at time t3, the analog switch ASW1 is turned off, and the supply of the clock signal CK to the node A is stopped. Here, since the reset signal RB maintains a high level (VDD), Mn6 is turned on and the inverter circuits 102 and 103 operate as a lock circuit. Therefore, the potential of the node A remains at the low level (VSS), and the potential of the node B and the output signal (OUT) remain at the high level (VDD).

When the reset signal RB becomes low level (VSS) at time t4, Mp3 will be turned on and Mn6 will be turned off. Therefore, Mn4 and Mp4 will not operate as the inverter circuit 102 to cancel the locked state. As Mp3 is turned on, the potential of node A becomes a high level, which is supplied to the individual electrodes of Mn5 and Mp5 constituting the inverter circuit 103. As a result, the potential of the node B and the output signal OUT become low level (VSS).

After time t5, the control signal GB is at a high level (VDD) and the signal CK will not be applied to the node A. In addition, since the reset signal RB is at a high level, Mp3 will be turned off and Mn6 will be turned on. This will operate the inverter circuit 102 and cause it to lock the node B potential and output the signal with the lock circuit 103. The potential of node B and the output signal OUT will be maintained at a low level (VSS).

In the following, referring to FIG. 20, another exemplary structure of the RS flip-flop is described.

The RS flip-flop shown in FIG. 20 will be configured to receive the control signal GB, the clock signal CK, the inverted clock signal CKB, and the reset signal RB, where the clock signal CK and the inverted clock The signal CKB has an amplitude smaller than that generated by VDD, which is the power supply of the flip-flop.

Like the RS flip-flop of FIG. 18, the RS flip-flop shown in FIG. 20 includes a gate area and a lock area. The lock area is the same as the lock area in the RS flip-flop of FIG. 18. Only the gate area is different.

In the gate area of the RS flip-flop shown in FIG. 20, Mp11 and Mn11 are connected in series between the power source VDD and the input terminal CKB, and Mp12 and Mn12 are connected in series between the power source VDD and the input terminal CK. Mn13 is arranged between the power source VSS and the junction of the source and drain of Mp11.

The individual gates of Mp11 and Mn13 are connected to the control terminal GB. The individual gates of Mn11 and Mn12 are connected to the junction between the source of Mp11 and the drain of Mn11. The drain of Mp12 is connected to the reset terminal RB. The junction between the source of Mp12 and the drain of Mn12 is connected to node A. The junction between the source of Mp11 and the drain of Mn11 is node C.

In the RS flip-flop of the structure shown in FIG. 20, for example, it is assumed that both the clock signal and the inverted clock signal CKB have an amplitude of 3.3V, and the VDD and VSS of the circuit are 8V and 0V, respectively. For example, when the GB terminal is low level and the critical value of the n-type transistor in the circuit is 3.5V, supplying low level signal CKB (VSS=0V) and 3.3V signal CK will turn on Mp11 and cause Mn11 to be similar to two Operate in polar body mode. In this way, the node C maintains a potential close to 3.5V, which is close to the critical value of Mn11.

Here, the clock signal CK will be supplied to the source of Mn12, and the gate of Mn12 will be supplied to node C. Therefore, the gate-source potential of Mn12 is approximately 0.2V. Here, when Mn12 has a critical value of about 3.5V like Mn11, it will be turned off.

On the other hand, when the inverted clock signal CKB and the clock signal CK are respectively 3.3V and 0V, and the 3.5V threshold of Mn11 plus the 3.3V value, the node C has a potential of about 6.8V. Here, since the clock signal CK is 0V, even when the critical value of Mn12 is 3.5V, the source-gate voltage of Mn12 is still about 6.8V. Therefore, Mn12 will be turned on, and node A will be 0V.

In the following, referring to FIG. 21, the RS flip-flop shown in FIG. 20 will be described.

The timing diagram shown in Figure 21 assumes that the control signal GB, the clock signal CK, the inverted clock signal CKB, and the reset signal RB are respectively input to the control terminal GB, input terminal CK, and input terminal of the RS flip-flop CKB, and reset terminal RB.

At time t1, the control signal GB becomes low level (VSS), Mp11 will be turned on and Mn13 will be turned off. Here, since the critical values of the inverted clock signal CKB, clock signal CK, and Mn11 are 0V, 3.3V, and 3.5V, respectively, the gate potential of Mn12 (node C potential) is about 3.5V, And the source potential of Mn12 is 3.3V. In this way, Mn12 will shut down. Here, since the reset signal RB is at a high level (VDD=8V), Mp12 is turned off and Mn6 is turned on, causing Mp4 and Mn4 to operate as the inverter circuit 102. The inverter circuit 102 and the inverter circuit 103 including Mp5 and Mn5 form a lock circuit together. Therefore, the node A is maintained at a low level.

At time t2, when the inverted clock signal CKB and the clock signal CK become 3.3V and 0V, respectively, 3.3V plus the 3.5V threshold of Mn11, node C will become approximately 6.8V. The potential of node C is applied to the gate of Mn12. Here. Since the source of Mn12 is 0V, Mn12 will be turned on and node A will become a low level. Here, the reset signal RB is still at a high level (VDD=8V), therefore, Mp12 is turned off and Mn6 is turned on, causing Mp4 and Mn4 to operate as the inverter circuit 102. When the node A becomes a low level, the lock circuit implemented by the inverter circuits 102 and 103 changes its state and the output signal OUT becomes a high level (VDD=8V).

At time t3, the control signal GB becomes high level (VDD=8V), Mp11 is turned off, and Mn13 is turned on. As a result, the individual gates of Mn11 and Mn12 become low level (VSS=0V), cutting off the clock signal CK and the inverted clock signal CKB. In this way, when the control signal is at a high level (VDD=8V), regardless of the state of these clock signals, the flip-flop will not be affected by the clock signal CK or the inverted clock signal CKB. Here, since Mn12 is turned off, the clockless signal CK is supplied to node A. The node A is maintained at a low level by the latch circuit implemented by the inverter circuits 102 and 103, and the output OUT is maintained at a high level (VDD=8V).

After time t4, the reset signal RB becomes a low level (VSS=0V) and Mp12 will be turned on. At the same time, the reset signal RB will also be supplied to the gate of Mn6 to turn on Mn6. Therefore, Mn4 and Mp4 will not operate as the inverter circuit 102. As a result, the node A becomes a high level (VDD=8V), and when the output signal OUT passes through the inverter circuit 103, it becomes a low level.

At time t5, the reset signal RB becomes a high level, Mp12 is turned off, and Mn6 is turned on. This will cause the circuit including Mn4 and Mp4 to operate as the inverter circuit 102 again, causing the inverter circuit 102 and the inverter circuit 103 to operate as a latch circuit again. As a result, the node A will be maintained at a high level, and therefore, the output signal OUT will be maintained at a low level.

Fig. 22 shows an exemplary structure using the RS flip-flop shift register as described above. The shift register shown in FIG. 22 uses the RS flip-flop shown in FIG. 18.

The shift register includes a plurality of RS flip-flops FF1, FF2,... in series, of which the input terminal CK of the RS flip-flop FFa (a=2n-1, n=1, 2,...) The clock signal CK will be received, and the input CK of the RS flip-flop FFa (a=2n, n=1, 2,...) will receive the inverted clock signal CKB.

The GB terminal of the first stage RS flip-flop FF1 receives the start pulse signal SPB, and the output OUT from each stage RS flip-flop FFa becomes the output of the shift register (Q1, Q2, Q3,...) . In addition, the output Q1 (GB2, GB3,...) from each stage of RS flip-flops FF1, FF2,... will be supplied to the GB terminal of the next stage of RS flip-flops FF through an inverter.

In the RS flip-flops FF2, FF3,... of the second and subsequent stages, the inverted signal of the output (Q2, Q3,...) will be supplied to the GB terminal of the next stage, and also to the previous stage. The RB end of the RS flip-flop is output as a reset signal in the previous stage. For example, the signal GB3 is the inverted signal of the output Q2 of the second-stage RS flip-flop FF2, which will be supplied to the GB terminal of the third-stage RS flip-flop FF3 and supplied to the first-stage RS flip-flop FF1 RB end.

The following will explain the operation of the shift register with reference to the timing chart of FIG. 23.

At time t1, the start pulse signal SPB will be supplied to the GB terminal of FF1. When the clock signal becomes a low level at time t2, the OUT signal of FF1, that is, the signal Q1 will become a high level. The signal Q1 is supplied to the GB terminal of FF2 as the signal GB2 via an inverter. That is, the GB end of FF2 will receive the low-level signal.

As the low-level GB2 signal is supplied to the GB terminal of FF2, changing the inverted clock signal CKB to a low-level at time t3 will cause the OUT signal of FF2, that is, the signal Q2, to become a high-level. The signal GB3 is an inverted signal of the signal Q2, which becomes a low level. The signal GB3 will be supplied to the GB side of FF3. The signal GB3 will also be supplied to the RB terminal of FF1, reset FF1 and switch Q1 to a low level.

In this way, the cascaded setting-reset flip-flop will act as a shift register synchronized with the signal CK and signal CKB. Even if the signal CK and the signal CKB have an amplitude smaller than the power supply voltage VDD of the circuit, the shift register can still operate.

At the same time, Japanese Patent Publication No. 356728/2001 (published on December 26, 2001; US Patent No. 6,377,104B2) discloses a static clock generator including a multi-stage D-type flip-flop and a gate area.

The shift register disclosed in this announcement can be used in scanning line drive circuits or data signal line drive circuits of active matrix devices. In the scan line drive circuit, the shift register will continuously generate scan signals for individual scan lines at a predetermined timing. In the data signal line driving circuit, the shift register generates a sampling signal in a predetermined timing to transmit the data signal to the individual source line. The data signal is supplied via the data supply line.

The timing diagrams of Figures 19, 21, and 23 do not consider signal delay. In this way, in each stage of the flip-flop, the rise of the output signal OUT (or output Q) and the fall of the control signal CK occur substantially at the same time, and the fall of the output signal OUT (or output Q) and the fall of the reset signal RB Substantially happen at the same time. However, in a real flip-flop, when the output signal OUT rises or falls in response to the fall of the control signal CK or the reset signal RB, there is a delay.

For example, when the conventional shift register is used in the data signal line driving circuit, the signal delay in the output of the shift register will cause the following problems. In the data signal line drive circuit, the sampling signal generated by the shift register needs to be timed by the data signal fed by the data feeder. However, when the delay in the sampling signal causes the timing of the sampling signal and the data signal fed through the data feeder to shift, the required data will not be properly transmitted to the source line.

Since the scanning signal generated by the shift register needs to be timed by the data signal supplied to the source line, when the conventional shift register is used in the scanning line drive circuit, the problem of signal delay will also occur.

The signal in the shift register is expected to be delayed, and the above problems can be solved by adjusting the individual timings of different input signals. However, the problem with this method is that it requires a timing adjustment mechanism, which increases the circuit size. In addition, in order to provide sufficient latitude to adjust the timing of the input signal, the frequency of the main clock needs to be increased. This will increase the power consumption of the circuit.

By improving the rise and fall characteristics of the shift register, the signal delay can be reduced. However, this is related to the following problems.

For example, consider the output signal Q2 as follows. In order to reduce the time delay of the output signal Q2 falling, the reset signal (signal GB4) needs to be supplied to the reset terminal of FF2 without delay. In addition, the drop characteristics of FF2 itself need to be improved.

For example, when outputting the FF3 (which may have the structure shown in Figure 18 or 20) used to generate the output signal Q3 of the signal GB4, by improving the ability of Mp5, the output speed of the output signal Q3 can be improved (output The rising characteristic of signal Q3). This can be achieved by designing Mn5 such that its W size (channel width) is smaller than the width of Mp5. This will make it easier for current to flow through Mp5 and reduce the rise time of output Q.

At the same time, the output signal of FF2 will be inverted into signal GB3 and become the reset signal for FF1 of the previous stage. Again, in order to reduce the time delay in the fall of the output signal Q1, for the above reasons, it is necessary to improve the rise characteristic of the output signal Q2 in the FF2. (This is achieved by designing Mp5 so that its W size (channel width) is smaller than that of Mn5, thus improving the current flow energy of Mn5.) However, in order to also reduce the time delay in the output signal Q2 drop In other words, improving the rising characteristics of the output signal Q2 is better than improving the falling characteristics of the FF2 itself.

That is, the shift register using the traditional flip-flop has the following self-limiting problem: the output stage's falling characteristics will increase the output signal OUT due to the improvement of the reset ability of the previous stage. Characteristic, and sacrificed, the output stage will generate a signal that will drop in response to the reset signal supplied by the next stage.

The purpose of the embodiments of the present invention is to provide a flip-flop whose rise and fall characteristics can be improved at the same time. With the flip-flop, the embodiment of the present invention can reduce the signal delay in the shift register including a plurality of such flip-flops connected to each other, and reduce the use of the shift register in its scanning signal line drive circuit Or the signal delay in the active matrix display device in the data signal line drive circuit.

In order to achieve the purpose, the flip-flop of the embodiment of the present invention includes: a gate area, which transmits an externally supplied input signal to the next level of the lock area according to the control signal supplied separately from the input signal; and the lock area, which includes the lock The lock circuit is used for the input signal supplied by the lock gate area. The lock area further includes the lock cancel area and the output control area. The lock cancel area is reset by the external supply to the lock area The signal cancels the lock state of the lock circuit, and the output control area is used to output high or low potential as the power supply for operating the flip-flop.

According to this configuration, the output signal of the flip-flop will change to a high level (or low level) depending on the change of the locked signal (input signal supplied from the gate area) in the lock circuit. The low level is used as the power supply for operating the flip-flop and provides a low level (or high level) output signal.

For example, the output signal of the flip-flop will drop when the input signal locked by the lock circuit rises. When the lock state of the lock circuit is cancelled by the reset signal, the high potential supplied as the operating power supply of the flip-flop will be output as the output signal of the output control area.

In this case, by designing the lock circuit to prefer the drop feature, the drop time of the output signal can be reduced. On the other hand, by improving the drive capability of the output control area, the rise time of the output signal can be reduced.

That is, in the flip-flop configured as above, the drop and rise characteristics of the output signal will depend on the lock circuit and the output control area respectively, allowing completely independent adjustments. As a result, a flip-flop that can improve its rising and falling characteristics at the same time is obtained.

By connecting the flip-flops in multiple stages, the shift register according to the embodiment of the present invention is provided.

According to this configuration, the flip-flops used in the shift register can improve their rise and fall characteristics, thereby reducing the signal delay in the shift register.

The active matrix display device according to the embodiment of the invention includes a scanning signal line driving circuit and a data signal line driving circuit, at least one of which uses the shift register of the embodiment of the invention.

According to this configuration, the use of the shift register in the data signal line driving circuit reduces the delay in the sampling signal generated by the shift register. Therefore, there is no offset in the timing of the sampled signal and the data signal fed through the data feeder. Since there is no timing offset, the required data can be stably applied to the source line. On the other hand, using a shift register in the scanning signal line drive circuit makes it easier to time the scan signal generated by the shift register with the data line supplied to the source line, thereby achieving stable operation.

In order to fully understand the essence and advantages of the present invention, reference should be made to the following detailed description with accompanying drawings.

Hereinafter, embodiments of the present invention will be illustrated with reference to the drawings. FIG. 2 shows an exemplary structure of an image display device according to an embodiment of the present invention. The image display device shown in FIG. 2 includes a display area 12, a scanning signal line driving circuit 13, a data signal line driving circuit 14, and a control circuit 15.

The display area 12 includes n scan signal lines GL (GL1, GL2,..., GLn) parallel to each other, n data signal lines SL (SL1, SL2,..., SLn) parallel to each other, and a matrix Configured pixels ("PIX" in Figure 2). Each pixel 16 is formed in an area surrounded by two adjacent scan signal lines GL and two adjacent data signal lines SL. It is worth noting that, for the convenience of description, the number n of the scan signal line GL and the data signal line SL is the same. However, the scan signal line GL and the data signal line SL can also be provided with different numbers.

The scanning signal line driving circuit 13 includes a shift register 17. The shift register 17 generates scan signal lines to be supplied to the scan signal lines GL1 and GL2 connected to the individual pixel rows 16. Among them, according to the two clock signals GCK1 and GCK2 supplied from the control circuit 15 and the start The initial pulse signal GSP generates scan signals sequentially. The circuit structure of the shift register 17 will be explained later.

The data signal line driving circuit 14 includes a shift register 1 and a sampling area 18. The shift register 1 receives from the control circuit 15 two kinds of clock signals SCK and SCKB that are out of phase with each other, and a start pulse signal SSP. The sampling area 18 receives the video signal DAT from the control circuit 15. In the data signal line drive circuit 14, the sampling area 18 will sample the video signal DAT according to the output signals S1 to Sn supplied by the shift register 1 of the individual stage, and the resulting video data will be supplied to the individual lines connected to the output signals S1 to Sn. The data signal lines SL1, SL2, ... of the pixel 16.

The control circuit 15 generates different control signals to control the operations of the scanning signal line driving circuit 13 and the data signal line driving circuit 14. The clock signals GCK1, GCK2, SCK, SCKB, start signals GSP, SSP, and video signals are some of the control signals generated by the control circuit 15.

In the image display device 11, it is worth noting that the scanning signal line driving circuit 13, the data signal line driving circuit 14, and the pixels 16 in the display area 12 all include switching elements.

In the case where the image display device 11 is an active matrix liquid crystal display device, as shown in FIG. 3, each pixel 16 includes a pixel transistor SW implemented by a field-effect transistor and includes a liquid crystal capacitor C_L(And optional ground including auxiliary capacitor C_S). Here, the pixel 16 is configured such that the data signal line SL is connected to an electrode of the pixel capacitor Cp via the drain and source of the pixel transistor SW, and the gate of the pixel transistor SW is connected to the scan signal line GL. The other electrodes of the pixel capacitor Cp are connected to a common electrode line (not shown) common to all pixels.

Here, it is assumed that the pixel 16, PIX(i,j), is connected to the data signal SLi and the scan signal line GLj, where i and j are independent arbitrary integers satisfying 1i, jn, when the scan signal When the line GLj is selected, the pixel transistor SW is turned on, and a voltage is applied to the pixel capacitor Cp according to the video data applied to the data signal line SLj. Liquid crystal capacitor C applied to pixel capacitor Cp_LThe voltage will modulate the transmission or reflection of the liquid crystal. In this way, by selecting the scanning signal line GLj and applying the signal voltage to the data signal line SLi according to the video data, the display state of PIX(i,j) can be changed according to the video data.

In the image display device 11, the scan signal line drive circuit 13 selects the scan signal line GL, and the data signal line drive circuit 14 outputs the video data to the pixels selected by the scan signal line GL through the data signal line SL 16. As a result, the video data will be written in the pixel 16 connected to the selected scan signal line GL. In addition, the scanning signal line driving circuit 13 sequentially selects the scanning signal line GL, and the data signal line driving circuit 14 outputs the video data to the data signal line SL. As a result, the video data is written in all the pixels 16 in the display area 12, so that the display area 12 displays images according to the video signal DAT.

The video data for the pixels 16 will be sent from the control circuit 15 to the data signal line driving circuit 14 in the form of a video signal DAT in a time sequence. The data signal line driving circuit 14 extracts the video data from the video signal DAT according to the timing of the clock signal SCK, the clock signal SCKB, and the start pulse SSP. The clock signal SCK has a predetermined period with a duty ratio of not more than 50% (in some embodiments, a low period shorter than the High period). The phase difference between the clock signal SCKB and the clock signal SCK is 180°.

Specifically, in response to the start pulse SSP, the shift register 1 of the data signal line driving circuit 14 synchronizes with the clock signals SCK and SCKB by shifting the pulses of the half-clock period to synchronize them with the clock signals SCK and SCKB. Output, thereby generating output signals S1 to Sn that are offset from each other by one clock. The sampling area 18 of the data signal line driving circuit 14 will take out the video data from the video signal DAT at the timing of the output signals S1 to Sn.

On the other hand, in response to the start pulse GSP, the shift register 17 of the scan signal line drive circuit 13 will synchronize with the clock signals GCK1 and GCK2 by shifting the pulse with a half-clock period, and sequentially A half-clock period pulse is output, thereby outputting scan signals that are offset by one clock from each other to the individual scan signal lines GL1 to GLn.

The shift register 1 of the data signal line drive circuit 14 and the shift register 17 of the scan signal line drive circuit 13 may have an overall structure similar to that shown in FIG. 22. However, as described in the embodiment of the present invention, the shift register 1 or 17 adopts an RS flip-flop structure which is different from the conventional structure. In the following first to fifth embodiments, specific embodiments of the flip-flop according to the present invention will be described.

[First Embodiment]

With reference to FIG. 1, an exemplary structure of the RS flip-flop according to the first embodiment will be described below.

The RS flip-flop shown in FIG. 1 has two main parts, a gate area 21 and a lock area 22.

The gate region 21 includes an inverter circuit 23, which is implemented by a p-type transistor Mp1 and an n-type transistor Mn1 connected in series between the power supply VDD (high potential) and VSS (low potential) (hereafter, The p-type transistor and n-type transistor will be denoted by Mp and Mn respectively). The control terminal GB is connected to the input side of the inverter circuit 23, that is, to the gates of Mp1 and Mn1.

Connected between the input terminal CK and the node A is a CMOS analog switch ASW1 that connects Mn2 and Mp2 in parallel. The gate of Mn2 is connected to the output of the inverter circuit 23 (that is, it connects the source of Mp1 and the drain of Mn1. Junction), and the gate of Mp2 is connected to the control terminal GB.

When VSS is supplied, when the source and drain of Mn2 are disconnected, the gate of Mn2 in ASW1 supplied with VDD will be connected to the source and drain of Mn2. On the other hand, when VDD is supplied, when the source and drain of Mp2 are disconnected, the gate that supplies VSS to Mp2 will be connected to the source and drain of Mp2. Through these operations of Mn2 and Mp2, the analog switch ASW1 controls the supply of the input signal CK. The node A is the output of the gate 21.

The lock area 22 includes an inverter circuit 24 and an inverter circuit 25, each of which is disposed between the power supply VDD and VSS. The inverter 24 includes Mp3 and Mn3, and the inverter 25 includes Mp4 and Mn4. The input of the inverter circuit 24 is connected to the output of the inverter circuit 25. The output of the gate 21, that is, the node A, is connected to the input of the inverter circuit 24. The output of the inverter circuit 24 is node B, and the output of the inverter circuit 25 is node C.

Between the output of the inverter circuit 24 and the output terminal OUT of the RS flip-flop, a CMOS analog switch ASW2 (lock connection area) of Mn5 and Mp5 in parallel is connected. In the analog switch ASW2, the gate of Mn5 is connected to the control terminal R via the inverter 26, and the gate of Mp5 is connected to the control terminal R.

The junction between the analog switch ASW2 and the output terminal OUT is connected to the input of the inverter circuit 25. In this way, when the analog switch ASW2 is turned on, the output of the inverter circuit 24 and the input of the inverter circuit 25 are connected to each other. That is, the inverter circuit 24 and the inverter circuit 25 implement a lock circuit together by connecting their inputs and outputs to each other.

Between the power supply VSS and the output terminal OUT is Mn6 (output control area), the gate of which is connected to the control terminal R.

Referring to FIG. 4, the operation of the RS flip-flop shown in FIG. 1 will be described below.

The timing diagram of FIG. 4 assumes that the control signal GB, the clock signal CK, and the reset signal R are respectively input to the control terminal GB, the input terminal CK, and the reset terminal R of the RS flip-flop.

First, when the control signal GB drops to the low level (VSS) at time t1, the output of the inverter circuit 23 will become VDD, and VDD will be supplied to the gate of Mn2 in the analog switch ASW1. Here, the gate of Mp2 in the analog switch ASW1 will receive VSS (control signal GB). As a result, the analog switch ASW1 will be closed, and the clock signal CK will be supplied to the node A.

When the clock signal CK becomes the low level at time t2, the potential of the node A becomes the low level. The low level is input to the gate of the inverter circuit 24 including Mn3 and Mp3, and the node B-the output of the inverter circuit 24-is brought to the high level. Here, since the reset signal R will maintain a low level, the low level will be applied to the gate of Mp5 in the analog switch ASW2 including Mp5 and Mn5. Mn5 receives the inverted high-level reset signal R generated by the inverter circuit 26. In this state, the analog switch ASW2 will be closed, and the signal from node B will become the output OUT of the RS flip-flop through the analog switch ASW2.

The signal to calculate the node B is also applied to the individual gates of Mn4 and Mp4 in the inverter circuit 25, bringing the node C-the output of the inverter circuit 25-to a low level. As a result, the inverter circuit 24 and the inverter circuit 25 together serve as a latch circuit.

When the control signal GB becomes the high level at time t3, the analog switch ASW1 will be turned off, and the supply of the clock signal CK to the node A will be stopped. Here, since the reset signal R maintains a low level, the analog switch ASW2 remains closed and the output OUT is maintained at a high level by the latch circuit implemented by the inverter circuits 24 and 25.

When the reset signal R becomes high at time t4, the analog switch ASW2 will be turned off and Mn6 will be turned on. As a result, the output terminal OUT is disconnected from the node B and connected to the power supply VSS via Mn6. As a result, the output OUT becomes a low level. In addition, by turning off the analog switch ASW2, the output of the inverter circuit 24 is disconnected from the input of the inverter circuit 25, and the locked state of the inverter circuits 24 and 25 is cancelled. Here, the input of the inverter circuit 25 is at a low level and the node C is at a high level. Therefore, node B-the output of the inverter circuit 24-becomes a low level.

After time t5, the reset signal R is at a low level. Here, Mn6 will be turned on, and the output terminal OUT will be disconnected from the power supply VSS. However, since the analog switch ASW2 is closed, the inverter circuits 24 and 25 will again be in the locked state, and the output OUT will be maintained at a low level.

The following is to consider the rising characteristics of the output OUT in the RS flip-flop with the structure described in this embodiment. The low-level control signal GB is supplied to the RS flip-flop, and when the clock signal CK drops, the node A becomes the low-level. Here, by providing Mp3 with a larger channel width than Mn3, the rise time of the output OUT can be reduced. This will improve the driving ability of Mp3 to be greater than that of Mn3, thereby improving the ascent characteristics.

Figure 24 shows the input and output characteristics of the Pch transistor (Mp) and Nch transistor (Mn) of the inverter (current flow). Figure 25 shows the transient characteristics (output waveforms) of these transistors. In Figures 24 and 25, the following parameters are used.

(1) Mp has a higher ability than Mn (P>N) (2) Mp has the same ability as Mn (P=N) (3) Mn has a higher ability than Mp (P<N) Figure 26 and 27 represents the graphs of the rising waveform and the falling waveform of the output waveform of the inverter shown in FIG. 25, respectively. The following information can be obtained from these graphics.

For (P>N), good ascending characteristics are obtained but the descending characteristics are not good.

For (P=N), the rising characteristic and the falling characteristic are substantially the same (a typical inverter).

For (P<N), good descending characteristics are achieved but the ascending characteristics are not good.

It can be seen that it is difficult to improve the rise and fall characteristics of the same inverter. As such, in the RS flip-flop according to the embodiment of the present invention, the inverter implemented by Mn3 and Mp3 has an improved rising characteristic. Utilizing the fact that the channel width of Mp3 only affects the rising characteristics of the output OUT, this is achieved by providing Mp3 with a larger channel width than Mn3, thereby improving the driving capability of Mp3 more than Mn3.

On the other hand, with regard to the drop characteristics of the output OUT, the drop time can be reduced by improving the drive capability of Mn6 that brings the output OUT to a low level in response to the reset signal. This can be achieved by increasing the channel width of Mn6.

When the reset signal R rises, Mn6 will turn on. Here, since the output OUT is completely disconnected from circuits other than Mn6 due to the operation of the analog switch ASW2, from an electrical point of view, the output OUT is only affected by Mn6. That is, the droop characteristic depends only on the driving ability of Mn6.

With the described structure, the RS flip-flop can independently adjust the falling and rising characteristics of the output OUT. When used in a shift register, compared to the traditional structure, the delay time of the output signal Q can be greatly reduced.

[Second Embodiment]

Referring to FIG. 5, an example structure of an RS flip-flop according to other embodiments of the present invention will be described below.

The RS flip-flop shown in FIG. 5 includes two main parts, a gate area 21 and a lock area 27. Regarding the structure and operation of the gate region 21, since they are basically the same as the RS flip-flop of the first embodiment described with reference to FIG. 1, they are not described again.

The lock area 27 is similar to the lock area 22, but includes an analog switch ASW3 instead of the analog switch ASW2. It is worth noting that the components of the lock area 27 having a structure similar to the lock area 22 will be given the same code and the description thereof will be omitted.

The analog switch ASW3 is connected between the output of the inverter circuit 24 and the output terminal OUT of the RS flip-flop, and it acts as a CMOS analog switch connecting Mn7 and Mp7 in parallel. In the analog switch ASW3, the gate of Mn7 is connected to the power supply VDD, and the gate of Mp7 is connected to the reset terminal R.

Referring to FIG. 6, the operation of the RS flip-flop shown in FIG. 5 will be described below.

The timing diagram of FIG. 6 assumes that the control signal GB, the clock signal CK, and the reset signal R are respectively input to the control terminal GB, the input terminal CK, and the reset terminal R of the RS flip-flop.

First, the control signal GB drops to the low level (VSS) at time t1, the output of the inverter circuit 23 becomes VDD, and VDD is supplied to the gate of Mn2 in the analog switch ASW1. Here, the gate of Mp2 in the analog switch ASW1 will receive VSS (control signal GB). As a result, the analog switch ASW1 is closed, and the clock signal CK is supplied to the node A.

When the clock signal CK becomes the low level at time t2, the potential of the node A becomes the low level. The low level will be input to the gate of the inverter circuit 24 including Mn3 and Mp3, and the node B-the output of the inverter circuit 24-will be voltage high. Here, since the reset signal R maintains a low level, in the analog switch ASW3, the low level will be applied to the gate of Mp7 and the high level (power supply VDD) will be input to Mn7. In this case, the analog switch ASW3 will be closed, and the signal from the node B through the analog switch ASW3 will become the output OUT of the RS flip-flop.

The signal from the node B is also applied to the individual gates of the Mn4 and Mp4 of the inverter circuit 25, bringing the node C-the output of the inverter circuit 25-to a low level. As a result, the inverter circuit 24 and the inverter circuit 25 together serve as a latch circuit.

When the control signal GB becomes high level at time t3, the analog switch ASW1 will be turned off, and the clock signal CK will be stopped to be supplied to the node A. Here, since the reset signal R maintains a low level, the analog switch ASW3 remains closed and the output OUT is maintained at a high level by the latch circuit implemented by the inverter circuits 24 and 25.

The operation from time t1 to t3 is the same as the operation of the RS flip-flop described with reference to FIG. 1.

When the reset signal R becomes high at time t4', Mp7 in the analog switch ASW will be turned off. Here, since the gate and source of Mn7 receive the high level immediately after the reset signal R becomes the high level, Mn7 will also be turned off. Therefore, the analog switch ASW3 will be disconnected and the output terminal OUT and node B will be disconnected from each other. As the analog switch ASW3 is turned off, the output of the inverter circuit 24 and the input of the inverter circuit 25 are disconnected from each other, and the locked state of the inverter circuits 24 and 25 is cancelled.

With the reset signal R at the high level, Mn6 will be turned off. As a result, the output OUT is connected to the power supply VSS via Mn6, and the output OUT becomes a low level. Since Mn6 is turned on, the input of the inverter circuit 25 becomes a low level, and therefore, the node C and the node B become a high level and a low level, respectively. As the node B is at the low level, the gate and source of Mn7 in the analog switch ASW3 become high and low levels, respectively. As Mn7 turns on, the output terminal OUT is connected to node B (low level). Here, through the operation of Mn6, the output terminal OUT is already at a low level.

After time t5, the reset signal R is at a low level. At this point, Mn6 will be turned off, and the output terminal OUT will be disconnected from the power supply VSS. However, since the analog switch ASW3 is closed, the inverter circuits 24 and 25 are locked again, and the output OUT will be maintained at a low level.

The following is to consider the rising characteristics of the output in the RS flip-flop with the structure as described in this embodiment. With the low-level control signal GB supplied to the RS flip-flop, the node A becomes low when the clock signal CK drops. Here, by providing Mp3 with a larger channel width than Nn3, the rise time of the output OUT can be reduced. This will make Mp3 more improved driving ability than Mn3, thereby improving the ascent characteristics.

On the other hand, with regard to the drop characteristics of the output OUT, the drop time can be reduced by improving the driving capability of Mn6 that brings the output OUT to a low level in response to the reset signal R. This can be achieved by increasing the channel width of Mn6.

As the reset signal R rises, Mn6 will turn on. Here, immediately after the reset signal R rises, the output OUT will be completely disconnected from other circuits except Mn6 due to the analog switch ASW3. In this way, from an electrical point of view, the output OUT is only affected by Mn6. That is, the droop characteristic depends only on the driving ability of Mn6.

With the structure, the RS flip-flop can independently adjust the falling and rising characteristics of the output OUT, so compared to the traditional structure, when used in a shift register, the delay time of the output signal Q can be greatly reduced .

Since the RS flip-flop of the structure shown in FIG. 6 does not require an inverter 26 to operate the analog switch ASW2, it is more advantageous than the RS flip-flop of the structure shown in FIG. 1, thereby enabling the number of components to be reduced. .

[Third Embodiment]

With reference to FIG. 7, an exemplary structure of an RS flip-flop according to still another embodiment of the present invention will be described below.

The RS flip-flop shown in FIG. 7 includes two main parts, the gate area 28 and the lock area 22. Regarding the structure and operation of the lock area 22, since they are basically the same as in the RS flip-flop of the first embodiment described with reference to FIG. 1, no further explanation is provided.

The gate area 28 is configured to receive the control signal GB, the clock signal CK, and the inverted clock signal CKB, wherein the clock signal CK and the inverted clock signal CKB have an amplitude smaller than that generated by VDD , VDD is the power supply of the flip-flop.

In the gate region 28, Mp8 and Mn8 are connected in series between the power supply VDD and the input terminal CKB, and Mn9 is connected between the input terminal CK and the node A (the output of the gate region 28). Mn10 is disposed between the junction (node D) of the power source VSS and the source and drain of Mp8. The individual gates of Mp8 and Mn10 are connected to the control terminal GB. The gate of Mn8 is connected to node D.

In the following, referring to FIG. 8, the operation of the RS flip-flop shown in FIG. 7 will be explained.

The timing diagram shown in Figure 8 assumes that the control signal GB, the clock signal CK, the inverted clock signal CKB, and the reset signal R are respectively input to the control terminal GB, input terminal CK, and input of the RS flip-flop. Terminal CKB, and reset terminal R. For example, it is assumed here that the clock signal and the inverted clock signal CKB both have an amplitude of 3.3V, and the VDD and VSS of the circuit are 12V and 0V, respectively. The critical value of Mn8 and Mn9 is 3V.

When the control signal GB becomes low-level (VSS) at time t1, Mp8 will be turned on and Mn10 will be turned off. Here, since the threshold voltages of the inverted clock signal CKB, clock signal CK, and Mn8 are 0V, 3.3V, and 3V, respectively, the potential of the node D is about 3V, which is close to the threshold voltage of Mn8. Since the potential of the node D is the gate potential of Mn9, Mn9 has a gate potential of about 3V and a source potential of 3.3V. Since the gate-source voltage is about 0.3V, Mn9 will be turned off and node A will remain at its high level. According to the operation described in the first embodiment, in the lock area 22, the potential of the node A is maintained at a high level, and the output OUT is at a low level.

At time t2, when the inverted clock signal CKB and the clock signal CK become 3.3V and 0V, respectively, since 3.3V is added to the 3V threshold of Mn8, the node D becomes approximately 6.3V. The potential of node D is applied to the gate of Mn9. Here, since the source of Mn9 is 0V, Mn9 will be turned off and node A will become a low level.

At time t3, the control signal GB becomes high level (VDD=12V), Mp8 is turned off, and Mn10 is turned on. As a result, the individual gates of Mn8 and Mn9 become low level (VSS=0), and the clock signal CK and the inverted clock signal CKB are cut off. In this way, when the control signal GB is at a high level (VDD=12V), regardless of the state of these clock signals, the flip-flop will not be affected by the clock signal CK or the inverted clock signal CKB. Here, since Mn9 is turned off, the clockless signal CK is supplied to node A. The node A will be maintained at a low level by the lock area 22, and the output OUT of the lock area 22 will be maintained at a high level.

After the time t4, Mn9 will be turned off. Therefore, the output of the gate area 28 will not affect the operation of the lock area 22. That is, the RS flip-flop will operate in the same manner as described in the first embodiment.

It is worth noting that here, the structure of the RS flip-flop shown in FIG. 7 combining the gate area 28 and the lock area 22 of FIG. 1 can be modified as shown in FIG. 9, and the gate area 28 is combined with that shown in FIG. Locked 27. In this case, the relationship between the different input and output signals in the RS flip-flop shown in FIG. 7 also remains the same as that of the RS flip-flop shown in FIG. 9.

[Fourth Embodiment]

Referring to FIG. 10, an exemplary structure of an RS flip-flop according to still another embodiment of the present invention will be described below.

The RS flip-flop shown in FIG. 10 includes two main parts, a gate area 21 and a lock area 29. Regarding the structure and operation of the gate region 21, since they are basically the same as in the RS flip-flop of the first embodiment described with reference to FIG. 1, no further explanation is provided.

The lock area 29 is similar to the lock area 22 described in the first embodiment, but the difference is that it includes a clock inverter circuit 24' instead of the inverter 24, and does not include the analog switch ASW2.

The clock inverter circuit 24 is configured to further include Mp11 and Mn11 on both sides of Mp3 and Mn4 constituting the inverter circuit 24. In particular, Mp11 is arranged between Mp3 and the power supply VDD, and Mn11 is arranged between Mn3 and the power supply VSS. The gate of Mp11 directly receives the reset signal R, and the gate of Mn11 receives the reset signal R after it is inverted by the inverter 30.

In the RS flip-flop shown in FIG. 10, when the reset signal R is at a high level, Mp11 and Mn11 are turned off. In this state, Mp3 and Mn3 will be disconnected from the power supply VDD and VSS, and the circuit is in a floating state. This is equivalent to the state where the analog switch ASW2 is closed in the lock area 22 shown in FIG. 1. When the reset signal R is low, Mp11 and Mn11 will be turned on, and Mp3 and Mn3 will be connected to the power supply VDD and VSS. This is equivalent to the state where the analog switch ASW2 is turned on in the lock circuit 22 shown in FIG. 1.

In this way, the RS flip-flop according to this embodiment will operate in the same manner as the RS flip-flop shown in FIG. 1. In addition, when a circuit structure omitting the analog switch ASW2 and the clock inverter circuit 24' is used, the RS flip-flop will require a smaller circuit area.

The RS flip-flop according to this embodiment will be modified to have the structure shown in FIGS. 11 and 12. In these modified embodiments, a clock inverter circuit 25' (in the case of FIG. 11) or a clock inverter circuit 25" (in the case of FIG. 12) is used instead of the structure shown in FIG. 1 The inverter circuit 25.

The clock inverter circuit (NOR circuit) 25' includes Mp12 connected between the output terminal OUT and Mp4, and Mn12 connected in parallel with Mn4 between the power supply VSS and the output terminal OUT. The individual gates of Mp12 and Mn12 receive the reset signal RB.

Figures 13 and 14 show the input signal and output signal waveforms of the RS flip-flop shown in Figures 11 and 12, respectively. Here, the special description about the RS flip-flops of these input and output signals is omitted.

[Fifth Embodiment]

In the RS flip-flops described in the first to third embodiments, an inverter (that is, the inverter circuit 24) is used to improve the output rising characteristic, and the output terminal and the low potential VSS are used to pass through the transistor at the same time. The structure of Mn6 connected to each other improves the drop characteristics.

Conversely, an inverter can be used to improve the output drop characteristics, and the output terminal out and the high potential VDD are connected to each other via a transistor to improve the rise characteristics. Figure 15 shows the structure of an example of this RS flip-flop.

The RS flip-flop shown in FIG. 15 includes two main parts, the gate area 21 (or the gate area 28 shown in FIG. 7), and the lock area 31. Regarding the structure and operation of the gate region 21, since they are basically the same as the structure and operation of the RS flip-flop of the first embodiment described with reference to FIG. 1, no further description will be given.

The lock area 21 is similar to the lock area 22 described in the first embodiment, but does not include Mn6. Instead, the lock area 31 includes Mp14 between the power supply VDD and the output terminal OUT. The gate of Mp14 is connected to the control terminal R via the inverter 26.

FIG. 16 shows the waveforms of the input and output signals of the RS flip-flop shown in FIG. 15. However, the operation of the circuit will not be specifically described. In the RS flip-flop, since ASW2 will be turned on when the output OUT drops, the drop characteristic can be improved by designing the inverter circuit to prefer the drop feature. On the other hand, because when the output OUT rises, ASW2 is closed, so by improving the driving capability of Mp14, the rising characteristics of the RS flip-flop can be improved.

As described above, the flip-flop of the embodiment of the present invention includes: a gate area, which transmits an externally supplied input signal to the subsequent stage's lock area according to a control signal supplied separately from the input signal; and, includes a lock circuit In the lock area, the lock circuit is used for the input signal supplied by the lock gate area. The lock area also includes a lock cancel area, which is externally supplied to the lock state of the lock circuit in the lock area to cancel the lock circuit The locked state and the output control area are used to output high or low potential as the power supply for operating the flip-flop.

With this configuration, according to the change of the signal locked in the locker (input signal supplied from the gate area), the output signal of the flip-flop becomes high level (or low level). However, by outputting high level or The low potential is used as the power supply for operating the flip-flop, and provides a low-level (or high-level) output signal.

For example, the output signal of the flip-flop will drop when the input signal locked by the lock circuit rises. When the lock state of the lock circuit is cancelled by the reset signal, the high potential supplied as the operating power of the flip-flop will be output from the output control area as the output signal.

In this case, by designing the lock circuit to prefer the drop feature, the drop time of the output signal can be reduced. On the other hand, by improving the drive capability of the output control area, the rise time of the output signal can be reduced.

That is, in the flip-flop configured as above, the falling and rising characteristics of the output signal will depend on the lock circuit and the output control area, respectively, allowing completely independent adjustments. As a result, a flip-flop that can improve the ascent and descent characteristics at the same time is obtained.

In the flip-flop according to the embodiment of the present invention, the lock circuit includes two inverter circuits, the respective inputs of the two inverter circuits are connected to their respective outputs, and the lock cancel area is an analog switch , Its on/off will switch according to the reset signal, and it is arranged between the output terminal of the flip-flop and the output of any inverter circuit connected to the output terminal of the flip-flop in the two inverter circuits, and , The output control area is a switching element whose on/off is switched according to the reset signal and is arranged between the output terminal of the flip-flop and the high-potential or low-potential input terminal of the power supply for operating the flip-flop.

With this configuration, in the second inverter circuit implementing the lock circuit, one of the inverter circuits whose output is connected to the output terminal of the flip-flop can be used to improve the falling or rising characteristics of the output signal, while other characteristics will Improved by switching elements.

In addition, in the flip-flop according to the embodiment of the present invention, the analog switch includes a CMOS analog switch of a p-type transistor and an n-type transistor connected to each other via a source and a drain, and a p-type transistor and an n-type transistor. The crystal is directly switched on or off according to the reset signal.

According to this configuration, the operations of both the p-type transistor and the n-type transistor are directly switched by the reset signal. This ensures the operation of the analog switch.

In addition, according to the flip-flop of the embodiment of the present invention, the analog switch is a CMOS analog switch. The CMOS analog switch includes a p-type transistor and an n-type transistor. The drains are connected to each other, and they will be switched on or off, so that one of the p-type transistor and the n-type transistor will switch directly according to the reset signal, and the other of the p-type transistor and the n-type transistor One will switch according to the fluctuation of the gate-source potential relative to the supplied fixed gate potential.

With this configuration, p-type transistors and n-type transistors that implement analog switches, only the operation of one of these transistors will be directly switched by the reset signal. Compared with a configuration where two transistors are directly switched by a reset signal, this reduces the number of inverter components.

In addition, in the flip-flop according to the embodiment of the present invention, the latch circuit includes two inverter circuits, their respective inputs are connected to their respective outputs, and the clock inverter is used for the two inverter circuits. The input of the inverter circuit is connected to one of the output terminals of the flip-flop, so that the lock circuit is also used as a lock cancel area.

With this configuration, the clock inverter is used to implement one of the two inverter circuits of the lock circuit, so that the lock circuit is also used as a lock cancel area. This will reduce the circuit area.

The flip-flops are connected in multiple stages to provide the shift register according to the embodiment of the present invention.

With this configuration, the flip-flops used in the shift register can improve their rising and falling characteristics, thereby reducing the signal delay in the shift register.

The active matrix display device according to the embodiment of the invention includes a scanning signal line driving circuit and a data signal line driving circuit, at least one of which uses the shift register of the embodiment of the invention.

With this configuration, the use of the shift register in the data signal line driving circuit will reduce the delay in the sampling signal generated by the shift register. Therefore, the timing of the sampling signal and the data signal fed through the data feeder will not be offset. Since there is no timing offset, the required data can be stably applied to the source line. On the other hand, using the shift register in the scanning signal line driving circuit makes it easier to time the scan signal of the generated shift register with the data signal supplied to the source line, thereby achieving stable operation.

The invention thus described can obviously be changed in many ways in the same way. These changes will not be regarded as deviating from the spirit and scope of the present invention, and all these modifications that are obvious to those who are accustomed to the art are included in the scope of the appended patent application.

<p>1. . . Shift register</p><p>13. . . Scanning signal line drive circuit</p><p>14. . . Data signal line drive circuit</p><p>17. . . Shift register</p><p>twenty one. . . Gate area</p><p>twenty two. . . Locked area</p><p>twenty four. . . Inverter circuit</p><p>twenty four'. . . Clock inverter circuit (lock cancel area)</p><p>25. . . Inverter circuit</p><p>25'. . . Clock inverter circuit (lock cancel area)</p><p>25"... Clock inverter circuit (lock cancel area)</p><p>27. . . Locked area</p><p>28. . . Gate area</p><p>29. . . Locked area</p><p>31. . . Locked area</p><p>ASW2. . . Analog switch (lock cancel area)</p><p>Mn6. . . n-type transistor</p><p>GB. . . Control signal</p><p>CK. . . Clock signal (input signal)</p><p>CKB. . . Inverted clock signal</p><p>R. . . Reset signal</p><p>OUT. . . Output signal</p>

Fig. 1 is a circuit diagram showing the structure of the RS flip-flop according to the first embodiment of the present invention.

Figure 2 shows the structure of an image display device, using a shift register in its driving circuit.

Figure 3 shows the pixel structure in the image display device.

FIG. 4 is a timing diagram of the input and output signal waveforms of the flip-flop shown in FIG. 1.

FIG. 5 is a circuit diagram showing the structure of the RS flip-flop according to the second embodiment of the present invention.

Figure 6 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in Figure 5.

FIG. 7 is a circuit diagram showing the structure of the RS flip-flop according to the third embodiment of the present invention.

FIG. 8 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in FIG. 7.

Fig. 9 is a circuit diagram showing another structure of the RS flip-flop according to the third embodiment of the present invention.

FIG. 10 is a circuit diagram showing the structure of the RS flip-flop according to the fourth embodiment of the present invention.

FIG. 11 is a circuit diagram showing another structure of the RS flip-flop according to the fourth embodiment of the present invention.

Fig. 12 is a circuit diagram showing yet another structure of the RS flip-flop according to the fourth embodiment of the present invention.

FIG. 13 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in FIG. 11.

Figure 14 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in Figure 12.

Fig. 15 is a circuit diagram showing the structure of the RS flip-flop according to the fifth embodiment of the present invention.

Figure 16 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in Figure 15.

Figure 17 shows the basic structure of the reset flip-flop.

Figure 18 illustrates the structure of a conventional RS flip-flop.

Figure 19 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in Figure 18.

Fig. 20 is a circuit diagram showing another exemplary structure of a conventional RS flip-flop.

FIG. 21 is a timing diagram showing the waveforms of the input and output signals of the flip-flop shown in FIG. 20.

Fig. 22 is a block diagram showing the structure of an exemplary shift register using RS flip-flops.

FIG. 23 is a timing diagram showing the waveforms of the input and output signals of the shift register shown in FIG. 22.

Figure 24 is a graph representing the input and output characteristics of the inverter.

Figure 25 is a graph representing the transient characteristics (output waveform) of the inverter.

FIG. 26 is a graph representing the rising waveform of the output waveform of the inverter of FIG. 25.

FIG. 27 is a graph representing the falling waveform of the output waveform of the inverter of FIG. 25.