Method and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device

Method and device for manufacturing ultra-thin semiconductor chip and method and device for manufacturing ultra-thin backlight solid-state image capturing element

The present invention relates to an ultra-thin semiconductor wafer based on a novel ultra-thin silicon-on-insulator (SOI) substrate manufacturing method. More specifically, it relates to a novel ultra-thin SOI substrate manufacturing method. A basic method and apparatus for manufacturing a back-light solid-state image capturing device, which can be used to detect incident light from the back surface of an ultra-thin single-sided resin-sealed chip-size hollow package substrate.

As for an image sensor that can sense UV rays, soft X-rays, or electron beams, it can be made by using a backlit charge coupled device (CCD) or the like.

In other words, UV rays, soft X-rays, and electron beams all have extremely large absorption coefficients, so that a CCD does not have any polysilicon electrodes or other obstacles at the incident surface, that is, to irradiate from the back of the CCD forming surface A backlit CCD is preferred.

The thickness of a common silicon substrate is 400 to 500 μm, but it cannot be used as a backlight substrate. Therefore, the back of the silicon substrate must be thinned mechanically or chemically, that is, the back is ground down, the back is ground down and the back is polished, or the back is ground down and chemically etched.

For example, the technology disclosed in Japanese Unexamined Patent Application (Kokai) No. 6-326293 includes forming a polyacrylic resin film on the surface of a substrate on which a CCD backlight function can be formed. , Paste a first-generation silicon substrate on it, grind down the entire back of the CCD substrate, and then polish the back into a mirror state. Then, the polished substrate surface can be chemically etched to remove the deformed layer formed near the front surface of the substrate due to mechanical grinding, so that a backlight light detection with the expected substrate thickness can be obtained Substrate.

In addition, the technology disclosed in Japanese Unexamined Patent Application (Kokai) No. 7-245386 includes forming a silicon nitride film on the back of a substrate on which a CCD backlight function can be formed, in the frame state Remove the silicon nitride film at the center of the back of the wafer that will be irradiated by light while leaving the silicon nitride film around the wafer, and use it as a photomask for silicon chemical etching, and chemically etch The back, thereby obtaining a predetermined thickness of 10 to 20 μm.

To sum up, the problems that the present invention uses such mechanical, chemical, or mechanical plus chemical methods to solve are as follows: the change in the thickness of the necessary substrate at the center of the back of the wafer that will be irradiated by light, and the light of the CCD sensor The receiving sensitivity will become uneven, the fixed pattern noise caused by the dark current will increase, and other problems that are prone to occur.

In addition, the wafer is very susceptible to mechanical shocks, temperature changes, and thickness reductions, and cracks and thus chipping, resulting in a decline in yield and quality. Similarly, increasing the number of work steps will also lead to a decrease in productivity, and therefore cost increases cannot be avoided.

The technology disclosed in the Japanese Unexamined Patent Application (Kokai) No. 2001-267542 is related to an infrared sensor, which is composed of an SOI layer formed by a pn junction; and the Japanese Unexamined Patent Application The technology disclosed in Kokai No. 2000-88640 and Japanese Unexamined Patent Application (Kokai) No. 9-166497 relates to an infrared detector using an SOI substrate.

Therefore, it is also considered to use an SOI layer as a thin semiconductor layer of the backlight in the backlight solid-state image capturing device, so as to save mechanical and chemical polishing. In fact, the technology disclosed in Japanese Unexamined Patent Application (Kokai) No. 10-209417 is related to a solid-state image capturing element using a soldered SOI substrate to detect X-rays, gamma rays, and electrification. particle.

Hereinafter, the problems that occur when trying to manufacture a thin semiconductor chip and a thin back-light solid-state image capturing device using the well-known SOI substrate manufacturing process are explained in detail.

The methods known so far that can be used to manufacture SOI substrates are as follows: ELTRAN (Canon) method, hydrogen ion lift-off method (also known as "smart cutting method" (Commissariat a 1'Energie Atomique; France)), SIMOX method and so on.

In the ELTRAN method disclosed in the well-known ELTRAN technical paper Japanese Patent No. 2608351, the surface of a Si seed wafer is chemically treated by anodizing method to make it into an infinite number of pores with a diameter of 0.01 μm. The formed porous Si layer. Then, a single crystal Si layer can be epitaxially grown on the porous Si layer. In addition, the surface of the single crystal Si layer can be thermally oxidized to form an insulating film, which is welded to a hand-held Si wafer, and then the Si seed wafer in the porous layer can be divided by water jet . Then, an ultra-high selective etching method can be used to remove the porous layer still remaining on the hand-held Si wafer, and finally the surface can be planarized by a hydrogen annealing method, thereby manufacturing the SOI substrate.

That is, this is a combination of epitaxial growth and surface planarization by hydrogen annealing treatment on a porous Si layer that can be processed by an ultra-high selective etching method. )structure.

The above method is characterized by the use of water jets to divide the Si seed wafer located in the porous Si layer. The thinner the single crystal Si layer and the larger the wafer size, the higher the difficulty of the division. Relations such as cracking and crushing are more prone to problems in yield and quality.

In addition, the technique disclosed in Japanese Unexamined Patent Application (Kokai) No. 11-195562 requires the formation of multiple porous Si layers with different porosities as the upper porous layer, thereby facilitating peeling. In particular, when the porous Si layer is pulled tightly for peeling, it is also prone to problems in yield and quality due to cracking, chipping, and crushing.

The hydrogen ion splitting method (smart cutting method) involves forming a hydrogen ion implantation layer at a predetermined depth from the surface of the Si layer, and soldering the result to a Si wafer that has been thermally oxidized separately. An insulating film is formed, and then the result is heat-treated, and the layers are peeled off the hydrogen ion implantation layer, and finally the surface can be flattened by the hydrogen annealing method, thereby manufacturing an SOI substrate (for example, Refer to Japanese Patent No. 3048201, Japanese Unexamined Patent Publication (Kokai) No. 2000-196047, Japanese Unexamined Patent Publication (Kokai) No. 2001-77044, and Japanese Unexamined Patent Publication Application (Kokai) No. 5-211128).

The above method is characterized in that strain is generated in the high hydrogen ion implantation layer by the pressure effect in the hydrogen microbubbles, the crystal rearrangement effect, and the separation and division of the two substrates. In this method, the thinner the single crystal Si layer and the larger the wafer size, the higher the difficulty of segmentation, and the easier it is to have problems in yield and quality due to cracks, chipping, and shattering. .

As explained above, when trying to use these well-known SOI substrate manufacturing processes to manufacture a thin semiconductor chip and a thin backlit solid-state image capturing device, in each case, it becomes more difficult when the size of the wafer becomes larger. Split, and will cause problems in output, quality and reliability due to cracks, fragments, and crushing.

The object of the present invention is to provide a method and apparatus for manufacturing an ultra-thin semiconductor chip (more specifically, an ultra-thin backlight solid-state image capturing device), which utilizes an insulating layer formed on a single crystal support substrate (Hereinafter referred to as "support substrate") on the single crystal semiconductor layer, and improve the separation performance between the single crystal semiconductor layer and the support substrate, so as to improve yield, quality, and productivity.

In order to achieve the above objective, according to the first aspect of the present invention, a method for manufacturing an ultra-thin semiconductor wafer is provided. A first single crystal semiconductor layer is formed on the seed substrate"); the seed substrate at the end of the first single crystal semiconductor layer is welded to a support substrate through an insulating layer, and the support substrate has passed through a second porous semiconductor peeling layer in A second single crystal semiconductor layer is formed thereon; the seed substrate is divided by using the first porous semiconductor peeling layer as an interface; and the supporting substrate is divided by using the second porous semiconductor peeling layer as an interface to obtain The first single crystal semiconductor layer formed on the insulating layer. An ultra-thin SOI substrate can be used to manufacture an ultra-thin semiconductor wafer using the so-called double-porous layer division method.

In addition, in order to improve the peeling effect between the ultra-thin SOI substrate and the support substrate, according to the second aspect of the present invention, a method for manufacturing an ultra-thin semiconductor chip (specifically, an ultra-thin backlight solid-state image capturing device) is provided. ) Method, the steps are as follows: forming a base composed of a supporting substrate, on which a second porous semiconductor peeling layer, a second single crystal semiconductor layer, an insulating layer, and a first A single crystal semiconductor layer, and a semiconductor element unit (specifically, a solid-state image capturing sensor unit) is formed in the first single crystal semiconductor layer and is to be connected to the semiconductor element unit (specifically, a A plurality of protruding connection electrodes of a solid-state image capturing sensor unit); a notch ( For example, using a blade dicing method) to divide it into another semiconductor chip (specifically, a solid-state image capture device); to form a resin protective film to fill the inside of the groove and cover the The surface of the first single crystal semiconductor layer; by polishing one of the surfaces of the resin protective film to expose the protruding connection electrodes on the surface; using a conductive protective tape without residual conductive adhesive (for example, UV Radiation-cured tape) to cover the surface of the resin protective film and the surfaces of the protruding connection electrodes; use the second porous semiconductor peeling layer as an interface to peel off the support substrate; and along the resin filled in the groove The protective film is cut from the end of the second single crystal semiconductor layer (for example, using a blade cutting method) to separate another semiconductor chip (specifically, a solid-state image capturing device).

According to the third aspect of the present invention, a method for manufacturing an ultra-thin semiconductor wafer is provided. The steps are as follows: For example, a first ion implantation peeling layer implanted by hydrogen ions is formed on a seed substrate. A single crystal semiconductor layer; solder the seed substrate at the end of the first single crystal semiconductor layer to a supporting substrate through an insulating layer; use the first ion implantation lift-off layer as an interface to divide the seed substrate; and for example Using a second ion implantation stripping layer implanted by hydrogen ions as an interface to divide the support substrate to obtain the first single crystal semiconductor layer formed on the insulating layer. An ultra-thin SOI substrate can be used to manufacture an ultra-thin semiconductor wafer using the so-called dual ion implantation layer division method.

In addition, in order to improve the peeling effect between the ultra-thin SOI substrate and the supporting substrate, according to the fourth aspect of the present invention, a method for manufacturing an ultra-thin semiconductor chip (specifically, an ultra-thin backlight solid-state image capturing device) is provided. ) Method, the steps are as follows: forming a base composed of a supporting substrate, on which a second ion implantation lift-off layer implanted by hydrogen ions, a second single crystal semiconductor layer, and a An insulating layer and a first single crystal semiconductor layer, and a semiconductor element unit (specifically, a solid-state image capturing sensor unit) is formed in the first single crystal semiconductor layer and is to be connected to the semiconductor element unit (Specifically, a solid-state image capture sensor unit) a plurality of protruding connection electrodes; along a line from the end of the first single crystal semiconductor layer to at least the second ion implantation peeling layer of the substrate The dividing line forms a groove (for example, using a blade cutting method) to divide it into another semiconductor chip (specifically, a solid-state image capturing device); a resin protective film is formed to fill the carved The inside of the groove and covering the surface of the first single crystal semiconductor layer; by polishing one of the surfaces of the resin protective film to expose the protruding connection electrodes on the surface; using a conductive protective tape without residual conductive adhesive To cover the surface of the resin protective film and the surfaces of the protruding connection electrodes; use the second ion implantation peeling layer as an interface to peel off the support substrate; and follow the resin protective film filled in the groove from the first The two single crystal semiconductor layer ends are diced (for example, using a blade dicing method) to separate another semiconductor chip (specifically, a solid-state image capturing device). Please note that in ion implantation, in addition to hydrogen, diluent gases such as nitrogen and helium can also be used.

According to the fifth aspect of the present invention, a method for manufacturing an ultra-thin semiconductor wafer is provided. The steps are as follows: For example, a first ion implantation lift-off layer implanted by hydrogen ions is formed on a seed substrate. Crystal semiconductor layer; solder the seed substrate from the end of the single crystal semiconductor layer through an insulating layer to a support substrate on which a porous semiconductor peeling layer has been formed; use the ion implantation peeling layer as an interface to divide the crystal Seed substrate; and the porous semiconductor peeling layer is used as an interface to divide the supporting substrate to obtain the single crystal semiconductor layer formed on the insulating layer. According to the so-called porous layer/ion implanted layer division method, an ultra-thin SOI substrate can be used to manufacture an ultra-thin semiconductor wafer.

In addition, in order to improve the peeling effect between the ultra-thin SOI substrate and the support substrate, according to the sixth aspect of the present invention, a method for manufacturing an ultra-thin semiconductor chip (specifically, an ultra-thin backlight solid-state image capturing device) is provided. ) Method, the steps are as follows: forming a base composed of a supporting substrate, on which a porous semiconductor peeling layer, a second single crystal semiconductor layer, an insulating layer, and a first single crystal can be stacked Crystalline semiconductor layer, and a semiconductor element unit (specifically, a solid-state image capturing sensor unit) is formed in the first single-crystal semiconductor layer and to be connected to the semiconductor element unit (specifically, a solid-state image Acquire a plurality of protruding connection electrodes of the sensor unit); form a notch along a dividing line from the end of the first single crystal semiconductor layer to at least the porous semiconductor peeling layer of the substrate to divide it Into another semiconductor chip (specifically, a solid-state image capturing device); forming a resin protective film to fill the inside of the groove and cover the surface of the first single crystal semiconductor layer; to protect the resin by polishing One of the surfaces of the film exposes the protruding connection electrodes on the surface; the conductive protective tape without residual conductive adhesive is used to cover the surface of the resin protective film and the protruding connection electrodes; the porous semiconductor peeling layer Used as an interface to peel off the support substrate; and cut along the resin protective film filled in the groove from the end of the second single crystal semiconductor layer to separate another semiconductor wafer (specifically, a solid Image capture component).

In the present invention, in order to manufacture an ultra-thin semiconductor chip (specifically, an ultra-thin backlight solid-state image capturing device), the semiconductor chip is composed of a first single crystal semiconductor layer on which a semiconductor device unit is formed (Specifically, a solid-state image capturing sensor unit) and a plurality of protruding connection electrodes to be connected to the semiconductor device unit (specifically, a solid-state image capturing sensor unit), the present invention Use a base composed of a supporting substrate on which an ion implantation layer or a porous material peeling layer, a second single crystal semiconductor layer, an insulating layer, and a first single crystal semiconductor layer are stacked, and The following steps are to improve the peeling effect of the support substrate.

First, it will form a notch along a dividing line from the end of the first single crystal semiconductor layer to at least the ion implantation layer or the porous peeling layer of the substrate (for example, using a blade cutting method) , Used to divide it into another semiconductor chip (specifically, a solid-state image capture device).

Then, a resin protective film is formed to fill the inside of the groove and cover the surface of the first single crystal semiconductor layer, and to provide the curing shrinkage stress and strain of the resin protective film to the release layer of the supporting substrate, thereby It helps to peel off the support substrate by using the peeling layer as an interface.

In addition, it can be achieved by polishing one surface of the resin protective film to expose the protruding connection electrodes on the surface, and using a conductive protective tape without residual conductive adhesive (for example, a UV-ray cured tape ) To cover the surface of the resin protective film and the surfaces of the protruding connection electrodes to avoid electrostatic damage during peeling and mounting on a mounting board.

In addition, the porous semiconductor peeling layer can be used as an interface to peel off the supporting substrate, and then it can be cut from the end of the second single crystal semiconductor layer along the resin protective film filled in the groove (for example, cutting with a blade Method), used to divide another semiconductor chip (specifically, a solid-state image capturing device).

In this way, a single-surface resin-sealed ultra-thin semiconductor chip (specifically, a single-surface resin-sealed ultra-thin backlight solid-state image capturing device) can be manufactured.

According to the seventh aspect of the present invention, there is provided an ultra-thin semiconductor chip manufacturing apparatus (specifically, an ultra-thin backlight solid-state image capturing device manufacturing apparatus), which can dispense liquid (water, water, Etching solution, alcohol, etc.), gas (air, nitrogen, argon, etc.), a mixture of liquid and gas (which will mix the gas in the liquid) in a suitable ratio, or containing solid fine particles and powder (polishing agent, ice The same fluid of ultrafine particles composed of blocks, plastics, etc.) is released onto a substrate with at least two porous semiconductor peeling layers inside, which is used to divide the substrate in a predetermined porous semiconductor peeling layer as an interface during rotation. , The manufacturing device of the ultra-thin semiconductor chip (specifically, a manufacturing device of the ultra-thin backlight solid-state image capturing device) has: a plurality of supporting parts for rotatably supporting the front and back of the substrate; The releasing part is used to release the fluid toward the porous semiconductor peeling layer; and a blocking layer part is used to prevent the fluid flowing out of the releasing part from invading other porous semiconductor peeling layers.

According to the manufacturing device of the ultra-thin semiconductor wafer of the present invention (specifically, a manufacturing device of an ultra-thin backlit solid-state image capturing device), because when the fluid is released into a device with at least two porous semiconductor peeling layers inside When the substrate is used to divide the substrate by using a predetermined porous semiconductor peeling layer as an interface, the present invention provides a blocking layer portion to prevent the fluid flowing from the release portion from invading other porous semiconductor peeling layers. The peeling action of the fluid does not affect the other porous semiconductor peeling layers, so the expected porous semiconductor peeling layer can be used as an interface to divide the substrate.

According to the eighth aspect of the present invention, there is provided an ultra-thin semiconductor wafer manufacturing apparatus (specifically, an ultra-thin backlight solid-state image capturing device manufacturing apparatus), which can utilize a predetermined porous semiconductor peeling layer or ion implantation. The peeling layer is used as an interface to divide a substrate with at least two porous semiconductor peeling layers or ion implanted peeling layers obtained by ion implantation. The ultra-thin semiconductor wafer manufacturing device (specifically, a super thin semiconductor wafer) The manufacturing device of a thin-type backlight solid-state image capturing device) includes: a plurality of supporting parts for rotatably supporting the front and back of the substrate; and a laser output part for peeling the layer toward the predetermined porous semiconductor Or the ion implantation peeling layer emits a laser beam.

Hereinafter, referring to these drawings, the manufacturing method of the single-sided resin-sealed ultra-thin chip-size hollow package backlight solid-state image capturing device according to the manufacturing method of the ultra-thin SOI substrate of the present invention will be explained. Specific examples.

The first specific embodiment

Among the various novel ultra-thin SOI substrate manufacturing methods, the method explained in this specific embodiment is to use a double porous layer division method (for example, using a first porous Si layer formed on a seed substrate to divide A seed substrate and a method for dividing the support substrate by using a second porous Si layer formed on the support substrate Manufacturing device.

Step 1: Form porous layer

In this step, anodization is used to form a porous Si layer on a seed wafer (hereinafter referred to as "seed substrate") and a hand-held wafer (hereinafter referred to as "support substrate"). At this time, in order to facilitate the division of the seed crystal substrate, the thickness and porosity of the highly porous Si layer on the seed crystal substrate will be greater than the thickness and porosity of the porous Si layer of the support substrate.

Please note that when the seed substrate and supporting substrate use the various semiconductor substrates used here, single crystal Si substrates prepared by CZ process, MCZ process, or FZ process may be used, as well as substrates with hydrogen annealing. Single crystal Si substrate on the surface, epitaxial single crystal Si substrate, etc.

Of course, the present invention is not limited to Si substrates. It is also possible to use SiGe substrates or even SiC substrates, GaAs substrates, InP substrates, or other single crystal compound semiconductor substrates.

When an anode conversion method is used to form the porous Si layer, the porous Si layer may be composed of multiple layers with different porosities.

For example, a three-layer structure can be used on the supporting substrate, a first low-porosity Si layer, a high-porosity Si layer, and a second low-porosity Si layer; it can also be used on the supporting substrate A two-layer structure, a high-porosity Si layer and a low-porosity Si layer.

For example, the porosity of the highly porous Si layer may be 40 to 80%. For example, the porosity of the low-porosity Si layer that can be used is in the range of 10 to 30%.

Changing the current density and application time when performing the anode conversion method, or changing the type or concentration of the conversion solution when performing the anode conversion method, can form multiple layers with different porosities of any thickness.

These steps will be explained in detail below.

First, the CVD method using monosilane or diborane gas is doped with boron. A seed substrate 10 made of p-type Si single crystal with a diameter of 8 inches and a thickness of 800 μm (with a resistivity of 0.01 to 0.02 Ωcm ), the concentration is about 1×10¹⁹/cm³Thus, a high-concentration p-type impurity layer made of an epitaxial growth single crystal Si layer containing high-concentration impurities is formed, and the thickness is about 10 μm.

Then, the surface of the high-concentration p-type impurity layer is doped with boron by the CVD method of monosilane or diborane gas, with a concentration of about 5×10¹⁴/cm³, Used to form a low-concentration p-type impurity layer made of an epitaxial growth single crystal Si layer containing low-concentration impurities, with a thickness of about 20 μm.

In addition, the surface of this low-concentration p-type impurity layer is doped with boron by the CVD method using monosilane or diborane gas, with a concentration of about 5×10¹⁹/cm³, Used to form a high-concentration p-type impurity layer made of an epitaxial growth single crystal Si layer containing high-concentration impurities, with a thickness of about 5 μm.

Please note that when the semiconductor film is a single crystal Si layer, in addition to SiH₄(Monosilane), SiH can also be used₂Cl₂, SiHCl₃, Or SiCl₄To make the raw material gas.

Next, using the anode conversion method, for example, a 50% hydrogen fluoride solution and ethanol can be mixed in a volume ratio of 2:1 to produce a liquid mixture as the electrolyte. At 10 mA/cm²The current density is circulated for about 5 minutes. In this anode conversion method, the substrate can be used as an anode to supply power in the electrolyte. This anode conversion technique was disclosed in "Anodic Conversion of Porous Silicon" published by Ito et al. in Surface Technology, vol. 46, no. 5, pages 8 to 13 in 1995.

In this anodic conversion method, the porosity can be determined according to the impurity concentration used to form the porous layer in the layer, the current density passed through, the concentration of the electrolyte, and the like. For example, the lower the impurity concentration, the higher the porosity; the higher the impurity concentration, the lower the porosity.

Therefore, as shown in FIG. 1A, a high-concentration p-type impurity layer, a low-concentration p-type impurity layer, and a high-concentration p-type impurity layer can be sequentially formed on the seed crystal substrate 10. After the anode conversion method, a porous Si layer 11 can be formed on the seed substrate 10, which includes a low-porosity Si layer 11a with a thickness of about 10 μm and a thickness of about 20 μm. A high-porosity Si layer 11b with a high porosity and a low-porosity Si layer 11c with a thickness of about 5 μm and a low porosity.

In the same way as described above, a support substrate 20 (resistor The rate is 0.01 to 0.02 Ωcm), the concentration is about 1×10¹⁹/cm³, Used to form a high-concentration p-type impurity layer made of an epitaxial growth single crystal Si layer containing high-concentration impurities, with a thickness of about 10 μm.

Then, the surface of this high-concentration p-type impurity layer is doped with boron by the CVD method of monosilane or diborane gas, with a concentration of about 1×10¹⁵/cm³, Used to form a low-concentration p-type impurity layer made of an epitaxial growth single crystal Si layer containing low-concentration impurities, with a thickness of about 2 μm.

In addition, the surface of this low-concentration p-type impurity layer is doped with boron by the CVD method using monosilane or diborane gas, with a concentration of about 3×10¹⁹/cm³, Used to form a high-concentration p-type impurity layer made of an epitaxial growth single crystal Si layer containing high-concentration impurities, with a thickness of about 10 μm.

Please note that in the same way as the above description, when the semiconductor film is a single crystal Si layer, except for SiH₄(Monosilane), SiH can also be used₂Cl₂, SiHCl₃, Or SiCl₄To make the raw material gas.

Then, the anodic conversion method can be used in the same manner as above. For example, a 50% hydrogen fluoride solution and ethanol can be mixed in a volume ratio of 2:1 to produce a mixed solution as the electrolyte, and the temperature is 10 mA/ cm²The current density is circulated for about 5 minutes to change the high-concentration p-type impurity layer into a low-porosity low-porosity Si layer and the low-concentration p-type impurity layer into a high-porosity high-porosity Si layer. Thereby, as shown in FIG. 1B, a porous Si layer 21 can be formed on the supporting substrate 20, which includes a low-porosity Si layer 21a with a thickness of about 10 μm and a thickness of about 2 A high-porosity Si layer 21b with a high porosity of μm and a low-porosity Si layer 21c with a thickness of about 10 μm and a low porosity.

After the porous Si layer 11 is formed on the seed substrate 10 and the porous Si layer 21 is formed on the support substrate 20, it is preferable to perform a dry oxidation method at about 400°C to oxidize the Each inner wall of about 1 to 3 nm in the pores of the porous Si prevents structural changes of the porous Si layer due to high temperature treatment.

In the decomposition reaction of Si in the above anodic conversion method, the anodic reaction of Si in the HF solution requires many positive holes. Therefore, the substrate is preferably a p-type silicon that is easy to become porous.

Preferably, the low-porosity Si layers 11a, 11c, 21a and 21c all have extremely high impurity concentrations (1×10¹⁹/cm³Above) and very low porosity (approximately 10 to 30%). At this time, in order to form a semiconductor layer made of single crystal Si with excellent crystallinity, so that the device of the solid-state image capturing device can be formed on the low-porosity Si layer 11c in the next step. Preferably, the porosity and thickness of the low-porosity Si layer 11c can be smaller than the porosity and thickness of the low-porosity Si layer 21c.

In addition, the high-porosity Si layers 11b and 21b all have extremely low impurity concentrations (1×10¹⁹/cm³Below) and extremely high porosity (approximately 40 to 70%). In this case, in the following steps, in order to help peel off the seed substrate 10 and avoid peeling off the support substrate 20 when the seed substrate 10 is peeled off, the porosity and thickness of the highly porous Si layer 11b are better It can be greater than the porosity and thickness of the highly porous Si layer 21b.

Step 2: Formation of semiconductor layer and insulating film

In this step, a plurality of epitaxially grown single crystal Si layers can be formed on the two substrates of the seed substrate 10 and the support substrate 20, and a silicon oxide film or a silicon oxide film can be formed on at least one of the two substrates. A multilayer film (which includes a silicon oxide film, a silicon nitride film, and a silicon oxide film) is used as the insulating film. This step will be explained in detail below.

Both the seed substrate 10 and the support substrate 20 can be pre-baked in a CVD epitaxial growth device in a hydrogen environment at about 1000 to 1100°C to seal the surfaces of the porous Si layers 11 and 21 In order to smooth the surface.

Then the temperature can be lowered to 1020°C, and silane gas or di-silica boron gas can be used as the raw material gas to implement the CVD method to form a plurality of layers of p-type single crystals on the seed substrate 10 and the support substrate 20 The epitaxial growth semiconductor layer made of the Si layer has a thickness of 5 to 20 μm. For example, as shown in FIG. 2A, a first semiconductor layer 12 made of a p-type single crystal Si layer with a thickness of about 5 to 10 μm can be formed on the porous Si layer 11 of the seed substrate 10 And as shown in FIG. 2B, a second semiconductor layer 22 made of a p-type single crystal Si layer with a thickness of about 15 to 20 μm can be formed on the porous Si layer 21 of the support substrate 20.

At this time, the impurity concentration can be arbitrarily controlled according to the expected characteristics. Of course, not only can a p-type single crystal Si layer be formed according to the type and characteristics of the device, but also an n-type single crystal Si layer can be formed.

In terms of the thickness of the first semiconductor layer 12 and the second semiconductor layer 22, the thickness of the second semiconductor layer 22 of the support substrate 20 is set to be at least equal to the first semiconductor layer 12 of the seed substrate 10.

This setting is to reduce or avoid strain in the first semiconductor layer 12 due to the thermal oxidative expansion of the porous Si layer 21 during device processing of the first semiconductor layer 12 in the subsequent steps.

In the device manufacturing, because the incident light of the backlight needs to be sensed, the thickness of the first semiconductor layer 12 must be about 5 to 20 μm. In addition, as explained later, the second semiconductor layer 22 and the low-porosity Si layer 21c can be finally removed, thereby defining an air gap (height) between the sealing glass and the incident surface, so the The total thickness of the second semiconductor layer 22 and the low-porosity Si layer 21c is preferably about 10-50 μm.

Next, an insulating film 23 made of silicon oxide or the like with a thickness of about 200 to 300 nm is used to form the first semiconductor layer 12 of the seed substrate 10 or the second semiconductor layer 22 of the support substrate 20 At least one of them. As shown in FIG. 2B, an example of forming the insulating film 23 on the supporting substrate 20 can be seen in this embodiment.

Please note that the insulating film 23 may also be a silicon oxide single layer formed by thermal oxidation, CVD, or similar methods; it may also be a silicon oxynitride film or multilayer film formed by a low-pressure CVD method (which includes Silicon oxide film/silicon nitride film or silicon oxide film/silicon nitride film/silicon oxide film) is used to form a silicon nitride film on the second semiconductor layer 22 and thermally oxidize it. For example, in this case, the thickness of the silicon oxide film is set to about 200 nm, the thickness of the silicon nitride film is set to about 50 nm, and the thickness of the silicon oxide film is set to About 200 nm.

According to this method, since the nitride-type silicon film has a suitable thickness, it is possible to avoid contamination by halogen elements originating from the end of the support substrate 20 during packaging or device processing. In addition, it is also possible to reduce or avoid deformation and strain in the epitaxially grown first semiconductor layer 12 during device manufacturing due to the oxidative expansion of the porous Si layer 21 during device processing. In addition, there is an effect that a highly accurate sensor unit can be prepared, because it can serve as an etching stop region when the second semiconductor layer 22 under the insulating film 23 and the porous Si layer 21 are etched away.

Step 3: Soldering

As shown in FIG. 3A, the first semiconductor layer 12 of the seed substrate 10 and the insulating film 23 of the support substrate 20 can be brought into contact with each other at room temperature, and the welding can be performed by van der Waals force. Heat treatment can then be carried out to promote covalent linkage to enhance the welding effect.

At this time, it must be confirmed whether any dust or dirt appears on the surfaces of the two substrates 10 and 20. If there is any foreign matter, it must be stripped and washed away.

In addition, preferably, the heat treatment can be performed in nitrogen or a passive gas or a mixed gas of nitrogen and passive gas. For example, the heat treatment temperature can be set to 400°C and the treatment can be performed for about 30 minutes to enhance the welding effect.

In addition, two stacked substrates can also be set in a low-pressure heat treatment furnace, and the two substrates can be fixed at a predetermined pressure (for example, 133 Pa or less) using an evacuation method, and enter the atmospheric pressure after a predetermined time When the force is applied, pressure is applied to make the two substrates close together, and then the two substrates can be heated in nitrogen or passive gas or a mixture of nitrogen and passive gas at high temperature to continue operation.

Step 4: Divide the seed substrate

Next, as shown in the high-pressure fluid jet injection and stripping device of FIG. 3B, an air jet, a water jet, or a similar jet can be used to divide the seed substrate 10 in the highly porous Si layer 11b. At this time, as explained previously, the porosity and thickness of the high-porosity Si layer 11b are greater than the porosity and thickness of the high-porosity Si layer 21b, so the seed crystal can be peeled off by the pressure of the water jet The substrate 10.

In this step, the end of the support substrate 20 will be sucked by a support substrate holder 301, and the support substrate holder 301 can rotate around a rotating shaft 301a; the end of the seed substrate 10 will be held by a seed substrate holder 301 302 is sucked, the seed substrate holder 302 can rotate around a rotating shaft 302a, and the supporting substrate holder 301 and the seed substrate holder 302 will both rotate. In this state, fluid (for example, air jet or water jet) can be released onto the porous Si layer 11 from the release portion 303 of more than one fine nozzle. At this time, in order to prevent the peeling action of air jets, water jets, etc. from acting on the high-porosity Si layer 21b, it is preferable to provide a stop zone clamp 304 (stop layer part), such as a guard ring stop zone. The relative position of the high-porosity Si layer 21b and the blocking area clamp 304 can be fine-tuned, and the height of the supporting substrate holder 301 can be fine-tuned so that the peeling action caused by air jets, water jets or other fluids will not take effect.

Accordingly, the pressure of the air jet, water jet, etc. will only act on the high porosity Si layer 11b to divide the seed substrate 10.

As mentioned above, when rotating or peeling by tension, the porous Si layer can be divided by spraying a high-pressure fluid (gas or liquid) jet from the lateral direction by using more than one fine nozzle. Seed substrate 10. At this time, ultrasonic waves can be injected into the fluid to achieve the purpose of effective peeling.

The fluid may be water, etching solution, alcohol, or other liquids; it may also be air, nitrogen, argon, or other gases. In addition, a liquid/gas mixture can also be obtained by mixing gas into the liquid in an appropriate ratio. In addition, if each fluid contains ultra-fine solid particles and powders (polishing agent, ice cubes, plastics, etc.), the peeling operation can be carried out very effectively.

In addition, more than one laser beam can be emitted from the lateral direction to the porous Si layer during rotation, and the seed substrate 10 can be divided by a laser method (ablation, heating, etc.).

The laser beam may be a visible light laser beam, near UV rays, far UV rays, near infrared rays, and far infrared rays emitted by carbon dioxide lasers, YAG lasers, excimer lasers, high harmonic modulation lasers, etc. infrared.

The laser method includes the following methods: emitting a laser beam with a wavelength that can be absorbed by the target object, and dividing it by heating or ablation; and having a wavelength that is transparent to the target object At least one of the pulsed-wave near-infrared laser beam or continuous-wave near-infrared laser beam (Nd: YAG laser, Nd: YV04 laser, Nd: YLF laser, titanium sapphire laser, etc.) focuses on the target On the inside of the object, the optical damage phenomenon is caused by multiple photon absorption to form a modified area (for example, the broken area, the melting area, the refractive index change area, etc.), and use it as a starting point to use a smaller Power comes to divide it.

In the latter case, a condensing lens is used to focus the laser beam on the inside of the target object (that is, the inside of the porous semiconductor layer or the inside of the ion implantation layer) while rotating, and the target Moving the focus step by step inside the object can be divided.

Specifically, in the case of the present invention, the segmentation layer is composed of the porous Si layer or an ion implantation layer, so that the laser beam can be segmented very accurately and effectively.

That is, the laser peeling device has the same structure as the fluid high-pressure jet injection peeling device shown in FIG. 3B. The release part 303 of the one or more fine nozzles corresponds to the laser output part.

At this time, if necessary, the seed substrate can be divided from the porous Si layer when the counter substrate end is cooled by using a cooled supporting jig through the UV tape.

Please note that the stripped seed crystal substrate can be reused.

Step 5: Hydrogen annealing

Then, a hydrogen annealing process can be used to etch the entire portion of the low-porosity Si layer 11c remaining after the stripping and a portion of the surface of the first semiconductor layer 12 to form a thickness of about 5 μm with a desired thickness and flatness. The first semiconductor layer 12 is made of single crystal Si. 4A is a cross-sectional view of the state after this step in the case where the insulating film 23 is formed using a single layer of silicon oxide film; 23b, and a silicon monoxide film 23c) to form the insulating film 23, a cross-sectional view of the state after this step.

The hydrogen annealing treatment will etch Si at an etch rate of 0.0013 nm/min at 1050°C and an etch rate of 0.0022 nm/min at 1100°C.

Please note that HF, H can also be used in etching₂O₂With H₂A mixture of O or HF, HNO₃With CH₃The low-porosity Si layer 11c remaining after stripping is carried out with a mixture of COOH and then hydrogen annealing is used to etch the surface of the first semiconductor layer 12 made of single crystal Si.

Step 6: Component shaping

Then, for example, a plurality of CCDs, CMOS sensors, or other backlight solid-state image capturing sensors (which include A plurality of photoelectric conversion parts, a charge transfer part, and a plurality of charge transfer electrodes), and a plurality of bump electrodes connected thereto are formed.

Please note that it is of course possible to form a plurality of front surface light solid-state image capturing sensors and a plurality of raised electrodes connected thereto as in the prior art.

In addition, it is a matter of course that not only front-surface light solid-state image capturing sensors and backlight solid-state image capturing sensors can be formed, but also MOSLSI, BipLSI, BiCMOSLSI, or other silicon-type or silicon-germanium-type semiconductor components can be formed.

In addition, of course, the seed substrate and the supporting substrate can be changed to compound semiconductors to form a SiC, GaAs, InP, or other compound semiconductor device.

A CCD sensor can be constructed by using an image capturing area, which has a plurality of photodiodes arranged in a two-dimensional manner on the Si single crystal substrate to convert light into electric charges (electrons); And a circuit for transferring and outputting the charges.

According to the configuration of the transmission part, it has an inter-line (IL) system and a frame transmission (FT) system.

The inter-line (IL) system can use the vertical transmission line located at the end of the photo sensor to transmit the electric charge obtained by the isophotodiode in a vertical manner in each stage, and use a plurality of electric charges in a continuous series of electric charges. The horizontal register sends it to the output part and amplifies it into a signal voltage.

The frame transfer (FT) system can transfer the charge to a storage part at a high speed, using a plurality of horizontal registers to output it in a continuous charge string, and amplify it into a signal voltage.

In addition, the light diodes can usually be arranged in a square grid, but they can also be arranged in a commercial zigzag manner into light receiving elements to form a so-called honeycomb grid array.

It can be said with certainty here that when an inter-line (IL) system CCD sensor is formed, the photodiodes can be formed in a matrix in the horizontal and vertical directions, which will form a vertical made of a plurality of CCDs. Transmission registers, which will be jointly connected to the photodiodes arranged in the vertical direction, and will form a horizontal transmission register made of a plurality of CCDs, which will be jointly connected to the vertical Transmission register. In addition, the output part can be provided in the transfer stage of the horizontal transfer registers.

The CCD sensor can use the vertical transfer registers and the horizontal transfer registers to transfer the electrons converted by the photodiodes to the output part, and amplify the electrons to the signal voltage.

CMOS sensors will use features such as low power consumption and a single power supply, and can be used as video input components for mobile phones or other mobile components that have attracted much attention.

Basically, CMOS sensors can be manufactured using the same CMOS process as memory, logic LSI, etc.

When forming a CMOS sensor, a photodiode and a switching element composed of a MOS transistor can be combined to form a unit pixel. A plurality of unit pixels can be arranged in a matrix, and the connected pixels can be formed. Multiple horizontal and vertical shift registers. In the CMOS sensor, by sequentially switching the pulses applied from the shift registers, the signal charges of the pixels can be extracted and sent to the output.

Figure 5 is an example of a CCD situation. An ion implantation method can be used to introduce n-type impurities into the first semiconductor layer 12 made of p-type single crystal Si, which can be separated into a plurality of element formation regions by an element isolation insulating film 31 (for example, a field oxide film), It is used to form an unshown photodiode or implant the transmission channel region 12a, and activate it at 750°C for 30 minutes. Please note that in addition to this, p-type impurities can also be introduced to form the channel stop region.

Then, a gate insulating film 32 made of silicon oxide and a transmission electrode 33 made of polysilicon can be formed on the embedded transmission channel region 12a, and an interlayer made of silicon oxide can be formed. Insulating film 34. Please note that the above transmission register is constructed by the implanted transmission channel area 12a and the transmission electrode 33.

Then, a contact hole can be formed in a part of the interlayer insulating film 34, and an electrode external terminal made of metal (such as aluminum or aluminum-silicon alloy) can be formed near the chip or inside and near the chip. The point 35 is used to electrically contact the transmission electrode 33, and can form a protruding raised electrode 36 to be connected to the external terminal 35 of the electrode.

The bump electrode 36 may be a surrounding bump in the periphery of the wafer, an internal bump inside the wafer, or a mixed type bump. The bumps may be any bumps mainly formed by electroplating or terminal bumps composed of Au lines, etc. However, in the latter case, great care must be taken so as not to damage the first due to the sudden shock of line welding. A semiconductor layer 12, a base second semiconductor layer 22, and a porous Si layer 21. Please note that the height can be freely selected in the range of 10 to 100 μm.

As for the method for forming a flux bump, a well-known forming method can be used, such as a super "jaffit" method, a super welding method, or a beam welding PC method.

Here, the super "Yafi" method is a demonstration method, which only forms a barrier metal layer made of a multilayer film composed of Cr and Cu on the Al pad, and treats its surface with a chemical agent to form a Adhesive coating film, and contacting the adhesive coating film with the flux powder, allowing the flux powder to adhere to the surface of the barrier metal layer, and heat-treating it to form a flux bump. Therefore, a bump made of lead-free Sn-Ag type solder or Sn-Zn type solder can be formed.

The super soldering method is a method of forming flux in the paste produced by the reaction of organic acid lead and organic acid tin. The system does not contain flux powder, and it can be used to form flux bumps with the above It is deposited on the copper on the surface of the barrier metal layer in the same way. Therefore, a bump made of Sn-Pb type solder can be formed.

The PC method of beam welding uses a substitution reaction method, which uses a Jaffani battery composed of copper, tin and lead below, to allow tin and lead to precipitate on the surface of the copper and form a coating film. And the use of electroplating to form a flux bump. Therefore, a bump made of Sn-Pb type solder can be formed.

As mentioned above, a solid-state image capturing sensor unit with CCD or CMOS configuration can be formed. By forming a raised electrode 36 through the electrode external part 35 made of aluminum, aluminum-silicon alloy, or similar materials connected to the transmission electrode, etc., a raised electrode 36 can be provided for driving the solid-state image capturing sensor unit. Expected potential for charge transfer etc.

Step 7: Form grooves and protective film

Next, as shown in FIG. 6A, a blade cutting method can be used along a predetermined granular dividing boundary line in a scribe line, starting from the end of the first semiconductor layer 12 and passing through at least a single crystal Si made The second semiconductor layer 22 is formed with a notch S, and then can be sealed by the following materials using transmission molding process, injection molding process, extrusion process, insert molding process, compression molding process, spin coating process, or similar process The inside of the groove S and the surface of the first semiconductor layer 12: epoxy resin, polyimide resin, phenol resin, epoxy acrylate resin, acrylic resin, silicon resin, polyimide silicon resin, unsaturated polyester resin , Or other thermosetting resin, or liquid crystal polymer, polyphenylene sulfide resin, polycarbonate resin, or other thermal resistance type thermal plastic resin, or other transparent, translucent, or opaque resin protective film 40. The film can then be cured according to the molding process and resin characteristics.

Then, an optical polishing method, a chemical mechanical polishing method (CMP), etc. can be used to polish one side of the resin protective film 40 to expose the protruding electrode 36. If necessary, a thin layer of gold can be plated on the surface of the raised electrode 36, and a protective tape 50 can be used to protect the surface.

As for the protective tape 50, a conductive UV curing adhesive and tape that is transparent and has no residual adhesive is suitable to avoid electrostatic damage.

Please note that the transparent, translucent, or opaque resin protective film 40 must be a high-purity product that does not generate alpha rays, so as to avoid impairing image quality.

Step 8: Divide the support substrate

Next, as shown in FIG. 6B, the support substrate 20 can be divided at the highly porous Si layer 21b by using an air jet, a water jet, or the like. At this time, the resin protective film 40 fills the groove S reaching the porous Si layer 21. The strain caused by the curing shrinkage stress of the resin protective film 40 made of epoxy resin or the like is also added. Therefore, the efficiency of dividing the support substrate 20 by using a water jet or the like from the lateral side at the highly porous Si layer 21b becomes better. According to this, it is possible to reduce the mechanical shock caused to the components already formed in the first semiconductor layer 12.

Please note that at this time, it is preferable to use a ring-shaped stop region clamp to protect the resin protective film 40 containing the first semiconductor layer 12 to avoid damage by the lateral pressure of the gas-controlled jet or the water jet.

In addition, during rotation, the supporting substrate can be divided by spraying a high-pressure fluid (gas or liquid) jet from the lateral direction by using more than one fine nozzle or by the tension peeling method. At this time, if ultrasonic waves are injected into the fluid, a more effective effect can be expected.

The fluid may be water, etching solution, alcohol, or other liquids; it may also be air, nitrogen, argon, or other gases. In addition, a liquid/gas mixture can also be obtained by mixing gas into the liquid in an appropriate ratio. In addition, if each fluid contains ultra-fine solid particles and powders (polishing agent, ice cubes, plastics, etc.), the peeling operation can be carried out very effectively.

In addition, more than one laser beam can be emitted from the lateral direction to the porous Si layer during rotation, and the support substrate can be divided by laser (ablation, heating, etc.). The laser beam may be a visible light laser beam, near UV rays, far UV rays, near infrared rays, and far infrared rays emitted by carbon dioxide lasers, YAG lasers, excimer lasers, high harmonic modulation lasers, etc. infrared.

The laser method includes the following methods: emitting a laser beam with a wavelength that can be absorbed by the target object, and dividing it by heating or ablation; and having a wavelength that is transparent to the target object At least one of the pulsed-wave near-infrared laser beam or continuous-wave near-infrared laser beam (Nd:YAG laser, Nd:YV04 laser, Nd:YLF laser, titanium sapphire laser, etc.) focuses on the target On the inside of the object, the optical damage phenomenon is caused by multiple photon absorption to form a modified area (for example, a broken area, a melting area, a refractive index change area, etc.), and use it as a starting point to use a smaller Power comes to divide it.

In the latter case, a condensing lens is used to focus the laser beam on the inside of the target object (that is, the inside of the porous semiconductor layer or the inside of the ion implantation layer) while rotating, and the target Moving the focus step by step inside the object can be divided.

Specifically, in the case of the present invention, the segmentation layer is composed of the porous Si layer or an ion implantation layer, so that the laser beam can be segmented very accurately and effectively.

That is, the laser peeling device has the same structure as the fluid high-pressure jet injection peeling device shown in FIG. 3B. The release part 303 of the one or more fine nozzles corresponds to the laser output part.

At this time, if necessary, the supporting substrate in the porous Si layer can be divided when the counter substrate end is cooled by using a cooled supporting jig through the UV tape.

Please note that the supporting substrate can be reused.

Step 9: Prepare the backlit solid-state image capturing device chip

Next, the resin protective film 40 made of epoxy resin or the like filled in the groove S can be completely cut from the end of the second semiconductor layer 22. Then, the low-porosity Si layer 21c and the rest of the second semiconductor layer 22 can be etched. If necessary, the insulating film 23 can also be etched to obtain a single-sided resin sealing type ultra-thin backlight solid-state image capturing device chip. This step will be explained in detail below.

First, as shown in FIG. 7B, a cross calibration mark M (which is formed in the second semiconductor layer 22 and exposed outside the surface of the second semiconductor layer 22 is filled in the groove S due to A resin protective film 40 made of epoxy resin or the like is used as a reference, and a complete cutting method is implemented along the exposed resin protective film 40. At this time, the cutting depth of the protective tape 50 is approximately between 20 and 30 μm. Fig. 7A is a cross-sectional view of the state after this complete cutting method.

In the complete dicing method, a dicing blade thinner than that used to form the notch S in the previous step shown in FIG. 6A can be used to cut the center of the exposed resin protection film, leaving the resin protection on the sides of the wafersmembrane40. Film 40.

Please note that when it is desired to enlarge the air gap and limit the acid resistance of the resin protective film, then a cutting blade thicker than that used to form the notch S in the previous step shown in FIG. 6A can be used to cut the The rough center of the resin protective film is exposed, leaving the resin protective film 40 in the side surfaces of the chips.

According to the material of the object, the following methods can be selectively used to cut and divide: blade cutting method, laser cutting method (carbon dioxide gas laser, YAG laser, excimer laser or similar laser), diamond Cutting machine, hard carbide cutting machine, ultrasonic cutting machine, or similar method.

Then, as shown in Figure 8A, you can use HF+H₂O₂+H₂O mixed liquid, HF+HNO₃+CH₃The COOH mixture or similar mixture is used to etch the low-porosity Si layer 21c and the rest of the second semiconductor layer 22. Please note that when a single layer of silicon oxide film is used to form the insulating film 23, if necessary, the silicon oxide film may be sequentially etched using a mixture of hydrofluoric acid and aluminum fluoride.

Alternatively, as shown in FIG. 8B, when a multilayer film composed of a silicon oxide film 23a, a silicon nitride film 23b, and a silicon oxide film 23c is used to form the insulating film 23, it can also be used if necessary The fluoric acid + aluminum fluoride mixture is used to sequentially etch the silicon oxide film 23a to form a multilayer film composed of a silicon oxide film 23c and a silicon nitride film 23b.

Please note that it is preferable to use a resin protective film 40 and an acid-resistant epoxy type that can prevent corrosion by a hydrofluoric acid type etching solution (used to etch the second semiconductor layer 22 made of the exposed single crystal Si). Protective tape 50 made of resin.

Step 10: Fix the transparent substrate

Next, as shown in FIG. 9A, the step difference between the resin protective film 40 on the side surfaces of the backlight solid-state image capturing element chip and the insulating film 23b on the back of the chip is used as an air gap, and a sealant 61 is used for bonding A transparent substrate 60. The transparent substrate 60 and the sealant 61 can seal the back of the chip in an airtight manner, and then the protective tape 50 can be peeled off to manufacture a single-sided resin-sealed ultra-thin chip with a hollow size Packaged backlight solid-state image capture device.

Please note that when there is no step difference between the resin protective film 40 and the insulating film 23b on the back of the chip and an air gap cannot be obtained, the air gap with a size equivalent to the expected air gap can be used, and the weight percentage is between 10 to 30% The sealant 61 of the partition in between is used to coat the entire peripheral part of the back of the wafer, and the transparent substrate 60 is sealed in an airtight manner.

In order to avoid impairing the image quality, a sealing glass that does not generate alpha rays, a moisture-proof transparent film, or the like can be used as the transparent substrate 60.

In addition, the sealant 61 may be any one of the following: a low-temperature heat-curing adhesive, a UV-curing adhesive, or a UV-curing and low-temperature heat-curing adhesive, but it must be a material that does not generate alpha rays and is highly moisture-proof.

Step 11: Install on the mounting plate

Next, as shown in FIG. 9B, silver paste, solder paste or other conductive paste 101 can be used to mount the chip-size hollow package manufactured in the previous step on a glass epoxy substrate, a flexible printed circuit board, Or a printed circuit board (PCB) 100 made of similar materials.

At this time, before being mounted on the printed circuit board 100, the surface of the chip is protected and fixed by a protective tape 50 made of a conductive adhesive with strong adhesion and no residual adhesive, and the bumps The electrodes are in a short-circuit state, so that electrostatic damage can be avoided, bumping connection failure can be avoided, and chip cracking, chipping, and chipping can be further avoided, thus improving yield, quality, and reliability.

As described above, the single-sided resin-sealed ultra-thin chip-size hollow package backlight solid-state image capturing device according to the specific embodiment of the present invention can be manufactured.

According to the method of manufacturing a back-light solid-state image capturing device according to the above embodiment, an SOI substrate composed of a supporting substrate 20 is formed by stacking a porous Si layer 21 on the supporting substrate 20 , A second semiconductor layer 22 composed of a single crystal Si layer, an insulating film 23, and a first semiconductor layer 12 composed of a single crystal Si layer; a notch S is formed in advance until above the expected divided portion In one layer, that is, up to the second semiconductor layer 22 and the porous Si layer 21; and a resin protective film 40 is used to seal the surface of the first semiconductor layer 12 and the inside of the groove S. In addition, the epoxy resin The relationship between the strain caused by the curing shrinkage stress of the resin protective film 40 made of or similar material, and the efficiency of dividing the support substrate 20 from the porous Si layer 21 in the lateral direction using water jets, air jets, or the like It will be very good, so yield, quality and productivity can be improved.

In addition, before being mounted on a printed circuit board 100, the surface of the solid-state image capturing device chip is protected and fixed by a protective tape 50 made of a conductive adhesive with strong adhesion and no residual adhesive. Therefore, it is possible to avoid electrostatic damage, avoid bulge connection failure, and further avoid chip cracking, chipping, and chipping, thereby improving yield, quality and reliability.

In addition, the insulating film 23 is inserted between the first semiconductor layer 12 and the second semiconductor layer 22 to form the CCD part or CMOS sensor unit (which includes the photoelectric conversion part, the charge transfer part) Parts, as well as the charge transport electrodes and the bump electrodes, etc.), the insulating film may not only be a single layer of silicon monoxide film, but may also be a nitrogen-type silicon film with a suitable thickness (which may use a silicon oxynitride film, Or a multilayer film composed of a silicon monoxide film 23a, a silicon nitride film 23b, and a silicon monoxide film 23c) can further improve the yield and quality.

In other words, it is possible to avoid contamination by halogen elements (sodium ions, etc.) originating from the end of the support substrate 20 during packaging or device processing.

In addition, the insulating film can also reduce or avoid deformation and strain in the first semiconductor layer 12 due to the oxidative expansion of the porous Si layer 21 during device processing.

In addition, when the second semiconductor layer 22 made of the single crystal Si layer and the porous Si layer 21 are etched away, it can be used as an etching stop area, so a high-precision sensor unit can be manufactured and obtained A high-sensitivity and high-precision solid-state image capturing device.

In addition, because it is a high-performance insulating film with very little leakage current, it can achieve excellent low-noise characteristics and can be further used as an anti-reflective film.

In addition, the resin protective film 40 made of epoxy resin or the like filled in the groove S is completely cut from the back, so as to obtain the remaining surface through the side of the chip and the back of the chip. The air gap formed by the height of the resin protective film 40 is a chip-size hollow package sealed by a transparent substrate 60 (for example, sealing glass), and an ultra-thin single-sided resin-sealed chip-size hollow package backlight solid-state image capturing device can be obtained.

Second specific embodiment

Among the various novel ultra-thin SOI substrate manufacturing methods, the method explained in this specific embodiment is to use the dual ion implantation layer division method (for example, this method precedes the implantation of hydrogen atoms in the seed substrate to form a The first ion implantation layer is used to divide a seed substrate, and hydrogen is implanted in the supporting substrate to form a second ion implantation layer to divide the supporting substrate). Backlight of a single-sided resin-sealed ultra-thin chip size hollow package Manufacturing method and manufacturing device of solid-state image capturing device.

Step 1: Form hydrogen ion implantation layer

As shown in FIG. 10A, a seed substrate 10 (with a resistivity of 0.01 to 0.02 Ωcm) made of p-type Si single crystal, which is 8 inches in diameter and 800 μm thick, is implanted by hydrogen ions to form a Ion implantation layer 13. The depth of the ion implantation layer 13 from the seed substrate 10 must consider the thickness of the first semiconductor layer 12 (which forms the solid-state image capturing element from the surface of the seed substrate 10). For example, it can be 500 KeV power, 5×10¹⁶To 1×10¹⁷/cm²The dose of is about 5 μm deep to implant the hydrogen ions. Please note that in addition to hydrogen, the implanted ions may also be nitrogen, helium, or other diluent gases.

Step 2: Form the insulating film

A support substrate 20 (resistivity of 0.01 to 0.02 Ωcm) made of p-type Si single crystal can be formed on a support substrate 20 (with a resistivity of 0.01 to 0.02 Ωcm) made of silicon oxide or similar materials with a thickness of about Insulating film 23 between 200 and 300 nm.

Please note that the insulating film 23 may be the same silicon oxide film single layer as in the first embodiment as shown in FIG. 10B; it may also be composed of a silicon oxide film 23a and a silicon nitride film 23b as shown in FIG. 10C. , And a multilayer film composed of a silicon oxide film 23c, which can be obtained by forming a silicon nitride film on the support substrate 20 by low-pressure CVD and thermally oxidizing it. For example, in this case, the thickness of the silicon oxide film 23a is set to about 200 nm, the thickness of the silicon nitride film is set to about 50 nm, and the thickness of the silicon oxide film 23c is set to Set to about 200 nm.

The advantages of particularly producing a silicon nitride film with a suitable thickness in this way are the same as those explained in the first embodiment.

Step 3: Soldering

Then, in the same manner as in the first embodiment, the surface of the insulating film 23 of the support substrate 20 and the surface of the seed substrate 10 can be cleaned, and then the insulating film 23 end of the support substrate 20 and the surface of the seed substrate 10 can be cleaned at room temperature. The end of the first semiconductor layer 12 of the seed substrate 10 allows the substrates to contact each other, and is soldered by van der Waals force. Then heat treatment can be carried out to promote covalent linkage, thereby enhancing the welding effect. 11A is a cross-sectional view of the state after the soldering when the insulating film 23 is a single layer of silicon oxide film; FIG. 11B is a multilayer film (silicon monoxide film 23a, a nitride In the case of the silicon film 23b and the silicon monoxide film 23c), a cross-sectional view of the state after soldering.

At this time, it must be confirmed whether any dust or dirt is deposited on the surfaces of the two substrates 10 and 20. If there is any foreign matter, it must be peeled off and washed away.

In addition, preferably, the heat treatment can be performed in nitrogen or a passive gas or a mixed gas of nitrogen and passive gas. For example, the heat treatment temperature can be set to 400°C and the treatment can be performed for about 30 minutes to enhance the welding effect.

In addition, two stacked substrates can also be set in a low-pressure heat treatment furnace, and the two substrates can be fixed at a predetermined pressure (for example, 133 Pa or less) using an evacuation method, and enter the atmospheric pressure after a predetermined time When the force is applied, pressure is applied to make the two substrates close together, and then the two substrates can be heated in nitrogen or passive gas or a mixture of nitrogen and passive gas at high temperature to continue operation.

Step 4: Divide the seed substrate

Then, as shown in Figure 12, for example, heating at 500°C for 10 to 20 minutes or rapid heating and rapid cooling (heating with a halogen lamp at about 800°C for a few seconds, or with Xe flash lamp at about 1000°C for several seconds Milliseconds) for stripping annealing treatment, the ion implantation layer 13 will be strained due to the pressure effect of the hydrogen microbubbles existing in the ion implantation layer 13 and the crystal rearrangement effect. UV tape can be used 51 and 52 weld the backs of the substrates 10 and 20 to each other, and peel off the substrates by tension. Then, the result is UV cured, and the UV tapes 51 and 52 are peeled off.

Please note that the stripped seed crystal substrate can be reused. Please note that in the same way as above, it can also be divided from the ion implanted layer by laser.

Step 5: Hydrogen annealing

In the same manner as in the first embodiment, after stripping off the seed substrate 10, a hydrogen annealing process can be used to etch a part of the surface of the first semiconductor layer 12 made of single crystal Si to form a The first semiconductor layer 12 is made of a single crystal Si layer and has a desired thickness (for example, 5 μm) and flatness. The hydrogen annealing treatment will etch Si at an etch rate of 0.0013 nm/min at 1050°C and an etch rate of 0.0022 nm/min at 1100°C.

Step 6: Component shaping

Common techniques can be used to form a CCD, CMOS sensor, or other backlit solid-state image capturing sensor unit (which includes a photoelectric conversion part, a charge transfer part, and a plurality of charges) in the first semiconductor layer 12 Transmission electrode). After the heat treatment is performed at 500°C or higher, for example, high-concentration hydrogen ions can be implanted into a position in the insulating film 23 that is 8 to 10 μm deep from the surface of the first semiconductor layer 12 (that is, From the depth of 3 to 5 μm of the supporting substrate 20), then an annealing treatment for peeling can be performed to cause strain. Then, aluminum interconnection lines and a plurality of bump electrodes connected to the lines can be formed. The CCD sensor and the CMOS sensor are the same as explained in the first embodiment.

Figure 13 is an example of a CCD situation. The n-type impurity phosphorus ion can be implanted into each of the first semiconductor layer 12 made of p-type single crystal Si (on which it can be separated into a plurality of isolation regions by a field oxide film or other element isolation insulating film 31) Among the element formation regions, an embedded transmission channel region 12a is formed. The ions can be activated at 750°C for 30 minutes. Please note that in addition, p-type impurities can also be introduced to form a channel stop region.

Then, a CVD method or a similar method can be used to form a gate insulating film 32 made of silicon oxide and a transfer electrode 33 made of polysilicon on the implanted transmission channel region 12a to form a Interlayer insulating film 34 made of silicon oxide. Please note that the transmission register of the CCD is constructed by the implanted transmission channel area 12a and the transmission electrode 33.

For example, after a heat treatment step above 500°C, a high concentration of hydrogen ions can be implanted into a depth of 8 to 10 μm from the surface to form an ion implantation layer 24, and then the peeling can be performed Use annealing treatment to cause strain. Please note that in addition to hydrogen, the ion implantation is also performed using nitrogen, helium, or other diluent gases.

When setting the depth of the ion implantation layer 24 from the soldering interface between the support substrate 20 and the insulating film 23, the thickness of the second semiconductor layer 22 to be formed must be considered. For example, it can be 1000 KeV power, 5×10¹⁶To 1×10¹⁷/cm²The dosage is about 8 to 10 μm deep to implant the hydrogen ions.

For the annealing treatment for stripping purposes, heat treatment can be performed at 500°C for 10 to 20 minutes in the same manner as above, or rapid heating and rapid cooling methods (heating with a halogen lamp at about 800°C for a few seconds, or The Xe flash lamp is heated at about 1000°C for several milliseconds). In this way, strain is generated in the ion implantation layer 24 due to the pressure effect in the hydrogen microbubbles existing in the ion implantation layer 24 and the crystal rearrangement effect.

At this time, there are a total of the first semiconductor layer 12 made of a single crystal Si layer, a silicon oxide film, a silicon nitride film, a polysilicon film, and other element forming films. The ion implantation layer 24 is formed under the insulating film 23, can penetrate it, and will cause strain by heat treatment.

At the same time, the annealing process for stripping uses the remaining implanted ions in the first semiconductor layer 12 made of a single crystal Si layer, silicon oxide film, silicon nitride film, polysilicon film, and other element formation films. The activation effect of, can reduce the crystal defects in the first semiconductor layer and is expected to improve the interface state between the first semiconductor layer and the film formed by each element.

Then, a contact hole can be formed in a part of the interlayer insulating film 34, and an electrode external terminal 35 made of aluminum or aluminum-silicon alloy can be formed near the chip or inside and near the chip. The transmission electrode 33 is electrically contacted, and a protruding raised electrode 36 to be connected to the external terminal 35 of the electrode can be formed.

The bump may be any bump mainly formed by electroplating or a terminal bump composed of Au lines, but in the latter case, great care must be taken so as not to damage the first due to the sudden shock of the line welding. A semiconductor layer 12 and a base second semiconductor layer 22. Please note that the height can be freely selected in the range of 10 to 100 μm.

Step 7: Form grooves and protective film

Next, as shown in FIG. 14A, in the same manner as in the first embodiment, a scribe line can be cut along a predetermined granular dividing boundary line, from the end of the first semiconductor layer 12 to at least The ion implantation layer 24 forms a groove S, and then the groove S and the surface of the first semiconductor layer 12 can be sealed with epoxy resin by a transfer molding process, a spin coating process, or a similar process. An optical polishing method, a chemical mechanical polishing method (CMP), or other polishing methods can be implemented on one of the surfaces to form a resin protective film 40 so that the bump electrode 36 is exposed. If necessary, a thin layer of Au can be plated on the surface of the exposed bump electrode 36.

Step 8: Divide the support substrate

Next, as shown in FIG. 14B, a protective tape 50 made of UV tape or the like is welded to the end of the resin protective film 40, and the UV tape 53 is welded to the end of the support substrate 20, and tension is used from the end The support substrate 20 is peeled off at the ion implantation layer 24. For the protective tape 50 and the UV tape 53, a conductive type UV curing adhesive that is transparent and has no residual adhesive is suitable to avoid electrostatic damage.

At this time, the resin protective film 40 can be used to fill the groove S reaching the ion implantation layer 24. Due to the curing shrinkage stress of the resin protective film 40 made of epoxy resin or similar materials, strain may also occur. Therefore, due to the strain of the ion implantation layer 24, the efficiency of peeling by the tension of the support substrate 20 becomes better. According to this, it is possible to reduce the mechanical shock caused to the components already formed in the first semiconductor layer 12.

Please note that the supporting substrate can be reused. Please note that in the same way as above, it can also be divided from the ion implanted layer by laser.

Step 9: Manufacture the backlit solid-state image capture device chip

In this step, the resin protective film 40 made of epoxy resin filled in the groove S can be completely cut from the end of the second semiconductor layer 22, and then the remaining ion implantation layer and the The second semiconductor layer 22, if necessary, can also etch the insulating film 23, and irradiate UV light for curing to obtain a single-sided resin-sealed ultra-thin backlit solid-state image capturing device chip.

This step is the same as step 9 of the first specific embodiment. Taking a cross calibration mark (which is filled in the groove S and exposed outside the surface of the second semiconductor layer 22 and made of a resin protective film 40 made of epoxy resin) as a reference, along The exposed resin protective film 40 is subjected to a complete cutting method.

In the complete dicing method, a dicing blade thinner than that used to form the notch S in the previous step shown in FIG. 14A can be used to cut the center of the exposed resin protective film 40 to leave the side surfaces of the wafers The resin protective film 40.

As explained in the first specific embodiment, the second semiconductor layer 22 can be removed using a hydrofluoric acid type etching solution after the complete dicing method. Therefore, it is preferable to use an epoxy resin The resin protective film 40 and the acid-resistant protective tape 50 that can withstand the erosion of the hydrofluoric acid type etching solution.

Please note that when it is desired to enlarge the air gap and limit the acid resistance of the resin protective film, then a cutting blade thicker than that used to form the notch S in the previous step shown in FIG. 14A can be used to cut the The rough center of the resin protective film is exposed, leaving the resin protective film 40 in the side surfaces of the chips.

After implementing the step of pasting the transparent substrate (step 10) and the step of mounting on the mounting board (step 11) explained in the first specific embodiment, a single-sided resin-sealed chip size hollow package as shown in FIG. 9B can be produced. Thin-type backlight solid-state image capture device.

Please note that when there is no air gap in the step difference between the resin protective film 40 and the insulating film 23b on the back of the chip, the air gap with a size equivalent to the expected air gap and a weight percentage of 10 to 30% can be used. The sealant 61 of the intermediate partition coats the entire peripheral portion of the back of the wafer, and the transparent substrate 60 is sealed in an airtight manner.

According to the method of manufacturing a backlight solid-state image capturing device according to this embodiment, an SOI substrate composed of a supporting substrate 20 is formed by stacking an ion implantation layer 24 on the supporting substrate 20, A second semiconductor layer 22 made of a single crystal Si layer, an insulating film 23, and a first semiconductor layer 12 made of a single crystal Si layer; an annealing treatment for lift-off is performed, and then the expectation A notch S is formed in the layer above the divided portion, that is, from the first semiconductor layer 12 to the ion implantation layer 24; and a resin protective film 40 is used to seal the surface of the first semiconductor layer 12 and the The inside of the groove S is also strained due to the curing shrinkage stress of the resin protective film 40 made of epoxy resin or similar materials. Therefore, the strain of the ion implantation layer 24 is used to change the tension of the substrate 20. The efficiency of segmentation will be excellent, so yield, quality and productivity can be improved.

In addition, in the same manner as in the first embodiment, because before being mounted on a printed circuit board 100, the surface of the solid-state image capturing device chip is protected and protected by a strong adhesive force and no residual adhesive. The protective tape 50 made of conductive adhesive is fixed, so that electrostatic damage can be avoided, bumping connection failure can be avoided, and chip cracking, chipping, and chipping can be further avoided, thereby improving yield and quality.

In addition, the insulating film 23 is inserted between the first semiconductor layer 12 and the second semiconductor layer 22 to form the CCD part or CMOS sensor unit (which includes the photoelectric conversion part, the charge transfer part) Parts, as well as the charge transport electrodes and the bump electrodes, etc.), the insulating film may not only be a single layer of silicon monoxide film, but may also be a nitrogen-type silicon film with a suitable thickness (which may use a silicon oxynitride film, Or a multilayer film composed of a silicon monoxide film 23a, a silicon nitride film 23b, and a silicon monoxide film 23c). Based on the same reason as the first embodiment, the yield and quality can be further improved.

In addition, the resin protective film 40 made of epoxy resin or the like filled in the groove S is completely cut from the back, so as to obtain a portion that passes through the side of the chip and the remaining on the back of the chip. The air gap formed by the height of the resin protective film 40 is a chip-size hollow package sealed by a transparent substrate 50 (for example, sealing glass), and an ultra-thin single-sided resin-sealed chip-size hollow package backlight solid-state image capturing device can be obtained.

Third specific embodiment

Among the various novel ultra-thin SOI substrate manufacturing methods, this specific embodiment will explain the use of the porous layer/ion implanted layer division method (which combines the above-mentioned porous layer division method and ion implanted layer division method, that is, , The method of dividing a seed substrate by implanting hydrogen atoms into the seed substrate to form an ion implantation layer and the method of dividing the supporting substrate by the porous Si layer formed on the supporting substrate). Surface resin-sealed ultra-thin chip size hollow package manufacturing method and manufacturing device for backlight solid-state image capturing elements.

Step 1: Form hydrogen ion implantation layer

First, in the same manner as in the second embodiment, as shown in FIG. 15A, a seed substrate 10 ( The resistivity is 0.01 to 0.02 Ωcm) to form an ion implantation layer 13. Please note that in addition to hydrogen, the implanted ions may also be nitrogen, helium, or other diluent gases. The depth of the ion implantation layer 13 from the seed substrate 10 must consider the thickness of the first semiconductor layer 12 (which forms the solid-state image capturing element from the surface of the seed substrate 10). For example, it can be 500 KeV power, 5×10¹⁶To 1×10₁₇/cm₂The dosage is about 5 to 6 μm deep to implant the hydrogen ions.

Step 2: Form the porous layer

In the same way as the steps shown in Figures 1B and 2B of the first embodiment, a seed substrate (with a resistivity of 0.01) made of a p-type Si single crystal with a diameter of 8 inches and a thickness of 800 μm To 0.02Ωcm), a porous Si layer was formed by the anode conversion method and an insulating film was formed.

In other words, as shown in FIG. 15B, a porous Si layer 21 may be formed on the support substrate 20, which includes a low-porosity Si layer 21a with a thickness of about 10 μm and a thickness of about 2 μm. The high-porosity high-porosity Si layer 21b, and a low-porosity Si layer 21c with a thickness of about 10 μm.

Then, pre-baking can be performed in a CVD epitaxial growth device in a hydrogen environment at about 1000 to 1100° C. to seal the holes in the surface of the porous Si layer 21c to flatten the surface.

Then the temperature can be lowered to 1020°C, and silane gas, di-silica boron gas, or similar gas can be used as the raw material gas to implement the CVD epitaxial growth method to form a second layer made of single crystal Si The semiconductor layer 22 has a thickness of about 5 to 10 μm.

Then, a silicon nitride film is formed on the support substrate 20 by low-pressure CVD, and then it can be thermally oxidized to form a multilayer film (which is composed of a silicon oxide film, a silicon nitride film, and an oxide film). The insulating film 23 is composed of a silicon film). For example, in this case, the thickness of the silicon oxide film is set to about 200 nm, the thickness of the silicon nitride film is set to about 50 nm, and the thickness of the silicon oxide film is set to About 200 nm.

The advantages of particularly producing a silicon nitride film with a suitable thickness in this way are the same as those explained in the first embodiment.

Please note that in the same manner as in the first embodiment, the insulating film 23 may also be a single layer of silicon oxide film or silicon nitride film.

Step 3: Soldering

Next, as shown in FIG. 16, in the same manner as in the first embodiment, the surface of the insulating film 23 of the support substrate 20 and the surface of the seed substrate 10 can be cleaned, and then the support substrate 20 can be removed from the support substrate 20 at room temperature. The end of the insulating film 23 and the end of the first semiconductor layer 12 of the seed substrate allow the two substrates to contact each other, and are soldered by van der Waals force. Heat treatment can then be carried out to promote covalent linkage to enhance the welding effect.

At this time, it must be confirmed whether any dust or dirt appears on the surfaces of the two substrates 10 and 20. If there is any foreign matter, it must be stripped and washed away.

In addition, preferably, the heat treatment can be performed in nitrogen or a passive gas or a mixed gas of nitrogen and passive gas. For example, the heat treatment temperature can be set to 400°C and the treatment can be performed for about 30 minutes to enhance the welding effect.

In addition, two stacked substrates can also be set in a low-pressure heat treatment furnace, and the two substrates can be fixed at a predetermined pressure (for example, 133 Pa or less) using an evacuation method, and enter the atmospheric pressure after a predetermined time When the force is applied, pressure is applied to make the two substrates close together, and then the two substrates can be heated in nitrogen or passive gas or a mixture of nitrogen and passive gas at high temperature to continue operation.

Step 4: Divide the seed substrate

Next, as shown in FIG. 17, in the same manner as in the second embodiment, heating at 500°C for 10 to 20 minutes or rapid heating and rapid cooling (heating with a halogen lamp at about 800°C for a few seconds, or Xe flash heating at about 1000 °C several milli seconds) to release embodiment uses an annealing process, as will be present in the hydrogen micro-bubbles 13 in the ion implantation layer and the crystalline rearrangement pressure acting on the ion implanted layer When strain occurs in 13, the backs of the substrates 10 and 20 can be welded to each other with UV tapes 51 and 52, and the substrates can be peeled off by tension. At this time, in order to avoid separation from the porous Si layer 21, it is important to optimize the porosity of the porous Si layer 21. Then, the result is UV cured, and the UV tapes 51 and 52 are peeled off. Please note that the stripped seed crystal substrate can be reused. Please note that in the same way as above, it can also be divided from the ion implanted layer by laser.

Step 5: Hydrogen annealing

In the same manner as in the first embodiment, after stripping off the seed substrate 10, a hydrogen annealing process can be used to etch a part of the surface of the first semiconductor layer 12 made of single crystal Si to form a The first semiconductor layer 12 is made of a single crystal Si layer and has a desired thickness (for example, 5 μm) and flatness. The hydrogen annealing treatment will etch Si at an etch rate of 0.0013 nm/min at 1050°C and an etch rate of 0.0022 nm/min at 1100°C.

Carry out the device forming step explained in the first specific embodiment (step 6), forming grooves and resin protective film (step 7), dividing the support substrate (step 8), and manufacturing the backlight solid-state image pickup device wafer step (step 9) After the step of pasting the transparent substrate (step 10) and the step of mounting on the mounting board (step 11), an ultra-thin backlit solid-state image capture device with a single-sided resin-sealed chip size hollow package as shown in FIG. 9B can be produced .

According to the method of manufacturing a backlight solid-state image capturing device of this embodiment, the seed substrate 10 on which the first semiconductor layer 12 and the ion implantation layer 13 are formed and the insulating film are formed thereon 23. The second semiconductor layer 22 and the support substrate 20 of the porous Si layer 21 are welded to each other, and the ion implanted layer 13 is used as an interface to peel off the seed substrate 10 by tightening to form An SOI substrate composed of a supporting substrate 20, on which the porous Si layer 21, the second semiconductor layer 22, the insulating film 23, and the first semiconductor layer 12 are stacked; Groove S into the layer above the expected divided portion, that is, the second semiconductor layer 22 and the porous Si layer 21 made of the single crystal Si layer; and the resin protective film 40 is used to seal the second semiconductor layer 22 and the porous Si layer 21; The relationship between the surface of a semiconductor layer 12 and the inside of the groove S due to the strain caused by the curing shrinkage stress of the resin protective film 40 made of epoxy resin or the like, using water jets and air jets from the lateral direction The efficiency of separating the support substrate 20 from the porous Si layer 21 by a jet or similar jet will be excellent, so that the yield, quality and productivity can be improved.

In addition to this, the same effects as explained in the first and second specific embodiments can also be obtained.

Fourth specific embodiment

The examples explained in the first to third embodiments are the air formed through the side of the chip (as shown in FIG. 9B) and the remaining resin protective film 40 made of epoxy resin on the back of the chip. The gap is sealed with a transparent substrate 60 (such as sealing glass) to form a single-sided resin-sealed ultra-thin chip-size hollow package backlight solid-state image capture device. The example that will be explained now is by fixing a color filter To replace the transparent substrate, to form a single-sided resin-sealed ultra-thin chip size hollow package color backlight solid-state image capture device.

First, in the same manner as in the first to third embodiments, the steps from step 1 to step 8 can be followed to peel off the support substrate 20, as shown in FIG. 6B or FIG. 14B. Please note that in the formation of the resin protective film in step 7, a resin protective film 40 made of a transparent epoxy resin or the like is formed. Then, before performing the complete cutting method, the remaining parts of the porous Si layer 21 and the second semiconductor layer 22 can be etched, and the remaining parts of the ion implantation layer 24 and the second semiconductor layer 22 can be etched, and if necessary, also The insulating film 23 can be etched. In addition, if necessary, an etching method or the like can also be used to remove the protruding part of the resin protective film 40 produced by etching the second semiconductor layer 22 and the like.

Then, for the use of a CCD sensor unit or a CMOS sensor unit of a solid-state image capturing element, a transparent adhesive 71 can be used to bond a color filter substrate 70 (in which a color filter substrate 70 is formed with corresponding red, edge, and blue The color filter layer 70a) made of the resin film of the pigment is welded to the end of the insulating film 23. For example, the color filter substrate 70 is made of a glass substrate, a transparent resin substrate, and the like.

18A is a cross-sectional view of the state after the color filter substrate 70 is pasted in the case where the insulating film 23 is a single layer; and FIG. 18B is in the case where the insulating film 23 is a multilayer film, A cross-sectional view of the state after the color filter substrate 70 is pasted. Please note that the situation shown in FIG. 18 is that the insulating film is composed of a double layer of a silicon nitride film 23b and a silicon oxide film 23a, and the silicon oxide film in the previous step is removed.

At this time, the alignment marks on the wafer surface and the alignment marks on the color filter substrate 70 can be arranged through an integrated front/rear microscope through the resin protective film 40 made of a transparent epoxy resin-like material The transparent adhesive 71 is then cured at the correct position for bonding the substrates.

The transparent adhesive 71 is preferably a UV curing and thermal curing adhesive. That is, it is preferable to use UV curing treatment to temporarily fix the positions of the substrates immediately after the position arrangement is performed, and then perform thermal curing treatment.

In addition, we hope that the protective tape 50 is a transparent conductive UV-curable adhesive that has no residual adhesive and can prevent electrostatic cracking.

Next, as shown in FIG. 19A, the color filter substrate 70 and the resin protective film 40 made of epoxy resin filled in the groove S can be completely cut from the end of the color filter substrate 70, Then, UV light can be irradiated to cure the result, and the protective tape 50 is peeled off, so as to obtain a color backlit solid-state image capturing device chip.

This step is the same as step 9 of the first specific embodiment. The cross calibration mark (which is composed of a resin protective film 40 made of epoxy resin filled in the groove S) can be used as a reference to implement a complete cutting method along the resin protective film 40.

In the complete dicing method, a dicing blade thinner than that used to form the notch S in the previous step can also be used to cut the center of the exposed resin protection film 40, leaving the resin protection film on the sides of the wafers 40, in an attempt to improve moisture resistance. Please note that when the component has no reliability problem, it is not necessary to leave the resin protective film 40 on the side of the chip.

Finally, as shown in FIG. 19B, silver paste, solder paste or other conductive paste 101 can be used to mount the color backlit solid-state image capture device chip formed in the previous step on a glass epoxy substrate, flexible printing A printed circuit board (PCB) 100 made of a circuit board or the like.

At this time, before being mounted on the printed circuit board 100, the surface of the chip is protected and fixed by a protective tape 50 composed of a conductive adhesive with strong adhesion and no residual adhesive, and the raised electrodes It is in a short-circuit state, so it can avoid the occurrence of electrostatic damage and avoid the occurrence of bump connection failure, thus improving the yield and quality.

According to the above-mentioned backlight solid-state image capturing device of this embodiment, the support substrate 20 is stripped off by the same method as the first to third embodiments, and then the porous Si layer 21 is etched or ion implanted The rest of the layer 24 and the second semiconductor layer 22 are used to obtain the single-sided packaged backlight solid-state image capturing device; through the transparent resin protective film 40, an integrated front/rear microscope is used to monitor The alignment mark on the surface of the wafer and the alignment mark on the color filter substrate 70 are used to adjust the position relative to the resin protective film, and the transparent adhesive 71 is used to stick the color filter substrate 70; The method divides the color filter substrate 70 into individual chips from its back port; then peels off the protective tape 50 to obtain an ultra-thin chip size single-sided resin-sealed color backlight solid-state image capturing device. In addition, the same effects as explained in the first embodiment to the third embodiment can also be obtained.

Fifth specific embodiment

The examples explained in the first to third embodiments are the air formed through the side surface of the chip (as shown in FIG. 9B) and the remaining resin protective film 40 made of epoxy resin on the back of the chip. The gap is sealed with a transparent substrate 60 (such as sealing glass) to form the chip-size hollow package. However, the example explained in this embodiment is to further form an on-chip color filter (OCCF) on the insulating film 23 ) And an on-chip lens (OCL), and then a single-sided resin-sealed ultra-thin chip-size hollow package color backlight solid-state image capturing device to be sealed with the transparent substrate can be formed.

First, in the same manner as in the first to third embodiments, the steps from step 1 to step 8 can be followed to peel off the support substrate 20, as shown in FIG. 6B or FIG. 14B. Then, before performing the complete cutting method, the remaining parts of the porous Si layer 21 and the second semiconductor layer 22 can be etched away, and the remaining parts of the ion implantation layer 24 and the second semiconductor layer 22 can be etched away. It is necessary At this time, the insulating film 23 can also be etched away. In addition, if necessary, an etching method can also be used to remove the protruding portion of the resin protective film 40 produced by etching the second semiconductor layer 22. Please note that in the formation of the resin protective film in step 7, a resin protective film 40 made of a transparent epoxy resin or the like is formed. In addition, in the following steps, a glass substrate 55 or the like can be soldered to the surface of the resin protective film 40 with a double-sided soldering protective tape 54 for forming color filters on the chip and on the chip. The support substrate for the lens. FIG. 20A is a cross-sectional view of the state after this step. Regarding the double-sided solder protection tape 54, it is advisable to manufacture it with a transparent conductive UV curing adhesive and tape to avoid electrostatic damage and without residual adhesive.

Next, as shown in FIG. 20B, for example, a lithographic etching method can be used to form a color resin (which is photosensitive and contains pigments dispersed in the color filter pattern) for use on the insulating film 23 An on-chip color filter 81 is formed thereon. Specifically, it is formed by the following method: coating a colored resin (which is photosensitive and containing pigments dispersed in it); baking it on a hot plate at a temperature between 90°C and 100°C 90 seconds to 120 seconds; then expose it with an electron beam stepper or similar device; use TMAH (tetramethyldisilane) aqueous solution or other alkali metal developing solutions to develop it; then use a temperature of 100°C It is cured by a hot plate between 120°C and 120°C for 90 seconds to 120 seconds. These steps can be repeated as many times as necessary.

For example, in the case of a primary color type image sensor, these steps can be repeated three times for red, green, and blue; in the case of a complementary color type image sensor, these steps can be performed for cyan, magenta, yellow, Green is repeated four times.

Then, as shown in FIG. 20B, a lens material of a light-transmitting resin (for example, a negative photosensitive resin) can be used to form the on-chip color filter 81, and a reflow method is used to apply a reflow method to each of the CCD sensor or the CMOS sensor. A photoresist pattern having a lens shape with a predetermined curvature is formed on the lens material of each pixel, and the lens material is etched using the photoresist pattern as a mask to form an on-wafer microlens 82 with a predetermined curvature.

When forming the on-chip color filter 81 and the on-chip microlens 82, the chip can be confirmed through the glass substrate 55, the double-sided soldering protective tape 54, and the resin protective film 40 made of epoxy resin A calibration mark on the surface, and using the calibration mark as a reference, the on-chip color filter 81 and the on-chip microlens 82 are formed on the insulating film 23 corresponding to the pixels in a plurality of CCD or CMOS sensor units.

Next, as shown in FIG. 21A, the resin protective film 40 made of transparent epoxy resin filled in the groove S is completely cut from the end of the microlens 82 on the wafer.

In this step, the cross calibration mark (which is composed of a resin protective film 40 made of epoxy resin filled in the groove S) can be used as a reference to move along the resin protective film 40 Implement the complete cut method.

In the complete dicing method, a dicing blade thinner than that used to form the notch S in the previous step can also be used to cut the approximate center of the exposed resin protection film 40, leaving the resin protection in the side surfaces of the wafers. Membrane 40 in an attempt to improve moisture resistance. Please note that when the component has no reliability problem, it is not necessary to leave the resin protective film 40 on the side of the chip.

Then, as shown in FIG. 21B, the single-sided resin-sealed backlight solid-state image capturing element chip can be mounted on a transparent substrate 60 made of sealing glass or a moisture-proof transparent film or the like by using a sealant 61. There is a predetermined air gap between them. Then, UV light can be irradiated, and the double-sided soldering protective tape 54 and the glass substrate 55 can be peeled off, thereby manufacturing the single-sided resin-sealed ultra-thin wafer-size hollow package.

The sealant 61 used in this step may also be any of the following: low temperature heat curing adhesive, UV curing adhesive, or UV curing and low temperature heat curing adhesive, but it must be a material with high moisture resistance .

In addition, in order to obtain a predetermined air gap between the transparent substrate 60 and the microlens 82 on the wafer, it is preferable to mix the sealant 61 into a partition having the same size as the air gap. The partitions may be any of the following: glass, metal, plastic, or a mixture thereof. The mixing ratio of the partitions and the sealant is preferably set at a level that does not impair the moisture-proof ability, for example, the weight percentage is about 10 to 30%.

Please note that the transparent substrate 60, the sealant 61, the spacers, the on-chip microlens 82, the on-chip color filter 81, the resin protective film 40, the raised electrode 36, and the The other materials of the solid-state image capturing element must be high-purity materials that do not generate alpha rays to avoid impairing image quality.

Finally, silver paste, solder paste or other conductive paste 101 can be used to mount the color backlit solid-state image capture device chip formed in the previous step on a glass epoxy substrate, flexible printed circuit board, etc. Printed circuit board (PCB) 100 above.

At this time, before being mounted on the printed circuit board 100, the surface of the chip is protected and fixed by a double-sided adhesive protective tape 54 composed of a conductive adhesive with strong adhesion and no residual adhesive, and the The raised electrode is in a short-circuit state, so electrostatic damage and connection failure of the raised connection can be avoided, thereby improving the yield and quality.

According to the manufacturing method of the backlight solid-state image capturing device of this embodiment, the support substrate 20 is stripped off by the same method as the first to third embodiments, and then the porous Si layer 21 or ion is etched away. The rest of the implantation layer 24 and the second semiconductor layer 22, through the glass substrate 55, double-sided adhesive protective tape 54 and the resin protective film 40 made of epoxy resin to confirm the alignment marks on the surface of the chip , And using the calibration mark as a reference, an on-chip color filter 81 and an on-chip microlens 82 are formed on the insulating film 23 of a plurality of CCD or CMOS sensor units, and then the transparent is pasted with a predetermined air gap With the substrate 60, an ultra-thin single-sided resin-sealed chip-size hollow package color backlight solid-state image capturing device can be obtained. In addition, the same effects as explained in the first embodiment to the third embodiment can also be obtained.

Sixth specific embodiment

The example to be explained in this embodiment is to use the single-sided resin-sealed ultra-thin chip size hollow package according to this embodiment of the manufacturing method and manufacturing device of a backlight solid-state image capturing device to form a manufacturing method that can be as Japanese The technology disclosed in the Unexamined Patent Publication (Kokai) No. 10-209417 generally detects X-rays, γ-rays, discharge particles, or other high-energy rays. Backlit solid-state radiation detection element.

Step 1: Form porous Si layer

In the same manner as the steps shown in FIGS. 1 and 2 of the first embodiment, an anode conversion method can be used to form a plurality of porous Si layers on the seed substrate and the support substrate and form an insulating film.

In other words, as shown in FIG. 22A, a porous Si layer 11 can be formed on the seed substrate 10 by an anode conversion method, which is constructed as follows: a low-porosity, low-porosity layer with a thickness of about 10 μm The flexible Si layer 11a, a high-porosity Si layer 11b with a thickness of about 20 μm and a high porosity 11b, and a low-porosity Si layer 11c with a thickness of about 5 μm and a low porosity.

In addition, as shown in FIG. 22B, a porous Si layer 21 can be formed on the support substrate 20, which is constructed as follows: a low-porosity Si layer 21a with a thickness of about 10 μm, A high porosity Si layer 21b with a thickness of about 2 μm and a low porosity Si layer 21c with a thickness of about 10 μm.

Step 2: Formation of semiconductor layer and insulating film

In this step, a plurality of epitaxially grown single crystal Si layers can be formed on the two substrates of the seed substrate 10 and the support substrate 20, and a silicon oxide film or a silicon oxide film can be formed on at least one of the two substrates. A multilayer film (which includes a silicon oxide film, a silicon nitride film, and a silicon oxide film) is used as the insulating film.

In other words, as shown in FIG. 22A, both the seed substrate 10 and the support substrate 20 can be pre-baked in a CVD epitaxial growth device in a hydrogen environment at about 1000 to 1100°C to seal the two substrates. The holes in the surfaces of the porous Si layers 11 and 21 are used to level the surfaces.

After that, the temperature can be increased to 1020°C, silane gas or di-silica boron gas can be used as the raw material gas to implement the CVD method, and the same procedure as in step 2 of the first embodiment can be followed for the seed substrate 10 Forming a p grown by epitaxial^-The first semiconductor layer 12 made of the type single crystal Si layer has a thickness of about 5 to 10 μm, and is used to form a CCD, a barrel device (BBD), or other charge transfer device (CTD).

Next, for example, an insulating film 23 made of silicon oxide can be formed on the seed substrate 10, with a thickness of about 200 to 300 nm.

Please note that in the same manner as in the first embodiment, the insulating film 23 may be a single layer of silicon oxide, or a multilayer film obtained by low-pressure CVD (which includes a silicon oxide film, a silicon nitride film). , And a silicon oxide film) for forming a silicon nitride film on the support substrate 20 and thermally oxidizing it. For example, in this case, the thickness of the silicon oxide film is set to about 200 nm, the thickness of the silicon nitride film is set to about 50 nm, and the thickness of the silicon oxide film is set to About 200 nm. The advantages of particularly producing a silicon nitride film with a suitable thickness in this way are the same as those explained in the first embodiment.

In addition, as shown in FIG. 22B, an epitaxially grown p⁺The second semiconductor layer 22a made of type Si single crystal has a thickness of about 2 to 5 μm, and a layer made of p^-The third semiconductor layer 22b made of type Si single crystal has a thickness of about 20 to 30 μm. In addition, phosphorus ions can be used as n-type impurities and implanted into the third semiconductor layer 22b by ion implantation or the like to form an n-type semiconductor region. This n-type semiconductor region, the p of the third semiconductor layer 22b^-Type region, and the p of the second semiconductor layer 22a⁺The type zone will constitute a photoelectric conversion element made of a PIN photodiode. In addition, boron ions can be used as p-type impurities and implanted into the third semiconductor layer 22b by ion implantation or similar methods to form a channel stop region.

Step 3: Soldering

Next, as shown in FIG. 23A, the surface of the insulating film 23 of the seed substrate 10 and the surface of the support substrate 20 can be cleaned, and then the end of the insulating film 23 of the seed substrate 10 and the support substrate 20 can be removed at room temperature. The end of the third semiconductor layer 22b allows the substrates to contact each other, and is soldered by van der Waals force. Then heat treatment can be carried out to promote covalent linkage, thereby enhancing the welding effect.

At this time, it must be confirmed whether any dust or dirt is deposited on the surfaces of the two substrates 10 and 20. If there is any foreign matter, it must be peeled off and washed away.

In addition, preferably, the heat treatment can be performed in nitrogen or a passive gas or a mixed gas of nitrogen and passive gas. For example, the heat treatment temperature can be set to 400°C and the treatment can be performed for about 30 minutes to enhance the welding effect.

In addition, two stacked substrates can also be set in a low-pressure heat treatment furnace, and the two substrates can be fixed at a predetermined pressure (for example, 133 Pa or less) using an evacuation method, and enter the atmospheric pressure after a predetermined time When the force is applied, pressure is applied to make the two substrates close together, and then the two substrates can be heated in nitrogen or passive gas or a mixture of nitrogen and passive gas at high temperature to continue operation.

Step 4: Divide the seed substrate

Next, as shown in FIG. 23B, an air jet, a water jet, or the like can be used to divide the seed substrate 10 from the porous Si layer 11b. At this time, by forming a highly porous Si layer 11b with a porosity and thickness greater than the porosity and thickness of the highly porous Si layer 21b, the seed substrate can be peeled off by the pressure of an air jet, a water jet, or a similar jet. 10.

At this time, in the same way as in the first embodiment, a jig with a guard ring blocking area guard wall can also be used, so that the peeling action of air jets, water jets, or similar jets will not act on the highly porous Si layer 21b. Above. The height of the blocking area of the guard ring and the height of the high-porosity Si layer 21b can be fine-tuned, and the height of the support substrate holder can be fine-tuned so that it does not feel the peeling effect of air jets, water jets or similar jets. Please note that the peeled seed substrate can be reused.

Please note that in the same way as above, it can also be divided from the porous Si layer by laser.

Step 5: Hydrogen annealing

Then, as shown in FIG. 24A, a hydrogen annealing process can be used to etch the entire low-porosity Si layer 11c and part of the surface of the first semiconductor layer 12 remaining after the stripping to form a desired thickness (for example, The first semiconductor layer 12 is made of single crystal Si with a thickness of about 5 μm) and flatness.

In the hydrogen annealing treatment, Si is etched at an etching rate of 0.0013 nm/min at 1050°C and an etching rate of 0.0022 nm/min at 1100°C.

Please note that HF, H can also be used in etching₂O₂With H₂Mixture of O or HF, HNO₃With CH₃The low-porosity Si layer 11c remaining after the stripping is carried out with a mixed solution composed of COOH, and then hydrogen annealing is used to etch the surface of the first semiconductor layer 12 made of single crystal Si.

Step 6: Component shaping

Next, using the well-known technique disclosed in Japanese Unexamined Patent Application (Kokai) No. 10-209417, the^-A CCD, BBD, or other CTD is formed on the first semiconductor layer 12 made of the type single crystal Si layer, and a plurality of raised electrodes connected to these devices.

In other words, as shown in FIG. 24B, n-type impurity ions can be implanted into the p^-In the first semiconductor layer 12 made of a type single crystal Si layer, an embedded transmission channel region 121 is used as an embedded channel CCD or CTD, and can be further formed by an insulating film 37 to form two layers Transmission electrodes 38 and 39 made of polysilicon. In addition, for example, after the transfer electrodes 38 and 39 are formed, part of the first semiconductor layer 12 and the insulating film 23 can be removed by etching or the like to form an opening C.

Please note that an n-type semiconductor region 201 and a p-type channel stop region 202 formed by ion implantation in the previous step shown in FIG. 22B can be formed on the third semiconductor layer 22b. This n-type semiconductor region, the p of the third semiconductor layer 22b^-Type region, and the p of the second semiconductor layer 22a⁺The type zone will constitute a photoelectric conversion element made of a PIN photodiode.

Please note that although not shown, a transmission gate or the like can be formed in the opening C to transmit the charge between the PIN photodiode and the embedded transmission channel region 121.

In the backlight solid-state radiation detection device disclosed in FIG. 24B, the PIN photodiode is used to extend a depletion layer deeply, which can improve the detection efficiency of high-energy rays. The PIN light diode converts the incident rays emitted from the back of the first semiconductor layer 12 (that is, the end of the third semiconductor layer 22b) into electric charges. The charge generated by the photoelectric conversion is transferred to the implanted transfer channel area 121 via a transfer gate not shown in the figure, and is further transferred to the level transfer CTD and output from the output gate.

In addition, the PIN is formed in the second semiconductor layer 22a and the third semiconductor layer 22b by forming the embedded transmission channel region 121 as the vertical transmission CTD and the transmission electrodes 38 and 39 in the first semiconductor layer 12 The photodiode obtains a multilayer structure, which can enlarge the substantial light receiving area of the photoelectric conversion element without comparing the transmission circuit and the photoelectric conversion element.

Step 7: Form grooves and protective film

Then, as shown in FIG. 25A, a scribe line can be cut along a predetermined granular dividing boundary line, passing through at least the second semiconductor layer composed of the single crystal Si from the end of the first semiconductor layer 12 The semiconductor layer 22a is formed with a notch S, which can then be sealed with an epoxy resin or other resin protective film 40. The surface of the resin protective film 40 can be polished by optical polishing method, chemical mechanical polishing method (CMP), etc., so that the protruding electrode 36 is exposed. If necessary, a thin layer of Au can be plated on the surface of the exposed raised electrode 36, and a UV tape or other protective tape 50 can be used to protect it. Please note that in this step, in order to later use the resin protective film 40 to form the air gap, it is preferable to form the notch S in the second semiconductor layer 22a so that it reaches the porous hole exactly. At a predetermined depth in the Si layer 21.

As far as the protective tape 50 is concerned, it is advisable to manufacture it with a transparent conductive UV curable adhesive and tape without residual adhesive to avoid electrostatic damage.

Step 8: Divide the support substrate

Next, as shown in FIG. 25B, an air jet, a water jet, or the like can be used to divide the support substrate 20 at the highly porous Si layer 21b. At this time, the resin protective film 40 can be used to fill the groove S reaching the porous Si layer 21. The strain caused by the curing shrinkage stress of the resin protective film 40 made of epoxy resin or the like is also added. Therefore, the efficiency of dividing the support substrate 20 by using a water jet or the like at the high porosity Si layer 21b from the lateral side becomes better. According to this, it is possible to reduce the mechanical shock caused to the elements formed in the first semiconductor layer 12, the second semiconductor layer 22a, and the third semiconductor layer 22b. Please note that the supporting substrate can be reused.

Please note that in the same way as described above, it can also be divided from the porous Si layer by laser.

The subsequent steps can implement the same steps as steps 9 to 11 explained in the first specific embodiment.

In other words, in the same manner as in step 9 of the first embodiment, the resin protective film 40 made of epoxy resin filled in the scribe line can be completely cut from the end of the second semiconductor layer 22 and etched away The remaining part of the high-porosity Si layer 21b and the low-porosity Si layer 21c can obtain a single-sided resin-sealed type backlight solid-state image capturing device chip.

Then, in the same manner as in step 10 of the first embodiment, the resin protective film 40 made of epoxy resin at the side of the back-light solid-state image capturing element chip and the second back of the chip are used. The step difference between the semiconductor layers 22a is used as an air gap, and a transparent substrate 60 made of sealing glass, moisture-proof transparent film, or similar materials is adhered to the single-sided resin sealing type backlight solid-state image capture using a sealant 61 In the device chip, and the protective tape 50 is peeled off, the chip size hollow package can be formed.

In addition, the chip-size hollow package prepared in the previous step is mounted on a printed circuit made of glass epoxy substrate, flexible printed circuit board, or similar materials by using silver paste, solder paste or other conductive paste 101 On the PCB 100, the backlit solid-state image capturing device shown in FIG. 26 can be produced.

As in this specific embodiment, the semiconductor layer 22 under the first semiconductor layer 12 is not removed through the insulating film 23 as in the first to third specific embodiments. On the contrary, using it as an element forming film can also form a The above-mentioned backlight radiation detection element. In this case, after the element is formed in the first semiconductor layer 12, a groove S reaching the porous Si layer 21 can be formed, and a resin protective film 40 can be formed to seal the surface of the first semiconductor layer 12 And the notch S, adding the strain caused by the curing shrinkage stress of the resin protective film 40 made of epoxy resin or the like, and dividing it from the porous Si layer 21 by a water jet or the like in the lateral direction The efficiency of the support substrate 20 will be improved, and thus the yield and productivity can be improved. In addition, the same effects as explained in the first embodiment to the third embodiment can also be obtained.

The present invention is not limited to the explanation part of the above specific embodiment.

For example, the structure of the CCD sensor unit or CMOS sensor unit of the backlight solid-state image capturing element is not particularly limited. BBD sensor unit etc. can also be used. In addition, the examples explained in these specific embodiments are all forming a notch to promote peeling from the porous Si layer or the ion implantation layer. However, the present invention is not limited to the porous Si layer or the ion implantation layer. Implantation layer. In the method of manufacturing the SOI substrate, a layer with the same function can also be used.

In addition, the insulating film 23 may be a silicon nitride film or a multilayer film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and may also be a silicon nitride film. A multilayer film composed of a silicon oxide film, a silicon oxide film, and a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, and can also be constructed using other insulating materials.

In addition, various changes can be made without departing from the scope of the spirit of the present invention.

Summarizing the effects of the present invention, according to one of the viewpoints of the present invention, by forming a base composed of a supporting substrate, a porous semiconductor peeling layer, a second single crystal semiconductor layer, and a supporting substrate can be stacked on the supporting substrate. Insulating layer, and a first single crystal semiconductor layer; forming a notch in advance to the layer above the expected divided portion, that is, the second single crystal semiconductor layer and the porous semiconductor peeling layer; and using a resin protective film to Sealing the surface of the first single crystal semiconductor layer and the inside of the groove, due to the relationship between the strain caused by the curing shrinkage stress of the resin protective film, the efficiency of using the porous semiconductor peeling layer as an interface to separate the support substrate will be extremely Good, so it can improve yield, quality and productivity. In addition, because the semiconductor chip (specifically, the solid-state image capturing element) can be fixed when the conductive protective tape without residual conductive adhesive is used to protect the surface of the resin protective film and the protruding connection electrode, the occurrence of Electrostatic damage avoids bumping connection failure, and can further avoid chip cracking, chipping, and chipping, thereby improving yield, quality, and reliability.

According to one aspect of the present invention, by forming a base composed of a supporting substrate, an ion implantation lift-off layer, a second single crystal semiconductor layer, an insulating layer, and a first layer can be stacked on the supporting substrate. A single crystal semiconductor layer; a notch is formed in the layer above the expected divided portion in advance, that is, a peeling layer from the first single crystal semiconductor layer and the ion implantation; and a resin protective film is used to seal the second The relationship between the surface of a single crystal semiconductor layer and the inside of the groove, due to the strain caused by the curing shrinkage stress of the resin protective film, the strain of the release layer is implanted with the ion, and the support substrate is stretched for separation The efficiency will be excellent, so the output, quality and productivity can be improved. In addition, because the semiconductor chip (specifically, the solid-state image capturing element) can be fixed when the conductive protective tape without residual conductive adhesive is used to protect the surface of the resin protective film and the protruding connection electrode, the occurrence of Electrostatic damage avoids bumping connection failure, and can further avoid chip cracking, chipping, and chipping, thereby improving yield, quality, and reliability.

According to another aspect of the present invention, by inserting an insulating layer between the first single crystal semiconductor layer and the second single crystal semiconductor layer, the insulating layer may not only be a silicon oxide film single layer, but may also have A silicon nitride film with a suitable thickness (such as a silicon oxynitride film, or a multilayer film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film) can further improve the yield and quality.

In other words, it is possible to avoid contamination by halogen elements (sodium ions, etc.) originating from the end of the supporting substrate during packaging or device processing.

In addition, it is possible to reduce or avoid deformation and strain in the first single crystal semiconductor layer used to prepare the device due to the oxidative expansion of the porous semiconductor peeling layer during device processing.

In addition, when the second single crystal semiconductor layer and the porous semiconductor peeling layer are etched away, the insulating layer can be used as an etching stop layer, so a high-precision sensor unit can be manufactured, and a high sensitivity and High-precision solid-state image capture device.

In addition, the insulating layer has extremely high performance, so there is very little leakage current, so it can provide excellent low-noise characteristics, and can be further used as an anti-reflective film.

In addition, the ultra-thin SOI substrate of the present invention can suppress the leakage current to a very low level, accelerate the LSI, and reduce the operating voltage, thereby reducing power consumption and cost.

In addition, in the method for manufacturing an ultra-thin backlight solid-state image capturing device according to other aspects of the present invention, after the step of dividing into individual solid-state image capturing devices, the second single crystal semiconductor layer is removed to form A resin protective film that protrudes from the surface of the insulating layer exactly corresponds to the thickness of the second single crystal semiconductor layer and surrounds the side protective wall of the solid-state image capturing element, and uses the protruding distance of the resin protective film as With an air gap, a transparent substrate is pasted into the solid-state image capturing element from the end of the insulating layer to obtain an ultra-thin chip-size hollow package backlight solid-state image capturing element.

In addition, in the method of manufacturing an ultra-thin backlight solid-state image capturing device according to the viewpoints of the present invention, after the step of peeling off the supporting substrate and before the step of dividing into individual solid-state image capturing devices, positioning is performed Method, observe the alignment mark of the first single crystal semiconductor layer and the alignment mark of a color filter substrate through a transparent resin protective film, and stick the color filter substrate from the insulating layer end of the solid-state image capturing element By cutting the color filter substrate along the resin protective film filled in the groove, and dividing the individual solid-state image capturing elements, an ultra-thin chip size color backlight can be obtained Solid-state image capture device.

In addition, the ultra-thin semiconductor device manufacturing device according to the present invention, specifically, the ultra-thin backlight solid-state image capturing device manufacturing device, is used when releasing fluid to a substrate with at least two porous semiconductor peeling layers inside. When dividing the substrate by using a predetermined porous semiconductor peeling layer as an interface, by providing a stop layer part to prevent the fluid from intruding into another porous semiconductor peeling layer from the released part, the fluid peeling can be avoided Acts on the other porous semiconductor peeling layer, so the predetermined porous semiconductor peeling layer can be used as an interface to divide the substrate, so that the efficiency of using the porous semiconductor peeling layer as an interface to divide the supporting substrate will be further improved. The ground is improved, so the yield, quality and productivity can be further improved.

In addition, the manufacturing device of the ultra-thin semiconductor device according to the present invention, specifically, the manufacturing device of the ultra-thin backlit solid-state image capturing device, emits a laser beam to a semiconductor device with at least two layers of porous semiconductor inside. When the substrate with one-layer or two-layer ion implantation layer is used to divide the substrate by using a predetermined porous semiconductor peeling layer or ion implantation layer as an interface, the substrate can be divided by a relatively small force. Specifically, in the present invention, the target of the laser beam is a porous semiconductor peeling layer or an ion implantation layer, so the laser beam can be used for segmentation very accurately and very effectively. Therefore, the yield, quality and productivity can be further improved.

Although the present invention has been described with reference to specific specific embodiments for clarifying purposes, it should be understood that those skilled in the art can still make various modifications to it without departing from the basic concept and scope of the present invention.

<p>10. . . Seed substrate</p><p>11. . . Porous Si layer</p><p>11a. . . Low porosity Si layer</p><p>11b. . . High porosity Si layer</p><p>11c. . . Low porosity Si layer</p><p>12. . . First semiconductor layer</p><p>12a. . . Implanted transmission channel area</p><p>13. . . Ion implantation layer</p><p>20. . . Support substrate</p><p>twenty one. . . Porous Si layer</p><p>21a. . . Low porosity Si layer</p><p>21b. . . High porosity Si layer</p><p>21c. . . Low porosity Si layer</p><p>twenty two. . . Second semiconductor layer</p><p>22a. . . Second semiconductor layer</p><p>22b. . . Third semiconductor layer</p><p>twenty three. . . Insulating film</p><p>23a. . . Silicon oxide film</p><p>23b. . . Silicon Nitride Film</p><p>23c. . . Silicon oxide film</p><p>twenty four. . . Ion implantation layer</p><p>301. . . Support substrate holder</p><p>301a. . . Shaft</p><p>302. . . Seed substrate holder</p><p>302a. . . Shaft</p><p>303. . . Release part</p><p>304. . . Stop zone fixture</p><p>31. . . Component isolation insulating film</p><p>32. . . Gate insulating film</p><p>33. . . Transfer electrode</p><p>34. . . Interlayer insulating film</p><p>35. . . Electrode external terminal</p><p>36. . . Raised electrode</p><p>37. . . Insulating film</p><p>38. . . Transfer electrode</p><p>39. . . Transfer electrode</p><p>C. . . Perforation</p><p>S. . . Notch</p><p>40. . . Resin protective film</p><p>50. . . Protective tape</p><p>51. . . UV tape</p><p>52. . . UV tape</p><p>53. . . UV tape</p><p>54. . . Protective tape</p><p>55. . . glass substrate</p><p>M. . . Cross calibration mark</p><p>60. . . Transparent substrate</p><p>61. . . Sealants</p><p>70. . . Color filter substrate</p><p>70a. . . Color filter layer</p><p>71. . . Transparent adhesive</p><p>81. . . On-chip color filter</p><p>82. . . On-chip microlens</p><p>100. . . A printed circuit board</p><p>101. . . Conductive paste</p><p>121. . . Implanted transmission channel area</p><p>201. . . n-type semiconductor region</p><p>202. . . p-channel blocking zone</p>

The above objectives and features of the present invention can be more easily understood from the above description of the preferred embodiments with reference to the accompanying drawings. Among them:

1A and 1B are cross-sectional views of the state after forming a porous Si layer in manufacturing the backlight solid-state image capturing device of the first embodiment of the present invention;

2A and 2B are cross-sectional views of the state after the steps of forming a semiconductor layer and an insulating layer are performed in manufacturing the backlight solid-state image capturing device of the first embodiment;

3A and 3B are cross-sectional views of the state after substrate soldering and peeling off a seed substrate in the manufacturing of the backlight solid-state image capturing device of the first embodiment;

4A and 4B are cross-sectional views of the state after the hydrogen annealing step is performed in manufacturing the backlight solid-state image capturing device of the first embodiment;

5 is a cross-sectional view of the state after forming a device in the manufacturing of the backlight solid-state image capturing device of the first embodiment;

6A and 6B are cross-sectional views of a state after forming a groove and a resin protective film and dividing a supporting substrate in the manufacturing of the backlight solid-state image capturing device of the first embodiment of the present invention;

7A and 7B are cross-sectional views of the state after complete cutting is performed in manufacturing the backlight solid-state image capturing device of the first embodiment;

8A and 8B are cross-sectional views of the state after manufacturing the backlight solid-state image capturing device chip in manufacturing the backlight solid-state image capturing device of the first embodiment;

9A and 9B are cross-sectional views of a state after a transparent substrate is pasted and mounted on a mounting board in manufacturing the backlight solid-state image capturing device of the first embodiment of the present invention;

10A to 10C are cross-sectional views of the state after forming a hydrogen ion implantation layer and an insulating film in manufacturing the backlight solid-state image capturing device of the second embodiment;

11A and 11B are cross-sectional views of the state after the substrates are soldered in manufacturing the backlight solid-state image capturing device of the second embodiment;

12 is a cross-sectional view of a state after dividing a seed substrate in manufacturing the backlight solid-state image capturing device of the second embodiment;

13 is a cross-sectional view of a state after forming a device in the manufacturing of the backlight solid-state image capturing device of the second embodiment;

14A and 14B are cross-sectional views of a state after forming a groove and a resin protective film and dividing a supporting substrate in the manufacturing of the backlight solid-state image capturing device of the second embodiment;

FIGS. 15A and 15B show that an ion implantation layer is formed in the seed substrate and a porous Si layer and a second semiconductor are formed in the supporting substrate in the manufacture of a backlight solid-state image capturing device of the third embodiment. A cross-sectional view of the state after the layer and an insulating film;

16 is a cross-sectional view of the state after the substrates are soldered in the manufacturing of the backlight solid-state image capturing device of the third embodiment;

17 is a cross-sectional view of a state after dividing a seed substrate in manufacturing the backlight solid-state image capturing device of the third embodiment;

18A and 18B are cross-sectional views of a state after pasting a color filter substrate in manufacturing a backlight solid-state image capturing device of a fourth embodiment;

19A and 19B are cross-sectional views of the state after complete cutting is performed and mounted on the mounting board in manufacturing the backlight solid-state image capturing device of the fourth embodiment;

20A and 20B are cross-sectional views of a state after forming an on-chip color filter and repeating several on-chip lenses in manufacturing a backlight solid-state image capturing device of a fifth embodiment;

21A and 21B are cross-sectional views of the state after complete cutting is performed and mounted on the mounting board in manufacturing the backlight solid-state image capturing device of the fifth embodiment;

22A and 22B are cross-sectional views of a state after forming a porous Si layer, a semiconductor layer, and an insulating film in manufacturing a backlight solid-state image capturing device of a sixth embodiment;

23A and 23B are cross-sectional views of the state after substrate welding and peeling off the seed substrate in manufacturing the backlight solid-state image capturing device of the sixth embodiment;

24A and 24B are cross-sectional views of the state after the hydrogen annealing step is performed and a device is formed in manufacturing the backlight solid-state image capturing device of the sixth embodiment;

25A and 25B are cross-sectional views of the state after forming a groove and a resin protective film and dividing the supporting substrate in manufacturing the backlight solid-state image capturing device of the sixth embodiment; and

26 is a cross-sectional view of the state after being mounted on a mounting board in manufacturing the backlight solid-state image capturing device of the sixth embodiment.