A damascene interconnect structure with cap layer

Internal wiring structure of integrated circuit and its forming method

The present invention relates to a metallization process of an integrated circuit, and particularly relates to a damascene process.

The conventional integrated circuit includes a plurality of metal circuit patterns separated by inner wiring pitches, and a plurality of inner wirings. The aforementioned interconnects are, for example, bus lines, bit lines, word lines, or logic interconnects. Generally, the metal patterns of the vertically arranged metallization layers are connected to each other through the vias. The metal lines formed in the trench-like openings generally extend in a direction parallel to the semiconductor substrate. According to the current technology, this type of semiconductor device may include eight or more metallization layers to meet the geometric shape and miniaturization requirements of the device.

The usual method of forming metal lines or plugs is to use the well-known damascene method. Generally speaking, this method includes: firstly, forming an opening in the dielectric layer, wherein the dielectric layer separates the vertically disposed metallization layer, and the opening is usually formed by a traditional photolithography technique. Then, the above-mentioned opening is filled with copper or copper alloy to form a via. Then, the excess metal material on the surface of the dielectric layer is removed by chemical mechanical polishing.

Copper has a lower resistivity than aluminum, and copper has a higher diffusion activation energy than aluminum, so the reliability of copper is better, so copper has replaced aluminum. However, as the geometric shape of the semiconductor device continues to shrink and the current density increases, copper still encounters problems that affect the reliability of the device, such as the electron migration effect and the stress migration effect.

FIG. 1 is a cross-sectional view of the interconnect structure 1 without a conductive covering layer according to the damascene process. The metal wire 2 formed in a semiconductor substrate 6 and the metal wire 4 above are usually formed of copper or copper alloy, and the metal wires 2 and 4 are connected to each other through the via 10. The inter-metal dielectric layer 8 separates the two conductive layers where the metal lines 2 and 4 are located. The etching stop layer 5 is formed on the metal wire 2. The diffusion barrier layers 12 and 14 are used to prevent copper from diffusing into surrounding materials. The above interconnection structure 1 encounters problems that affect the reliability of the device, such as the electron migration effect and the stress migration effect. Because the metal line 2 is in direct contact with the etch stop layer 5, and the difference in characteristics between the metal line 2 and the etch stop layer 5 causes more serious problems of the electron transfer effect and the stress transfer effect, the reliability of the device is reduced.

FIG. 2 is a cross-sectional view of the interconnection structure 15 formed on the metal wire 2 with a conductive covering layer 16 according to the prior art. The conductive covering layer 16 usually uses materials that are less likely to cause electron migration effects. The conductive covering layer 16 improves the reliability of the interconnect structure 15 by removing the interface between the metal line 2 and the etching stop layer 5. Therefore, the chance of the electron migration effect on the surface of the metal wire 2 will be much lower. Due to the reduction of the electron migration effect, the mean time to fail (MTTF) of the interconnect structure 15 is 10 times the average damage time of the interconnect structure 1 under voltage application. In addition, with the conductive covering layer 16, the chance of generating stress-causing holes is significantly reduced.

However, the above-mentioned conductive covering layer 16 may also cause other problems. For example, in order to form a via window, the inter-metal dielectric layer 8 and the etching stop layer 5 must be etched. Usually, over-etching is used to etch through the conductive covering layer 16 and the etching stop layer 5 in the etched part. In the traditional interconnect structure manufacturing process, the over-etching is stopped within a certain period of time, that is, when part of the etching stop layer 5 is removed. Generally, excessive etching may stop on the conductive cover layer 16 or the metal line 2.

If the over-etching stops on the conductive cover layer 16, since the conductive cover layer 16 usually has a higher resistance, the remaining conductive cover layer 16 will increase the resistance of the interconnect structure. The high resistance will cause the problem of RC delay.

If excessive etching stops on the metal wire 2, since the metal wire 2 is composed of copper and there is no remaining conductive coating layer 16, the contact resistance will be lower.

In summary, the problems of contact resistance and RC delay will vary with different manufacturing processes and are not easy to predict.

Therefore, in order to reduce the contact resistance, solve the RC delay problem, and simplify the manufacturing process, the industry urgently needs a new method for forming the interconnection structure.

In order to achieve the above and other objectives, the method of the present invention mainly provides a method for forming an interconnect structure with a conductive covering layer. The method includes: forming a first wire on a semiconductor substrate, and then forming a conductive wire on the first wire. Covering layer. Afterwards, an etch stop layer is formed above the conductive covering layer, and an inter-metal dielectric layer is formed above the etch stop layer. Then, a via opening and a trench are formed in the etch stop layer, the inter-metal dielectric layer, and the conductive covering layer. Then, a recess is formed in the first wire. The recess can be formed by over-etching when etching the first dielectric layer; the recess can also be formed by another method, such as argon ion sputter etching. Afterwards, the trenches, openings and recesses are filled to form a second wire.

Since a conductive covering layer is formed on the first wire, the reliability and performance of the interconnect structure are significantly improved. According to a preferred embodiment of the present invention, the method of the present invention reduces the problems of high contact resistance and RC delay caused by the second wire being coupled to the first wire through the conductive covering layer.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are listed below in conjunction with the accompanying drawings, which are described in detail as follows:

FIGS. 3 to 10 are cross-sectional views of the manufacturing process of an interconnect structure with a conductive covering layer according to a preferred embodiment of the present invention. Among them, a via window connecting two wires is formed.

As shown in FIG. 3, a trench 26 is formed in a base material 20. In a preferred embodiment, the base material 20 is an inter-metal dielectric layer, the inter-metal dielectric layer includes a material, and the dielectric constant (k value) of this material is about less than 3.3 and includes nitrogen, carbon, Hydrogen, oxygen, fluorine, and combinations of the above elements. In another embodiment, the base material 20 may be a silicon substrate or other non-conductive materials.

As shown in FIG. 4, a diffusion barrier layer 30 and a wire 32 are formed in the trench 26.

In a preferred embodiment, the diffusion barrier layer 30 is formed of a material including titanium, titanium nitride, tantalum, or tantalum nitride.

In a preferred embodiment, the material of the wire 32 includes copper or a copper alloy, and the copper alloy contains at least 10 atomic percent copper. In this specification, the wire 32 may also refer to a copper wire 32. In another preferred embodiment, the material of the wire 32 includes an aluminum alloy, and the aluminum alloy contains at least 50 atomic percent aluminum. In another preferred embodiment, the material of the wire 32 includes an alloy of aluminum, silver, and gold, and the alloy contains at least 50 atomic percent of aluminum, silver, and gold. The wire 32 has good conductivity and the resistivity is about less than 4 ohm-cm.

The wire 32 is usually formed by depositing a thin copper seed layer or copper alloy, and then plated in the trench 26 to fill the trench 26. Next, the surface of the copper wire 32 is flattened by a chemical mechanical polishing method.

As shown in FIG. 5, a conductive covering layer 33 is formed on the wire 32. In another preferred embodiment, the conductive covering layer 33 is selectively formed on the diffusion barrier layer 30.

In a preferred embodiment, the conductive covering layer 33 includes cobalt, nickel, tungsten, molybdenum, tantalum, boron, or phosphorus. The above-mentioned materials may include the following forms: cobalt phosphide, cobalt boride, cobalt tungsten phosphate, cobalt tungsten phosphate, cobalt tungsten phosphate, cobalt tin phosphate, nickel boron tungsten, copper silicide, zirconium nitride, molybdenum phosphate Nickel, or a combination of the above compounds. The thickness of the conductive covering layer 33 is approximately between 2 nanometers and 20 nanometers.

Compared with a dielectric material, the characteristics of the conductive covering layer 33 are more compatible with the characteristics of the wires 32, so the electron migration effect and the stress migration effect (stress migration) are reduced, and the reliability of the device is therefore improved.

In a preferred embodiment, the material of the wire 32 includes copper and copper alloy, so the conductive covering layer 33 can be formed of a copper silicide. The formation method of the conductive coating layer 33 includes a chemical vapor reaction process (chemical vapor reaction process), which is to introduce silane (SiH) into a reaction chamber.₄) The chemical vapor reacts with copper at a temperature of about 200°C to 420°C. In another preferred embodiment, the conductive covering layer 33 can be formed by an electroless plating method. In another preferred embodiment, the conductive covering layer 33 can be deposited by general techniques, such as sputtering and chemical vapor deposition. Then, an etching process is performed on the conductive covering layer 33. The preferred thickness of the conductive covering layer 33 is about 2 nm to 20 nm, and the best thickness is about 10 nm.

In a preferred embodiment, after the wire 32 and the conductive covering layer 33 are formed, a dual damascene process is then performed to form a via and the second copper wire. In other embodiments, the above-mentioned via and the second copper wire are formed by a single damascene process. As shown in FIG. 6, an etch stop layer 34 of a via is formed on the conductive covering layer 33 and the base material 20. The etch stop layer 34 of the above-mentioned dielectric window is a dielectric material. The dielectric material includes carbon, silicon, nitrogen, or oxygen, and the dielectric constant of the dielectric material is about less than 5. The thickness of the etch stop layer 34 of the above-mentioned via is about less than 80 nanometers.

Next, a metal interlayer dielectric layer 36 of a via is formed above the etching stop layer 34 of the above via to provide an insulating layer between the wire 32 (copper wire) and the second copper wire formed subsequently . Then, a silicon nitride layer 38 is formed on the inter-metal dielectric layer 36.

In a preferred embodiment, the metal interlayer dielectric layer 36 of the interlayer window includes carbon-doped silicon oxide, fluorine-doped silicon oxide, organic low-k material, porous low-k material, and has The dielectric constant is approximately lower than 3.4. The method for forming the metal interlayer dielectric layer 36 of the via includes spin coating, chemical vapor deposition, or other deposition methods.

Then, as shown in FIG. 6, an intermetal dielectric layer 40 of a trench is formed on the intermetal dielectric layer 36 of the via window. The method of forming the inter-metal dielectric layer 40 of the trench is similar to the method of forming the inter-metal dielectric layer 36 of the via window. Moreover, the etch stop layer 34 of the via, the metal interlayer dielectric layer 36 of the via window, and the metal interlayer dielectric layer 40 of the trench are made of materials commonly used in this technical field. Next, a silicon nitride layer 42 is formed on the intermetal dielectric layer 40 of the trench.

After that, a right-angled shape (not shown in the figure) or a wide top and bottom narrow via opening 44 is formed, as shown in FIG. 7. First, a photoresist material (not shown) is formed on the inter-metal dielectric layer 40 of the trench, and a pattern is defined on the photoresist material.

Next, use a fluorine-containing etching gas to perform an anisotropic etching process to etch through the metal interlayer dielectric layer 40 of the trench and the metal interlayer dielectric layer 36 of the via window, and stop at the etching stop of the via window On the layer 34, a via opening 44 is thus formed. This via opening 44 prevents the wires 32 below from being etched. The length (not shown) and width W of the via opening 44 are approximately less than 500 nm.

Then, a trench opening 46 is formed, as shown in FIG. 8. Wherein, an anisotropic etching process is performed to etch through the metal interlayer dielectric layer 40 of the trench to form the trench opening 46, and expose a part of the surface of the etching stop layer 38 of the via. Then, the trench opening 46 will be used to form the second wire, that is, the trench opening 46 will be filled with conductive material.

In a preferred embodiment, an etching process is subsequently performed to etch a portion of the exposed surface of the etch stop layer 34 of the via. The etching agent used in the above-mentioned etching process includes carbon tetrafluoride, tetracarbon octafluoride, or oxygen. FIG. 9 shows the structure after the etching stop layer 34 of the via is etched. Since the etch stop layer 34 of the via window is very thin relative to the metal interlayer dielectric layer 36 of the via window and the metal interlayer dielectric layer 40 of the trench, the process control and the detection of the etching end point are both tight Under the control, the possibility of over-etching of the wires 32 below is also reduced. After the etch stop layer 34 of the via is etched through, the conductive cover layer 33 is then etched.

In another preferred embodiment, the conductive covering layer 33 is etched through, and the wire 32 under the conductive covering layer 33 is also over-etched, and a recess 48 is formed in the wire 32.

In another preferred embodiment, when etching to the conductive covering layer 33 or the wires 32, sputter etching may be performed to remove the remaining conductive covering layer 33 and part of the wires 32, thereby forming a recess 48. The above-mentioned sputter etching usually uses an inert substance, such as argon or helium. In a preferred embodiment, the recess 48 has a depth D, which is approximately between 1 nanometer and 100 nanometers, and more preferably between 10 nanometers and 100 nanometers.

As shown in FIG. 10, a second wire 50 and a via 52 are formed in the via opening 44, the trench opening 46, and the recess 48, wherein the via opening 44 and the trench opening 46 are filled with conductive material. In a preferred embodiment, the second wire 50 and the via 52 are formed of copper or copper alloy. Similar to the wire 32, the material of the second wire 50 and the via 52 includes an alloy containing at least 10% copper by atomic percentage. In a preferred embodiment, the material of the second wire 50 includes an alloy containing at least 50% by atomic percentage of aluminum, silver or gold. The resistivity of the second wire 50 and the via 52 is about less than 4 ohm-cm.

Then, a chemical mechanical polishing process is performed to planarize the surface of the second wire 50. In addition, before forming the second wire 50, a barrier layer (not shown) may be formed first. In a preferred embodiment, the material of the barrier layer includes titanium, titanium nitride, tantalum, or tantalum nitride. The thickness of the barrier layer is approximately between 2 nanometers and 40 nanometers.

In another preferred embodiment, after the structure of FIG. 8 is formed, a barrier layer is formed on the sidewalls of the via opening 44 and the trench opening 46, and on the partially exposed surface of the etch stop layer 34 of the via . Then, an anisotropic etching process or sputter etching is performed to remove the material at the bottom of the via opening 44, the barrier layer, the etch stop layer 34 of the via, and the conductive covering layer 33, thereby forming a recess 48. In the above process, the barrier layer between the via 52 and the wire 32 is also removed. Therefore, the direct contact between copper and copper forms a better conductive effect.

In a preferred embodiment, forming the recess 48 in the wire 32 can ensure that no conductive coating 33 remains in the exposed portion of the via opening 44. Therefore, contact resistance and RC delay can be reduced. And it is easier to predict the contact resistance, and it can also reduce process variables.

Although the present invention has been disclosed in several preferred embodiments as above, it is not intended to limit the present invention. Anyone familiar with the art can make any changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

<p>1. . . Inline structure</p><p>2. . . metal wires</p><p>4. . . metal wires</p><p>5. . . Etch stop layer</p><p>6. . . Semiconductor substrate</p><p>8. . . Inter-metal dielectric layer</p><p>10. . . Via</p><p>12. . . Diffusion barrier</p><p>14. . . Diffusion barrier</p><p>15. . . Inline structure</p><p>16. . . Conductive coating</p><p>20. . . Binder</p><p>26. . . ditch</p><p>30. . . Diffusion barrier</p><p>32. . . wire</p><p>33. . . Conductive coating</p><p>34. . . Etch stop layer of via</p><p>36. . . Metal interlayer dielectric layer of via window</p><p>38. . . Silicon nitride layer</p><p>40. . . Inter-metal dielectric layer of trench</p><p>42. . . Silicon nitride layer</p><p>44. . . Via opening</p><p>46. . . Ditch opening</p><p>48. . . Recess</p><p>50. . . Second wire</p><p>52. . . Via</p><p>D. . . depth</p><p>W. . . width</p>

FIG. 1 is a cross-sectional view of the interconnection structure without a conductive covering layer according to the prior art.

FIG. 2 is a cross-sectional view of the interconnection structure with a conductive covering layer according to the prior art.

FIGS. 3 to 10 are cross-sectional views of the manufacturing process of an interconnect structure with a conductive covering layer according to a preferred embodiment of the present invention.