Method for manufacturing metal damascene and structure thereof

Manufacturing method and structure of metal inlay

The present invention relates to a method for manufacturing metal damascene and its structure, and more particularly to a method for manufacturing metal damascene and its junction trenches used in interconnects of semiconductor devices.

Semiconductor products are connected to semiconductor components by metal wires, and the operating state of each semiconductor component is controlled by applying voltage. Traditionally, metal inlays are used as metal wires. Please refer to the figures 1A~1D for illustration. Schematic diagram of the cross-sectional structure process of the technical production of metal inlays.

First, as shown in FIG. 1A, an etching stop layer 11, a dielectric layer 12, and a dielectric anti-reflection layer 13 are sequentially formed on a semiconductor base layer 10.

In FIG. 1B, an opening 14 is formed in the dielectric material anti-reflection layer 13, the dielectric layer 12, and the etching stop layer 11 by using the photolithography process and etching technology.

In Figure 1C, a barrier layer 15 is deposited on the surface of the dielectric material anti-reflection layer 13 and the sides and bottom of the opening 14. The barrier layer 15 is more commonly used material of tantalum nitride.

Then, a metal layer 16 is deposited on the surface of the barrier layer 15 and the opening 14. The material of the metal layer 16 is copper.

As shown in FIG. 1D, chemical mechanical polishing is performed again, and the dielectric layer 12 is stopped to complete the metal damascene fabrication.

However, as shown in Figure 2 (showing an enlarged view of area 17 in Figure 1), in order to improve the performance of semiconductor products, when the dielectric layer 12 uses a porous low-dielectric constant material (for example: porous SiLK, Aerogel or Xerogel), the structure of the dielectric layer 12 made of porous low-k material makes the side of the opening 14 formed after etching not a flat surface, so that the thickness of the subsequently deposited barrier layer 15 cannot be Uniformity, the thinner region 18 of the barrier layer 15 cannot completely prevent the metal layer 16 from diffusing into the dielectric layer 12, which not only generates leakage current, but also shortens the time-dependent dielectric breakdown related to the reliability of the device. Breakdown, TDDB) time and degraded bias temperature stress (BTS) performance, the lack of conventional technology can be seen in general.

In view of the deficiencies of the conventional technology, the purpose of the present invention is to provide a method and structure of the metal damascene to avoid leakage current caused by the semiconductor device.

Another object of the present invention is to provide a method and structure for inlaid metal to maintain the time-dependent dielectric breakdown time.

Another object of the present invention is to provide a manufacturing method and structure of metal inlay to improve the bias temperature shock performance.

Another object of the present invention is to provide a method and structure for inlaying metal in order to increase the production capacity of semiconductor products.

According to the above-mentioned objective, one aspect of the present invention provides a method for manufacturing damascene. The manufacturing method first deposits an etch stop layer and a dielectric layer on a base layer in sequence, and then forms a metal damascene layer in the dielectric layer and the etch stop layer. The hole is opened, and then a silicon carbide layer is deposited on the surface of the dielectric layer and the sides and bottom of the hole, and finally a metal layer is formed in the hole.

Another aspect of the present invention provides a metal damascene structure. The structure includes a base layer, an etch stop layer above the base layer, a dielectric layer above the etch stop layer, and one in the dielectric layer and the etch stop layer The opening is a silicon carbide layer located on the surface of the dielectric layer and the sides and bottom of the opening, and a metal layer located in the opening.

The material of the metal layer can be copper, the dielectric layer is a porous low-k dielectric layer (such as porous SiLK, Aerogel or Xerogel), and the thickness of the silicon carbide layer is preferably between 100 and 200<img file="TWI246739B_D0001.tif" />。

The silicon carbide layer of the present invention can prevent the metal layer from diffusing into the dielectric layer, thereby reducing leakage current, and can increase the time-dependent dielectric breakdown time related to the reliability of the device and improve the bias temperature shock performance.

Please refer to FIGS. 3A to 3E, which are schematic diagrams illustrating the cross-sectional structure flow of the metal inlay in the present invention. First, as shown in FIG. 3A, an etch stop layer 31, a dielectric layer 32, and an organic anti-reflection layer 33 are sequentially deposited on a semiconductor base layer 30. Wherein, the material of the etching stop layer 31 can be silicon nitride or silicon carbide, preferably, the thickness of the etching stop layer 31 is 400<img file="TWI246739B_D0002.tif" />. The material of the dielectric layer 32 of the present invention can be a porous low-permittivity dielectric layer, such as porous SiLK, Aerogel or Xerogel. Especially for the use of a porous low-permittivity dielectric layer, the technology of the present invention Can overcome the aforementioned lack of knowledge. Among them, the organic anti-reflective layer 33 is used to avoid light reflection during exposure to reduce the resolution. Of course, it is not absolutely necessary to deposit an organic anti-reflective layer in the present invention.

In FIG. 3B, an opening 34 is formed in the organic anti-reflective layer 33, the dielectric layer 32, and the etching stop layer 31. Wherein, the opening 34 can be formed by first depositing a photoresist layer (not shown in the figure) on the organic anti-reflective layer 33, and then defining the photoresist layer pattern by a lithography process, and then using the patterned photoresist layer as a mask. The etching stops at the etching stop layer 31, and finally, the patterned photoresist layer is used as a mask for etching, and the etching stops at the base layer 30.

In Figure 3C, the organic anti-reflective layer 33 is removed by heating, for example, the organic anti-reflective layer 33 can be removed by heating in a chemical vapor deposition machine.

In FIG. 3D, a silicon carbide layer 35 is deposited on the surface of the dielectric layer 32 and the sides and bottom of the opening 34, and then a metal layer 36 is deposited on the surface of the silicon carbide layer 35 and the opening 34. Among them, the silicon carbide layer 35 is deposited by chemical vapor deposition (the silicon carbide layer 35 can be deposited in the same chemical vapor deposition machine that removes the organic anti-reflective layer 33 by heating), preferably, the silicon carbide layer The thickness is between 100~200_A. Among them, the deposited metal layer 36 can be deposited on the surface of the silicon carbide layer 35 and the side and bottom of the opening 34 with a tantalum layer (not shown in the figure) to increase adhesion, and then sputtering on the surface of the tantalum layer A deposition seed crystal of the metal 36 is formed on the side and bottom of the opening 34, and then electrochemical plating is performed to deposit a metal layer 36 on the surface of the tantalum layer and the side and bottom of the opening 34. Among them, the material 36 of the metal layer can be copper or other materials with good conductivity and easy deposition and etching.

Finally, as shown in FIG. 3E, the metal layer 34 is chemically mechanically polished to stop at the silicon carbide layer 35, and the fabrication of the damascene is completed.

The present invention replaces the barrier layer in the conventional technology with a silicon carbide layer. The deposition ability of the silicon carbide layer is better than that of the barrier layer in the conventional technology, which can reduce leakage current and improve the reliability of semiconductor components. Depends on the dielectric breakdown time and improves the bias temperature shock performance.

In addition, the present invention (FIG. 3E) does not polish and remove the silicon carbide layer 35, and the retention of the silicon carbide layer 35 can also reduce the leakage current. In the conventional technology (FIG. 1D), a part of the barrier layer 15 must be polished and removed, and The anti-reflective layer 13 of dielectric material must be removed by grinding. The organic anti-reflective layer of the present invention can be removed by heating, and it is not absolutely necessary to remove it by grinding. Therefore, the present invention can remove the organic anti-reflective layer 33 (Figure 3C) by heating and deposit the silicon carbide layer 35 (Figure 3D). Figure) is performed in the same chemical vapor deposition machine. Therefore, the present invention can further reduce the process time and increase the production capacity in the production of metal inlays.

As those skilled in the art understand, the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the patent application of the present invention; everything else is done without departing from the spirit of the present invention. Effective changes or modifications should be included in the scope of the following patent applications.

<p>10. . . Base layer</p><p>11. . . Etch stop layer</p><p>12. . . Dielectric layer</p><p>13. . . Anti-reflective layer of dielectric material</p><p>14. . . Perforation</p><p>15. . . Barrier layer</p><p>16. . . Metal layer</p><p>17. . . area</p><p>18. . . area</p><p>30. . . Base layer</p><p>31. . . Etch stop layer</p><p>32. . . Dielectric layer</p><p>33. . . Organic anti-reflective layer</p><p>34. . . Perforation</p><p>35. . . Silicon carbide layer</p><p>36. . . Metal layer</p>

The preferred embodiment of the present invention is explained in more detail in the foregoing description text supplemented by the following figures, in which:

Figures 1A~1D are schematic diagrams showing the cross-sectional structure flow of metal inlays produced by conventional techniques;

Figure 2 is an enlarged view showing area 17 in Figure 1; and

Figures 3A to 3E are schematic diagrams showing the cross-sectional structure flow of the metal inlay production of the present invention.