Write path scheme in synchronous DRAM

Design of write path in synchronous dynamic random access memory

The present invention relates to a write path design of a synchronous dynamic random access memory (DRAM), specifically, to a write path design of a DDR II SDRAM.

Since DDR I SDRAM has been replaced by DDR II SDRAM, in order to increase the bus efficiency, new write latency (latency) regulations have been applied. According to the new regulations of the present invention, the line operation is defined on the basis of two clocks, and the specification of the interrupt operation is not strictly defined.

Figure 1 shows a block diagram of the conventional write path design.

Please refer to FIG. 1, the input data Din is input to a data input buffer 10 in a serial manner. According to the rising edge signal dsrp4 and the falling edge signal dsfp4 of a data strobe signal DQS from a DQS buffer 80, such serial input data is latched in a data conversion unit, and the data conversion unit includes first to seventh Latches 20 to 80. Then, according to the rising edge signal dsrp4 and the falling edge signal dsfp4 of the data strobe signal DQS, four parallel aligned data (ie, Algn_dinr0, Algn_dinf0, Algn_dinr1, Algn_dinf1) are simultaneously input to a Din multiplexer 100 in a parallel manner. Depending on the X4, X8 or X16 mode, the Din multiplexer 100 outputs 16, 32 or 64 data din_algn_data to a data input/output sense amplifier 110. The data input/output sense amplifier 110 is composed of 64 sense amplifiers, and is used to input/output the data sensed in the sense amplifier 110 according to a control signal dinstbp generated by a data input strobe signal generator 90 The measured data is output to a write driver 120 through 64 global input/output lines.

The write driver 120 is individually operated according to the X4 and X8 mode selection signals to load input data on the local input/output lines LIO and LIOB.

For the conventional write path design as described above, the 64 sense amplifiers in the data input/output sense amplifier are equipped to operate in a manner independent of the X4, X8 or X16 modes, so that they can be triggered. 64 global input/output lines. As a result, since the unused global input/output lines are also triggered in X4 or X8 mode, there is a question of how much power consumption is required.

Accordingly, the object of the present invention is to provide a synchronous dynamic random access memory capable of eliminating the aforementioned shortcomings.

Furthermore, the purpose of the present invention is to individually operate the data input/output sense amplifiers according to the mode selection signal, so as to reduce the power consumption.

According to the present invention, a write path design for a synchronous dynamic random access memory includes: a data conversion unit for converting a serial input data signal into a parallel output data; a multiplexer for according to a first mode The selection signal and a second mode selection signal output data from the data conversion unit; a data input/output sense amplifier, which has a plurality of sense amplifiers, is used for selecting the first mode selection signal and the second mode selection The signal individually operates the plurality of sense amplifiers to sense the data from the multiplexer, and then load the data on a global input/output line; and a write driver for loading on a local input/output line Data from this global input/output line.

The present invention will now be described in detail with reference to the preferred embodiments of the drawings. Similar reference numerals will be used in the drawings to identify the same similar components.

According to the present invention, the data input/output sense amplifiers are individually operated according to the mode selection signal in the write path structure shown in FIG. 1. Since other components are similar to those of the prior art, the following description is only related to the data input/output sense amplifier.

Figure 2 shows a block diagram of a data input/output sense amplifier according to the present invention.

Generally, the data input/output sense amplifier includes 64 sense amplifiers S1 to S64. The data din_algn_data from the Din multiplexer 100 is input to each of the sense amplifiers S1 to S64, and the corresponding inverted data din_algn_datab is input to each of the sense amplifiers S1 to S64.

The first to sixty-fourth sense amplifiers S1 to S64 can be classified into 4 blocks.

The first to sixteenth sense amplifiers S1 to S16 are activated according to the output din_iosa1 from the first enabling circuit 130. The seventeenth to thirty-second sense amplifiers S17 to S32 are activated according to the output din_iosa2 from the second enabling circuit 140. The thirty-third to forty-eighth sense amplifiers S33 to S48 are activated according to the output din_iosa3 from the third enabling circuit 150. The forty-ninth to sixty-fourth sense amplifiers S49 to S64 are activated according to the output din_iosa4 from the fourth enabling circuit 160.

Each output of the first to fourth enable circuits 130 to 160 is generated according to control signals (ie, dinstb, enable_din0, enable_din1, enable_din2, and enable_din3). How to generate control signals (ie, enable_din0, enable_din1, enable_din2, and enable_din3) will be explained with reference to FIGS. 3A and 3B.

The encoding unit 300 in FIG. 3A includes first through third through encoding units 170 through 190.

According to the column address x_add<13>, the control signals F<0:3> and E<0:3>, the mode selection signals x4 and x8, and the power-on signal pwrup, the first encoding circuit 170 generates the encoding signal xa13_wt.

According to the row address y_add<11>, the control signal F<0:3>, the mode selection signal x4, and the power-on signal pwrup, the second encoding circuit 180 generates the encoding signal ya11_wt.

According to the output ya11_wt of the second encoding circuit 180, the output xa13_wt of the first encoding circuit 170, and the mode selection signals x4 and x8, the third encoding circuit 190 generates the control signal enable_din<0:3>.

FIG. 3B shows a detailed circuit diagram of the first to fourth enabling circuits 130 to 160 shown in FIG. 2.

The output enable_din<0:3> of the third encoding circuit 190 and the output dinstb of the data input strobe signal generator shown in FIG. 1 are input to the NAND gate G1. The output of the NAND gate G1 is inverted by the inverter G2 to generate control signals din_iosa1, din_iosa2, din_iosa3, and din_iosa4.

Based on the reference purpose, the way to establish the control signal E<0:3> is to perform a "logical AND" operation on the memory bank addresses and pulses generated in the active state .

If a memory group <0> is in the active state, the control signal E<0> will change to a high level, and the control signals E<1>, E<2> and E<3> will change to a low level. If a memory group <1> is in the active state, the control signal E<1> will change to a high level, and the control signals E<0>, E<2> and E<3> will change to a low level. If a memory group <2> is in the active state, the control signal E<2> will change to a high level, and the control signals E<0>, E<1> and E<3> will change to a low level. If a memory group <3> is in the active state, the control signal E<3> will change to a high level, and the control signals E<0>, E<1> and E<2> will change to a low level.

In addition, a "logical AND" operation is performed on a memory bank address and a signal activated when the write operation is executed, thereby generating the control signal F<0:3>.

If a write operation of memory group <0> is to be executed, the control signal F<0> will change to a high level, and the control signals F<1>, F<2> and F<3> will change to a low level. If a write operation of memory group <1> is to be executed, the control signal F<1> will change to a high level, and the control signals F<0>, F<2> and F<3> will change to a low level. If a write operation of memory group <2> is to be executed, the control signal F<2> will change to a high level, and the control signals F<0>, F<1> and F<3> will change to a low level. If a write operation of memory group <3> is to be executed, the control signal F<3> will change to a high level, and the control signals F<0>, F<1> and F<2> will change to a low level.

Fig. 4A shows a detailed circuit diagram of the first encoding unit.

According to the operation of the transmission gates T1 to T4, X_add<13> is latched in the latches L1 to L4. The transmission gates T1 to T4 are opened according to the control signal E<0:3>. The inverters G3 to G6 invert the outputs of the latches L1 to L4, respectively.

According to the operation of the transmission gates T5 to T8, the outputs of the inverters G3 to G6 are forwarded to a node K, and then latched in the latch L5. The transmission gates T5 to T8 are opened according to the control signal F<0:3>.

The inverter G6 inverts the output of the latch L5. Then, the NOR gate G7 performs a NOR operation on the mode selection signals X4 and X8. The inverter G8 inverts the output of the "NOR" gate G7. The NAND gate G9 performs a NAND operation on the outputs of inverters G6 and G8. The inverter G10 inverts the output of the NAND gate G9 to generate the encoded signal xa13_wt.

At the same time, use the power-on signal pwrup to set an initial value.

Fig. 4B shows a detailed circuit diagram of the second encoding unit.

According to the operation of the transmission gates T9 to T12, the row address Y_add<11> is forwarded to a node H, and then latched in the latch L6. The transmission gates T9 to T12 are opened according to the control signal F<0:3>.

The inverter G12 inverts the output of the latch L6. The NAND gate G13 performs a NAND operation on the output of the inverter G12 and the mode selection signal X4. The inverter G14 inverts the output of the NAND gate G13 to generate the encoded signal yall_wt.

At the same time, similar to FIG. 4A, the power-on signal pwrup is used to set an initial value.

Fig. 4C shows a detailed circuit diagram of the third encoding unit.

The mode selection signal X4 passes through inverters G16 and G17, and then is input to the "NAND" gate G18. The NAND gate G18 performs a NAND operation on the output of the inverter G17 and the encoded signal ya11_wt to generate an output A. The NAND gate G19 performs a NAND operation on the output of the NAND gate G18 and the output of the inverter G17 to generate an output B.

The NOR gate G20 performs a NOR operation on the mode selection signals X4 and X8, and is then inverted by the inverter G21. The NAND gate G22 performs a NAND operation on the output of the inverter G21 and the encoded signal xa13_wt, thereby generating an output C. The NAND gate G23 performs a NAND operation on the output C of the NAND gate G22 and the output of the inverter G21 to generate an output D.

The NAND gate G24 performs a NAND operation on the outputs A and C, and then forwards its output to a node P after passing through the inverter G25. The NAND gate G26 performs a NAND operation on the outputs B and C, and then forwards its output to the node P after passing through the inverter G27. The NAND gate G28 performs a NAND operation on the outputs A and D, and then forwards its output to the node P after passing through the inverter G29. The NAND gate G30 performs a NAND operation on the outputs B and D, and then forwards its output to the node P after passing through the inverter G31. Finally, a control signal enable_din<0:3> is output from the node P.

The present invention is summarized based on the foregoing description.

The invention is suitable for GC 512M DDR II SDRAM. In the first encoding circuit, if the x8 mode is executed, the encoding operation will be executed by using the column address x_add<13>, and if the x4 mode is executed, the encoding operation will be executed by using the column address x_add<13> and the row position Address y_add<11> to perform the encoding operation. The control signal E<0:3> contains information about an active state and a memory bank address. If Bank0, Bank3, Bank1 and Bank2 are in the active state and the control signals E<0:3> are activated respectively, the data of the column address x_add<13> will be latched. The signal F<0:3> contains the information of a memory bank address and the information of a write operation that has been completed. If the control signal F<0:3> is in the active state, the transmission gate will be opened to generate the encoded signal xa13_wt.

Since the signal F<0:3> also activates the row address y_add<11>, if the x4 mode is executed, the encoding transmission timing of the row address y_add<11> is the same as the encoding transmission timing of the column address x_add<13>.

According to the signal enable_din<0:3> generated by the combination of the encoded signals x_add<13> and y_add<11>, the control signal dinstb of domain crossing is implemented.

Domain crossing means that the input data changes from the DQS domain to the clock domain. For DDR, after inputting the input data that has been aligned with a DQS signal, it will be internally converted to the clock domain. In other words, when the control signal dinstb becomes a high level, the data input/output sense amplifier will start to operate so as to load input data on the inverter G10.

Only the data input/output sense amplifier selected by the encoding operation of column address x_add<13> and row address y_add<11> can operate in x4 mode, and only by column address x_add<13> The selected data input/output sense amplifier can operate in x8 mode.

In view of the timing range or tCK limitation, a control signal enable_din<0:3> should be generated to safely wrap the control signal dinstbp. For this purpose, the enable timing of the control signal F<0:3> should be fixed to "internal write delay-0.5tCK", as shown in Figure 5. By loading the information of the memory bank address and the information of the executed write operation on the signal (this is the signal that is activated when the "internal write delay-0.5tCK"), a control signal with a fixed activation timing can be realized. If in x4 mode, the row address y_add<13> must arrive before the control signal F<0:3>. This can be achieved by latching and outputting the address buffer during the "internal write delay-1tCK" .

The timing diagram shown in FIG. 5 depicts the burst length set to 4 and the write command input in a gapless manner.

The combination of encoding signals xa13_wt and ya11_wt in x4 mode and x8 mode becomes "internal write delay-0.5tCK", and the deactivation timing of control signal enable_din becomes "internal write delay-1.5tCK". This is because 4-bit pre-fetching is used in DDR II, so each packet is composed of 4 bits. Therefore, there will be no interruption of the job at BL=4. In other words, this means that 4 bits will always be maintained. For this purpose, at least 2tCK can be maintained for the control signal enable_din (that is, if the transmission length in a gapless operation=4, or if the transmission length in an interrupt operation=8, then 2tCK can be maintained). The control signal dinstbp is activated when the internal write delay occurs, which is the strobe signal of the data input/output sense amplifier. Therefore, the timing amplitude of the control signal dinstbp is sufficient.

Fig. 6A shows the IDD4W simulation result of the prior art, and Fig. 6B shows the result according to the present invention.

Figure 7 shows a graph of the IDD4W current simulation results under the conditions of slow processing or rapid processing, voltage and temperature.

As described above, compared with the DRAM according to the prior art, the power consumption in the DRAM according to the present invention can be reduced by 23%.

According to the present invention, the power consumption in the DRAM can be reduced. In addition, since the entire global line is not triggered in the x4 mode or the x8 mode, but only 16 or 32 global lines are triggered, the defect of polarity change due to coupling adjacent to the global line can be reduced.

Although the present invention has been described with reference to its current preferred specific embodiments, those skilled in the art should know that various changes and modifications can be made without departing from the spirit and scope of the present invention and the scope of the accompanying patent applications.

<p>10. . . Data input buffer</p><p>20 to 80. . . Latches</p><p>80. . . DQS buffer</p><p>90. . . Data input strobe signal generator</p><p>100. . . Din multiplexer</p><p>110. . . Data input/output sense amplifier</p><p>120. . . Write drive</p><p>130. . . First enable circuit</p><p>140. . . Second enable circuit</p><p>150. . . Third enable circuit</p><p>170. . . First encoding circuit</p><p>180. . . Second encoding circuit</p><p>190. . . Third encoding circuit</p><p>300. . . Coding unit</p><p>S1 to S64. . . Sense amplifier</p><p>G1, G9, G13, G18, G19, G22, G23, G24, G28, G30. . . NAND gate</p><p>G2 to G6, G8, G10, G12, G16, G17, G21, G27, G29, G31. . . Inverter</p><p>G7, G20. . . NOR gate</p><p>L1 to L6. . . Latches</p><p>T1 to T12. . . Transmission gate</p>

[Embodiment] The description content will cooperate with the accompanying drawings to explain the aforementioned viewpoints and other functions of the present invention, among which:

Figure 1 shows a block diagram of the conventional write path design;

Figure 2 shows a block diagram of a data input/output sensing amplifier according to the present invention;

3A and 3B show detailed circuit diagrams of the first to fourth enabling circuits shown in FIG. 2;

FIG. 4A shows a detailed circuit diagram of the first encoding unit shown in FIG. 3A;

FIG. 4B shows a detailed circuit diagram of the second encoding unit shown in FIG. 3A;

FIG. 4C shows a detailed circuit diagram of the third encoding unit shown in FIG. 3A;

Figure 5 shows a timing diagram for explaining the present invention;

6A and 6B show the IDD4W simulation results for comparing the present invention and the prior art; and

Fig. 7 shows a graph of the reduction effect of IDD4W according to the present invention.