Build-up circuit board with conductive barrier structure and method for fabricating the same

Layer-added circuit board with conductive barrier structure and manufacturing method thereof

The invention relates to a build-up circuit board with a conductive barrier structure and a manufacturing method thereof, particularly to a circuit having a barrier layer formed on the circuit surface of a build-up circuit board with an asymmetric structure to prevent the migration of metal particles. Board structure and manufacturing method thereof.

Due to the rapid growth of various portable products such as communication, internet and computers, such as mobile phones, laptops, portable video recorders or personal digital assistants, the production of these electronic products It is necessary to use smaller and thinner circuit boards and electronic components than before. With the trend of shrinking, the development of fine circuit, high density and small aperture packaging substrates is undoubtedly integrated circuit (IC). The industry and even other related electronics industries are important research and development topics for the next generation of technology.

In the circuit board manufacturing industry, in order to achieve this goal, a build-up technology has been developed. The so-called build-up technology basically refers to the interactive stacking of multiple insulating layers and conductive layers on the surface of a core board. An electrical via is then made in the insulating layer to provide electrical connection between the conductive layers.

In order to achieve the process of designing reliable vias in a multilayer circuit board, the ones shown in Figures 2A to 2C are three types of common via processes in the industry, as described below: Figure 2A shows a plated via (Plated (through hole, PTH). The opening of the via extends through the insulating layer 201 and the circuit layers 202 and 203 covering the surface. An electrical layer is formed on a sidewall of the via. After the electroplating is completed, a conductive or non-conductive filling material 205 is filled to fill the remaining gaps to ensure the reliability of the vias.

FIG. 2B shows another form of via hole, which is a so-called blind via. The opening of the blind hole extends into the insulation layer 206, but does not penetrate the circuit layer 207. After the plating layer 208 is deposited, a conductive or non-conductive filling material 209 is filled in the recess to provide proper flatness for subsequent processes.

FIG. 2C shows a third type of via hole, in which the opening of the blind hole extends through the insulating layer 210 but does not penetrate the circuit layer 211. After the conductive material 213 is filled in the via hole, a circuit layer 212 is formed.

The above-mentioned conventional technology needs to be filled into the gap of the through hole. However, when the diameter of the through hole is less than 0.05 mm, the manufacturing process will become difficult to implement. Therefore, in general mass production, the above three processes must be used in the through hole It can be implemented with a diameter of 0.75 mm or more. In this case, the circuit board cannot meet the requirements of higher wiring density due to the limitation of the process technology of the via size.

In addition, compared with the traditional Substractive etching method, the industry currently uses the Additive method that can produce finer circuits to respond to higher wiring density circuit boards; the typical method is electroless copper plating. A seed layer is formed on the insulating circuit board, and then a circuit layer is directly formed on the insulating layer. This method can be further divided into a full-additive method and a semi-additive method. Two processes. At present, a typical process for making a semi-additive method for making thinner circuits is shown in FIG. 3; first, referring to FIG. 3A, a core circuit board 301 includes a patterned The circuit layer 302, an insulating layer 303 between the two circuit layers 302, and a plated-through hole 304 for electrical interconnection between the circuit layers 302. Two organic insulating layers 305 are vacuum-bonded on the surface of the core circuit board 301, as shown in FIG. 3B; then, referring to FIG. 3C, most of the blind holes 306 are formed in the organic insulating layer 305, and the organic insulating layer An electroless copper thin layer 307 is formed on the surface of 305, and a patterned resist layer 308 is disposed on the electroless copper thin layer 307. Opening in the resist layer by electroplating A circuit layer 309 is formed in 310, as shown in FIG. 3D. After that, the resist layer 308 and a part of the electroless copper thin layer 307 are removed, and a four-layer circuit board 300 of an incremental type is completed. The four-layer circuit board The 300 series includes a core circuit board 301 and two build-up structures 311, and the build-up structure 311 includes an organic insulating layer 305 and a circuit layer 309, and the circuit layer 309 is formed by a conventional circuit formation. Made by the method, as shown in Figure 3E.

The package substrate made by the aforementioned process can already process the wire size of the circuit layer to 20 ~ 30μm, and can be applied to higher-efficiency chips and packages. However, if you want to increase the precision of the wire to improve the wiring Density, there is a problem that the process accuracy cannot be overcome; in addition, when drilling holes in these insulating layers to form blind holes, a large amount of slag is easy to remain, and the slag will become a blind hole and conduct with the inner layer conductor after electroplating Bad reasons, resulting in deterioration of connectivity and even disconnection, leading to increased difficulty in substrate manufacturing process and decline in process yield.

Furthermore, in the above-mentioned conventional semi-additive method, such as a layered technology, the seed layer of the current conduction path of the circuit layer formed by electroplating, that is, the electroless copper thin layer, is formed by Since the material is the same as the circuit layer formed, all of which are metallic copper, and when the seed layer is removed by subsequent etching, the circuit layer will be subject to side erosion and shrinkage and deformation. This is especially the case for the formation of thin wires. Circuit boards with high accumulation density will cause severe contraction and deformation of the circuit.

In addition, in order to meet the demand for electronic products to shrink and increase functions, the circuit design of circuit boards is becoming more and more dense, and is limited by the area and thickness of the circuit board. If the complexity of the circuit increases, it must be increased by adding layers. The layers are becoming thinner and smaller, and the tighter the circuit of the circuit board, or the thinner the layers are, due to the characteristics of the material, it is possible that the conductive copper particles that make up the circuit are possible when the circuit is conducting. It migrates and diffuses and penetrates into the insulation layer, so that copper particles migrate from the insulation part between two adjacent lines.

And because the two lines, or the layers are very dense, the insulating part is relatively small. When copper particles migrate, the conductive copper particles in the insulating layer of the insulating part cause the insulation. The effect is reduced. In this way, it is easy to cause a short circuit between the two lines or between layers, making the circuit board unable to operate normally; and as the usage time increases, the phenomenon of copper particle migration will become more obvious, making the insulation The copper particles in the part keep increasing, so that the insulating part gradually becomes conductive and loses the effect of insulation.

And with the development trend of high-density circuits, layer-to-layer or circuit-to-line, because of material limitations and thinner and thinner insulation layers, how to overcome the phenomenon of copper atom migration has become the future. An important issue for the development of electronic products.

In view of the lack of the aforementioned conventional technology, the main object of the present invention is to provide a layered circuit board with a conductive barrier structure and a method for manufacturing the same. The phenomenon of metal particle migration avoids short circuits or interference, which enables densely laid out circuits of multi-layer circuit boards, and makes layers between layers thinner and smaller, so as to make circuit boards with more layers.

Another object of the present invention is to provide a layered circuit board with a conductive barrier structure and a manufacturing method thereof, so as to avoid etching and removing the seed layer which is commonly used for electroplating, and also damage the formed circuit layer. problem.

Another object of the present invention is to provide a layered circuit board with a conductive barrier structure and a method for manufacturing the same. The circuit layer is covered with a metal barrier layer, so that the circuit layer and the insulation can be enhanced by the metal barrier layer. Layer adhesion.

Another object of the present invention is to provide a layered circuit board with a conductive barrier structure and a method for manufacturing the same. The insulating layer between the circuit layers first forms an opening, and then a conductive metal layer is formed by electroplating in the opening. The conductive metal layer is electrically connected to the circuit layers on both sides of the insulating layer, and the via structure is not known to simplify the manufacturing process.

Another object of the present invention is to provide a layered circuit board with a conductive barrier structure and a manufacturing method thereof, so as to form an asymmetric structure with stacked through holes and fine lines.

To achieve the above object, the present invention provides a layered circuit board with a conductive barrier structure and a method for manufacturing the same. The preferred implementation steps include: providing a conductive base layer and forming a conductive base layer thereon. Patterning the first resistance layer, forming the first resistance layer to expose the conductive base layer outside the opening, and passing through the conductive base layer to form a first circuit layer by electroplating in the opening, and then removing the first resistance layer, The first circuit layer is exposed, and then a build-up process is used to form at least one patterned insulation layer on the first circuit layer, and the insulation layer has a circuit layer exposed and covered thereunder outside the opening. And forming a conductive metal layer by electroplating in the opening, then forming a seed layer on the surface of the insulating layer and the conductive metal layer, and forming a patterned second resist layer on the surface of the seed layer, And the second resistive layer has the seed layer exposed outside the opening, and a second circuit layer is formed by electroplating in the opening, and then the second resistive layer and the seed layer covered by the second resistive layer are removed to make the second circuit layer After being exposed, a metal barrier layer is formed on the surface of the second circuit layer. After that, an insulating layer and a circuit layer can be continuously formed on the second circuit layer, and a metal resist layer is formed on the surface of the circuit layer. After the electroplating process is completed, the conductive base layer can be removed as a conductive path for the plating current. The surface of the first circuit layer is exposed outside to complete the layered circuit board with the conductive barrier structure of the present invention.

Through the aforementioned process, the present invention also provides a layered circuit board with a conductive barrier structure. The circuit board mainly includes: a first circuit layer formed by electroplating through a conductive base; at least one An insulating layer is formed on the first circuit layer, and the insulating layer has a conductive metal layer formed by electroplating through the conductive base layer to be electrically connected to the first circuit layer; at least one seed layer; ), Is patterned on the surface of the insulating layer, and electrically connects the seed layer to the conductive metal layer; at least one second circuit layer, The conductive base layer is formed on the seed layer, and is electrically connected to the first circuit layer through the conductive metal layer; and at least one metal barrier layer is coated on the surface of the second circuit layer.

In the present invention, the surface of the circuit layer is covered with a metal barrier layer, such as a group consisting of chromium (Cr), nickel (Ni), cobalt (Co), palladium (Pd), tantalum (Ta), and titanium (Ti). One of them is to suppress the migration of metal particles between layers or adjacent circuits, so the insulation layer in the circuit board can be thinner and lighter, so that a thinner and lighter multilayer circuit board can be produced. At the same time, the metal barrier layer (for example, using chromium metal) can be used to inhibit the migration of metal particles, and can also be used to enhance the adhesion between the circuit layer and the insulating layer, so that the circuit layer is tightly bonded to the insulating layer to avoid Occurrence of detachment results in better use. Furthermore, in the layer-increasing technology of the present invention, it is used as a current conduction path for forming a circuit layer by electroplating. The material of the seed layer can be a metal barrier material different from the copper material of the circuit layer. When seeding the layer, the shrinkage and deformation of the circuit layer due to side etching can be avoided, and the circuit layer formed on the seed layer can provide a good effect of suppressing the migration of metal particles; and the conductive metal layer of the insulating layer can be used Electrically connect the circuit layers between the build-up layers without knowing the via structure to simplify the process.

In addition, the present invention is to build a first, a second circuit layer, or more layers on the conductive base layer, and the layer build-up process is performed only on a single surface of the conductive base layer, which is an upper and lower asymmetric structure.

In order to make the purpose, features, and effects of the present invention more understandable and agreeable, the detailed description with the drawings is as follows. Of course, the present invention can be many This form of implementation is described below as a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Please refer to FIGS. 1A to 1K, which are schematic cross-sectional views of a manufacturing method of a conductive barrier structure according to an embodiment of the present invention.

As shown in FIG. 1A, a conductive base layer 10 is first provided. The conductive base layer 10 is mainly made of metal copper, and the conductive base layer 10 is mainly used to form the main current of the circuit layer by electroplating in the circuit board. Conduction path.

A patterned first resist layer 11 is formed on one surface of the conductive base layer 10, and the first base layer 10 is formed with a plurality of openings 110 to expose the conductive base layer 10. The first resist layer 11 may be, for example, a photoresist layer such as a dry film or a liquid photoresist, and the first resist layer 11 may be formed by a patterning process such as exposure and development. The plurality of openings 110 are used to expose a part of the conductive base layer 10.

As shown in FIG. 1B, the first circuit layer 13 is formed by electroplating through the conductive base layer 10 as a current conduction path in the opening 110 of the first resist layer 11, and the first circuit layer 13 is electroplated. The material is mainly electroplated gold or nickel / gold metal layer or even copper plating layer. For example, after electroplating a layer of gold, electroplating a layer of nickel and copper thereon, the conductive base layer is removed after the final electroplating process is completed. 10 Sometimes, the gold or nickel / gold metal layer in the first circuit layer 13 is exposed on the surface of the circuit board, and is used as an electrical connection pad for connecting conductive elements.

As shown in FIG. 1C, the first resist layer 11 is then removed to reveal the First circuit layer 13.

As shown in FIG. 1D, a patterned first insulating layer 14 is formed on the exposed first circuit layer 13, and the insulating layer 14 has a portion of the first circuit layer 13 exposed outside the opening 140. The first insulating layer 14 may be a photo-sensitive insulating layer, for example, a material such as a photoimageable resin, and the photo-sensitive insulating layer is exposed by lithography technology (Exposure). Processes such as development and development are used to selectively form the openings 140, so that the first circuit layer 13 exposes the openings 140. In addition, the insulating layer may also be a thermosetting resin for forming an opening 140 by using laser-via. However, the opening 140 is preferably formed by using a photosensitive insulating layer through lithography technology. .

As shown in FIG. 1E, an electroplating process is performed to pass the conductive base layer 10 as a current conduction path, and a conductive metal layer 141 is formed in the opening 140 of the first insulating layer 14, and the conductive metal layer 141 is electrically Sexually connected to the first circuit layer 13.

Next, a seed layer 15 is formed on the outer surfaces of the first insulating layer 14 and the conductive metal layer 141, and the seed layer 15 is electrically connected to the conductive metal layer 141. The conductive base layer, the first A circuit layer, a conductive metal layer, and a seed layer serve as a current conduction path required for electroplating to form a subsequent patterned build-up structure.

The seed layer 15 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition, such as sputtering, evaporation, and arc vapor deposition ( Arc vapor deposition, ion beam sputtering, laser ablation deposition, plasma-assisted chemical vapor deposition, or electroless plating; in addition, to avoid subsequent plating after the circuit layer is completed That is, the circuit layer generated when removing part of the seed layer is contracted and deformed by side erosion, and metal particles migrate. The material of the seed layer can be different from the circuit layer (metal copper) material. The barrier metal is, for example, one of the group consisting of chromium (Cr), nickel (Ni), cobalt (Co), palladium (Pd), tantalum (Ta), and titanium (Ti). And the resistance values of these barrier metals at room temperature are: nickel (13 μ Ω-cm), chromium (6.84 μ Ω-cm), cobalt (6.24 μ Ω-cm), palladium (10.8 μ Ω-cm) , Tantalum (11.5μ Ω-cm), titanium (80μ Ω-cm) (see John, Wiley & Sons, Inc. (Modern Electroplating) published in 2000, and the resistance value of copper is 1.673 μ Ω-cm, so these barrier metals are good conductors of electricity.

In addition, the inventor in a previous study sputtered a 1 μ chromium layer on an organic material as a conductive layer, and then used copper sulfate as a plating solution to form a 20 μ copper layer by electroplating. Based on this experiment, it can be inferred that chromium (Cr), nickel (Ni), cobalt (Co), palladium (Pd), tantalum (Ta), and titanium (Ti) as low-resistance values can be electroplated smoothly on it. Form a circuit layer made of copper.

As shown in FIG. 1F, a patterned second resist layer 16, such as a dry film or a liquid photoresist, is formed on the surface of the seed layer 15, and the second resist layer 16 has a portion of the seed layer exposed outside the opening 160.

As shown in FIG. 1G, an electroplating process is performed to pass through the conductive base layer 10, the first circuit layer 13, the conductive metal layer 141, and the seed crystal. The layer 15 serves as a current conduction path, and a second circuit layer 17 is formed on the seed layer in the opening 160 of the second resistive layer 16, and the second circuit layer 17 is electrically conductive by the conductive metal layer 141. Connected to the first circuit layer 13.

As shown in FIG. 1H, the second resistive layer 16 and a part of the seed layer 15 covered by the second resistive layer 16 are removed to expose the second circuit layer 17. And when removing part of the seed layer 15, because the material is different from the formed circuit layer, the size of the circuit layer will not be destroyed when it is removed by etching or the like, which will cause the circuit to shrink and deform and even affect it. Problems such as electrical continuity.

As shown in FIG. 1I, the surface of the exposed second circuit layer 17 continues to penetrate the current conduction path formed by the conductive base layer, the conductive metal layer, and the circuit layer, and the surface of the second circuit layer is suppressed by electroplating. The metal barrier layer 18 for migration of metal particles is used to cover and isolate the second circuit layer 17 by the metal barrier layer 18. The material of the metal barrier layer 18 is, for example, one of the group consisting of chromium (Cr), nickel (Ni), cobalt (Co), palladium (Pd), tantalum (Ta), and titanium (Ti).

Because the present invention uses the conductive base layer 10 as the current conduction path required for the electroplated metal layer to first fabricate the first circuit layer 13, and then to form the insulating layer 14 for layering, and the second circuit layer 17, The second circuit layer 17 is coated with the metal barrier layer 18, so that the metal barrier layer 18 or even the seed layer 15 having conductive resistance characteristics can be used to cover and block the second circuit layer 17 mainly composed of copper, to avoid The phenomenon of copper particles migration can make the wiring of the circuit layer closer, without causing short circuit or interference.

As shown in Figure 1J, the circuit can be further increased in accordance with the foregoing steps to form a second insulating layer on the circuit layer on the surface of the increased layer structure of the circuit. 14 ', and a conductive metal layer 141' is electroplated in the opening of the second insulating layer 14 'according to the above steps, and a stacked via is formed by the conductive metal layers and the circuit layer previously. ) 19 in the circuit board. In addition, the current conducting path formed by the conductive base layer 10 can be used to continuously form a metal protective layer such as nickel / gold on the surface circuit of the circuit board to protect the surface circuit of the circuit board. Conductive components, such as gold wires, bumps, pre-solders or solder balls, have good electrical conductivity with the chip or circuit board, or even can be directly plated on the surface of the circuit with a pre-solder material for power supply connection to External device (not shown).

As shown in FIG. 1K, after the layered structure of the multilayer circuit board is completed, the bottommost conductive base layer 10 must be removed, and the first circuit layer 13 is exposed outside to complete a multilayer circuit board.

The circuit board with a conductive barrier structure in the present invention uses the conductive base layer 10 as a current conduction path to directly form circuit layers 13 and 17 thereon, and a metal barrier layer 18 is formed on the surface of the circuit layer by electroplating. Effectively suppress the migration of copper particles between adjacent circuits, so the insulation part of the circuit board can be thinner and thinner, so it is possible to make thinner and thinner multilayer asymmetric circuit boards. In addition to the metal barrier layer 18 being used to suppress the migration of metal particles, when the barrier layer is chromium, it can also be used to enhance the adhesion between the circuit layer 17 and the insulating layer 14 so that the circuit layer 17 is tightly bonded. On the insulating layer 14, the occurrence of detachment is avoided, and a better use effect is provided.

An opening 140 is formed in the insulating layer 14 between the first circuit layer 13 and the second circuit layer 17, and then a conductive metal layer 141 is formed in the opening 140. The first circuit layer 13 and the second circuit layer 17 are connected by a conductive metal layer 141, so that a layer can be added to make a circuit by stacking. Without a conventional structure, a conductive via must be made first, and then the material is filled. The inconvenience and inconvenience, so the process must be simplified to reduce manufacturing costs.

In addition, since the present invention sequentially stacks and makes the first circuit layer 13 and the second circuit layer 17 on the conductive base layer 10 by using its current conduction path, it can continue to stack and make another insulating layer and circuit layer according to the above manufacturing method. To become an asymmetric circuit board structure.

In summary, the above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of patent applications described below. The completed technical entity or method, if it is exactly the same as defined in the patent application scope described below, or the same equivalent change, will be considered to be covered by this patent application scope.

<p>10. . .Conductive substrate</p><p>11. . .First barrier layer</p><p>110. . .Opening</p><p>13. . .First circuit layer</p><p>14. . .First insulation layer</p><p>140. . .Opening</p><p>141,141 '. . .Conductive metal layer</p><p>14 '. . .Second insulation layer</p><p>15. . .Seed layer</p><p>16. . .Second barrier layer</p><p>160. . .Opening</p><p>17. . .Second circuit layer</p><p>18. . .Metal barrier</p><p>201. . .Insulation</p><p>202,203. . .Circuit layer</p><p>204. . .Electroplated metal</p><p>205. . .Filling material</p><p>206. . .Insulation</p><p>207. . .Circuit layer</p><p>208. . .Plating</p><p>209. . .Filling material</p><p>210. . .Insulation</p><p>211,212. . .Circuit layer</p><p>213. . .Conductive material</p><p>300. . .Four-layer circuit board</p><p>301. . .Core circuit board</p><p>302. . .Circuit layer</p><p>303. . .Insulation</p><p>304. . .Plated via</p><p>305. . .Organic insulation</p><p>306. . .Blind hole</p><p>307. . .Electroless copper thin layer</p><p>308. . .Barrier layer</p><p>309. . .Circuit layer</p><p>310. . .Barrier opening</p><p>311. . .Layered structure</p>

Figures 1A to 1K are schematic cross-sectional views of a method of manufacturing a circuit board with a conductive barrier structure according to the present invention; Figure 2A is a schematic view of a plated via structure of a conventional technique; Figure 2B is a plated layer of a conventional technique after deposition Schematic diagram of the blind hole structure filled with filling material in the depression; Figure 2C is a schematic diagram of the blind hole structure completely filled with conductive material in the conventional technology; and Figures 3A to 3E are used to make finer details in the conventional technology. Schematic of the semi-additive process of the circuit.