Method and apparatus for forming a thin semiconductor film, method and apparatus for producing a semiconductor device, and electro-optical apparatus

Method and device for forming thin semiconductor film, method and device for manufacturing semiconductor device, and electro-optical device

Background of the invention

1. Field of Invention

The present invention is directed to a method and device for forming a thin semiconductor film such as a polycrystalline silicon film on a substrate, a method and device for manufacturing a semiconductor device having such a thin semiconductor film formed on a substrate, and an electro-optical device Device.

2. Description of related skills

Traditionally, vapor phase deposition (such as plasma enhanced chemical vapor deposition (CVD), reduced pressure CVD, and catalytic CVD), solid phase growth, liquid phase growth, and excimer laser annealing are used (excimer laser annealing) is used to deposit polycrystalline silicon film to form the drain and channel regions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), such as MOSTFT (Metal Oxide Semiconductor Thin Film Transistor; Metal oxide semiconductor thin film transistors).

For example, in Unexamined Japanese Patent Application No. 7-13030, Unexamined Japanese Patent Application No. 9-116156, and Examined Japanese Patent Application No. 7-118443, an improvement by plasma-enhanced CVD or reduced pressure CVD was published. The carrier mobility of the amorphous or microcrystalline silicon film formed by the process is converted into a polycrystalline form by high temperature annealing or excimer laser annealing (ELA). The highest carrier mobility achieved by this technology is about 80 to 120 cm²/Vsec.

Because the MOSTET produced by using a polycrystalline silicon film formed by performing ELA on an amorphous silicon film deposited by plasma CVD has a relatively high electric power Sub-mobility (e.g. 100 cm²/Vsec), and form a MOSTFT suitable for high-precision applications. An LCD that uses a MOSTFT composed of polycrystalline silicon and has a driving circuit integrated on an LCD (liquid crystal display) has attracted attention (Unexamined Japanese Patent Application No. 6-242433). In the excimer laser annealing technology, the film in the leading form is irradiated with a short-wave short pulse laser beam (such as XeCl excimer laser), thereby melting and recrystallizing the film in a short working time. In this technology, the illuminance of the amorphous silicon film irradiated with a laser beam can convert it into a polycrystalline form without damaging the glass substrate. Another advantage of this technology is the high total processing power.

However, if the ELA technology is used to manufacture MOSTFTs, recrystallization will occur rapidly at the nanosecond (nsec) level during the excimer laser annealing process. Therefore, the polycrystalline silicon formed by the excimer laser annealing process The particle size is almost about 100 nanometers (nm). Even if the substrate is heated to about 400°C during irradiation with a short-wave, short-pulse laser beam to remove hydrogen and oxygen that inhibit crystal growth, and to control the solidification rate, it is difficult to obtain a particle size larger than 500 nm. A known technique to avoid the aforementioned problem is to repeatedly perform laser irradiation several times (for example, 5 times or 30 times) to apply sufficient energy to obtain a polycrystalline silicon film with a large particle size. However, this technology has various other problems such as the instability of the output power of the excimer laser, and when large-sized devices are used, there are problems of increased cost and reduced yield/quality. Specifically, for large-sized substrates such as 1mx1m, the problems described above are very serious, and it is extremely difficult to achieve high performance/quality at low cost.

For example, in the recently published Unexamined Japanese Patent Application No. 11-97353 In the technique of forming a crystalline silicon film, the amorphous silicon film is heated to 450°C to 600°C for a period of 4 to 12 hours, so that the element (such as Ni, Fe or Co) used as a catalytic element diffuses. This enhances the crystallization of the amorphous silicon film. However, the problem with this technology is that the catalytic element remains in the formed crystalline silicon film. In order to avoid the aforementioned problems, Unexamined Japanese Patent Application No. 8-339960 published a technique for removing (inhaling with a getter) the catalytic element by one of the following methods: at room temperature containing halogens such as chlorine Perform a heating process; perform a heating process after selectively adding phosphorus to the crystalline silicon film; and use a laser beam or high-intensity light rays to irradiate the crystalline silicon film containing the catalytic element so that the catalytic element becomes easily diffused. Then by selectively adding elements, a getter is used to inhale the catalytic element. However, these methods are very complicated, the gettering effect of the getter is insufficient, the characteristics of the silicon semiconductor film are degraded, and the stability and reliability of the manufactured device are degraded.

On the other hand, in the method of manufacturing polycrystalline silicon MOSTFT by solid-phase growth, it is necessary to perform annealing treatment at a temperature higher than 600°C for a time length of 10 hours or more, and to form a gate by high-temperature thermal oxidation at 1000°C. Oxide SiO₂. In order to perform these processing steps, semiconductor production equipment must be used. This limits the diameter of the substrate size to 8 to 12 inches. Moreover, it is necessary to use expensive quartz glass to ensure that the substrate can withstand high temperatures. This makes it difficult to reduce costs, and therefore restricts applications to EVF, data/audio-visual projectors, etc.

In recent years, catalytic CVD technology has been developed, which is one of thermal CVD technology, and can deposit polycrystalline silicon film, silicon nitride, etc. on insulating substrates such as glass substrates at low temperature (Japanese patent application has been examined No 63-40314, Examined Japanese Patent Application No. 8-250438). Now this technology has been improved for practical use. In the catalytic CVD technology, although about 30cm can be obtained²/Vsec carrier mobility, without the need to perform crystallization annealing treatment, but the carrier mobility is still not enough to manufacture high-performance MOSTFT. Regarding the formation of a polycrystalline silicon film on a glass substrate, depending on the deposition conditions, an inversion layer (with a thickness of 5 to 10 nm) is formed on the amorphous silicon. This makes it difficult to obtain carrier mobility sufficient to manufacture a bottom-gate type MOSTFT. In LCDs that use polycrystalline silicon MOSTFTs and include integrated drive circuits, bottom injection gate-type MOSTFTs can improve production yield and productivity. However, the problems described above will encounter bottlenecks.

Summary of the invention

The object of the present invention is to provide a method for easily forming a high-quality, high-crystallinity polycrystalline or single-crystalline thin semiconductor film on a large area at low cost. Another aspect of the present invention is to provide an apparatus for manufacturing the semiconductor film according to the aforementioned method.

Another object of the present invention is to provide a method of manufacturing a semiconductor device such as a MOSTFT, wherein the semiconductor device includes a polycrystalline or single crystalline thin semiconductor film. Another object of the present invention is to provide an apparatus for manufacturing such a semiconductor device.

According to one aspect of the present invention, the present invention provides a method for manufacturing a thin semiconductor film and a semiconductor device including a thin semiconductor film, wherein a polycrystalline or single crystalline thin semiconductor film is formed on a substrate, or One includes a polycrystalline or single crystalline thin semiconductor film arranged on a substrate The semiconductor device is manufactured, and its manufacturing method includes: a first forming step for forming a thin semiconductor film of low crystalline quality on the substrate; and a second performing step for performing condensing light on the thin semiconductor film of low crystalline quality Annealing treatment to melt or semi-melt the low crystalline quality thin semiconductor film, or heat the low crystalline quality thin semiconductor film while the low crystalline quality thin semiconductor film maintains a non-melting state, and then cool the low crystalline quality thin semiconductor film, by This enhances the crystallization of the low crystalline quality thin semiconductor film.

According to another aspect of the present invention, the present invention provides a device for manufacturing a thin semiconductor film or a semiconductor device including a thin semiconductor film, wherein the device includes: a first forming device for forming a thin film on the substrate Crystalline quality thin semiconductor film; and a second execution device for performing a focused annealing process on the low crystalline quality thin semiconductor film to melt or semi-melt the low crystalline quality thin semiconductor film, or when the low crystalline quality thin semiconductor film When the semiconductor film is maintained in a non-melted state, the low crystalline quality thin semiconductor film is heated, and then the low crystalline quality thin semiconductor film is cooled, thereby enhancing the crystallization of the low crystalline quality thin semiconductor film.

According to another aspect of the present invention, the present invention provides an electro-optical device, which includes a cathode or anode disposed under the organic or inorganic electroluminescent layer of various colors, and connected to a thin semiconductor film composed of polycrystalline or single crystalline The drain or source of a thin film gate isolated field effect transistor, including the active element and a diode of the thin film gate isolated field effect transistor covered by the cathode, or the organic or inorganic electroluminescent layers of various colors The surface of and all areas between the organic or inorganic electroluminescent layers are covered by the cathode or anode.

According to another aspect of the present invention, the present invention provides an electro-optical device in which the emitter of a field emission display device is connected to a polycrystalline or single-crystalline thin semiconductor film through a polycrystalline or single-crystalline thin semiconductor film. The thin film gate isolates the drain of the field effect transistor, and the emitter of the field emission display device is formed by an n-type polycrystalline semiconductor film or an n-type polycrystalline semiconductor film formed on the polycrystalline or single-crystalline thin semiconductor film ( Polycrystalline diamond) film.

The present invention has the following advantages (1) to (10). This is because the feature of the present invention is that a single crystal or polycrystalline thin semiconductor is manufactured by using a thin semiconductor film of low crystal quality formed on a substrate. The method is to perform a concentrating annealing treatment on the low crystalline quality thin semiconductor film, thereby melting or semi-melting the low crystalline quality thin semiconductor film, or heating the low crystalline quality thin semiconductor film when the low crystalline quality thin semiconductor film maintains a non-melting state Thin the semiconductor film, and then cool the low crystalline quality thin semiconductor film, thereby enhancing the crystallization of the low crystalline quality thin semiconductor film.

(1) In the concentrating annealing process, the light emitted by the ultra-high pressure mercury lamp is focused into the desired form, and a thin semiconductor film of low crystal quality such as an amorphous silicon film is irradiated with focused light to reduce the low crystal quality The thin semiconductor film is heated to a molten or semi-melted state, or when the low crystalline quality thin semiconductor film is maintained in a non-melted state, the low crystalline quality thin semiconductor film is heated, and then the low crystalline quality thin semiconductor film is cooled. That is, in this method, high illuminance energy irradiated on a thin semiconductor film of low crystalline quality will heat the thin semiconductor film of low crystalline quality to a molten or semi-melted state, or when the thin semiconductor film of low crystalline quality maintains a non-melted state When heating the thin semiconductor film of low crystalline quality, Then, the thin semiconductor film of low crystalline quality is cooled, thereby obtaining a single crystalline semiconductor film or a large-grained polycrystalline semiconductor film such as a single crystalline silicon or a polycrystalline silicon film with high carrier mobility and high quality. This technology can greatly increase productivity and significantly reduce costs.

(2) In the concentrating annealing treatment according to the present invention, since the zone melting and recrystallization are performed when the melting zone is continuously moved, the pre-added catalytic element (such as Ni) and other impurities used to strengthen the crystallization are isolated It becomes a melted zone, so such catalytic elements or impurities can be easily removed. Therefore, no impurities remain in the resulting annealed film. In this way, a polycrystalline thin semiconductor film of large particle size, high carrier mobility, and high quality (high purity) can be easily obtained. Specifically, if multiple-zone melting and recrystallization are performed by repeatedly performing melting and cooling using a plurality of condensing rays emitted from a plurality of lamps, a larger particle size and high-quality (high-purity) polycrystal can be obtained. Thin semiconductor film. The high purity obtained by this technology can produce highly stable and highly reliable devices without degrading semiconductor characteristics. In addition, in the concentrating annealing technology, a simple process is used to perform zone melting and recrystallization or multiple zone melting and recrystallization, which can efficiently remove the catalytic elements that have completed the enhancement of the crystallization role, and can also be highly efficient Remove other impurities. Simplified manufacturing process can reduce costs.

(3) The crystal grains in the polycrystalline silicon film are arranged in the condensing scanning direction. Therefore, if the TFT is formed in this direction, the mismatch and stress at the edge of the crystal grains can be minimized, and the resulting polycrystalline thin silicon film has high mobility.

(4) If concentrating annealing treatment technology is used to recrystallize by zone melting Or multi-zone melting and recrystallization to form another low-crystalline silicon film on the polycrystalline silicon film, and if the crystallization is performed again using the concentrating annealing process, a thicker, large-grained, high-carrier mobility can be formed And high crystalline quality polycrystalline silicon film. By repeatedly performing this process, a total thickness on the order of several microns can be obtained. In this way, not only MOS LSI can be manufactured, but also other types of devices such as bipolar LSI, CMOS sensor, CCD area/linear sensor, and solar battery can be manufactured with high efficiency and high quality.

(5) Regardless of whether an ultraviolet (UV) lamp or an infrared lamp is used, it is easy to focus the light emitted by the lamp into a linear, rectangular or square shape, and it can emit light continuously. In addition, the beam size and scanning pitch can be arbitrarily set. High light intensity can increase melting efficiency and total processing capacity, so cost reduction can be achieved.

(6) It is easy to control the wavelength, light intensity and irradiation time of the lamp used in the concentrating annealing treatment device. In addition, the heating/melting speed and cooling speed can be controlled by controlling the speed of moving the substrate or lamp. By controlling these parameters, a polycrystalline silicon film with desired particle size and purity can be formed.

(7) The lamp used in the concentrating annealing treatment device is cheaper than the excimer laser generator used in the excimer laser annealing treatment device, so a significant cost reduction can be achieved.

(8) In the concentrating annealing process, especially in the annealing process using ultra-high pressure mercury lamps, light with the same wavelength as the XeCl excimer laser (wavelength: 308 nm) can be used to continuously irradiate the entire film surface with a small change in energy. , The resulting crystallized semiconductor film has consistent characteristics, and There is little variation in characteristics between devices for manufacturing TFTs. Therefore, high total processing capacity and high productivity can be achieved, thereby reducing costs.

(9) Concentrating annealing process can be used at low substrate temperature (200 to 400°C). Therefore, low-strain-point glass or heat-resistant resin can be used as the substrate material, and a large-area substrate can be manufactured at low cost. Therefore, weight and cost reduction can be achieved.

(10) The use of single-crystal or poly-crystal semiconductor films with high carrier mobility formed by concentrating annealing technology can not only manufacture top-gate type TFTs, but also other TFTs. , Such as bottom-gate type (bottom-gate type) MOSTFT and dual-gate type (dual-gate type) MOSTFT. Therefore, high-efficiency semiconductor films can be used to manufacture high-speed and high-current semiconductor devices, electro-optical devices, and high-efficiency solar storage batteries. Specific examples of devices that can be manufactured by this technology include: silicon semiconductor devices, silicon semiconductor integrated circuits, silicon germanium semiconductor devices, silicon germanium semiconductor integrated circuits, silicon carbide semiconductor devices, silicon carbide semiconductor integrated circuits, composite semiconductors ( Such as GaAs) devices, composite semiconductors (such as GaAs) semiconductor integrated circuits, polycrystalline diamond semiconductor devices, polycrystalline diamond semiconductor integrated circuits, liquid crystal displays, (inorganic/organic) electroluminescent displays, field emission displays (FED) , Light-emitting polymer display, light-emitting diode display, photoreceptor, CCD area/linear sensor, CMOS sensor and solar battery.

In the present invention, the term "low crystalline quality thin semiconductor film" is used to describe a semiconductor film that has a physically amorphous structure and can contain microcrystalline (grain size less than 10 nm), and the term "polycrystalline thin semiconductor film" is used To describe the large particle size that can be obtained by removing non-crystalline components that may contain micro-crystals (Usually greater than 100 nm) physically polycrystalline structure. The term "single crystalline semiconductor film" is used to describe various single crystalline semiconductor films. Examples include single-component substrate single crystal semiconductors (such as single crystal silicon), single crystal composite semiconductors (such as single crystal silicon arsenide), and single crystal silicon germanium. Among them, crystals include sub-edges or dislocations that are also regarded as "single crystals." "Polycrystalline diamond film" represents a diamond film that does not substantially contain non-crystalline components but contains polycrystalline diamond components and microcrystalline diamond components.

1A to 1L show diagrams for explaining the sequence of processing steps for manufacturing MOSTFT according to the first specific embodiment of the present invention; FIG. 2 shows a cross-sectional view of a catalytic CVD device used in the production process, where the device is in a specific state; Figure 3 shows a cross-sectional view of the catalytic CVD device used in the production process, where the device is in another state; Figure 4A shows a schematic diagram of a concentrating annealing device; Figure 4B shows a schematic diagram of another concentrating annealing device; Figure 4C shows Fig. 4D shows a schematic diagram of another concentrating annealing device; Fig. 5 shows a schematic diagram of a cluster device used to fabricate MOSTFT; Figs. 6A and 6B show a schematic diagram of a cluster device used to fabricate MOSTFT Figure 7 shows a schematic diagram of another cluster device used to fabricate MOSTFT; Figure 8 shows a diagram for explaining the concentrating annealing process; Figures 9A to 9D show a diagram for explaining the concentrating annealing process Schematic of an example of the device; Figures 10A to 10L show a second specific embodiment according to the present invention Fig. 11 shows a perspective view of the general structure of LCD; Fig. 12 shows the equivalent circuit of LCD; Figs. 13A to 13G show the process steps for manufacturing LCD according to specific embodiments of the present invention Sequence cross-sectional view; Figures 14A to 14C show cross-sectional views to illustrate the use of various MOSTFTs in LCD; Figures 15A to 15C show cross-sectional views to illustrate another example of the process sequence for manufacturing LCD; Figures 16A to 16B show Diagrams used to illustrate the graphoepitaxial growth process; Figures 17A to 17F show cross-sectional views used to illustrate various types of stepped recesses; Figures 18A to 18C show another process sequence used to illustrate LCD manufacturing Figure 19A shows the equivalent circuit of the main component of the organic EL display according to the third embodiment of the present invention; Figure 19B shows a cross-sectional view for explaining the main component; and Figure 19C shows a diagram for explaining the peripheral part of the pixel Figures 20A to 20D show diagrams illustrating another example of the process sequence for manufacturing an organic EL display; Figure 21A shows an equivalent circuit diagram of another main part of an organic EL display; Figure 21B shows an explanation of the main part And Figure 21C shows a cross-sectional view to explain the peripheral part of the pixel; Figures 22A to 22D show to explain the process of manufacturing an organic EL display Sequence diagrams of another example; Figure 23A shows the equivalent circuit of the FED main part according to the fourth embodiment of the present invention; and Figures 23B and 23C show the cross-sectional view and plan view of the FED main part; Figures 24A to 24H show A diagram to illustrate an example of the processing sequence for manufacturing an FED; Figure 25A shows the equivalent circuit of another FED main component; and Figures 25B and 25C show a cross-sectional view and a plan view of the FED main component; Figures 26A to 26H show for illustration A diagram of an example of the processing sequence for manufacturing FED; and FIGS. 27A to 27C show diagrams for explaining the sequence of processing steps for manufacturing a solar storage battery according to the fifth embodiment of the present invention.

Detailed description of preferred specific embodiments

In the present invention, the preferred way to perform the concentrating annealing treatment is to use the condensed rays emitted by the lamp to scan the entire substrate placed in a fixed position to promote the occurrence of zone melting and recrystallization, or to use a complex number emitted by a plurality of lamps. A concentrating ray scans the entire substrate placed in a fixed position to promote the occurrence of multiple zone melting and recrystallization. In this case, scanning is achieved by moving the condensing rays to maintain the substrate at a fixed position, or moving the substrate without moving the condensing rays.

In this concentrating annealing technology, a thin semiconductor film of low crystalline quality such as an amorphous silicon film is partially melted or semi-melted, and then cooled part by part while moving (scanning) the melted or semi-melted silicon part, by using The method of zone melting and recrystallization forms a large-grain single crystal or polycrystalline thin semiconductor film.

During the previous annealing process, the catalytic element and other impurities are concentrated (isolated) into high-temperature areas, and the single crystal or polycrystalline thin semiconductor film obtained after cooling does not contain any remaining impurity elements. In the case of repeatedly performing heating and cooling using a plurality of condensing rays, multiple zone melting and recrystallization will occur, so the single crystal or polycrystalline thin semiconductor film produced has a larger particle size and higher purity.

By repeatedly performing zone melting and recrystallization or multiple zone melting and recrystallization as needed, a single crystal semiconductor film or a large-grain polycrystalline semiconductor film with a thicker thickness (for example, on the order of several microns) can be manufactured. That is, after the single crystal semiconductor film or the large-grain polycrystalline silicon film is formed by performing the first concentrating annealing process, another thin semiconductor film of low crystal quality is formed on the single crystal or polycrystalline semiconductor film. Afterwards, by performing a second concentrating annealing process, the low-crystalline quality thin semiconductor film is converted into a single crystal form or a large-grained polycrystalline form. If necessary, the previous process may be repeated several times to obtain a single crystal semiconductor film or a large-granularity polycrystalline semiconductor film with a thickness of several micrometers.

In the above-mentioned multilayer film formation process, the single crystal semiconductor film or the large-granularity polycrystalline semiconductor film below provides the crystal growth nucleus, based on which the crystal grains in the lower film and the upper film are grown into better Crystallinity of larger grain size crystal grains. Therefore, in this multilayer film formation process, whenever a film is deposited on the previously formed film and an annealing treatment is performed, the crystal grain size becomes larger and the purity becomes higher. Please note that such thick semiconductor films belong to the category of "thin semiconductor films" according to the present invention.

The lamp used in the concentrating annealing process as mentioned above may be selected from Any type of lamp in the group consisting of ultraviolet (UV) lamps, near ultraviolet lamps, deep ultraviolet (DUV) lamps, visible light lamps and infrared lamps. The appropriate lamp can be selected based on the degree of heat resistance of the selective substrate. UV lamp and DUV lamp are suitable for performing low temperature annealing treatment on the film on the glass substrate. The infrared lamp is suitable for performing high-temperature annealing treatment on a film on a quartz substrate or a crystallized glass substrate. The radiated light rays can be focused into rectangles or squares to improve melting efficiency and overall processing capacity. Specific examples of UV lamps include high-pressure mercury lamps, ultra-high-pressure mercury lamps, and xenon short-arc lamps. Specific examples of DUV lamps include low-pressure mercury lamps and xenon mercury lamps. Specific examples of infrared lamps include halogen lamps, xenon lamps, and arc lamps.

The light emitted by the lamp can be divided into UV components, visible light components, and infrared components, and the divided components can be used to continuously irradiate the substrate in the order of visible light components, infrared components, and UV components. In this process, a thin semiconductor film or substrate with low crystalline quality is preheated by visible light components and infrared components before being heated by UV components. Another advantage of this technology is that the film cooling rate is slower, so crystallization can be increased.

The light of the light rays emitted by the ultra-high pressure mercury lamp can be focused into the desired form, for example, the following steps are performed: (1) After the light rays emitted by the ultra-high pressure mercury lamp are focused into the desired shape, the light rays are passed through a cold semi-transparent mirror. Divided into UV component, visible light component and infrared component. (2) The thin semiconductor film of low crystalline quality is irradiated with the UV component so that the UV component enters the film at a substantially right angle, thereby melting or semi-melting one by one and cooling the film, thereby crystallizing the film. (3) The visible light component and infrared component are irradiated on the substrate and the thin semiconductor film of low crystal quality to heat it.

In the previous irradiation process, if a thin semiconductor film of low crystalline quality is to be melted in a high-efficiency manner and the substrate is heated, it is desirable to meet the following conditions: 1. The part irradiated with the visible light component and the infrared component is larger than and includes the part irradiated with the UV component.

2. When using light rays to scan the film and substrate, the visible light and infrared components will be irradiated first, and then the UV components will be irradiated. In addition to the local heating as described above, it is further desirable to use electric wire heaters, infrared lamps, etc. to heat the entire substrate.

The heating of the substrate can also be accomplished by blowing hot air against the substrate during the concentrating annealing process. For example, blowing hot air or inert gas (such as nitrogen) at a temperature of 100 to 400°C against the front or back of the substrate or against the front and back of the substrate to make the substrate have a uniform temperature distribution, which can uniformly crystallize the film and reduce crystallization To reduce the stress of the film and the substrate and achieve cooling at a slower rate.

As mentioned above, during the annealing process using concentrated light, depending on the substrate material, it is desirable to heat the substrate to a temperature below the strain point using an electric wire heater, infrared lamp line or laser beam. Specifically, for glass substrates, the substrate is heated to 200 to 500°C, and preferably to 300 to 400°C. On the other hand, for a quartz substrate, the substrate is heated to 200 to 800°C, and preferably to 300 to 600°C.

The concentrating annealing treatment can be performed by any of the methods (1) and (2) described below. (1) Maintaining the substrate at a fixed position, use a galvanometer to scan the entire substrate with UV rays focused into a square (for example, 100x100 mm), thereby performing annealing treatment on the substrate. (2) Maintain the UV rays focused into a square (for example, 100x100 mm) in a fixed state, and be precise in the X and Y directions The substrate is moved, thereby performing annealing treatment on the substrate.

In the present invention, a thin semiconductor film of low crystalline quality can be formed by catalytic CVD, plasma enhanced CVD, reduced pressure CVD or sputtering. In the case of film formation by vapor phase deposition, the source gas may be silicon hydride or its derivatives, a mixture of silicon hydride or its derivatives and a gas containing hydrogen, nitrogen, germanium, carbon or tin, silicon hydride or its derivatives Mixtures of substances and gases containing Group III or Group V elements, or of silicon hydride or its derivatives, gases containing hydrogen, nitrogen, germanium, carbon or tin, and gases containing Group III or Group V elements mixture.

For example, hydrogen-based carrier gas and source gas or at least a part of these two gases will contact a catalytic element heated to 800 to 2000°C (below the melting point) to deposit by catalytic reaction or thermal decomposition. Such as radicals or ions, and deposited on a substrate that has been heated to 200 to 400°C, thereby forming a low-crystalline quality semiconductor film. Alternatively, plasma CVD, reduced pressure CVD, sputtering, etc., which are widely used in the art, can deposit a low-crystalline quality semiconductor film on a substrate heated to 200 to 400°C.

Specific examples of thin semiconductor films of low crystalline quality formed in this technology include amorphous silicon films, amorphous silicon films containing microcrystalline silicon, microcrystalline silicon films (containing amorphous silicon), and those containing amorphous silicon and microcrystalline silicon. Polycrystalline silicon film, amorphous germanium film, amorphous germanium film containing microcrystalline germanium, microcrystalline germanium film (containing amorphous germanium), polycrystalline germanium film containing amorphous germanium and microcrystalline germanium, with Si_xGe_1-x(0<x<1) Composite amorphous silicon germanium film, amorphous carbon film, amorphous carbon film containing microcrystalline carbon, microcrystalline carbon film (containing amorphous carbon), containing amorphous carbon and microcrystalline carbon The polycrystalline carbon film, with Si_xC_1-x(0<x<1) Amorphous silicon carbon film of the composite and having Ga_xAs_1-x(0<x<1) Amorphous gallium arsenide film of composite. The basic structure of the thin semiconductor film of low crystalline quality is preferably amorphous. In the case where a thin semiconductor film of low crystalline quality contains microcrystals, it is desirable that the diameter of each microcrystal particle is less than 10 nm, and the microcrystal particles are dispersed.

During or after the growth of a thin semiconductor film of low crystal quality, if an appropriate amount (for example, a total of 10¹⁷To 10²⁰Atoms/cc (atoms/cc)) catalytic elements (at least selected from the group consisting of Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb and Sn) A catalytic element) is added to a thin semiconductor film of low crystal quality, and if the thin semiconductor film of low crystal quality containing such a catalytic element is annealed by the above-mentioned concentrated annealing treatment technology, the low crystal quality thin semiconductor film can be enhanced. The semiconductor film is crystallized into a polycrystalline form, and the resulting polycrystalline semiconductor film has higher carrier mobility and better crystal quality. The catalytic element can be mixed in the source gas by ion implantation or ion doping, or added to a thin semiconductor film with low crystallinity.

In the concentrating annealing treatment according to the present invention, because the melting zone is continuously moved and the melting zone is continuously moved, the partition melting and recrystallization are performed, so the pre-added catalytic element (such as Ni) and other impurities used to enhance the crystallization are isolated into melted Therefore, it is easy to remove such catalytic elements or impurities. Therefore, no impurities remain in the resulting annealed film. In this way, a polycrystalline thin semiconductor film of large particle size, high carrier mobility, and high quality (high purity) can be easily obtained. Specifically, if multiple-zone melting and recrystallization are performed by repeatedly performing melting and cooling using a plurality of condensing rays emitted by a plurality of lamps, a larger particle size and high quality (high purity) can be obtained. The polycrystalline thin semiconductor film. The high purity obtained by this technology can produce highly stable and highly reliable devices without degrading semiconductor characteristics. In addition, in the concentrating annealing technology, a simple process is used to perform zone melting and recrystallization or multiple zone melting and recrystallization, which can efficiently remove the catalytic elements that have completed the enhancement of the crystallization role, and can also be highly efficient Remove other impurities. Simplified manufacturing process can reduce costs.

The concentration of oxygen, nitrogen and carbon contained in the single crystal semiconductor film or the large-grained polycrystalline semiconductor film formed according to the present invention is preferably less than 1x10¹⁹ atoms/cc, less than 5x10¹⁹ Atoms/cc is the best, and the concentration of hydrogen is preferably greater than 0.01 atm% (atomic percentage).

In the above-mentioned concentrating annealing process example, a thin semiconductor film of low crystalline quality such as a low crystalline quality silicon film is converted into a thin semiconductor film of polycrystalline such as a polycrystalline silicon film. The concentrating annealing process according to the present invention can also be used to convert a thin silicon film of low crystalline quality into a single crystal form. For example, the way to achieve the conversion is to form stepped recesses of predetermined shape and size in the specific area of the substrate where the device is to be formed, and form a thin semiconductor film of low crystal quality (which may or may not contain one type) on the substrate with stepped recesses. Or more than one catalytic element), and then perform a concentrating annealing process, thereby using graphoepitaxy to grow monocrystalline silicon in the stepped recesses used as growth seeds.

The thin silicon form of low crystalline quality can also be converted into a single crystal form by the following steps. First, a crystalline layer of a material that can be lattice-matched to single crystal silicon (such as sapphire) is formed in the area on the substrate where the device is to be formed. Then, a thin silicon film of low crystalline quality (may or may not contain one or more catalytic elements) Is formed on the crystalline layer. After that, a concentrating annealing process is performed to grow single crystal silicon by hetero-epitaxial growth on the crystal layer used as a growth seed.

By repeatedly performing the combination of forming a thin silicon film of low crystalline quality and concentrating annealing treatment several times as needed, a single crystal semiconductor film with a thicker thickness (for example, several micrometers) or a large-grain polycrystalline semiconductor film can be manufactured. That is, after the single crystal semiconductor film or the large-grain polycrystalline silicon film is formed by performing the first concentrating annealing process, another thin semiconductor film of low crystal quality is formed on the single crystal or polycrystalline semiconductor film. Afterwards, by performing a second concentrating annealing process, the low-crystalline quality thin semiconductor film is converted into a single crystal form or a large-grained polycrystalline form. If necessary, the previous process may be repeated several times to obtain a large-granularity polycrystalline semiconductor film or a single crystalline semiconductor film with a total thickness on the order of several microns. In the process of forming a film in a layer-on-layer manner, the lower semiconductor layer in the form of single crystal or large-granularity polycrystalline form is used as the growth seed of the upper layer, so the particle size and purity of the upper semiconductor layer are higher than and Better than the underlying semiconductor layer. In the previous process, it is very important to prevent the low-quality oxide film from growing on the surface of the crystallized film through the annealing process, and to prevent the surface of the crystallized film from being impure due to impurities.

In order to avoid low-quality oxide films and contamination, and to improve productivity, the formation equipment (such as plasma enhanced CVD, decomposition CVD, or sputtering) for forming thin semiconductor films of low crystalline quality and concentrating annealing treatment equipment will be integrated In a single device, the step of forming a thin semiconductor film of low crystalline quality and the step of concentrating annealing treatment are performed in an integrated manner. Specifically, the construction of the device is in-line (including linear or rotary continuous processing chambers), multiple processing chambers, or cluster processing chambers, so that the aforementioned two steps can be performed continuously.

Among the various devices described above, the cluster formula (1) or (2) described below is the best.

(1) The first cluster integrated device includes a CVD unit and an annealing processing unit. First, in the CVD unit, a thin semiconductor film of low crystalline quality is formed on the substrate. After that, in the annealing treatment unit, the film is crystallized by light-concentrating annealing treatment. Then, the substrate returns to the CVD unit, and another thin semiconductor film of low crystalline quality is formed. Then, the substrate is transported to the annealing treatment unit again to perform crystallization by the concentrating annealing treatment. Repeat the steps described above as many times as necessary.

(2) The second cluster integrated device includes a first, a second, and a third CVD unit, an ion doping/implantation unit, and an annealing processing unit. First, in the first CVD unit, a first lower protective film (such as a silicon oxide/silicon nitride film) is formed on the substrate, and then in the second CVD unit, a thin semiconductor film of low crystal quality is formed. Afterwards, a catalytic element is added to the ion doping/implantation unit. In the annealing treatment unit, crystallization is performed by concentrating annealing treatment. In addition, in the third CVD unit, a gate insulating film (such as a silicon oxide film) is formed. Continue to perform the steps described above.

Before performing the concentrating annealing treatment again, it is best to clean the surface of the polycrystalline thin semiconductor film, or remove the low-quality oxide film on the surface of the polycrystalline thin semiconductor film, by means of hydrogen plasma discharge or by catalytic reaction (That is, by plasma treatment or atomic hydrogen annealing treatment) the hydrogen-based active species (hydrogen-based active species) produced are laid on the polycrystalline thin semiconductor film, and after the cleaning is completed, a low crystal quality thin semiconductor film is formed , And perform concentrating annealing treatment. In this case, its best to decompress hydrogen or contain reduced The concentrating annealing process is performed in a gas chamber under pressure of hydrogen gas or in a vacuum (such as a processing chamber that is usually desired when performing concentrating annealing treatment).

Specifically, the conditions (1) or (2) described below are optimal.

(1) Before the plasma-enhanced CVD film is deposited, only hydrogen-based carrier gas is supplied to the CVD chamber, and no source gas is supplied, and plasma treatment or AHA treatment is performed to expose the first The surface of the polycrystalline silicon film formed by the sub-focus annealing treatment to generate hydrogen-based active species (such as activated hydrogen ions), by removing surface contamination (low-quality oxide film, water, oxygen, nitrogen, carbon oxide, etc.) ), and in this way the cleaning sheet surface. In addition, in the plasma AHA process, the remaining amorphous silicon in the film is etched and the film is converted into a high crystallinity polycrystalline silicon film. When the next concentrating annealing process is performed after depositing a low-crystalline silicon film on the lower layer with the cleaned surface, this lower layer provides a crystallization seed, so a high-quality large-grain polycrystalline or single-crystalline semiconductor film can be obtained.

(2) In order to prevent oxidation and nitridation, it is desirable to perform the concentrating annealing treatment in a reduced-pressure hydrogen gas or a gas chamber containing reduced-pressure hydrogen gas or in a vacuum. Specifically, the treatment chamber used in the concentrating annealing treatment may be a mixture of hydrogen or hydrogen and an inert gas (such as argon, chlorine, krypton, xenon, neon, or radon), and the pressure is preferably 1.33 Pa to atmospheric pressure, and 133 Pa to 4x10⁴ Pa is the best. As far as vacuum is concerned, the air pressure is preferably 1.33 Pa to atmospheric pressure, and 13.3 Pa to 1.33x10⁴ Pa is the best. When a thin semiconductor film of low crystallinity quality is covered by a protective insulating film (such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxide/silicon nitride film), or when it is not necessary to continuously perform processing steps immediately In other words, the concentrating annealing treatment can be performed in air or atmospheric nitrogen.

If the concentrating annealing process is performed in a decompressed hydrogen or an environment containing decompressed hydrogen, the gas molecules in the ambient gas (having a specific heat and therefore a high cooling effect) will collide with the surface of the film, and when the gas molecules leave the film Will remove the heat of the film. As a result, low-temperature spots are formed locally, and crystal nuclei that can enhance crystal growth are generated at the local low-temperature spots. For the use of hydrogen or a mixture of hydrogen and inert gas (such as He, Ne, or Ar) as the ambient gas, it is best to set the gas pressure to 1.33 Pa to atmospheric pressure and 133 Pa to 4x10⁴ Pa is the best to ensure that the above-mentioned performance can be achieved by the movement of hydrogen molecules with a high specific heat.

In order to reduce the reflection of the focal light and increase the melting effect, it is best to form a protective insulating film (such as a silicon oxide film, a silicon oxynitride film or a silicon oxide/silicon nitride multilayer film) with an appropriate thickness on a thin semiconductor film of low crystal quality. Concentrating annealing treatment. When performing concentrating annealing treatment on a thin semiconductor film of low crystal quality formed on a substrate, or when performing concentrating annealing treatment on a thin semiconductor film of low crystal quality that has been coated with a protective insulating film, it is best to use the above or below The concentrated light emitted by the lamp irradiates the substrate (where the substrate is adjusted so that when the light comes from below, it can penetrate a wavelength of less than 400 nm).

A thin semiconductor film of low crystalline quality or a thin semiconductor film of low crystalline quality coated with a protective insulating film is preferably formed in the shape of one or more islands. It is preferable to perform the condensing irradiation in an atmospheric pressure nitrogen gas, a reduced pressure hydrogen gas, a gas chamber containing a reduced pressure hydrogen gas, or in a vacuum (such as an environment generally desired when performing condensing irradiation).

In order to reduce the increasing substrate temperature and film stress, and to avoid cracks caused by the instantaneous expansion of the gas (hydrogen) contained in the film, and also to To avoid the formation of crystal grains of too large a size due to the slow cooling rate, it is desirable to pattern the low crystal quality thin semiconductor film coated with the protective insulating film into an island form and then perform the concentrating annealing treatment.

It is better to perform the concentrating annealing treatment when a magnetic field or an electric field is applied.

In this annealing process, due to the mutual influence between the electric field and the electron spin of the silicon atoms in the melted part of the thin silicon film of low crystalline quality, the silicon atoms will be aligned in a specific direction. Therefore, when cooling and When the melted part is solidified, the part is crystallized in a specific direction. Therefore, in the case of applying a magnetic field, the crystal grains are aligned in a specific direction, so that improved carrier mobility can be achieved. In addition, irregularities on the film surface can be reduced. In addition, high light irradiation efficiency can be achieved.

During the concentrating annealing process, both electric and magnetic fields can be applied at the same time. This can be achieved by supplying high-frequency voltage (or DC voltage or both high-frequency voltage and DC voltage) to the electrodes, so that the magnetic field applied by permanent magnets (or electromagnets) arranged around the vacuum chamber where the substrate is placed When the electrode will apply an electric field.

In this annealing process, due to the interaction between the magnetic field and electric field and the electron spin of the silicon atoms in the melted part of the thin silicon film with low crystalline quality, the silicon atoms will be aligned in a specific direction. When the melted part is cooled and solidified, the part is crystallized in a specific direction. In this way, the arrangement of the crystal grains in a specific direction can be further enhanced, so that the carrier mobility can be further improved. In addition, irregularities on the film surface can be further reduced. In addition, high light irradiation efficiency can be achieved.

When performing concentrating annealing treatment, it is best to heat the substrate to below its strain It is best to heat the temperature to 400°C to 450°C, so that during the annealing process, the hydrogen removal of the thin semiconductor film with low crystalline quality will occur, and the crystallization will be more uniform. It will also reduce the stress of the film and the substrate, increase the irradiation efficiency, and increase the total processing capacity.

In this way, single or polycrystalline semiconductor films obtained by concentrating annealing can be used to form channels and source/drain regions of MOSTFT, or to form diodes, interconnections, resistors, capacitors, or electron-emitting elements . In this case, if the thin semiconductor film with low crystalline quality is patterned into the form corresponding to the channel, source region, drain region, diode, resistor, capacitor, interconnection, or electron emitting element (one or more islands) ) After performing concentrating annealing treatment, the n-type or p-type impurities in the film can be re-crystallized and activated by the annealing treatment. If the above-mentioned parts are patterned into islands and then subjected to concentrating annealing treatment, damage (cracking) of the substrate due to an increase in temperature can be avoided, and film rupture due to a rapid increase in temperature can also be avoided.

The advantage of the present invention is that it can be used to form films used in the following devices: silicon semiconductor devices, silicon semiconductor integrated circuits, silicon germanium semiconductor devices, silicon germanium semiconductor integrated circuits, silicon carbide semiconductor devices, silicon carbide semiconductor integrated circuits, Composite semiconductor device, composite semiconductor integrated circuit, polycrystalline diamond semiconductor device, polycrystalline diamond semiconductor integrated circuit, liquid crystal display, (inorganic/organic) electroluminescence (EL) display, field emission display (FED), luminescence Polymer display, light emitting diode display, photoreceptor, CCD area/linear sensor, CMOS or MOS sensor and solar battery.

Using this type of film, top injection gate type, bottom injection gate type or double gate type MOSTFT can be manufactured. Using this type of MOSTFT, a variety of electrical Circuits and devices, such as peripheral drive circuits, video signal processing circuits, liquid crystal displays with integrated memory, organic EL displays and FED devices.

When manufacturing semiconductor devices, electro-optical devices, or solid-state imaging devices containing built-in circuits and peripheral circuits, the above-mentioned polycrystalline or single-crystalline thin semiconductor film can be used to form at least one of the built-in circuits and peripheral circuits. The channel area, source area and drain area of MOSTFT. Various circuits can be integrated, such as peripheral drive circuits, video signal processing circuits and memory.

The EL device preferably has a structure in which the cathode or anode is arranged under the organic or inorganic electroluminescence (EL) layer of each color, and the cathode or anode is connected to the drain or source of the MOSTFT.

In this EL device, if active elements such as MOSTFT and diodes are also covered by the cathode, the light-emitting area can be added to the structure where the anode is arranged above. In addition, the cathode prevents the emitted light from entering the active device. This prevents leakage current. If the surface of the organic or inorganic EL layer of each color and all areas between the organic or inorganic EL layer are covered by the cathode or the anode, the organic EL layer and other electrodes can be prevented from degradation or oxidation due to moisture intrusion. This ensures extended service life, improved quality and reliability. In addition, the cathode covering the entire surface can enhance heat radiation. This can suppress structural changes (melting or recrystallization) of the organic EL film due to heat, and improve the service life, quality, and reliability. Using this technology, high-precision, high-quality, full-color organic EL layers can be manufactured at low cost and with high productivity.

In addition, chromium or chromium dioxide may be used to form a black mask layer in the area between the organic or inorganic EL layers of each color. The black mask layer prevents light mixing between different colors and between different pixels, so it can improve contrast.

When the present invention is applied to a field emission display (FED), it is preferable to connect the emitter (emission cathode) of the field emission display to the drain of the MOSTFT via a polycrystalline or single crystalline thin semiconductor film, and the emitter system is formed in the multicrystalline or single crystalline thin semiconductor film. It is formed by an n-type polycrystalline semiconductor film or an n-type polycrystalline diamond film on a crystalline or single-crystalline thin semiconductor film.

In this case, it is better to form a light-shielding metal film connected to the ground so that active elements such as MOSTFTs and diodes are covered by the light-shielding metal film via an insulating film (the same processing steps as those used to form FED gate lead electrodes can be used) And the same material directly forms a light-shielding metal film). If there is no such light-shielding metal film, when the gas existing in the sealed container is positively ionized by the electrons emitted by the emitter, the insulating film can be charged by the ionized gas, and the positive charge will cause the MOSTFT located under the insulating film An undesired inversion layer is formed, and excessive current will flow through the current path formed by the inversion layer, causing the emitter current to run out of control. When electrons emitted by the emitter collide with the phosphor, the phosphor emits light. The light emitted by the phosphor is blocked by the light-shielding metal film. Therefore, no electrons and holes are generated due to the light in the gate channel of the MOSTFT.

Hereinafter, the present invention will be described in further detail with reference to preferred specific embodiments.

The first specific embodiment

Hereinafter, the first specific embodiment of the present invention will be described with reference to FIGS. 1 to 9.

In the first specific embodiment, the present invention is applied to a top injection gate type polycrystalline silicon CMOS (Complementary MOS; complementary metal oxide semiconductor) TFT.

Catalytic CVD and its equipment

First, the catalytic CVD method used in this embodiment will be explained. In the decomposition CVD process, a reactive gas containing hydrogen-based carrier gas and a source gas such as silicon hydride comes into contact with heated catalytic elements such as tungsten to determine the type of radical deposition generated or its precursor and activation. Hydrogen-based active species such as hydrogen ions provide high energy, thereby using vapor phase deposition to grow thin semiconductor films of low crystalline quality on the substrate, such as microcrystalline silicon containing amorphous silicon.

The catalytic CVD can be performed using the apparatus shown in Figs. 2 and 3.

In this device, hydrogen-based carrier gas and source gas such as silicon hydride (for example, monosilane) 40 (and, if necessary, further doped) are added through the gas supply hole of the shower head 42 (not shown in the figure). Such as B₂H₆, PH₃Or SnH₄The gas) is supplied from the gas supply pipe 41 to the deposition chamber 44. A susceptor 45 has been deposited inside the deposition chamber 44 to support a substrate made of glass or the like. 1, made of a heat-resistant material (its melting point is preferably equal to or higher than the melting point of the catalytic element 46) The spray head 42 and the catalytic element 46 (such as tungsten in the form of a coil). In addition, the opening/closing light shielding plate 47 is arranged in the deposition chamber 44. Although not shown in the figure, a magnetic seal is provided between the sensitive body 45 and the deposition chamber 44, and the deposition chamber 44 is connected to the front chamber for performing pre-treatment. The deposition chamber 44 is evacuated by a turbo-molecular pump through a valve.

The substrate 1 is heated by a heating device such as a heater arranged in the sensitive body 45. The catalytic element 46 is constructed in the form of a resistance wire, so it can be heated to a temperature below the melting point (800 to 2000°C or 1600 to 1800°C in the case of tungsten). The two terminals of the catalytic element 46 are connected to the DC or AC catalytic element power supply 48, so that the current supplied by the catalytic element power supply 48 will accelerate The chemical element 46 is heated to a predetermined temperature.

In order to perform the catalytic CVD process using the device shown in Figure 2, the inside of the deposition chamber 44 is first evacuated to 1.33x10^-4To 1.33x10^-6 Pa pressure, and then supply hydrogen-based carrier gas at a flow rate of 100 to 200 SCCM. After heating the catalytic element to a predetermined temperature, the reaction gas 40 containing silicon hydride (such as monosilane, and if necessary, further containing such as B₂H₆Or PH₃The doping gas is supplied to the deposition chamber 44 through the gas supply pipe 41 and further through the gas supply hole 43 of the shower head 42 at a flow rate of 1 to 20 SCCM to maintain the gas pressure in the range of 0.133 to 13.3 Pa (for example, 1.33 Pa Pa). The hydrogen-based carrier gas used herein may be hydrogen or a mixture of hydrogen and inert gas, such as hydrogen + argon, hydrogen + helium, hydrogen + neon, hydrogen + xenon, and hydrogen + krypton. Such hydrogen-based carrier gas can also be used in other specific embodiments described below.

After that, as shown in FIG. 3, the light shielding plate 47 is opened. Therefore, at least a part of the source gas 40 will contact the catalytic element 46 and decompose in a catalytic reaction, thereby generating reactive species such as high-energy silicon ions or radicals (ie, deposition species or their precursors and radicals). Hydrogen ion). Using the result type 50 in the form of high-energy ions or radicals, the desired film is formed on the substrate 1 maintained at a temperature of 200 to 800°C (preferably 300 to 400°C) by vapor phase deposition, such as containing amorphous Microcrystalline silicon film of silicon.

As described above, in this technology, since high energy is provided to the reaction species in a thermal manner with the assistance of the catalytic action provided by the catalytic element 46 without generating plasma, the catalytic element 46 can be converted into the reaction species with high efficiency. And the film can be uniformly deposited on the substrate 1 by thermal CVD.

Even when the substrate temperature is low, high-energy deposition types can obtain sufficiently good film quality. This allows the temperature of the substrate to be lowered, so large-sized substrates made of low-cost insulating materials (for example, borosilicate glass, aluminosilicate glass, or heat-resistant resins such as polyimide) can be used. grass). This can also reduce costs.

In addition, since plasma is not generated, there is no damage due to plasma generation, and a simpler and cheaper device than a plasma CVD device can be used to form a low-stress film.

In this technology, the process can be performed under atmospheric pressure or reduced pressure (for example, 0.133 to 1.33 Pa). Compared with the pressure reducing device, the device for performing the process under the atmospheric pressure can be constructed at a lower cost and in a simpler way. In addition, even when the process is performed under atmospheric pressure, the density, uniformity, and adhesion of the deposited film are superior to those formed using traditional atmospheric pressure CVD technology. In addition, compared with the pressure reducing device, the atmospheric pressure process provides higher total processing capacity and higher productivity, so cost reduction can be achieved.

In the above-mentioned catalytic CVD process, the temperature of the substrate increases due to the radiant heat of the catalytic element 46. If further heating is required, a heater 51 for heating the substrate may be provided. Although only one catalytic element 46 in the form of a coil is used (the catalytic element 46 may also be in the form of a mesh, lead, or a perforated panel), it is more desirable to arrange the catalytic element of plural orders (for example, second or third order) in the airflow direction. In order to make the gas contact the catalytic element on a larger area. In this CVD apparatus, because the substrate 1 is arranged on the lower surface of the sensitive body 45 above the shower head 42, it is possible to prevent the undesirable particles generated in the deposition chamber 44 from being deposited on the substrate 1, or deposited on the substrate 1. superior ofOn the film. On the film.

Concentrating annealing treatment and its device

4A to 4D show schematic diagrams of an example of an annealing treatment apparatus (annealer) in a simplified manner. In the example shown in Figures 4A and 4B, the condensing system is generated by a concentrating supply system, which includes an ultra-high pressure mercury lamp 203 capable of emitting 10 kW light with a dominant wavelength of 308 nm, etc., and will use The condensing light continuously scans the substrate 1 (in FIGS. 4A and 4D, reference numeral 204 denotes a focusing mirror, and reference numeral 201 denotes a focusing lens). Will use 200 to 500 mJ/cm in an inert gas environment²The concentrated light of energy density irradiates the amorphous silicon film or microcrystalline silicon film 7A on the substrate 1, thereby melting or semi-melting the irradiated part. The irradiation light 210 will move across the substrate 1 fixed on the support 202 at an appropriate speed. On the contrary, in the example shown in FIGS. 4C and 4D, the substrate 1 is moved at an appropriate speed relative to the fixed illuminating light 210, thereby moving the molten silicon portion. Therefore, in this technology, the melted silicon part 7B is moved from the source region to the gate region and further to the drain region at an appropriate speed, and then the melted silicon part 7B is cooled by itself in the same order, thereby It is ensured that so-called zone melting recrystallization (FIGS. 4A and 4D) occurs, and a large-grain polycrystalline silicon film 7 is obtained.

In the previous process, the catalytic element (this is a catalytic element that has been added in advance to enhance crystallization and has completed its role) and other impurities are concentrated (isolated) into molten (semi-melted) silicon parts, and when moving and concentrating light When it is in the same position, the catalytic element and other impurities will be discharged to the end of the substrate. Therefore, the catalytic element and other impurities in the polycrystalline silicon film produced are removed (inhaled by a getter). Therefore, a large-size polycrystalline silicon film 7 can be obtained, and its catalytic element The concentration of parts and impurities has been reduced to equal to or lower than 1x10¹⁵ The degree of atoms/cc. In addition, in the previous manufacturing process, the crystal grains in the polycrystalline silicon film are arranged in the condensing scanning direction. Therefore, the mismatch of the crystal grain edges is minimized, and the resulting polycrystalline thin silicon film has a high mobility.

In the previous manufacturing process, multiple condensing rays emitted by multiple lamps can be used to repeatedly perform melting or semi-melting and cooling continuously, so that multiple zone melting and recrystallization (Figures 4B and 4D) can occur. This can achieve better crystallization quality, and strengthen the use of getters to absorb catalytic elements and other impurities, thereby improving purity. In this zone melting and recrystallization, the crystalline quality and purity of the melting part (a) will be improved by the melting part (b) and further by the melting part (c).

The light 210 emitted by the lamp 203 may be ultraviolet light, visible light or infrared light. The light can be selected according to the substrate temperature in the MOSTFT manufacturing process and the desired crystal grain size (carrier mobility).

(1) For glass substrates, it is desirable to use ultraviolet lamps or deep ultraviolet lamps that provide relatively low heating. Specific examples of ultraviolet lamps include high-pressure mercury lamps, ultra-high-pressure mercury lamps, high-pressure xenon mercury lamps, and xenon short-arc lamps. Specific examples of deep ultraviolet lamps include low-pressure mercury lamps and xenon mercury lamps.

(2) For heat-resistant substrates such as quartz glass substrates or crystallized glass substrates, any kind of lamps can be used. Specific examples of infrared lamps suitable for this purpose include halogen lamps, xenon lamps, and arc lamps. Specific examples of ultraviolet lamps suitable for this purpose include high-pressure mercury lamps, ultra-high-pressure mercury lamps, and xenon short-arc lamps. Specific examples of deep ultraviolet lamps suitable for this purpose include low-pressure mercury lamps and xenon mercury lamps.

No matter what kind of lamp is used in the annealing process, the light emitted by the lamp can be focused into linear (for example, the size is (500 to 600 mm) x (1 to 100 μm)), rectangular (for example, the size is (1 to 10 mm) )x (200 to 300 mm)) or square (for example, the size is 100x100 mm). Condensing light can increase the intensity of the illumination, so it can increase the melting efficiency. Furthermore, a high total processing capacity can be obtained.

The moving speed of the control substrate or the condensing beam can be controlled within the range of (for example) 1 to 100 millimeters per minute (mm/min) to control the heating/melting speed and cooling speed, so that the polycrystalline silicon film produced has Desired grain and desired purity.

The concentrating annealing treatment conditions (such as wavelength, illumination intensity) can be optimized according to (for example) the thickness of the amorphous silicon film of low crystalline quality, film quality, glass heat resistance temperature and crystal grain size (carrier mobility) And lighting time).

During the concentrating annealing process, the nozzle 206 is used to blow hot air or inert gas (such as nitrogen) from room temperature to 400°C (optimally 200 to 300°C) against the front or back of the substrate or against the front and back of the substrate. 205. In addition, air or inert gas will be blown, and an infrared lamp (such as a halogen lamp) 207 will be used to heat the substrate, so that the substrate has a uniform temperature distribution, which can uniformly crystallize the film and reduce the stress on the crystallized film and the substrate. Reduce the lighting power required for the concentrating annealing process and achieve a slower cooling rate. The illuminating light 210 and the hot air/gas 205 of the lamp are simultaneously supplied from a symmetrical position above and below.

Continuous treatment of catalytic CVD (or plasma CVD) and concentrating annealing treatment

In order to avoid contamination and improve productivity, the formation equipment (such as plasma enhanced CVD, decomposition CVD, or sputtering) used to form thin semiconductor films of low crystalline quality and the concentrating annealing treatment equipment are integrated into a single device. The step of forming a thin semiconductor film of low crystal quality and the step of concentrating annealing treatment are performed in an integrated manner. Specifically, the construction of the device is in-line (including linear or rotary continuous processing chambers), multiple processing chambers, or cluster processing chambers, so that the aforementioned two steps can be performed continuously.

Among the various devices described above, the cluster formula (1) or (2) described below is the best.

(1) As shown in FIG. 5, the first cluster integrated device includes a CVD unit and an annealing processing unit. First, in the CVD unit, a thin semiconductor film of low crystalline quality is formed on the substrate. After that, in the annealing treatment unit, the film is crystallized by light-concentrating annealing treatment. Then, the substrate returns to the CVD unit, and another thin semiconductor film of low crystalline quality is formed. Then, the substrate is transported to the annealing treatment unit again to perform crystallization by the concentrating annealing treatment. Repeat the steps described above as many times as necessary. The device can also be constructed in an in-line manner, as shown in Figure 6A.

(2) As shown in FIG. 7, the second cluster integrated device includes a first, a second, and a third CVD unit, an ion doping/implantation unit, and an annealing processing unit. First, in the first CVD unit, a first lower protective film (such as a silicon oxide/silicon nitride film) is formed on the substrate, and then in the second CVD unit, a thin semiconductor film of low crystal quality is formed. Afterwards, an appropriate amount of group IV elements are added to the ion doping/implantation unit. In the annealing treatment unit, crystallization is performed by concentrating annealing treatment. In addition, in the third CVD unit, a gate insulating film (such as a silicon oxide film) is formed. Continue to perform the steps described above. The device can also be constructed in an in-line manner, as shown in Figure 6B.

The silicon oxide/silicon nitride film formed in the first CVD unit may be The bottom protection film of the top injection type gate type MOSTFT or the bottom injection type gate type insulating film of the bottom injection type gate type MOSTFT (also used as a protection film). The silicon oxide/silicon nitride film or the like formed in the third CVD unit may be a gate insulating film of a top-filled gate type MOSTFT or a protective film of a bottom-filled gate type MOSTFT.

The CVD unit may be a catalytic CVD unit, a plasma enhanced CVD unit, and so on. Alternatively, a splash unit can be used. In the case of film deposition by CVD, it is better to perform plasma treatment or catalytic AHA treatment before deposition. For example, before depositing a film by plasma-enhanced CVD, only hydrogen-based carrier gas is supplied to the CVD chamber, and no source gas is supplied, and plasma AHA treatment is performed to expose the formed polycrystalline silicon The surface of the film to generate hydrogen-based active species (such as activated hydrogen ions), by removing surface contamination (low-quality oxide film, water, oxygen, nitrogen, carbon oxide, etc.), and clean the surface in this way. In addition, in the plasma AHA process, the remaining amorphous silicon in the film is etched and the film is converted into a high crystallinity polycrystalline silicon film. When the next concentrating annealing process is performed after depositing a low-crystalline quality silicon film on the lower layer with the cleaned surface, this lower layer provides a crystallization seed, so a high-quality large-grain polycrystalline or single-crystalline semiconductor film can be obtained.

In order to prevent oxidation and nitridation, it is desirable to perform the concentrating annealing treatment in a reduced-pressure hydrogen gas or a gas chamber containing reduced-pressure hydrogen gas or in a vacuum. Specifically, the treatment chamber used in the concentrating annealing treatment may be a mixture of hydrogen or hydrogen and an inert gas (such as hydrogen, chlorine, krypton, xenon, neon or radon), and the pressure is preferably 1.33 Pa to atmospheric pressure. 133 Pa to 4x10⁴ Pa is the best. As far as vacuum is concerned, the air pressure is preferably 1.33 Pa to atmospheric pressure, and 13.3 Pa to 1.33 x10⁴ Pa is the best. When a thin semiconductor film of low crystallinity quality is covered by a protective insulating film (such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxide/silicon nitride film), or when it is not necessary to continuously perform processing steps immediately In other words, the concentrating annealing treatment can be performed in air or atmospheric nitrogen.

Since the catalytic CVD and concentrating annealing process can be performed without generating plasma, there will be no damage due to plasma generation, and a low-stress film can be formed. In addition, a simpler and cheaper device than the plasma CVD device can also be used.

As shown in FIG. 8, if a protective insulating film 235 (such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxide/silicon nitride film) is used to cover the crystalline-quality thin semiconductor film 7A, the concentrating annealing treatment is performed , The thin polycrystalline silicon film 7 can be formed in a highly reliable manner. However, if the protective insulating film is not used, the molten silicon will overflow, or surface tension will cause residual silicon crystal grains, or in some cases, no polycrystalline silicon film will be formed.

During the crystallization of the thin semiconductor film of low crystal quality by the concentrating annealing treatment, a magnetic field or an electric field can be applied, or a magnetic field and an electric field can be applied at the same time, so that the crystal grains are aligned in a desired crystal direction.

For example, a magnetic field can be applied, as shown in Fig. 9A or 9B. That is, the light emitted from the condensing source containing the lamp 203, the reflector 204 and the lens 201 is guided through the optical controller and the optical window to the vacuum chamber 211 where the substrate 1 is placed (the way of guiding the light may be similar to that described below. Other types of devices) to perform the concentrating annealing process under the condition that the permanent magnet 231 or the electromagnet 232 arranged around the vacuum chamber 211 is used to apply a magnetic field.

In this annealing process with a magnetic field applied, the magnetic field and the electron spins of the silicon atoms in the melted part of the thin silicon film 7A of low crystalline quality (electron spins) Interaction will occur between them, and the silicon atoms will align in a specific direction. When the melted part is cooled and solidified, the part is crystallized in a specific direction. In a crystallized film in which the crystal direction of the crystal grains is substantially aligned in a specific direction, the electron barriers on the edges of the crystal grains are in a low potential state, so high carrier mobility can be obtained. In the previous process, the most important thing is that the crystal direction is arranged in a specific direction, and the arrangement direction of the crystal direction is not important. The crystalline direction is aligned in the direction perpendicular to the thin polycrystalline silicon film 7 produced, or aligned in the direction parallel to the film, depending on the shell structure of the silicon atoms. The arrangement of crystal grains can remove irregularities on the surface of the thin polycrystalline silicon film. The resulting flat surface of the thin film can provide a good interface state between the thin film and the gate insulating film or the film formed on the thin film, etc., thereby improving the carrier mobility.

In the example shown in FIG. 9C, the power supply 233 is used to apply an electric field instead of a magnetic field. The electrodes 234 are arranged around the vacuum chamber 211 where the substrate 1 is placed, and supply high-frequency voltage (or direct current voltage or simultaneous supply of high-frequency voltage and direct current voltage) to the electrodes to perform concentrating annealing treatment under the condition of applying an electric field.

In this annealing process, since the electric field and the electron spin of the silicon atoms in the melted part of the low crystalline quality thin silicon film 7A interact with each other, the silicon atoms are aligned in a specific direction. When the melted part is cooled and solidified, the part will be crystallized while the crystallization direction is maintained in a specific direction. Therefore, in the case of applying a magnetic field, the crystal grains are aligned in a specific direction, so that improved carrier mobility can be achieved. In addition, irregularities on the film surface can be reduced. Another advantage of this technology is that when using By irradiating the substrate 1 with the light 210 emitted by the lamp, high lighting efficiency can be obtained.

In the example shown in FIG. 9D, both a magnetic field and an electric field are applied at the same time. A permanent magnet (or electromagnet) 231 for generating a magnetic field and an electrode 234 for generating a high-frequency voltage (or a DC voltage or a high-frequency voltage and a DC voltage at the same time) are all arranged around the vacuum chamber 211 where the substrate 1 is placed. , Thereby performing the concentrating annealing treatment under the condition of applying a magnetic field and an electric field.

In this annealing process, the magnetic field and electric field interact with the electron spin of the silicon atoms in the melted part of the thin silicon film 7A with low crystalline quality, and the silicon atoms will be aligned in a specific direction. When the melted part is cooled and solidified, the part is crystallized in a specific direction. In this way, the arrangement of the crystal grains in a specific direction can be further enhanced, so that the carrier mobility can be further improved. In addition, irregularities on the film surface can be further reduced. Another advantage of the present technology is that when the light 210 emitted by the lamp is used to illuminate the substrate 1, high lighting efficiency can be obtained.

Manufacturing top injection gate type CMOSTFT

Hereinafter, an example of the sequence of processing steps for manufacturing a top-shot gate type CMOSTFT using the concentrating annealing process according to a specific embodiment of the present invention will be described.

First, as shown in Figure 1A, by vapor phase deposition (such as plasma enhanced CVD, catalytic CVD or reduced pressure CVD) on the insulating substrate 1 (such as borosilicate glass, aluminosilicate glass, quartz or crystal The lower protective film 100 having a multilayer structure of a silicon nitride layer and a silicon oxide layer is formed on the chemical glass (made of material), wherein the lower protective film 100 is formed at least in the area where the TFT is to be formed. The method of forming the lower protective film 100 is as follows.

The insulating substrate 1 used in this article is made of glass material, which is based on The glass material selected appropriately according to the temperature at which the TFT manufacturing process is performed.

As far as the processing temperature is in the range of 200 to 500°C, glass substrates or heat-resistant resin substrates (size 500x600x0.5 to 1.1) made of borosilicate glass or aluminosilicate glass can be used. μm (thickness)) as the insulating substrate 1.

As far as the processing temperature is in the range of 600 to 1000°C, a heat-resistant glass substrate made of quartz glass or crystallized glass (size 6 to 12 inches in diameter, 700 to 800 μm in thickness) can be used. ). The nitride protective film is used as a Na barrier layer to prevent the formed film from being contaminated by Na ions of the glass substrate. In the case of using a synthetic quartz substrate, a nitride protective film is not required.

As far as the catalytic CVD process is used, an apparatus similar to that shown in Figs. 2 and 3 can be used. In order to prevent the catalytic element from being oxidized, after heating the catalytic element to a predetermined temperature (within the range of 1600°C to 1800°C, preferably 1700°C), it is necessary to supply hydrogen-based carrier gas to the device first, and to deposit it After the film is completed, after cooling the catalytic element to a sufficiently low temperature, the supply of hydrogen-based carrier gas is stopped.

When depositing the film, hydrogen-based carrier gas (such as hydrogen, argon+hydrogen, helium+hydrogen or neon+hydrogen) is supplied to the processing chamber during the entire process, and the gas pressure, gas flow rate, and sensitivity are controlled in the following manner Body temperature: Internal pressure of the processing chamber: 0.1 to 10 Pa (for example, 1 Pa) Sensitive body temperature: 350°C Hydrogen-based carrier gas velocity: 100 to 200 SCCM (For mixed gas, the hydrogen concentration is set to (E.g. 80 to 90 mol%) A silicon nitride film with a thickness of 50 to 200 nm is formed under the following conditions: Use H₂As a carrier gas, and use an appropriate proportion of monosilane (SiH₄) And ammonium base (NH₃) The mixture is used as the source gas. H₂Flow rate: 100 to 200 SCCM SiH₄Flow rate: 1 to 2 SCCM NH₃Flow rate: 3 to 5 SCCM

A silicon oxide film with a thickness of 50 to 200 nm is formed under the following conditions: Use H₂As a carrier gas, and use an appropriate proportion of monosilane (SiH₄) And O diluted with He₂The mixture is used as the source gas. H₂Flow rate: 100 to 200 SCCM SiH₄Flow rate: 1 to 2 SCCM using O diluted with He₂Flow rate: 0.1 to 1 SCCM

For film formation by RF plasma CVD, the following conditions can be used: The conditions for forming a silicon oxide film include: SiH₄Flow rate: 5 to 10 SCCM N₂O Flow rate: 1000 SCCM Air pressure: 50 to 70 Pa RF power: 1000 W Substrate temperature: 350°C The conditions for forming a silicon nitride film include: SiH₄Flow rate: 50 to 100 SCCM NH₃Flow rate: 200 to 250 SCCM N₂Flow rate: 700 to 1000 SCCM Air pressure: 50 to 70 Pa. RF power: 1300 W. Substrate temperature: 250°C. Then, as shown in Figure 1B, a low-crystalline silicon film 7A is formed by catalytic CVD or plasma-enhanced CVD with a thickness of 50 nm and doped Impurity concentration is 10¹⁸To 10²⁰ atoms/cc (for example) group IV elements (such as tin) (which can be doped during the CVD process, or doped by ion implantation after the film is formed). Please note that tin doping is not necessary (in other examples described below, tin doping is also not necessary). After that, a silicon oxide film with a thickness of 10 to 30 nm is immediately formed as a protective film and reflection attenuation film.

The apparatus shown in FIG. 2 or FIG. 3 can be used to form a silicon oxide film to deposit a low crystalline quality silicon film doped with tin or nickel by catalytic CVD. Regarding doping nickel, the doping can be performed by ion implantation or ion doping after depositing the thin film. On the other hand, tin doping can be performed by supplying the gas as described below during the film deposition.

Can use H under the following conditions₂As a carrier gas, and use an appropriate proportion of monosilane (SiH₄) And tin hydride (SnH₄) The mixture is used as the source gas, and the microcrystalline silicon containing amorphous silicon is deposited by decomposing CVD: H₂Flow rate: 150 SCCM SiH₄Flow rate: 15 SCCM SnH₄Flow rate: 15 SCCM In the previous process, if appropriate n-type impurities (such as phosphorus, arsenic or antimony) or p-type impurities (such as boron) are mixed with the source gas of silicon hydride-based gas (such as silicon hydride, ethyl silane) Or trisilane), you can get the desired N-type or P-type Doped tin-type silicon film with carrier concentration.

Specifically, PH can be used₃(Phosphine), AsH₃(Arsenide) or SbH₃(stibine) to provide n-type impurities, use B₂H₆(diborane) to provide p-type impurities.

For the formation of the aforementioned film in the same single processing chamber, hydrogen-based carrier gas must be supplied to the processing chamber, and after the catalytic element is heated to an appropriate predetermined temperature, the following precipitation can be performed Process.

First, monosilane and ammonia mixed in an appropriate ratio are used to form a silicon nitride film of the desired thickness. After the process of forming the silicon nitride film is completed, the source gas used in this process will be exhausted, and an appropriate mixing ratio of monosilane and O diluted with He will be used.₂To form a silicon oxide film of the desired thickness. After the process of forming the silicon nitride film is completed, the source gas used in this process will be exhausted, and an appropriate mixing ratio of monosilane and SnH will be used₄To form a desired thickness of doped tin-type microcrystalline silicon film containing amorphous silicon. After the process of forming the doped tin-type microcrystalline silicon film is completed, the source gas used in this process will be exhausted, and a proper mixing ratio of monosilane and O diluted with He will be used.₂To form a silicon oxide film of the desired thickness. After the deposition of the film is completed, the catalytic element is cooled to a sufficiently low temperature. After that, the supply of hydrogen-based carrier gas is stopped. In the previous process, the flow rate of the source gas used to form the insulating film may gradually decrease or increase, and the composition of the resulting film may gradually change.

Regarding the formation of films in different processing chambers, hydrogen-based carrier gas must be supplied to each processing chamber, and after the catalytic element is heated to an appropriate predetermined temperature, the following precipitation can be performed Process. Will base The plate is placed in the first processing chamber, and monosilane and ammonia mixed in an appropriate ratio are used to form a silicon nitride film. After that, the substrate is transferred to the second processing chamber, and monosilane mixed in an appropriate ratio and O diluted with He is used.₂To form a silicon oxide film. Then, transfer the substrate to the third processing chamber, and use monosilane and SnH mixed in an appropriate ratio₄To form a doped tin-type microcrystalline silicon film containing amorphous silicon. After that, the substrate was transferred to the second processing chamber again, using monosilane mixed in an appropriate ratio and O diluted with He₂To form a silicon oxide film. After the deposition of the film is completed, the catalytic element is cooled to a sufficiently low temperature. After that, the supply of hydrogen-based carrier gas is stopped. Alternatively, the hydrogen-based carrier gas and various source gases are continuously supplied without shutting down to maintain the standby state.

For the formation of low-crystalline silicon film by RF plasma CVD, the following conditions can be used to form the film: SiH₄Flow rate: 100 SCCM H₂Flow rate: 100 SCCM Air pressure: 1.33x10⁴ Pa RF power: 100 W Substrate temperature: 350°C, as shown in Figure 1C, the microcrystalline or amorphous silicon film 7A is converted into a large-grain polycrystalline silicon film 7 by performing a focused annealing process, as shown in Figure 4A or 4B As shown, in an inert gas (such as nitrogen) environment, using a concentrated light source including an ultra-high pressure mercury lamp 203 capable of outputting 10 kW of light with a dominant wavelength of 308 nm, continuous emission of 200 to 500 mJ/cm²The concentrated light 210 of energy density irradiates the microcrystalline/amorphous silicon film 7A to melt or semi-melt the microcrystalline/amorphous silicon film At the same time, the irradiated part of 7A is continuously moved by moving the melting or semi-melting part at an appropriate speed relative to the substrate 1 maintained at a fixed position (or by moving the substrate 1 by condensing light 210 relative to the fixed position), thereby continuously Melt or semi-melt the source, gate, and drain regions, and then continuously cool the source, gate, and drain regions by themselves. Through this annealing treatment, zone melting and recrystallization will occur, and the microcrystalline/amorphous silicon film 7A will be converted into a large-grain polycrystalline silicon film 7. In the previous process, the catalytic element (which is the catalytic element that has been added to enhance crystallization and has completed its role) and other impurities are concentrated (isolated) into molten (semi-melted) silicon parts, in this way, a large particle size is formed Polycrystalline silicon film 7, whose catalytic element and impurity concentration have been reduced to equal to or lower than 1x1x10¹⁵ The degree of atoms/cc.

In the previous manufacturing process, multiple condensing rays emitted by multiple lamps can be used to repeatedly perform melting or semi-melting and cooling continuously, so that multiple zone melting and recrystallization can occur. This can achieve better crystallization quality, and strengthen the use of getters to absorb catalytic elements and other impurities, thereby improving purity.

The light emitted by the lamp 203 may be ultraviolet light, visible light or infrared light. The light can be selected according to the substrate temperature in the MOSTFT manufacturing process and the desired crystal grain size (carrier mobility).

(1) For glass substrates, it is desirable to use ultraviolet lamps or deep ultraviolet lamps that provide relatively low heating. Specific examples of ultraviolet lamps include high-pressure mercury lamps, ultra-high-pressure mercury lamps, high-pressure xenon mercury lamps, and xenon short-arc lamps. Specific examples of deep ultraviolet lamps include low-pressure mercury lamps and xenon mercury lamps.

(2) For heat-resistant substrates such as quartz glass substrates or crystallized glass substrates, any kind of lamps can be used. Features of infrared lamps suitable for this purpose Certain examples include halogen lamps, xenon lamps and arc lamps. Specific examples of ultraviolet lamps suitable for this purpose include high-pressure mercury lamps, ultra-high-pressure mercury lamps, and xenon short-arc lamps. Specific examples of deep ultraviolet lamps suitable for this purpose include low-pressure mercury lamps and xenon mercury lamps.

No matter what kind of lamp is used in the annealing process, the light emitted by the lamp can be focused into linear (for example, the size is (500 to 600 mm) x (1 to 100 μm)), rectangular (for example, the size is (1 to 10 mm) )x (200 to 300 mm)) or square (for example, the size is 100x100 mm). Condensing light can increase the intensity of the illumination, so it can increase the melting efficiency. Furthermore, a high total processing capacity can be obtained. The moving speed of the control substrate or the condensing beam can be controlled within the range of (for example) 1 to 100 millimeters per minute (mm/min) to control the heating/melting speed and cooling speed, so that the polycrystalline silicon film produced has Desired grain and desired purity.

The concentrating annealing treatment conditions (such as wavelength, illumination intensity, and illumination time) can be optimized according to the thickness of the low-crystalline quality silicon film, the film quality, the heat resistance temperature of the glass, and the crystal grain size (carrier mobility). During the concentrating annealing process, hot air or inert gas (such as nitrogen) at room temperature to 400°C (preferably 200 to 300°C) is blown against the front or back of the substrate or the front and back of the substrate. In addition, It also blows air or inert gas, and uses infrared lamps (such as halogen lamps) to heat the substrate to make the substrate have a uniform temperature distribution, which can uniformly crystallize the film, reduce the stress of the crystallized film and the substrate, and reduce the concentration annealing process The required lighting power and achieve cooling at a slower rate.

Before performing the concentrating annealing process, it is best to use ion implantation, ion doping, etc. to dope the film 7A with a catalytic metal (such as nickel) to be equal to or less than 10%.²⁰The concentration of atoms/cc in 1x10¹³To 1x10²⁰atoms/cc range The concentration inside is the best. It is best to use a protective film (such as a silicon oxide film, a silicon oxynitride film or a silicon oxide/silicon nitride multilayer film) to cover the low crystalline quality silicon film and then perform the concentrating annealing process to prevent the molten silicon from splashing during the annealing process. It also prevents the residual silicon crystal grains caused by the surface tension that occurs in other methods, so a high-quality single-crystal silicon film can be obtained.

In order to suppress the increase in substrate temperature and to enhance crystallization, it is better to perform a focused annealing process after the pattern is formed into an island shape. The protective silicon oxide film can cover or not cover the low-crystalline silicon film, thereby obtaining a high-quality polycrystalline silicon film.

If the concentrating annealing process is performed under sufficient conditions after forming the gate channel region, source region, and drain region (described below), not only crystallization will occur, but also n-type or p-type impurities will also occur at the same time (Such as phosphorus, arsenic, or boron) is activated, so high productivity can be achieved.

After that, a MOSTFT including a source electrode, a channel region, and a drain electrode formed by the polycrystalline silicon film 7 is manufactured.

That is, as shown in FIG. 1D, the silicon oxide film serving as the protective film and the reflection attenuation film is removed by a photolithography process and an etching process well-known to those skilled in the art, and then the polycrystalline silicon film 7 is patterned into an island shape. Afterwards, in order to adjust the impurity concentration of the channel region of the nMOSTFT to its limit value (V_th) Adjusted to the optimal value, the pMOSTFT area will be covered by the photoresist 9, and will be doped (for example) 5x10 by ion implantation or heterodonization¹¹ atoms/cm²Dosage of p-type impurities (such as boron ions) 10, so that the receiver concentration of the channel region of the nMOSTFT becomes 1x10¹⁷ atoms/cc. In this way, the conductivity type of the doped portion of the polycrystalline silicon film 7 is switched, and the p-type polycrystalline film 11 is obtained.

Then, as shown in FIG. 1E, in order to adjust the impurity concentration of the channel region of the pMOSTFT to the limit value (V_th) Adjust to the optimal value, the nMOSTFT area will be covered by the photoresist 12, and will be doped by ion implantation or ion doping (for example) 1x10¹² atoms/cm²Dosage of n-type impurities (such as phosphorous ions) 13 so that the donor concentration in the channel region of the pMOSTFT becomes 2x10¹⁷ atoms/cc. In this way, the conductivity type of the doped portion of the polycrystalline silicon film 7 is switched, and the n-type polycrystalline film 14 is obtained.

After that, as shown in FIG. 1F, a silicon oxide film 8 with a thickness of 50 nm is formed by catalytic CVD or the like to serve as a gate insulating film. After that, use PH supplied at a flow rate of 2 to 20 SCCM₃, And SiH supplied at a flow rate of 20 SCCM₄And 20 is used as a gate electrode material by depositing a doped phosphorous polycrystalline film 15 with a thickness of 400 nm by catalytic CVD.

After that, as shown in FIG. 1G, a photoresist 16 having a predetermined pattern is formed, and the photoresist 16 is used as a pattern mask to pattern the doped phosphorous polycrystalline silicon film 15 into a gate electrode pattern . After the photoresist 16 is removed, as shown in FIG. 1H, a silicon oxide film 17 with a thickness of 20 nm is formed by catalytic CVD or the like.

After that, as shown in FIG. 1I, the pMOSTFT area is covered by the photoresist 18 and will be doped (for example) 1×10 by ion implantation or ion doping.¹⁵ atoms/cm²Dose of n-type impurities (such as phosphorous ions) 19, thereby forming the n-type of nMOSTFT⁺Type source region 20 and drain region 21, so that the generated source region and drain region have 2x10²⁰ Atoms/cc donor concentration.

After that, as shown in FIG. 1J, the nMOSTFT area is covered by the photoresist 22, and will be doped (for example) 1×10 by ion implantation or ion doping.¹⁵ atoms/cm²Dose of p-type impurities (such as boron ions) 23, thereby forming the p⁺Type source region 24 and drain region 25, so that the generated source region and drain region have 2x10²⁰ Atom/cc receiver concentration. Then, an annealing treatment is performed for 5 minutes at a temperature of about 900°C in a nitrogen environment, thereby activating the impurity ions doped in each pole region so that each pole region has all the impurity (carrier) concentration .

In this way, the gate, source, and drain are formed through the process described above. Please note that another process can be used to form these polar regions.

That is, for example, after the steps shown in FIG. 1B are completed, the polycrystalline silicon film 7 is formed into an island shape to form pMOSTFT and nMOSTFT in the island shape. This can be accomplished by the photolithography process and the etching process well known to those skilled in the art, to remove the silicon oxide film used as the protective film and the reflection attenuation film with a hydrofluoric acid-based etchant, by using CF₄, SF₆The plasma etching method of the others selectively removes the microcrystalline silicon film containing amorphous silicon, and finally uses an organic solvent or the like to remove the photoresist and clean it. During the concentrating annealing process performed later, since concentrating irradiation is used to melt the silicon, it causes a rapid increase in temperature and induces strain when the silicon cools. Therefore, when the polycrystalline silicon film is heated and cooled, the polycrystalline silicon film may crack. Forming the film into an island shape helps suppress the increase in substrate temperature. That is, performing the film formation into islands before the concentrating annealing treatment can reduce the heat dissipation, and then cool the molten silicon part at a lower speed, which can strengthen the crystal growth, and reducing the heat dissipation can also reduce the heat dissipation of the melted silicon part. The substrate temperature increases.

After the low crystalline quality silicon film 7A is annealed using a method similar to the above-mentioned method, the low crystalline quality silicon film 7A is removed, and the protective film and reflection degradation are removed. Reduced silicon oxide film. After that, as in the previous example, adjust the impurity concentration of each channel area to obtain the best V_th, The method is to use a photoresist mask as a doping mask to transfer the 1x10 mask by ion implantation or ion doping¹² atoms/cm²N-type impurities (such as phosphorous) are doped into the pMOSTFT part with a certain dose, so that the pMOSTFT part has a 2x10¹⁷ atoms/cc donor concentration, and 5x10¹¹ atoms/cm²P-type impurities (such as boron) are doped into the nMOSTFT area to make the nMOSTFT area 1x10¹⁷ Atom/cc receiver concentration.

After that, the source region/drain region is formed using a photolithography process well known to those skilled in the art. Specifically, for nMOSTFT, doping 1x10 by ion implantation or ion doping¹⁵ atoms/cm²Dose of N-type impurities (such as arsenic or phosphorus ions) to obtain 2x10²⁰ Atom/cc donor concentration, and for pMOSTFT, doped 1x10 by ion implantation or ion doping¹⁵ atoms/cm²Dosage of p-type impurities (such as boron ions) to obtain 2x10²⁰ Atom/cc receiver concentration.

After that, the n-type impurities and p-type impurities in the polycrystalline silicon film are activated. Specifically, by using a concentrated annealing treatment lower than the crystallization energy, or by using an infrared lamp (such as a halogen lamp) to perform RTA (Rapid Thermal Anneal; rapid thermal annealing), the temperature is about 1000 °C for about 30 seconds The heat treatment activates the impurities doped in the gate channel region and the source/drain regions. After that (or before activating the impurities), a silicon oxide film is formed as a gate insulating film. If desired, a silicon nitride film and a silicon oxide film are successively deposited to form a gate insulating film with a multilayer structure. Specifically, a hydrogen-based carrier gas and a proper mixing ratio of monosilane and O diluted with He are used.₂To form a silicon oxide film 8 with a thickness of 40 to 50 nm by catalytic CVD, Then, if desired, use a hydrogen-based carrier gas and an appropriate mixing ratio of monosilane and NH₃To form a silicon nitride film with a thickness of 10 to 20 nm, in addition, a silicon oxide film with a thickness of 40 to 50 nm is formed under the same conditions as described above.

Then, as shown in FIG. 1K, a silicon oxide film 26 with a thickness of (for example) 50 nm and a phosphosilicate glass (PSG) film with a thickness of (for example) 400 nm are formed in a multilayer manner by catalytic CVD. 28 and a silicon nitride film 27 with a thickness of, for example, 200 nm. Specifically, use O diluted with He supplied at a flow rate of 1 to 2 SCCM₂And monosilane supplied at a flow rate of 15 to 20 SCCM to form the silicon oxide film 26; use PH supplied at a flow rate of 1 to 20 SCCM₃, Supplied O diluted with He at a flow rate of 1 to 2 SCCM₂And SiH supplied at a flow rate of 15 to 20 SCCM₄To form a phosphosilicate glass film 28 with a thickness of, for example, 40 nm; and use NH supplied at a flow rate of 50 to 60 SCCM₃And monosilane supplied at a flow rate of 15 to 20 SCCM to form a silicon nitride film 27 with a thickness of, for example, 200 nm, wherein hydrogen-based carrier gas is supplied at a flow rate of 150 SCCM when either film is formed.

After that, as shown in FIG. 1L, a contact hole is formed at a predetermined position in the formed insulating film using the following process. Specifically, a photolithography process and an etching process that are well known to those skilled in the art are used to form a photoresist with patterns corresponding to the gate, source and drain of the nMOSTFT and pMOSTFT; use CF₄, SF₆Etching silicon nitride passivation film with plasma; and etching silicon oxide film and PSG film with hydrofluoric acid-based etchant. Then, the photoresist is removed using an organic solvent or the like. Thus, the gate area, source area and drain area of the nMOSTFT and pMOSTFT are exposed.

After that, an electrode material with a thickness of 1 μm, such as aluminum containing 1% silicon, is deposited on the entire surface including the area exposed through the contact hole by splashing or the like at a temperature of 150°C. Then, the deposited electrode material is patterned to form source/drain electrodes 29 (S or D) and gate electrodes and interconnection 30 (G) of pMOSTFT and nMOSTFT, thereby forming a top-filled gate type CMOSTFT. After that, the hydrogenation and calcining treatments were performed at 400° C. in a synthetic gas environment for a time period of 1 hour. In the previous process, aluminum forming gas (such as AlCl₃) To deposit aluminum film by catalytic CVD.

If the above-mentioned method is not used to form the gate electrode, the following method can also be used to form the gate electrode of nMOSTFT and pMOSTFT. Alloy), and then pattern the deposited refractory metal using a photolithography process and an etching process well known to those skilled in the art.

It is also possible to use silicon alloy and concentrating annealing treatment to manufacture top injection gate type polycrystalline silicon CMOSTFT by liquid phase growth. An example of the sequence of processing steps is described below. After forming the lower protective film, one of the methods (1) to (5) described below can be used to grow (deposit) an amorphous silicon layer/microcrystalline silicon layer with or without tin.

(1) After coating a melt of a low melting point metal (such as tin containing silicon), the melt is cooled.

(2) Immerse the substrate with the protective film underneath in the melt of low melting point metal (such as tin containing silicon). After immersing for an appropriate period of time, the substrate is taken out and cooled.

(3) After forming a low melting point metal film (such as tin containing silicon) on the lower layer, It is heated to melt the metal film. After that, the film is cooled.

(4) A silicon film is formed on the lower layer, and a low melting point metal film (such as tin) is formed on the silicon film. It is then heated to melt the film. After that, the film is cooled.

(5) A low melting point metal film (such as tin) is formed on the lower layer, and a silicon film is formed on the low melting point metal film. It is then heated to melt the film. After that, the film is cooled.

Afterwards, the microcrystalline silicon layer/amorphous silicon layer containing or not containing tin is patterned into island shapes to form pMOSTFT and nMOSTFT at the island shape. Adjust the impurity concentration in the channel region by ion implantation or ion doping to reduce V_thAdjust to the optimal value (use a method similar to that described above). After that, the source/drain regions of pMOSTFT and nMOSTFT are formed by ion implantation method or ion doping method (using a method similar to that described above).

After that, a focused annealing treatment is performed to crystallize and activate the ions (using a method similar to that described above). After that, a silicon oxide film is formed by catalytic CVD to serve as a gate insulating film. If desired, a silicon nitride film and a silicon oxide film are successively deposited to form a gate insulating film with a multilayer structure (using a method similar to that described above). The execution of the following processing steps is similar to the execution of the processing steps described above. The method of using liquid phase growth as described above can also be used to manufacture the bottom injection type gate type CMOSTFT and the double gate type CMOSTFT as described below.

In the previous process, ion crystallization and activation can be performed separately. For example, ion activation is performed by RTA, and ion crystallization is performed by concentrating annealing treatment.

The low crystalline quality silicon film formed by sputtering can also be used to make top shots Type gate type polycrystalline silicon CMOSTFT. In this case, the process includes the steps of forming a low-crystalline silicon film and performing a light-concentrating annealing process. The process is performed as follows: First, a lower protective film is formed by sputtering. Specifically, the silicon nitride target is sputtered in an argon atmosphere at a pressure of 0.133 to 1.33 Pa to deposit silicon nitride on the entire surface of the insulating substrate, thereby forming silicon nitride with a thickness of 50 to 200 nm membrane. Then, the silicon oxide target is sputtered in an argon atmosphere at a pressure of 0.133 to 1.33 Pa to deposit silicon nitride on the entire surface of the silicon nitride film, thereby forming a silicon oxide film with a thickness of 100 to 200 nm.

Afterwards, a silicon target containing or not containing 0.1 to 1 at% tin is sputtered in an argon atmosphere at a pressure of 0.133 to 1.33 Pa, thereby forming an amorphous film with a thickness of 50 nm on the insulating substrate at least in the area where the TFT is to be formed Silicon film (with or without tin or nickel).

After that, by sputtering the silicon oxide target in an argon atmosphere at a pressure of 0.133 to 1.33 Pa, a silicon oxide film with a thickness of 10 to 30 nm is formed on the entire surface of the amorphous silicon film as a protective film and also As a reflection attenuation film.

Or, in the case of changing the sputtering gas, the same silicon target is sputtered to form the front film. That is, a mixed gas of argon and nitrogen can be used to form a silicon nitride film (5 to 10 mol%), a mixed gas of argon and oxygen can be used to form a silicon oxide film (5 to 10 mol%), and an argon gas can be used to form a non-silicon nitride film. Crystalline silicon film, and use a mixed gas of argon and oxygen to form a silicon oxide film (5 to 10 mol%).

After that, the amorphous silicon layer containing or not containing tin or nickel is patterned into island shapes to form pMOSTFT and nMOSTFT at the island shape (similar to the aforementioned method of film formation by CVD as described above). Then, by ion implantation Or ion doping method to form the channel region, the source region and the drain region (similar to the aforementioned method of forming a film by CVD as described above).

Afterwards, the amorphous silicon layer containing or not containing tin or nickel is subjected to light-concentrating annealing treatment. The concentrating annealing treatment promotes the conversion of the amorphous silicon film into a polycrystalline form, and also promotes the activation of n-type and/or p-type impurities doped by ion implantation or ion doping to make the gate electrode The channel region, the source region, and the drain region have optimized carrier impurity concentrations (wherein, the light-concentrating annealing treatment can be performed in a similar manner as described above). As in the previous method, ion crystallization and activation can be performed separately. For example, ion activation is performed by RTA, and ion crystallization is performed by concentrating annealing treatment.

After that, a silicon oxide film is formed as a gate insulating film. If desired, a silicon nitride film and a silicon oxide film are successively deposited to form a gate insulating film with a multilayer structure. Specifically, a silicon oxide film with a thickness of 40 to 50 nm, a silicon nitride film with a thickness of 10 to 20 nm, and a silicon oxide film with a thickness of 40 to 50 nm are continuously deposited by catalytic CVD or the like (the deposition conditions are similar to The conditions used in the former method).

The execution of the following processing steps is similar to the execution of the processing steps of the previous method. The method of using a film formed by sputtering as described above can also be used to manufacture the bottom injection type gate type CMOS TFT and the double gate type CMOS TFT as described below.

If necessary, the low crystalline quality silicon film forming and the concentrating annealing process can be repeated several times to form an extremely thick, high-purity, large-grained polycrystalline film, which has a high crystalline quality close to that of single crystalline silicon. This type of film is suitable for the manufacture of CCD area/linear sensors, bipolar LSI or solar storage batteries that require thick films. specific In general, the method of manufacturing such a thick film is as follows. First, a large-grain polycrystalline silicon film with a thickness of, for example, 200 to 300 nm is formed through the first concentrating annealing process. After that, a low-crystalline silicon film with a thickness of 200 to 300 nm is formed thereon. Then, the second concentrating annealing treatment is performed. Crystallization occurs during the second concentrating annealing treatment, where the polycrystalline silicon film below the low crystalline quality silicon film provides a crystallization seed, thereby forming a large-grain polycrystalline silicon film with a total thickness of 400 to 600 nm. If necessary, the previous processing steps are repeated several times to form a large-grain polycrystalline silicon film with a total thickness on the order of several microns. Please note that such thick films belong to the category of polycrystalline thin silicon films according to the present invention.

As far as the thickness is formed by repeated deposition and annealing treatments, in the subsequent concentrating annealing treatment, the lower large-grained polycrystalline silicon film provides crystalline atomic nuclei (seeds), because the polycrystalline silicon layer above it has a larger Crystal grain size. Therefore, in the large-grained polycrystalline thick silicon film produced, the crystal quality and purity from the lower layer to the upper layer are getting better and better, and the crystal quality and purity of single crystal silicon are achieved. This type of thick film is not only suitable for the manufacture of MOSLSI, but also suitable for the manufacture of various devices that require active and passive components to be formed on the thick film, such as CCD area/linear sensor, bipolar LSI or solar storage battery.

[1] Regarding the spot annealing process performed after the pattern is formed into an island shape, the process can be performed using any one of the methods (1) and (4) described below.

(1) In the low-temperature process (A), a layer of silicon oxide (SiO₂)/Silicon Nitride (SiN_x) The covered amorphous silicon film is patterned into islands. After performing concentrating annealing treatment to convert the amorphous silicon film into a polycrystalline form, only SiN is removed_xmembrane. After that, deposit SiO₂Film or multilayer SiO₂/SiN_xThe film serves as a gate insulating film. In this context, the term "low-temperature process" is used to describe the process performed for a structure including a substrate made of low-melting glass (such as borosilicate glass or aluminosilicate glass). Please note that the silicon nitride film formed at a low temperature by plasma enhanced CVD etc. and ideal Si₃N₄There are errors between the composites, so SiN will be used_xTo indicate this type of silicon nitride film.

(2) In the low temperature process (B), the SiO₂(Or SiN_x) The amorphous silicon film covered by the film is patterned into an island shape, and then the amorphous silicon film is converted into a polycrystalline form by performing a focused annealing treatment. After that, remove SiO₂(Or SiN_x) Film and deposit SiO₂Film or multilayer SiO₂/SiN_x/SiO₂The film serves as a gate insulating film.

(3) In the low-temperature process (C), the amorphous silicon film is patterned into islands, and then concentrated annealing is performed. After that, deposit SiO₂Film or multilayer SiO₂/SiN_x/SiO₂The film serves as a gate insulating film.

(4) In the high-temperature process (A), the amorphous silicon film is patterned into islands, and then concentrated annealing is performed. After that, the surface of the polycrystalline silicon film is oxidized by high-temperature oxidation (1000° C., 30 minutes), thereby forming a gate insulating film. In this article, the term "high temperature process" is used to describe a process performed on a structure including a substrate made of quartz glass.

[II] As far as the spot annealing process is performed before the pattern is formed into an island shape, one of the processes (1) and (4) described below can be used to perform the process.

(1) In the low temperature process (D), for the multi-layer SiO₂/SiN_xThe amorphous silicon film covered by the film is patterned into islands after the concentrating annealing process is completed. After that, SiN is removed_xFilm and form SiO₂Film or multilayer SiO₂/SiN_xFilm with As a gate insulating film.

(2) In the low temperature process (E), for the SiO₂(Or SiN_x) After the amorphous silicon film covered by the film is subjected to a light-concentrating annealing process, it is patterned into an island shape. After that, remove SiO₂(Or SiN_x) Film and deposit SiO₂Film or multilayer SiO₂/SiN_x/SiO₂The film serves as a gate insulating film.

(3) In the low-temperature process (F), the amorphous silicon film is subjected to concentrating annealing treatment, and then patterned into an island shape. After that, deposit SiO₂Film or multilayer SiO₂/SiN_x/SiO₂The film serves as a gate insulating film.

(4) In the high-temperature process (B), the amorphous silicon film is subjected to concentrating annealing treatment and then patterned into islands. Then, the polycrystalline silicon film is thermally oxidized by high-temperature oxidation (1000° C., 30 minutes) to form a gate insulating film (in this case, a substrate made of quartz glass is required).

In process [I] and [II], when using low temperature process, SiO can be formed by catalytic CVD, plasma enhanced CVD or TEOS type CVD₂, SiN can be formed by catalytic CVD or plasma enhanced CVD_x. When using high and low temperature processes, high-quality SiO can be formed by thermally oxidizing polycrystalline silicon at high temperature₂, As described above. In this case, a polycrystalline silicon film with sufficient thickness should be formed.

From the foregoing discussion, it can be known that this specific embodiment provides advantages (a) to (k) as described below.

(a) In the concentrating annealing process, the light emitted by an ultra-high pressure mercury lamp is focused into a desired form, and a thin semiconductor film of low crystal quality such as an amorphous silicon film is irradiated with focused light to reduce the low crystal quality The thin semiconductor film is heated to a molten or semi-melted state, or when the thin semiconductor film of low crystallinity The thin semiconductor film of low crystalline quality is heated while maintaining the non-melted state, and then the thin semiconductor film of low crystalline quality is cooled. That is, in this method, high illuminance energy irradiated on a thin semiconductor film of low crystalline quality will heat the thin semiconductor film of low crystalline quality to a molten or semi-melted state, or when the thin semiconductor film of low crystalline quality maintains a non-melted state The thin semiconductor film of low crystalline quality is heated at time, and then the thin semiconductor film of low crystalline quality is cooled, so as to obtain a large-grained polycrystalline semiconductor with high carrier mobility and high quality, such as monocrystalline silicon or polycrystalline silicon film. membrane. This technology can greatly increase productivity and significantly reduce costs.

(b) In the concentrating annealing treatment according to the present invention, since the zone melting and recrystallization are performed when the melting zone is continuously moved, the pre-added catalytic element (such as Ni) and other impurities used to enhance the crystallization are isolated It becomes a melted zone, so such catalytic elements or impurities can be easily removed. Therefore, no impurities remain in the resulting annealed film. In this way, a polycrystalline thin semiconductor film with large particle size, high carrier mobility, and high quality can be easily obtained. Specifically, if multiple-zone melting and recrystallization are performed by repeatedly performing melting and cooling using a plurality of condensed rays emitted from a plurality of lamps, a polycrystalline thin semiconductor film with larger particle size and high quality can be obtained. The high purity obtained by this technology can produce highly stable and highly reliable devices without degrading semiconductor characteristics. In addition, in the concentrating annealing treatment technology, a simple process is used to perform zone melting and recrystallization or multiple zone melting and recrystallization, which can efficiently remove the catalytic element that has completed the enhancement of the crystallization role, and it can also be highly efficient Remove other impurities. Simplified manufacturing process can reduce costs.

(c) The crystal grains in the polycrystalline silicon film are arranged in the focusing scanning direction. Therefore, if the TFT is formed in this direction, the mismatch and stress at the edge of the crystal grains can be minimized, and the resulting polycrystalline thin silicon film has high mobility.

(d) If the concentrating annealing process is used to form another low-crystalline silicon film on the polycrystalline silicon film by zone melting recrystallization or multiple zone melting recrystallization, and if the concentrating annealing process is used to perform crystallization again If it is formed, a thicker polycrystalline silicon film with large particle size, high carrier mobility and high crystal quality can be formed. By repeatedly performing this process, a total thickness on the order of several microns can be obtained. In this way, not only MOS LSI can be manufactured, but also other types of devices such as bipolar LSI, CMOS sensor, CCD area/linear sensor, and solar battery can be manufactured with high efficiency and high quality.

(e) Regardless of whether ultraviolet (UV) lamps or infrared lamps are used, it is easy to focus the light emitted by the lamp into a linear, rectangular or square shape, and it can emit light continuously. In addition, the beam size and scanning pitch can be arbitrarily set. High light intensity can increase melting efficiency and total processing capacity, so cost reduction can be achieved.

(f) It is easy to control the wavelength, light intensity and irradiation time of the lamp used in the concentrating annealing treatment device. In addition, the heating/melting speed and cooling speed can be controlled by controlling the speed of moving the substrate or lamp. By controlling these parameters, a polycrystalline silicon film with desired particle size and purity can be formed.

(g) The lamp used in the concentrating annealing device is cheaper than the excimer laser generator used in the excimer laser annealing device, so it can achieve a large lower the cost.

(h) In the traditional annealing process using XeCl or KrF excimer lasers, the laser beam is output in the form of pulses in the order of several nanoseconds (nsec), and the output is unstable. The unstable output of the laser beam will cause the energy distribution of the entire surface irradiated by the laser beam to change. This in turn leads to changes in the quality of the resulting crystallized semiconductor film and changes in characteristics that vary from TFT to TFT. One known technique to avoid the aforementioned problem is to repeatedly perform excimer laser pulse irradiation several times (for example, 5 times or 30 times) while heating the film at a temperature of, for example, 400°C. However, even in this case, changes in the crystal quality of the semiconductor film and changes in device characteristics that vary from TFT to TFT cannot be completely ruled out. In addition, since the total processing capacity is reduced, it will lead to an increase in cost. Conversely, in the concentrating annealing process, especially in the annealing process using ultra-high pressure mercury lamps, light with the same wavelength as the XeCl excimer laser (wavelength 308 nm) can be used to continuously irradiate the entire film surface with a small irradiation energy change. The resulting crystallized semiconductor film has uniform characteristics, and the characteristics of the manufactured TFT vary little between devices. Therefore, high total processing capacity and high productivity can be achieved, thereby reducing costs.

(i) Concentrating annealing process can be used at low substrate temperature (200 to 400°C). Therefore, low-strain-point glass or heat-resistant resin can be used as the substrate material, and a large-area substrate can be manufactured at low cost. Therefore, weight and cost reduction can be achieved.

(j) For the use of high-temperature resistant substrates made of quartz glass, crystallized glass, etc., it is easy to use a simple process to form high-quality gate insulating films, so high-efficiency semiconductor devices can be manufactured at low cost .

(k) The use of single crystal or polycrystalline semiconductor films with high carrier mobility formed by concentrating annealing technology can not only manufacture top-gate TFTs, but also other TFTs. Such as bottom-gate type (bottom-gate) MOSTFT and dual-gate type (dual-gate type) MOSTFT. Therefore, high-efficiency semiconductor films can be used to manufacture high-speed and high-current semiconductor devices, electro-optical devices, and high-efficiency solar storage batteries. Specific examples of devices that can be manufactured according to this embodiment include: silicon semiconductor devices, silicon semiconductor integrated circuits, silicon germanium semiconductor devices, silicon germanium semiconductor integrated circuits, silicon carbide semiconductor devices, silicon carbide semiconductor integrated circuits, polycrystalline Drilling semiconductor devices, polycrystalline drilling semiconductor integrated circuits, composite semiconductor (such as GaAs) devices, composite semiconductor (such as GaAs) integrated circuits, liquid crystal displays, field emission displays (FED), (inorganic/organic) electroluminescence Displays, light-emitting polymer displays, light-emitting diode displays, photoreceptors, CCD area/linear sensors, CMOS sensors and solar batteries.

Second specific embodiment

Example of the first manufacturing LCD process

In this second specific embodiment, the present invention is applied to an LCD (liquid crystal display) using a polycrystalline silicon MOSTFT formed by a high-temperature process. The following describes an example of the sequence of processing steps for manufacturing an LCD.

First, as shown in FIG. 10A, in the pixel area (shown on the left of FIG. 10A) and the peripheral circuit area (shown on the right of FIG. 10A), quartz glass, crystallized glass, etc. ( It has a strain point of 800 to 1100°C and a thickness of 50 μm to several millimeters (mm). A lower protective film 100 (not shown in the figure) is formed on the main surface of the high temperature resistant insulating substrate 61 made of material As shown), a low-crystalline silicon film 67A is formed on the lower protective film 100 by catalytic CVD or the like. If necessary, a silicon oxide film with a thickness of 10 to 30 nm is formed on the low crystalline quality silicon film to serve as a protective film and also as a reflection attenuation film.

After that, as shown in FIG. 10B, the low crystalline quality silicon film 67A is subjected to a light-concentrating annealing treatment, thereby forming a polycrystalline silicon film 67 with a thickness of 50 nm.

After that, as shown in FIG. 10C, the silicon oxide film serving as the protective film and the reflection attenuation film is removed, and the polycrystalline silicon film 67 is patterned into islands by a photolithography process and an etching process well known to those skilled in the art. The active devices (such as transistors and diodes) and the active layers that form passive devices (such as resistors, capacitors, and inductors). Although the process described below is related to the manufacture of TFTs, this process is also applicable to the manufacture of other Type device.

Using a method similar to that described above, the channel regions of the polycrystalline silicon film 67 are doped with impurities (such as boron or phosphorus) by ion implantation or ion doping to control the impurity concentration corresponding to Best V_thValue. After that, as shown in FIG. 10D, a silicon oxide film 68 having a thickness of (for example) 50 nm is formed on the surface of the polycrystalline silicon film 67 by a method similar to that described above by catalytic CVD or the like to serve as a gate electrode. Insulating film. Regarding the use of catalytic CVD to form the silicon oxide film 68 as a gate insulating film, oxygen supplied at a flow rate of 1 to 2 SCCM, monosilane supplied at a flow rate of 15 to 20 SCCM, and a flow rate of 150 SCCM can be used. The hydrogen-based carrier gas is supplied, and the catalytic CVD process is performed at the substrate temperature and the temperature of the catalytic element similar to the above-mentioned temperature.

After that, as shown in FIG. 10E, a material (such as a Mo-Ta alloy) with a thickness of, for example, 400 nm is deposited by sputtering to serve as the gate electrode and the gate line. After that, make To supply hydrogen-based carrier gas at a flow rate of 150 SCCM, PH supplied at a flow rate of 2 to 20 SCCM₃, And monosilane supplied at a flow rate of 20 SCCM, using a method similar to that described above to deposit a doped phosphorous polycrystalline silicon film with a thickness of, for example, 400 nm by catalytic CVD or the like. After that, the gate electrode is patterned by a photolithography process and an etching process well known to those skilled in the art to form the gate electrode 75 and the gate line. In the case of using the doped phosphorous polycrystalline silicon film, after removing the photoresist mask, a silicon oxide film is formed on the surface of the doped phosphorous polycrystalline silicon film 75 by catalytic CVD or the like.

After that, as shown in FIG. 10F, the pMOSTFT area is covered by the photoresist 78, and will be doped (for example) 1×10 by ion implantation or ion doping.¹⁵ atoms/cm²N-type impurities (such as arsenic or phosphorus ions) 79 to form the n-type of nMOSTFT⁺Type source region 80 and drain region 81, so that the resulting source region and drain region have 2x10²⁰ Atoms/cc donor concentration.

After that, as shown in FIG. 10G, the nMOSTFT area is covered by the photoresist 82 and will be doped (for example) 1×10 by ion implantation or ion doping.¹⁵ atoms/cm²Dose of p-type impurities (such as boron ions) 83, thereby forming the p⁺Type source region 84 and drain region 85, so that the resulting source region and drain region have 2x10²⁰ Atom/cc receiver concentration. Then, an annealing treatment is performed for 5 minutes at a temperature of about 900°C in a nitrogen environment, thereby activating the impurity ions doped in each pole region so that each pole region has all the impurity (carrier) concentration .

After that, as shown in FIG. 10H, a method similar to that described above is used to form an interlayer insulating film 86 in a multilayer form by catalytic CVD or the like. The multilayer form is composed of a silicon oxide film having a thickness of, for example, 100 nm, The thickness is (example For example, a 400 nm phosphosilicate glass (PSG) film and a silicon nitride film with a thickness of (for example) 200 nm are composed. Among them, O diluted with He supplied at a flow rate of 1 to 2 SCCM can be used₂, Monosilane supplied at a flow rate of 15 to 20 SCCM and a hydrogen-based carrier gas supplied at a flow rate of 150 SCCM (hydrogen-based carrier gas is also supplied when forming other layers) to form a silicon oxide film; use 1 to 20 Phosphine supplied at SCCM flow rate, O diluted with He supplied at 1 to 2 SCCM flow rate₂And silicon hydride supplied at a flow rate of 15 to 20 SCCM to form a PSG film; and ammonia supplied at a flow rate of 50 to 60 SCCM and silicon hydride supplied at a flow rate of 15 to 20 SCCM to form a silicon nitride film. Please note that different processes can be used to form the interlayer insulating film.

After that, as shown in FIG. 10I, a contact hole is formed at a predetermined position in the formed insulating film 86, and an electrode material with a thickness of 1 μm is deposited by sputtering or the like at a temperature of 150°C so as to cover the entire surface of the contact. Covered by deposited electrode material. Then, the deposited electrode material is patterned to form the source electrode 87 and the data line of the nMOSTFT in the pixel area, and the source electrodes 88 and 90, the drain electrodes 89 and 91 of the pMOSTFT and the nMOSTFT are formed in the peripheral circuit area and connected to each other. In the previous process, a catalytic CVD process can be used to deposit aluminum.

Then, by, for example, a CVD process, an interlayer insulating film 92 of silicon oxide or the like is formed on the surface. After that, the hydrogenation and calcining process was performed at 400° C. in a synthetic gas environment for a time length of 30 minutes. After that, as shown in FIG. 10J, contact holes are formed in the interlayer insulating films 92 and 86 at positions corresponding to the drain region of the nMOSTFT in the pixel area, and a transparent electrode material is deposited on the entire surface by vacuum evaporation or the like ( Such as ITO (Indium Tin Oxide; oxidation Indium tin), which is tin-doped indium oxide). Then, the transparent electrode material is patterned to form a transparent pixel electrode 93 connected to the drain region 81 of the nMOSTFT in the pixel area. After that, heat treatment (performed in a synthetic gas environment at a temperature of 200 to 250° C. for 1 hour) is performed to reduce the contact resistance and improve the transparency of the ITO film.

Therefore, an active matrix substrate (hereinafter also referred to as a TFT substrate) is obtained, and the obtained TFT substrate can be used to manufacture a light-transmitting LCD. As shown in FIG. 10K, the method of manufacturing a light-transmitting LCD is to form a multilayer structure on the pixel electrode 93, including an alignment film 94, a liquid crystal 95, an alignment film 96, a transparent electrode 97 and a reverse substrate 98.

The process described above can also be used to manufacture reflective LCDs. Figure 14A shows an implementation of a reflective LCD structure. In the implementation shown in FIG. 14A, the reflective film 101 is deposited on the insulating film 92 having a rough surface, and is connected to the drain of the MOSTFT.

The liquid crystal cell of this LCD can be constructed by facing the panel to the skin (applicable to liquid crystal panels with a medium/large size equal to or greater than 2 inches). In this case, the polythioimide alignment films 94 and 96 are formed on the TFT substrate 61, and the entire surface of the reverse substrate 98 is covered with an ITO (Indium Tin Oxide; indium tin oxide) electrode 97 to make the polysulfide The ammonia alignment film contacts the surface of the component to be formed. A polythioimide film with a thickness of 50 to 100 nm can be formed by a roll coating method, a spin coating method, etc., and curing is performed at a temperature of 180°C for 2 hours.

Then, the TFT substrate 61 and the reverse substrate 98 are subjected to polishing treatment or optical alignment treatment. Cotton, man-made fibers, etc. can be used as polishing materials. most It is better to use cotton because it does not form a polished powder and provides a better retarding effect. In the optical alignment process, the liquid crystal molecules are irradiated with linearly polarized ultraviolet rays, so that the liquid crystal molecules are arranged in a non-contact manner. If the polishing method is not used, polarized or non-polarized light rays can also be irradiated at an oblique angle to obtain the alignment film, thereby forming a macromolecular alignment film (for this purpose, a specific example of a macromolecular composition that can be used is a Polymethylmethacrylate (polymethylmethacrylate).

After cleaning, a common agent is then applied on the TFT substrate 61, and a sealant is applied on the reverse substrate 98. Water or isopropanol can be used for cleaning to remove polished powder. Common agents may be acrylics, epoxy acrylics or epoxy adhesives containing conductive fillers. The sealant may be an acrylic, epoxy acrylic, or epoxy adhesive. The curing may be performed using heating, ultraviolet ray irradiation, or ultraviolet ray irradiation and heating. From the standpoint of registration accuracy and productivity, it is desirable to use ultraviolet ray irradiation and heating at the same time.

Then, after spreading the interval to obtain a gap on the reverse substrate 98, the TFT substrate 61 and the reverse substrate 98 are combined together. The relative positioning between the reverse substrate 98 and the TFT substrate 61 is performed by accurately aligning the alignment mark formed on the reverse substrate 98 with the alignment mark formed on the TFT substrate 61. After that, the sealant is temporarily semi-cured by ultraviolet radiation, and the sealant is cured by heating.

After that, scribing and separation are performed to obtain a liquid crystal panel including the TFT substrate 61 and the reverse substrate 98.

Then, the liquid crystal 95 is injected into the gap between the two substrates 61 and 98. After that, the injection hole was sealed with ultraviolet adhesive and cleaned with isopropyl alcohol. Although the liquid crystal 95 used herein may be any kind of liquid crystal, the most widely used liquid crystal is nematic liquid crystal. When nematic liquid crystals are used in TN (twist nematic) mode, high-speed response can be achieved.

After that, in order to align the liquid crystal 95, the liquid crystal 95 is heated and rapidly cooled.

By thermoelectric compression welding, the flexible lead is connected to the panel terminal of the TFT substrate 61 via an anisotropic conductive film. In addition, the polarizer is soldered to the reverse substrate 98.

As far as the liquid crystal panel is constructed as a single panel structure (the size of the liquid crystal panel is preferably less than 2 inches), after the polythioimide alignment films 94 and 96 are formed on the device surface of the TFT substrate 61 and the reverse substrate 98, Linearly polarized ultraviolet rays are used to polish the two substrates or non-contact alignment treatments.

After that, the TFT substrate 61 and the reverse substrate 98 are cut or scribed into individual units of the LCD panel, and cleaned using water or IPA. Then, after applying a common agent on the TFT substrate 61 and a sealant containing a gap on the reverse substrate 98, the TFT substrate 61 and the reverse substrate 98 are combined together. The execution of the following processing steps is similar to the execution of the processing steps described above.

In the LCD as described above, a CF (color filter) substrate including a color filter layer (not shown in the figure) disposed under the ITO electrode 97 is used as the reverse substrate 98. In this case, the light incident on the surface of the reverse substrate 98 is reflected by the reflective film 93 having a high reflection coefficient, and is output to the outside of the surface of the reverse substrate 98.

Just use the on-chip color filter (OCCF) structure In other words, the color filter plate is arranged on the TFT substrate 61, and only the ITO electrode (or the ITO electrode with a black mask) is arranged on the entire surface of the reverse substrate 98.

As for the light-transmitting LCD, the LCD may be produced as an on-chip color filter (OCCF) structure or an on-chip black (OCB) structure, as described below.

As shown in FIG. 10L, at a position corresponding to the drain electrode, an additional window is formed in a multilayer insulating film 86 composed of phosphosilicate glass/silicon oxide, and an embedded aluminum drain electrode is used to cultivate the window. After coating a predetermined thickness (1 to 1.5 μm) of photoresist 99 (with R, G, and B pigments scattered in the corresponding section), the photoresist is patterned to retain only the desired part (Corresponding to pixels), thereby forming color filter layers 99(R), 99(G), and 99(B) of each color (in the form of on-chip color filter plates). The drain window will also be formed in the previous processing steps. In this LCD, opaque substrates such as ceramic substrates, low-transmittance glass substrates, or heat-resistant resin substrates cannot be used.

Afterwards, the light-shielding layer 100' serving as a black mask layer is formed by patterning the metal so that the area containing the contact hole can be connected to the drain of the MOSTFT in the display area, and the color filter in the area around the contact hole The light layer is covered by the light shielding layer 100'. Specifically, the light-shielding layer 100' is formed by depositing molybdenum with a thickness of 200 to 250 nm by sputtering, and then patterning it so that only the area covered by the light-shielding layer 100' can be shielded from light.

After that, a transparent resin film 92 for polarization is formed, and a transparent ITO electrode 93 is formed on the polarization film 92 to connect the transparent ITO electrode 93 to the light-shielding layer 100' via a through hole formed on this polarization film 92 .

By forming the color filter 99 and the black mask 100' in the display array area, the aperture ratio of the liquid crystal panel can be improved, and the total power consumption of the display module including the backlight unit can be reduced.

FIG. 11 shows a schematic diagram of the entire structure of an active matrix liquid crystal display (LCD) including the above-mentioned top-filled gate type MOSTFT and an integrated driving circuit. The active matrix LCD is constructed as a flat panel structure, which is composed of a main substrate 61 (served as an active matrix substrate) and a reverse substrate 98 that are welded to each other via a gap (not shown in the figure), in which liquid crystal (not shown in the figure) is placed and Sealed between the two substrates 61 and 98. An array of pixel electrodes 93, display units (each display unit includes a switching element for driving a corresponding pixel electrode), and peripheral driving circuits (which are connected to the display unit) are arranged on the surface of the main substrate 61.

The switching element of each display unit is constructed by top-fill gate type nMOSTFT, pMOSTFT or CMOSTFT with LDD structure. It is also possible to use top injection gate type CMOSTFT, nMOSTFT or pMOSTFT or any hybrid method to construct peripheral circuits. The peripheral drive circuit includes a horizontal drive circuit and a vertical drive circuit. These drive circuits are usually arranged on different surfaces. The horizontal drive circuit is used to supply data signals and drive the MOSTFT of each pixel one by one horizontal line, and the vertical drive circuit is used To scan the lines one by one to drive the gates of the MOSTFTs of the respective pixels. The driving circuit can be constructed to be suitable for pixel-to-pixel/analog scanning mechanism or line-to-line/digital scanning mechanism.

As shown in FIG. 12, the MOSTFT is arranged at the intersection between the gate bus line and the data bus line, where the extension direction of each gate bus line is perpendicular to the extension direction of each data bus line. Image information is through Write MOSTFT to the liquid crystal capacitor (C_LC), and will retain the charge until the next information is supplied. However, the channel resistance of the MOSTFT is not enough to retain the image information to a sufficient degree, and the liquid crystal voltage corresponding to the image information will decrease due to leakage current. In order to reduce the liquid crystal voltage drop caused by this kind of leakage current, an additional storage capacitor (auxiliary capacitor) C can be configured in parallel with the liquid crystal capacitor_S. In LCDs, the necessary characteristics of MOSTFTs vary depending on whether they are used in pixels (display units) or peripheral drive circuits. When a MOSTFT is used in a pixel, the MOSTFT must be able to control its off-current at a sufficiently low level and provide a sufficiently large on-current. In order to meet the foregoing requirements, the MOSTFT used in the display unit is constructed with an LDD structure, which can reduce the electric field between the gate and the drain, so that the effective electric field supplied to the channel area can be reduced, thereby reducing the off current (off-current). This can also result in reduced characteristic changes. However, the LDD structure requires a complicated manufacturing process. Another problem is to increase the size of the device. In addition, the available on-current is reduced. Therefore, it must be optimized depending on the purpose.

Examples of liquid crystals that can be used in this article include: TN liquid crystal (nematic liquid crystal used in the TN mode of the active matrix addressing mechanism), STN (super twisted nematic; super twisted nematic) liquid crystal, GH (guest-host; guest-host) ) Liquid crystal, PC (phase change) liquid crystal, FLC (ferroelectric liquid crystal), AFLC (antiferroelectric liquid crystal) and PDLC (polymer-dispersed liquid crystal), Among them, these types of liquid crystals suitable for various modes can be used.

Example of the second manufacturing LCD process

The following describes a second example of the process step sequence for manufacturing an LCD (liquid crystal display) using a polycrystalline silicon MOSTFT formed through a low-temperature process (this process step sequence can also be used to manufacture organic EL or FED, as described below).

In this example, the substrate 61 used in the first example is not used, but a substrate made of aluminoborosilicate glass or borosilicate glass is used, and the implementation shown in FIGS. 10A and 10B step. That is, the polycrystalline silicon film 67 is formed on the substrate 61 by the catalytic CVD and concentrated annealing treatment, and the polycrystalline silicon film 67 is patterned into an island shape. After that, an nMOSTFT is formed in the display area, and nMOSTFT and pMOSTFT are formed in the peripheral circuit area. In the previous manufacturing process, other components are also formed, such as diodes, capacitors, inductors, and resistors. As in the first example, although the process described below is related to MOSTFT, the process described below is also applicable to manufacturing other devices.

After that, as shown in FIG. 13A, in order to reduce the V_thControl to the optimal value, the nMOSTFT in the display area and the nMOSTFT in the peripheral circuit area will be covered by the photoresist 82, and the 1x10 will be reduced by ion implantation or ion doping.¹² atoms/cm²A dose of n-type impurities (such as phosphorus or arsenic) 79 is doped into the pMOSTFT area in the peripheral circuit area, so that the doped part has a 2×10¹⁷ atoms/cc impurity concentration. Then, as shown in FIG. 13B, the pMOSTFT area in the peripheral circuit area is covered by the photoresist 82, and the nMOSTFT in the display area and the peripheral circuit area in the display area are covered by the ion implantation method or ion doping method. 5x10 doped in nMOSTFT area¹¹ atoms/cm²P-type Impurities (such as boron) 83, by ion implantation or ion doping, so that these regions have 1x10¹⁷ Atom/cc receiver concentration.

After that, as shown in FIG. 13C, in order to improve the switching performance, N^-Type LDD (Lightly Doped Drain; lightly doped drain) part. Using a photolithography process known to those skilled in the art, the gate area of the nMOSTFT in the display area and the entire pMOSTFT area and the entire nMOSTFT area in the peripheral circuit area are covered by the photoresist 82 and will be ion implanted Method or ion doping method, doping 1x10 in the exposed source region/drain region in the display area¹³ atoms/cm²Dosage of n-type impurity 79 (such as phosphorus), so that the doped area has 2x10¹⁸ atoms/cc donor body concentration, thereby forming n^-Type LDD site.

After that, as shown in FIG. 13D, the entire nMOSTFT in the display area and the entire nMOSTFT area in the peripheral circuit area are covered by the photoresist 82, and the gate area of the pMOSTFT in the peripheral circuit area is also covered by the photoresist.Agent82 Covered. Doping by ion implantation or ion doping, doping 1x10 in the exposed source/drain regions not covered by the photoresist 82¹⁵ atoms/cm²Dosage of P-type impurities 83 (such as boron), thereby forming a 2x10²⁰ atoms/cc receiver concentration P⁺-Type source region 84 and drain region 85.

After that, as shown in FIG. 13E, the pMOSTFT area in the peripheral circuit area is covered by the photoresist 82, and the LDD portion of the nMOSTFT in the display area and the gate area of the nMOSTFT in the peripheral circuit area are also covered by the photoresist 82. cover. Doping by ion implantation or ion doping, doping 1x10 in the exposed source/drain regions of the nMOSTFT in the display area and the peripheral circuit area¹⁵ atoms/cm²N-type impurity 79 (such as phosphorus or boron) at a dose, thereby forming a Have 2x10²⁰ atoms/cc donor concentration of N⁺-Type source region 80 and drain region 81.

Then, as shown in FIG. 13F, a multi-layer film serving as the gate insulating film 68 is formed by plasma enhanced CVD, reduced pressure CVD, or catalytic CVD, wherein the multi-layer film is composed of a silicon oxide layer with a thickness of 40 to 50 nm, A silicon nitride layer with a thickness of 10-20 nm and a silicon oxide layer with a thickness of 40-50 nm are composed. The RTA treatment is performed at a temperature of about 1000° C. for about 10 to 20 seconds using an infrared lamp or the like, thereby activating the doped n-type impurities and p-type impurities, so that the doped region has a desired carrier concentration.

After that, an aluminum film containing 1% silicon with a thickness of 400 to 500 nm is formed on the entire surface by sputtering. After that, the film is patterned by a photolithography process and an etching process well known to those skilled in the art to form the gate electrode 75 of each MOSTFT, and the gate line is formed. After that, a multi-layer insulating film 86 is formed by plasma enhanced CVD, catalytic CVD, etc., which is composed of a silicon oxide layer with a thickness of 100 to 200 nm and a phosphosilicate glass (PSG) layer with a thickness of 200 to 300 nm. Constituted.

Afterwards, through the photolithography process and the etching process well known by those skilled in the art, windows are formed at positions corresponding to the source/drain regions of all MOSTFTs in the peripheral circuit area and the source regions of nMOSTFTs in the display area. In this process, CF can be used₄The silicon nitride film is etched with plasma, and the silicon oxide film and phosphosilicate glass film are etched with a hydrofluoric acid-based etchant.

After that, as shown in FIG. 13G, an aluminum film containing 1% silicon with a thickness of 400 to 500 nm is formed on the entire surface by sputtering. Then, through the photolithography process and the etching process, all the MOSTFTs in the peripheral circuit area are formed. The source/drain regions 88, 89, 90, and 91 form the source electrode 87 and the data line of the nMOSTFT in the display area.

After that, although not shown in the figure, a silicon oxide film with a thickness of 100 to 200 nm and a phosphosilicate with a thickness of 200 to 300 nm are formed on the entire surface by plasma enhanced CVD, reduced pressure CVD, or catalytic CVD. A silicon nitride film with a glass (PSG) film thickness of 100 to 300 nm. Then, the hydrogenation and calcination treatments were performed at 400°C in a synthetic gas environment for a time period of 1 hour. Then, a contact hole in the drain region of the nMOSTFT in the display region is formed.

In the previous process, for plasma-enhanced CVD to form a passivation silicon nitride film containing a large amount of hydrogen with a thickness of 500 to 600 nm, if the hydrogenation treatment is performed at 420°C for 30 minutes in a nitrogen or synthetic gas environment After a period of time, hydrogen diffuses in the passivation silicon nitride film, thereby improving the interface characteristics, and because the dangling bonds are bonded with hydrogen, the crystalline quality of the polycrystalline silicon film can be improved. Thus, an increase in carrier mobility can be achieved. Silicon nitride film can be used to block hydrogen. Therefore, the hydrogenation effect can be enhanced by sandwiching the polycrystalline silicon film between the silicon nitride films, thereby confining hydrogen between the silicon nitride films, as in this embodiment. Specifically, it is best to form a multi-layer structure film, the composition of which is: glass substrate/silicon nitride film for blocking Na ions and protective effects + silicon oxide film/polycrystalline silicon film/gate insulating film (silicon oxide film) )/Gate electrode/silicon oxide film and silicon nitride film for passivation (other specific embodiments also hope to use this structure). In this structure, when the hydrogenation process is performed, the aluminum alloy film containing 1% silicon and the silicon in the source/drain regions are sintered at the same time, and ohmic contacts are formed.

For light-transmitting LCDs, the silicon oxide film and phosphorus in the pixel window will be removed. Silicate glass film and silicon nitride film. For reflective LCDs, there is no need to remove the silicon oxide film, phosphosilicate glass film, and silicon nitride film in the pixel window (the same applies to LCDs described in other content).

For the light-transmitting LCD, as shown in FIG. 10J, a transparent acrylic resin film with a thickness of 2 to 3 μm is formed by a spin coating method. A window is formed in the transparent resin film on the drain region of all MOSTFTs in the display area. Then, an ITO film with a thickness of 130 to 150 nm is formed on the entire surface by sputtering. After that, the ITO film is patterned to form a transparent ITO electrode connected to the drain of the nMOSTFT in the display area through a photolithography process and an etching process well known to those skilled in the art. After that, heat treatment (performed in a synthetic gas environment at a temperature of 200 to 250° C. for 1 hour) is performed, thereby reducing the contact resistance and increasing the transparency of the ITO film.

In the case of reflective LCDs, a photosensitive resin film with a thickness of 2 to 3 μm is formed on the entire surface by spin coating technology. After that, by the photolithography process and the etching process well known to those skilled in the art, a pattern including alternating concave and convex levels is formed in at least the pixel area. Then, reflowing is performed, thereby forming a lower alternating concave-convex-level reflector. At the same time, a window is formed in the photosensitive resin film at the position corresponding to the drain of the nMOSTFT in the display area. After that, an aluminum film containing 1% silicon with a thickness of 300 to 400 nm is formed on the entire surface by sputtering. After that, the aluminum film outside the pixel area is removed by the photolithography process and the etching process well known to those skilled in the art, thereby forming the alternate concave-convex aluminum reflector connected to the drain electrode of the nMOSTFT in the display area. After that, in a synthetic gas environment at 300°C The calcining treatment is performed for a length of time of 1 hour.

In the previous process, if the concentrating annealing process is performed after the source/drain regions of the nMOSTFT are formed, the temperature of the low-crystalline silicon film will be locally increased, thereby enhancing the crystallization. Therefore, a high-quality polycrystalline silicon film exhibiting high carrier mobility is obtained. In this case, impurities (such as phosphorus, arsenic, or boron) doped in the gate channel region, the source region, and the drain region are activated, thereby improving productivity.

Bottom injection gate type MOSTFT and double gate type MOSTFT

In LCDs or other devices that include top-filled gate type MOSTFTs, a degree-filled gate type MOSTFT or a double-gate type MOSTFT can be used instead of top-filled gate type MOSTFTs. The following describes a specific example of a light-transmitting LCD including this type of MOSTFT (a reflective LCD including this type of MOSTFT can also be manufactured).

In the example shown in FIG. 14B, bottom injection gate type nMOS TFTs are formed in the display area and the peripheral circuit area. In the example shown in FIG. 14C, double-gate nMOS TFTs are formed in the display area and the peripheral circuit area. If the MOSTFT is formed as a double-gate type, the upper and lower gates can increase the driving capability, thereby increasing the switching speed. If necessary, one of the upper gate and the lower gate of the double-gate type MOSTFT can be selectively used, so that the MOSTFT can be used as a top-filled gate type MOSTFT or a bottom-filled gate type MOSTFT.

In the bottom injection gate type MOSTFT shown in FIG. 14B, reference numeral 102 denotes a gate electrode made of a heat-resistant material (such as a Mo-Ta alloy). Reference numeral 103 denotes a silicon nitride film, and reference numeral 104 denotes a silicon oxide film to form Bottom injection insulating film. On the gate insulating film, a polycrystalline silicon film 67 similar to that used in the top injection gate type MOSTFT is used to form the channel region. In the double gate type MOSTFT shown in FIG. 14C, the bottom injection type gate portion is formed in a manner similar to the bottom injection type MOSTFT. The method of constructing the top injection type gate is to form a gate insulating film 106 composed of a silicon oxide film and a silicon nitride film, and form the top injection type gate electrode 75 thereon.

Manufacturing bottom injection gate type MOSTFT

First, a heat-resistant material (such as a Mo-Ta alloy) film with a thickness of 300 to 400 nm is formed on the entire surface of the glass substrate 61 by sputtering. After that, through the photolithography process and the etching process well known to those skilled in the art, the film is etched in a cone shape at an angle of 20 to 45° to form the bottom injection type gate electrode 102 at least in the area where the TFT is to be formed, and to form the gate line . The method of selecting the glass material of the substrate 61 is similar to the above-mentioned top injection gate MOSTFT.

After that, a silicon nitride film 103 and a silicon oxide film 104 are formed by vapor phase deposition (such as plasma-enhanced CVD, catalytic CVD, or low-pressure CVD) to serve as gate insulating films and protective films, and are formed with or without Amorphous/microcrystalline silicon film 67A of tin. Then, a concentrating annealing process is performed to convert the amorphous/microcrystalline silicon film 67A into a polycrystalline silicon film 67. In the previous process, the vapor phase deposition conditions used can be similar to the vapor phase deposition conditions used in the top-injection gate MOSTFT described above. The silicon nitride film, which serves as the bottom injection gate insulating film and protective film, prevents Na ions from invading the gate area from the glass substrate. When a substrate made of synthetic quartz is used, a silicon nitride film is not necessarily required.

After that, using a method similar to the previous example described above, through the photolithography process and the etching process well known to those skilled in the art, the formation of The island shape of pMOSTFT and nMOSTFT part (only one island shape is shown in the figure). Afterwards, an appropriate amount of n-type or p-type impurities are doped by ion implantation or ion doping, so that each channel region has an optimized value V_thThe impurity concentration. In addition, an appropriate amount of n-type or p-type impurities are doped into the source/drain regions of the respective MOSTFTs by ion implantation or ion doping. Then, an annealing treatment is performed by RTA or the like to activate the impurities.

The execution of the following processing steps is similar to the execution of the processing steps of the previous example described above.

Manufacture of double gate MOSTFT

In a manner similar to the bottom injection type gate type MOSTFT, the bottom injection type gate electrode 102, the bottom injection type gate insulating films 103 and 104, and the polycrystalline silicon film 67 (with or without tin) are formed. However, if a substrate made of synthetic quartz glass is used, the silicon nitride film 103 serving as a bottom injection type gate insulating film and a protective film is not necessarily required to prevent Na ions from entering from the glass substrate.

After that, as in the previous example described above, the islands of the pMOSTFT and the nMOSTFT are formed by the photolithography process and the etching process well known to those skilled in the art. Afterwards, an appropriate amount of n-type or p-type impurities are doped by ion implantation or ion doping, so that each channel region has an optimized value V_thThe impurity concentration. In addition, an appropriate amount of n-type or p-type impurities are doped into the source/drain regions of the respective MOSTFTs by ion implantation or ion doping. Then, an annealing treatment is performed by RTA or the like to activate the impurities.

After that, a silicon oxide film and a silicon nitride film are deposited to form a top injection gate Insulating film 106. In the previous process, the vapor phase deposition conditions used can be similar to the vapor phase deposition conditions used in the manufacture of top-injection gate MOSTFTs.

After that, an aluminum film containing 1% silicon with a thickness of 400 to 500 nm is formed on the entire surface by sputtering. After that, the film is patterned by a photolithography process and an etching process well known to those skilled in the art to form the gate electrode 75 of each MOSTFT, and the gate line is formed. After that, a multilayer insulating film 86 is formed by plasma-enhanced CVD, catalytic CVD, etc., which is composed of a silicon oxide layer with a thickness of 100 to 200 nm and a phosphosilicate glass (PSG) layer with a thickness of 200 to 300 nm. It is composed of a silicon nitride layer with a thickness of 100 to 200 nm. After that, through the photolithography process and etching process well known to those skilled in the art, a multilayer insulating film is placed on the position corresponding to the source/drain regions of all MOSTFTs in the peripheral circuit area and the source area of nMOSTFTs in the display area A window is formed on the 86.

After that, an aluminum film containing 1% silicon with a thickness of 400 to 500 nm is formed on the entire surface by sputtering. In addition, through the photolithography process and etching process well known to those skilled in the art, the aluminum source/drain electrodes 87 and 88 of all MOSTFTs in the peripheral circuit area, the aluminum electrode 89 of nMOSTFT in the display area, the source lines and the mutual connect. After that, the hydrogenation and calcining treatments were performed at approximately 400° C. in a synthetic gas environment for a time period of 1 hour.

As in the first embodiment, in this embodiment, by using a vapor phase deposition process (such as catalytic CVD or plasma-enhanced CVD) and a concentrated annealing process, a low-resistance polycrystalline silicon film can be easily manufactured , Which is suitable for forming the gate channel region, source region and drain region of MOSTFT used in the display unit or peripheral driving circuit. Among them, the low-resistance polycrystalline silicon film has High-speed operation characteristics. The liquid crystal display can be manufactured by using the top injection gate type, bottom injection gate type or double gate type MOSTFT formed by using the polycrystalline silicon film in the front, wherein the display unit includes an LDD with high switching efficiency and low leakage current. MOSTFT, and can integrate other peripheral circuits including high-performance drive circuits, video signal processing circuits and memory on a single substrate. Therefore, a high-efficiency, low-cost liquid crystal panel can be manufactured, which has a narrow frame and can display high-precision and high-quality images.

Since the polycrystalline silicon film can be performed at low temperatures (300 to 400°C) and the MOSTFT using the polycrystalline silicon film according to the present invention, low strain point glass can be used as a substrate material. Therefore, low-priced large-size substrates can be used, and cost reduction can be achieved. In addition, by forming a color filter plate and a black mask in the display array area, the aperture ratio of the liquid crystal panel can be improved. In this case, there is no need for an additional color filter plate, so productivity can be improved, and cost reduction can be further achieved.

Example of the third manufacturing LCD process

Hereinafter, another example of the sequence of the processing steps of the active matrix LCD will be described with reference to FIGS. 15 to 17.

First, as shown in FIG. 15A, on the main surface of an insulating substrate 61 (made of a material such as borosilicate glass, aluminosilicate glass, quartz glass or transparent crystallized glass), at least the TFT is to be formed on the main surface A photoresist having a predetermined pattern is formed in the area. Use this photoresist as a mask, use CF₄F in plasma⁺The ions impact the substrate 61, so the substrate 61 is etched by reactive ions to form a plurality of recesses having an appropriate size and a shape of the class 223.

Class 223 will be used as graphoepitaxial growth of monocrystalline silicon. The seeds in the process are as follows. The depth d of the formed stage 223 is 0.01 to 0.03 μm, the width w is 1 to 5 μm, the length (perpendicular to the direction of the drawing paper) is 5 to 10 μm, and the angle between the side wall and the bottom surface (bottom angle) is equal to 90° . In order to prevent the penetration of Na ions from the glass substrate, a multilayer silicon nitride layer with a thickness of 50 to 200 nm and a silicon oxide film with a thickness of 300 to 400 nm can be formed on the surface of the substrate 1 before the previous etching process. Film, and a plurality of levels are formed in the silicon oxide layer.

Then, after removing the photoresist, by catalytic CVD, plasma CVD, etc., a low crystalline quality silicon film 67A with a thickness of (for example) 100 nm is formed on the entire main surface (including stage 223) of the insulating substrate 61 (With or without tin or nickel), as shown in Figure 15B.

Then, as shown in FIG. 15C, the low-crystalline quality thin silicon film 67A is irradiated with the concentrated light beam 210 to melt the low-crystalline quality thin silicon film 67A one by one. When the melted part cools by itself, graphite epitaxially grows monocrystalline silicon from the recess 223 used as a seed, thereby forming a single crystal film 67 not only in the recess but also outside the recess. If necessary, the step of forming a thin semiconductor film of low crystal quality and the step of performing concentrating annealing treatment can be repeatedly performed to form a single crystal semiconductor layer in a laminated form, thereby forming a single crystal semiconductor layer with a total thickness of several microns (also available A film having this thickness is formed similarly to the method of the example described below).

During the graphite epitaxial growth process, the single crystal thin silicon film 67 will grow in the direction of (for example) <100>. In the graphite epitaxial growth process, when high energy is applied through concentrated light irradiation, the stage 223 acts as a seed to enhance the growth of monocrystalline silicon, so the resulting monocrystalline thin silicon film 67 has high crystallinity (thickness about 50%). nm). Specifically, as shown in FIG. 16B, if there is a straight wall such as level 223 on the amorphous substrate (glass) 61, the straight wall will forcibly grow crystals along the (100) surface of the level 223. Conversely, if there are no tiers on the amorphous substrate (glass) 61, crystals will grow in any direction, as shown in FIG. 16A. By changing the step shape in various ways, as shown in FIGS. 17A to 17F, the growth direction of the growth layer can be controlled. When manufacturing MOS transistors, a (100) surface is usually used. The angle (bottom angle) of the lower edge of the formed stage 223 may be 90°, or the stage wall may be inclined inward or outward, so that the wall orientation allows crystals to grow in the desired specific direction. Generally speaking, it is desirable that the bottom angle of the level 223 be 90° or less. In addition, it is desirable that the bottom edge of the stage 223 is slightly rounded.

After the single crystal thin silicon film 67 is formed on the substrate 61 by graphite epitaxial growth during the concentrating annealing process, a single crystal thin silicon film 67 with a thickness of 50 nm is used as a function using a method similar to the above. Layer to make top injection gate MOSTFT.

The substrate 61 may be formed of a heat-resistant resin material such as polythioimide. In this case, a step 223 having a desired shape and size will be formed in the region where the TFT is to be formed, and the manufacturing process will be performed using a method similar to that described above. Specifically, for example, an imprint mold is imprinted on a polythioimide plate with a thickness of 100 μm, wherein the imprint mold has a height of 0.03 to 0.05 μm, a width of 5 μm, and a length of 10 μm, thereby forming a A recess corresponding to the shape and size of the protruding part of the impression. Or, by coating method, screen printing method, etc., a heat-resistant resin material film such as polythioimide with a thickness of 5 to 10 μm is formed on a metal plate (such as a stainless steel metal plate used as a reinforcing member) . NS After that, at least in the area where the TFT is to be formed, a stamp with the desired protrusions is imprinted on the film, which has a height of 0.03 to 0.05 μm, a width of 5 μm, and a length of 10 μm, thereby forming a stamp corresponding to the stamp A recess in the shape and size of the protrusion. After that, a single crystal thin silicon film is manufactured using a method similar to that described above, and then a MOSTFT is manufactured.

In this embodiment, as described above, after the substrate 61 is formed with a recess of the desired shape and size of the class 223, the class 223 is used as the crystal growth seed during the concentrating annealing process, and the graphite epitaxial method is used. A single crystal thin silicon film 67 is grown. The resulting single-crystal thin silicon film 67 has high carrier mobility, so the single-crystal thin silicon film 67 can be used to manufacture high-efficiency circuits on the LCD in an integrated manner, such as a driving circuit, a video processing circuit, or a memory.

The fourth example of LCD manufacturing process

Hereinafter, another example of the sequence of processing steps for manufacturing an active matrix LCD will be described with reference to FIGS. 18A to 18C.

First, as shown in FIG. 18A, a crystalline thin sapphire film 224 having a thickness of 10 to 200 nm is formed on the main surface of the insulating substrate 61 at least in the region where the TFT is to be formed, the lattice of which is matched to single crystal silicon. For example, the method of forming the crystalline thin sapphire film 224 is to oxidize trymethyl aluminum gas by means of an oxidizing gas (oxygen or water) by high-density plasma CVD, catalytic CVD, etc. The insulating substrate 61 may be made of materials such as quartz glass, crystallized glass, borosilicate glass, aluminosilicate glass, and so on.

Thereafter, as shown in FIG. 18B, by catalytic CVD, plasma CVD, etc., a low crystalline thickness of (for example) 100 nm is formed on the crystalline thin sapphire film 224. Quality silicon film 67A.

After that, as shown in FIG. 18C, the low-crystalline quality thin silicon film 67A is irradiated with a focused beam 210 to perform a focused annealing process to melt and then slowly cool the low-crystalline quality silicon film 67A to use a crystalline thin sapphire film 224 is used as a growth seed to perform heteroepitaxial growth, thereby obtaining a single crystal thin silicon film 67. Because the crystalline thin sapphire film 224 is lattice-matched to single crystal silicon, the crystalline thin sapphire film 224 can be used as a growth seed, so it can be used for heteroepitaxial growth of single crystal thin silicon with a (100) surface during the concentrating annealing process. . In the previous process, after the formation of the tier 223 similar to that described above, if the thin crystalline sapphire film 224 is formed, the graphite epitaxial growth effect provided by the tier 223 is added to the heterogeneous epitaxial growth, and can be obtained with Single crystal thin silicon film 67 with higher crystallinity. If desired, the steps of forming a thin silicon film of low crystalline quality and the steps of performing the concentrating annealing treatment can be repeated.

After the single crystal thin silicon film 67 is formed on the substrate 61 by heteroepitaxial growth during the concentrating annealing process, the single crystal thin silicon film 67 (thickness about 50 nm) is manufactured using a method similar to that described above. (For example) Top injection gate MOSTFT.

According to this embodiment, as described above, a single crystal thin silicon film 67 with high carrier mobility can be obtained by melting and slowly cooling during the concentrating annealing process, and then forming it on the substrate 61 The monocrystalline silicon is heteroepitaxially grown on the upper crystalline thin sapphire film 224 (as a growth seed). In addition, high-efficiency circuits such as drive circuits, video signal processing circuits or memory can be manufactured in an integrated manner on the LCD.

The thin crystalline sapphire film 224 can be used as a diffusion barrier layer blocking various atoms. In this way, the diffusion of impurities from the glass substrate 61 is prevented. Because the thin crystalline sapphire film can block Na ions, if the thickness of the crystalline sapphire film is thick enough, at least a silicon nitride film as a protective film is not necessarily required.

If a thin crystalline gem film is not used, another similar film can also be used. Specific examples of materials for such films include materials having a spinel structure, calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide, and zirconium oxide. The film may be formed of one or more materials selected from the materials described above.

The third specific embodiment

In this third specific embodiment, the present invention is applied to an organic or inorganic electroluminescence (EL) display. An example of such a display structure and an example of the sequence of manufacturing steps are described below. Although the top injection gate MOSTFT is used in the examples described below, it is also applicable to other types of MOSTFTs such as bottom injection gate type or double gate type.

Example of the first organic EL device structure

19A and 19B show an example of the structure of the first organic EL device. In this structure, a polycrystalline silicon film with high crystallinity and large grain size is formed on a substrate 111 such as a glass substrate (although this example and the following examples use a single crystal film as an example, a single crystal silicon film can also be used) And the gate channel region 117, the source region 120 and the drain region 121 of the switching MOSTFT-1 and the current driving MOSTFT-2 are formed in the polycrystalline silicon film. Furthermore, a gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source region and the drain region. The drain of MOSTFT-1 and the gate of MOSTFT-2 are connected to each other through the drain electrode 128, and are connected to each other through the insulating film 136. A capacitor C is formed between the drain electrode of MOSTFT-1 and the source electrode 127 of MOSTFT-2. The drain electrode 131 of the MOSTFT-2 extends to be connected to the cathode 138 of the organic EL device. In order to improve the switching characteristics, an LDD part can be formed in the switching MOSTFT-1.

Each MOSTFT is covered with an insulating film 130. The green light-emitting organic layer 132 (or the blue light-emitting organic layer 133 or the red light-emitting organic layer (not shown in the figure)) of the organic EL device is formed on the insulating film 130 so that the cathode is covered by the green light-emitting organic layer 132. The anode (first layer) 134 is formed so that the light-emitting organic layer is covered by the anode. In addition, a common anode (second layer) 135 is formed on the entire surface. Using a method similar to the above-mentioned liquid crystal display, CMOST is used to form a driving circuit, a video signal processing circuit, or a memory (this type of circuit can also be formed in the example described below).

In this structure, the organic EL layer in the organic EL display part is connected to the drain of the current driving MOSTFT-2, and the cathode (Li-Al, Mg-Ag, etc.) 138 is arranged on the surface of the substrate 111, and Anodes (ITO film) 134 and 135 are formed thereon. Therefore, in this structure, light 136 is emitted from above. As far as the MOSTFT is covered by the cathode, a large light-emitting area can be achieved. In this case, the cathode serves as a light-shielding film to prevent the emitted light from entering the MOSTFT, thereby ensuring that the leakage current is suppressed to a very low amount, and the TFT characteristics will not be degraded.

As shown in FIG. 19C, by forming a black mask (chromium, chromium dioxide, etc.) 140 in the peripheral area of each pixel, undesired light leakage (crosstalk) can be prevented, and high contrast can be obtained.

The way to realize a full-color organic EL display is to form a three-color light-emitting layer (ie, Green light-emitting layer, blue light-emitting layer and red light-emitting layer), or use a color conversion layer, or a combination of color filter and white light-emitting organic layer. It is also possible to spin-coating macromolecular composites or vacuum evaporating metal composites to form luminescent materials of various colors. Furthermore, in this case, full-color organic EL components with high reliability, high quality, high accuracy and long service life can be manufactured in a highly productive manner (this goal can also be achieved in the example described below ).

The following describes an example of the sequence of the processing steps for manufacturing the organic EL device. First, as shown in FIG. 20A, after the source region 120, the channel region 117, and the drain region 121 are formed using the polycrystalline silicon film formed through the processing steps as described above, a gate insulating film 118 is formed, and by sputtering Mo-Ta alloy, etc. and the photolithography process and etching process well known to those skilled in the art are used to form the gate electrodes 115 of MOSTFT-1 and MOSTFT-2 on it. The gate line connected to the gate electrode of MOSTFT-1 is formed by sputtering and photolithography and etching processes that are well known to those skilled in the art (this process can also be used in the example described below). After that, a protective film (such as a silicon oxide film) 137 is formed by a vapor phase deposition technique (such as catalytic CVD) (this processing step can also be used in the example described below). Then, the source electrode 127 and the ground line of the MOSTFT-2 are formed. In addition, a protective film (silicon oxide/silicon nitride multilayer film) 136 is formed, and an RTA (Rapid Thermal Anneal) process (for example, at a temperature of about 1000°C for 30 seconds) is performed by using an infrared lamp or the like to The n-type impurities and p-type impurities doped by the ion doping method are activated.

After that, as shown in FIG. 20B, in the source region/drain region corresponding to MOSTFT-1 A window is formed at the position of the MOSTFT-2 gate area and the MOSTFT-2 gate area. Afterwards, as shown in FIG. 20C, an aluminum film containing 1% silicon is formed on the entire surface by sputtering, and the film is patterned by a photolithography process and an etching process well known to those skilled in the art, so that the film contains 1% The interconnection 128 formed by aluminum of silicon connects the drain electrode of MOSTFT-1 and the gate electrode of MOSTFT-2. At the same time, the source electrode of MOSTFT-1 and the source line connected to this source electrode are made of aluminum containing 1% silicon. form. After that, a protective film (silicon oxide/phosphosilicate glass/silicon nitride) 122 is formed, and a window is formed at a position corresponding to the drain of MOSTFT-2. Then, a cathode 138 connected to the drain of MOSTFT-2 is formed in the light-emitting area.

Thereafter, as shown in FIG. 20D, an organic light emitting layer 132 and anodes 134 and 135 are formed.

In a traditional active matrix organic EL display integrating peripheral driving circuits, pixels are designated by X signal lines and Y signal lines, and the switch MOSTFT at the designated position is turned on. Thus, the image data is stored in the signal storage capacitor located on the pixel. In this way, the current control MOSTFT is turned on, and the bias current corresponding to the image data is supplied to the organic EL device through the power line, thereby emitting light. However, when the MOSTFT is formed of amorphous silicon, V_thWill be different, so the current will respond to V_thChange and change. This will cause the image quality to change. In addition, low carrier mobility limits the maximum current that can be driven at high speed. There is also a problem that because it is difficult to form a p-channel, it is difficult to form a CMOS circuit, even if the circuit complexity of the CMOS circuit is extremely low.

On the contrary, as described above, the technology according to the present invention can be manufactured with high reliability Large-size polycrystalline silicon TFT with high temperature and high carrier mobility, and can be used to manufacture CMOS circuits.

In this technology, there are two ways to form a green (G) light-emitting organic EL layer, a blue (B) light-emitting organic EL layer and a red (R) light-emitting organic EL layer with a thickness of 100 to 200 nm, using small molecules The organic EL layer formed by the composite is by vacuum evaporation technology, and the organic EL layer formed by the macromolecular composite is by coating technology, such as immersion/coating technology or spin coating technology, or inkjet Technology so that R, G, and B light-emitting polymers are arranged in designated positions.

When a metal composite is used, a layer of sublimable material is deposited by vacuum evaporation.

Each organic EL layer can be formed as a single-layer type, a double-layer type, or a three-layer type, as described below. For example, in this article, it is assumed that a small molecule composition is used to form each organic EL layer into a three-layer structure.

Single-layer structure: anode/bipolar light-emitting layer/cathode double-layer structure: anode/hole transport layer/electron transport-light-emitting layer/cathode, or anode/hole transport-light-emitting layer/electron transport layer/cathode three-layer structure: Anode/hole transport layer/light-emitting layer/electron transport layer/cathode, or anode/hole transport-light-emitting layer/carrier blocking layer/electron transport light-emitting layer/cathode In the structure shown in Figure 19H, the organic light-emitting layer It is replaced by light-emitting polymers that are well known in the art to obtain passive matrix type or active matrix type light-emitting polymers (this goal can also be achieved in the examples described below).

Example of the second organic EL device structure

21A and 21B show an example of the structure of a second organic EL device. As in the first structure, in this second structure, the high crystallinity and large grain size polycrystalline silicon film formed according to the technology of the present invention as described above is used to form the switching MOSTFT-1 and the switch MOSTFT-1 on the substrate 111 such as a glass substrate. The current drives the gate channel region 117, the source region 120, and the drain region 121 of the MOSTFT-2. Furthermore, a gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source region and the drain region. The drain of MOSTFT-1 and the gate of MOSTFT-2 are connected to each other via a drain electrode 128, and a capacitor C is formed between the drain of MOSTFT-1 and the drain electrode 131 of MOSTFT-2 via an insulating film 136. The source electrode 127 of the MOSTFT-2 extends to be connected to the anode 144 of the organic EL device. In order to improve the switching characteristics, an LDD part can be formed in the switching MOSTFT-1.

Each MOSTFT is covered with an insulating film 130. The green light-emitting organic layer 132 (or the blue light-emitting organic layer 133 or the red light-emitting organic layer (not shown in the figure)) of the organic EL device is formed on the insulating film 130 so that the anode is covered by the green light-emitting organic layer 132. The cathode (first layer) 141 is formed so that the light-emitting organic layer is covered by the anode.

In addition, a common cathode (second layer) 142 is formed on the entire surface. In this structure, the organic EL layer in the organic EL display part is connected to the source of the current driving MOSTFT-2, and the organic EL layer is formed so that the anode 144 is formed on the surface of the substrate 111 such as a glass substrate. Covered by organic EL layer. The cathode 141 is formed so that the organic EL layer is covered by the cathode 141, and an additional cathode 142 is formed on the entire surface. Therefore, in this structure, light 136 is emitted from below. In this structure, the mediation The area between the organic EL layer and the MOSTFT is covered by the cathode. That is, for example, after the green light-emitting organic EL layer is formed by vacuum evaporation or the like, the green light-emitting organic EL component is formed by a dry etching process and a photolithography process, and the green light-emitting organic EL component and the red light-emitting component are continuously formed in a similar manner. Organic EL components. Finally, using a magnesium-silver alloy or an aluminum-lithium alloy, a cathode (electron injection layer) 141 is formed on the entire surface. In addition, an additional cathode layer (electron injection layer) 142 is formed so that the underlying structure is sealed by this layer of cathode layer 142. This structure (especially the cathode 142) prevents moisture from penetrating into the area between the organic EL layers, thereby preventing degradation of the organic EL layer and preventing electrode oxidation, thus ensuring long service life, high quality and high reliability (in The first structure shown in Figure 19 can also achieve this goal, in which the entire surface is covered by the anode). In addition, the cathode layers 141 and 142 can enhance heat radiation. This can suppress structural changes (melting or recrystallization) of the organic EL film due to heat, and improve the service life, quality, and reliability. Using this technology, high-precision, high-quality, full-color organic EL layers can be manufactured at low cost and with high productivity.

As shown in FIG. 21C, by forming a black mask (chromium, chromium dioxide, etc.) 140 in the peripheral area of each pixel, undesired light leakage (crosstalk) can be prevented, and high contrast can be obtained. The black mask 140 is covered by the silicon oxide film 143 (it can be formed at the same time using the same material as the gate insulating film 118).

The sequence of processing steps for manufacturing an organic EL device will be described below. First, as shown in FIG. 22A, after the source region 120, the channel region 117, and the drain region 121 are formed using a polycrystalline silicon film formed through the above-mentioned processing steps by a vapor phase deposition technique (such as catalytic CVD) , Form a gate insulating film 118, And by sputtering the Mo-Ta alloy and the like and the photolithography process and etching process well known to those skilled in the art, the gate electrodes 115 of MOSTFT-1 and MOSTFT-2 are formed on it. In this process, a gate line connected to the gate electrode of MOSTFT-1 is also formed at the same time. After that, a protective film (such as a silicon oxide film) 137 is formed by vapor phase deposition technology (such as catalytic CVD), and a MOSTFT is formed by sputtering Mo-Ta alloy, etc. and the photolithography process and etching process well known to those skilled in the art. -2 drain 131 and V_ddWire. In addition, a protective film (silicon oxide/silicon nitride) 136 is formed by vapor phase deposition technology (such as catalytic CVD). An RTA (Rapid Thermal Anneal) process (for example, at a temperature of about 1000° C. for 10 to 30 seconds) is performed using an infrared lamp or the like to activate the impurities doped by the ion implantation method.

Then, as shown in FIG. 22B, through a dry etching process and a photolithography process well known to those skilled in the art, windows are formed at positions corresponding to the source/drain regions of MOSTFT-1 and the gate region of MOSTFT-2. Then, as shown in FIG. 22C, an aluminum film containing 1% silicon is deposited on the entire surface by sputtering, and the film is patterned by a photolithography process and an etching process well-known to those skilled in the art, so that the film contains 1% The interconnection 128 formed by the aluminum of silicon connects the drain electrode of MOSTFT-1 and the gate electrode of MOSTFT-2. At the same time, the source line connected to the source electrode of MOSTFT-1 is formed of aluminum containing 1% silicon. Then, a protective film (silicon oxide/phosphosilicate glass/silicon nitride) 130 is formed, and a window is formed at a position corresponding to the source of MOSTFT-2 through an etching process and a photolithography process well-known to those skilled in the art. After that, the anode 144 of the light-emitting component is formed by sputtering ITO, etc., and the photolithography process and etching process well known to those skilled in the art, so that the anode 144 is connected to the anode 144. Connect to the source of MOSTFT-2.

After that, as shown in FIG. 22D, a light-emitting organic layer 132 and cathodes 141 and 142 are formed.

The materials applicable to each organic EL layer and its formation method are described below. These materials and methods are not only applicable to the structure shown in FIG. 21, but also applicable to the structure shown in FIG.

By continuously evaporating the small molecule composition in vacuum, a green light-emitting organic EL layer is formed on the transparent ITO electrode connected to the current-driven MOSTFT source and used as the anode (hole injection layer) disposed on the glass substrate, as shown below .

1) The power delivery layer is formed of an amine compound (such as triallylamine derivatives, arylamine-based oligomers or aromatic triamines).

2) The light-emitting layer is formed of a green light-emitting material, such as 8-hydroxyquinoline aluminum complex (Alq).

3) The electron transport layer is formed of 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazadiene derivative (TAZ) or similar materials.

4) The electron injection layer serving as the cathode is preferably formed of a material having a work function of less than 4 eV. For example, the electron injection layer may be formed of a magnesium-silver alloy thick film with a thickness of 10 to 30 nm and an atomic ratio of 10:1, or an aluminum-lithium with a thickness of 10 to 30 nm and an atomic ratio of 10:1. (0.5 to 1%) The alloy thick film is formed by the material.

In this electron injection layer, 1 to 10 atom% of silver is added to magnesium to increase adhesion to the organic interface, and 0.5 to 1 atom% of lithium is added to aluminum.

The way of forming green pixels is as follows. First, the green pixels are photoresisted Agent coverage, and use CCl₄The gas is used to remove the cathode formed by the aluminum-lithium alloy (as the electron injection layer) by plasma etching. In addition, oxygen plasma etching is used to remove the photoresist and small molecule composition used to form the electron transport layer, the light emitting layer, and the hole transport layer. In this way, green pixels are obtained. In this process, because there is an aluminum-lithium alloy under the photoresist, etching the photoresist will not cause any problems. In the previous process, the electron transport layer, light-emitting layer, and hole transport layer are all formed using small molecule composites, so that the size of each layer is larger than the transparent ITO electrode used as the hole injection layer, and will not be in contact with each other. Then, a short circuit is formed between the electron injection layers (magnesium-silver alloy) formed on the entire surface.

After that, by continuously evaporating the small molecule composition in vacuum, a blue light-emitting organic EL layer is formed on the transparent ITO electrode connected to the source of the current-driven MOSTFT and used as the anode (hole injection layer) disposed on the glass substrate. As shown below.

1) The power delivery layer is formed of an amine compound (such as triallylamine derivatives, arylamine-based oligomers or aromatic triamines).

2) The light-emitting layer is formed of a blue light-emitting material, such as a distyryl derivative (for example, DTVBi).

3) The electron transport layer is formed of 1,3,4-oxadiazole derivative (TAZ), 1,2,4-triazadiene derivative (TAZ) or similar materials.

4) The electron injection layer serving as the cathode is preferably formed of a material having a work function of less than 4 eV. For example, the electron injection layer may be formed of a magnesium-silver alloy thick film with a thickness of 10 to 30 nm and an atomic ratio of 10:1, or an aluminum-lithium with a thickness of 10 to 30 nm and an atomic ratio of 10:1. Alloy (0.5 to 1%) Thick films are formed by materials.

In this electron injection layer, 1 to 10 atom% of silver is added to magnesium to increase adhesion to the organic interface, and 0.5 to 1 atom% of lithium is added to aluminum.

The method of forming blue pixels is as follows. First, the blue pixels are covered by photoresist and CCl is used₄The gas is used to remove the cathode formed by the aluminum-lithium alloy (as the electron injection layer) by plasma etching. In addition, oxygen plasma etching is used to remove the photoresist and small molecule composition used to form the electron transport layer, the light emitting layer, and the hole transport layer. In this way, blue pixels are obtained. In this process, because there is an aluminum-lithium alloy under the photoresist, etching the photoresist will not cause any problems. In the previous process, the electron transport layer, the light-emitting layer and the hole transport layer are all formed using small molecule composites, so that the size of each layer is larger than the transparent ITO electrode used as the hole injection layer, and will not be in contact with each other. Then, a short circuit is formed between the electron injection layers (magnesium-silver alloy) formed on the entire surface.

By continuously evaporating the small molecule composition in vacuum, a red light-emitting organic EL layer is formed on the transparent ITO electrode connected to the current-driven MOSTFT source and used as the anode (hole injection layer) disposed on the glass substrate, as shown below .

1) The power delivery layer is formed of an amine compound (such as triallylamine derivatives, arylamine-based oligomers or aromatic triamines).

2) The light-emitting layer is formed of red light-emitting materials, such as Eu(Eu(DBM)₃(phen)).

3) The electron transport layer is formed of 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazadiene derivative (TAZ) or similar materials.

4) The electron injection layer used as the cathode should preferably have a work function of less than 4 eV Of the material. For example, the electron injection layer may be formed of a magnesium-silver alloy thick film with a thickness of 10 to 30 nm and an atomic ratio of 10:1, or an aluminum-lithium with a thickness of 10 to 30 nm and an atomic ratio of 10:1. Alloy (0.5 to 1%) thick film is formed by the material.

In this electron injection layer, 1 to 10 atom% of silver is added to magnesium to increase adhesion to the organic interface, and 0.5 to 1 atom% of lithium is added to aluminum.

The way of forming red pixels is as follows. First, the red pixels are covered by photoresist and CCl is used₄The gas is used to remove the cathode formed by the aluminum-lithium alloy (as the electron injection layer) by plasma etching. In addition, oxygen plasma etching is used to remove the photoresist and small molecule composition used to form the electron transport layer, the light emitting layer, and the hole transport layer. In this way, red pixels are obtained. In this process, because there is an aluminum-lithium alloy under the photoresist, etching the photoresist will not cause any problems. In the previous process, the electron transport layer, light-emitting layer, and hole transport layer are all formed using small molecule composites, so that the size of each layer is larger than the transparent ITO electrode used as the hole injection layer, and will not be in contact with each other. Then, a short circuit is formed between the electron injection layers (magnesium-silver alloy) formed on the entire surface.

The electron injection layer serving as the cathode is preferably formed of a material having a work function of less than 4 eV. For example, the electron injection layer may be formed of a magnesium-silver alloy thick film with a thickness of 10 to 30 nm and an atomic ratio of 10:1, or an aluminum-lithium with a thickness of 10 to 30 nm and an atomic ratio of 10:1. Alloy (0.5 to 1%) thick film is formed by the material. In this electron injection layer, 1 to 10 atom% of silver is added to magnesium to increase the adhesion to the organic interface, and 0.5 to 1 atom% of lithium is added to aluminum. The film can also be formed by splashing.

Fourth specific embodiment

In this fourth specific embodiment, the present invention is applied to a field emission display. An example of the structure of a field emission display and its manufacturing sequence are described below. Although the top injection gate MOSTFT is used in the examples described below, it is also applicable to other types of MOSTFTs such as bottom injection gate type or double gate type.

The first FED structure

Figures 23A to 23C show the first FED structure implementation. In this structure, the polycrystalline silicon film with high crystallinity and large grain size formed according to the technology of the present invention as described above is used to form the switching MOSTFT-1 and the current driving MOSTFT-2 gates on a substrate 111 such as a glass substrate. The channel region 117, the source region 120, and the drain region 121. Furthermore, a gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed on the source region and the drain region. The drain of MOSTFT-1 and the gate of MOSTFT-2 are connected to each other via a drain electrode 128, and a capacitor C is formed between the drain of MOSTFT-1 and the source electrode 127 of MOSTFT-2 via an insulating film 136. The drain region 121 of the MOSTFT-2 is extended to be connected to the FEC (Field Emission Cathode) of the FED, so that the extension part serves as the emitter region 152. In order to improve the switching characteristics, LDD components can be formed in the switching MOSTFT.

Each MOSTFT is covered with an insulating film 130. On this insulating film 130, the light-shielding metal film 151 is formed using the same process steps and the same material as the FEC gate lead electrode 150, so that each MOSTFT is covered by the light-shielding metal film 151. In FEC, the emission formed by the polycrystalline silicon film An n-type polycrystalline silicon film 153 is formed on the pole region 152 to serve as a field emission emitter. The insulating films 118, 137, 136, and 130 are patterned to form openings therein, thereby patterning the emitter region 152 into an mxn emitter. A gate lead electrode 150 is formed in the entire area of the patterned insulating film 130.

The phosphor 156 covered by the black metal layer 155 serving as an anode is formed on a substrate 157 such as a glass substrate, and the substrate 157 is arranged so that the substrate 157 and the FEC face each other. The gap between the substrate 157 and the FEC maintains a high vacuum state.

In this FEC structure, the n-type polycrystalline silicon film 153 formed on the polycrystalline silicon film 152 formed according to the technology of the present invention is exposed through the openings of the gate lead electrode 150, so that each exposed area is used as an emitter. Surface-emitting emitter of electron 154. Since the polycrystalline silicon film 152 located under the emitter is composed of large-size crystal grains (greater than several hundred nm), when the n-type polycrystalline silicon film 153 is formed on the polycrystalline silicon film 152 by catalytic CVD or the like The lower polycrystalline silicon film 152 serves as a crystal growth seed, so the crystal grains of the polycrystalline silicon film 153 can be grown to a larger grain size. As a result, micro-irregularities 158 that can enhance electron emission are formed on the surface of the emitter.

It is easy to manufacture FEC with a thin-film surface-emitting emitter, and it has stable emission characteristics and long service life.

Because all active elements (including the MOSTFT and diodes in the peripheral driving circuit, and the pixel array area) are maintained at the ground voltage of the light-shielding metal film 151 (it is better to use the same process steps and the same material as the gate lead electrode 150 ( Nb, Ti/Mo, etc.) to form a light-shielding metal film) covering, so the following advantages (1) and (2) can be obtained, so high quality and high performance can be achieved Reliable field emission display (FED) device.

(1) If the gas existing in the sealed container is positively ionized by the electrons emitted by the emitter (field emission cathode) 153, and if the insulating film is charged by the ionized gas, the positive charge will cause the MOSTFT located under the insulating film An undesirable inversion layer is formed in the inversion layer, and excessive current will flow through the current path formed by the inversion layer, causing the emitter current to run out of control. However, in the FED structure according to the present invention, because the insulating layer located above the MOSTFT is covered by the grounded light-shielding metal film 151, charging does not occur, and therefore, emitter current runaway does not occur.

(2) When electrons emitted from the emitter (field emission cathode) 153 collide with the phosphor 156, the phosphor 156 emits light. The light emitted by the phosphor 156 generates electrons and holes in the gate channel of the MOSTFT, resulting in leakage current. However, in the FED structure according to the present invention, the light-shielding metal film 151 formed on the MOSTFT prevents light from entering the MOSTFT, thus preventing the MOSTFT from malfunctioning.

The sequence of processing steps for manufacturing FED will be described below. First, as shown in FIG. 24A, after the polycrystalline silicon film 117 is formed on the entire surface through the processing steps described above, the polycrystalline silicon film 117 is patterned by an etching process and a photolithography process well known to those skilled in the art. It becomes an island shape to form MOSTFT-1, MOSTFT-2, and emitter in the island shape. Then, by plasma-enhanced CVD, catalytic CVD, etc., a protective silicon oxide film 159 is formed on the entire surface.

After that, in order to adjust the impurity concentration of the gate channel of MOSTFT-1 and MOSTFT-2 to reduce V_thThe control becomes the optimal value, which will be controlled by ion implantation Method or ion doping method doping 5x10 on the entire surface¹¹ atoms/cm²The dosage is like boron ion 83, so that the doped island has 1x10¹⁷ Atom/cc receiver concentration.

Then, as shown in FIG. 24B, using photoresist 82 as a doping mask, doping 1x10 in the source/drain and emitter regions of MOSTFT-1 and MOSTFT-2¹⁵ atoms/cm²Dosage of phosphorous ions 79 to form a 2x10²⁰ The source region 120, the drain region 121, and the emitter region 152 have a donor concentration of atoms/cc. After that, the protective silicon oxide film in the emitter region is removed by a photolithography process and an etching process that are well-known to those skilled in the art. Here, in order to improve the switching characteristics, the switching MOSTFT-1 can be formed containing 1 to 5x10¹⁸ LDD site of atoms/cc donor concentration.

After that, as shown in FIG. 24C, use an appropriate mixing ratio (for example, set the dopant gas concentration to 10²⁰ atoms/cc) monosilane and PH₃By catalytic CVD or bias-catalyzed CVD, an n-type polycrystalline silicon film 153 with a thickness of 1 to 5 μm and micro-irregularities 158 on the surface is formed on the polycrystalline silicon film 152 in the emitter region. During this period, the polycrystalline silicon film 152 serves as a growth seed. During the previous deposition, an n-type amorphous silicon film 160 with a thickness of 1 to 5 μm is formed on the silicon oxide film 159 and the glass substrate 111 in other regions.

After that, as shown in FIG. 24D, a catalytic AHA process is performed to remove the amorphous silicon film 160 by etching the amorphous silicon film 160 by using hydrogen-based active species (such as activated gas ions). Then, the silicon oxide film 159 is removed by etching. After that, a gate insulating film (silicon oxide film) 118 is formed by catalytic CVD or the like.

After that, as shown in Figure 24E, use the refractory metal deposited by splashing (such as Mo-Ta alloy), the gate electrodes 115 of MOSTFT-1 and MOSTFT-2 are formed, and the gate line connected to the gate electrode of MOSTFT-1 is formed. Then, after a protective film (such as a silicon oxide film) 137 is formed, an RTA (Rapid Thermal Anneal) process is performed using an infrared lamp or the like to activate the doped N-type impurities and P-type impurities. Then, a window is formed at a position corresponding to the source electrode of MOSTFT-2, and a refractory metal (such as a Mo-Ta alloy) deposited by sputtering is used to form the source electrode 127 and ground line of MOSTFT-2. In addition, a protective film (such as a silicon oxide/silicon nitride multilayer film) 136 is formed by plasma enhanced CVD, catalytic CVD, etc.

After that, as shown in FIG. 24F, windows are formed at the positions corresponding to the source/drain regions of MOSTFT-1 and the gate region of MOSTFT-2, and interconnects 128 of aluminum containing 1% silicon are formed to make MOSTFT The -1 drain and the MOSTFT-2 gate are connected to each other via interconnection 128. During this process, the source electrode of MOSTFT-1 and the source line 127 connected to the source electrode are also formed.

After that, the hydrogenation and calcining process was performed at 400° C. in a synthetic gas environment for a time length of 30 minutes.

After that, as shown in FIG. 24G, a protective film (silicon oxide/phosphosilicate glass/silicon nitride) 130 is formed, and a window of the GND line is formed. After that, as shown in FIG. 24H, the Nb film is vacuum-evaporated and then patterned to form the gate lead electrode 150 and the light-shielding metal film 151. In addition, a window is formed in the field emission cathode to expose the emitter 153 through the window, and the hydrogen-based active species (such as activated gas ions) generated during plasma treatment or AHA treatment are used for cleaning.

Traditional field emission displays can be classified into two types: single array FED and main Dynamic array FED. As far as field emission electron sources (field emitters) are concerned, various types are available. Including Spindt molybdenum emitter, conical silicon emitter, MIM tunneling emitter, porous silicon emitter, diamond emitter and surface conductivity emitter. In either type, the emitter can be integrated on a flat substrate. In the simple matrix addressing technique, the field emitters are arranged in an XY matrix, and one pixel is formed by one field emitter. The emission intensity is controlled pixel by pixel to display the image. In the active matrix addressing technology, the way to control the current emitted by the emitter is to control the gate voltage of the MOSTFT that is the drain of the MOSTFT connected to the emitter. This structure can be fabricated using a process widely used in the fabrication of silicon LSIs, because complex circuits can be formed in the peripheral area of the field emission display. However, this requires the use of a single crystal silicon substrate. Single crystal silicon substrates are very expensive, and wafer size is limited. The proposed method of manufacturing the emitter is to first deposit a conductive polycrystalline silicon film on the surface of the cathode by reduced pressure CVD, etc., and then deposit a crystalline diamond film on the polycrystalline silicon film by plasma enhanced CVD, etc. . However, the deposition temperature of the low-pressure CVD process is as high as 630°C. Therefore, glass substrates cannot be used, and the cost is increased. In addition, the crystal grain size of the polycrystalline silicon film produced by this low-pressure CVD technology is not large enough, so the crystal grain size of the crystal diamond film formed above is small, resulting in poor emitter characteristics. In addition, plasma-enhanced CVD cannot generate enough reaction energy to produce high-quality crystalline diamond films. Another problem is that a good electrical contact cannot be obtained between a transparent electrode or a cathode made of a metal such as Al, Ti, or Cr and the conductive polycrystalline silicon film. This leads to poor electron emission characteristics.

On the contrary, as mentioned above, the large-grained polycrystalline silicon film manufactured according to the present invention Excellent. That is, a large-grain polycrystalline silicon film can be formed on a glass substrate. If a large-grained polycrystalline silicon film is formed in the emitter region connected to the drain of the current driving TFT, and if an additional n-type (or n⁺Type) large-granularity polycrystalline (or single-crystalline) silicon (or cobalt) film, the lower polycrystalline silicon film is used as a growth seed, because the crystal grain size will be larger. Afterwards, if the catalytic AHA treatment is performed, the amorphous silicon film or the amorphous diamond (also called diamond-like carbon) film is reduced and etched, and a large-grain silicon/diamond film with a large number of micro-irregular surfaces is obtained. Emitter. This emitter has excellent electron emission efficiency, and good contact characteristics can be obtained between the drain and the emitter. Therefore, a high-efficiency emitter can be achieved. The emitter according to the present invention can solve the problems of the conventional technology.

The emitter region of one pixel is divided into two or more parts, and a switch MOSTFT can be connected to each part. In this structure, even if one MOSTFT fails, another MOSTFT can operate to emit electrons in the pixel. Therefore, the cost can be reduced, the production yield can be improved, and the high-reliability and high-quality emitter can be manufactured (for the same purpose, a similar structure can also be used in the examples described below). As mentioned above, when some MOSTFTs become electronically open due to malfunctions, serious problems will not occur. If some MOSTFTs become electronically short-circuited due to failures, it is necessary to isolate the failed MOSTFTs by, for example, laser repair technology. The structure according to the present invention can perform such repairs. This also helps to achieve high-reliability and high-efficiency emitters at reduced costs (this goal can also be achieved in the examples described below).

Second FED structure

Figures 25A to 25C show a second FED structure implementation. As mentioned above The first structure. In this structure, the high crystallinity and large-grain polycrystalline silicon film formed according to the technology of the present invention as described above is used to form a switching MOSTFT-1 and a current driving MOSTFT on a substrate 111 such as a glass substrate. -2 gate channel region 117, source region 120 and drain region 121. Furthermore, a gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed on the source region and the drain region. The drain of MOSTFT-1 and the gate of MOSTFT-2 are connected to each other via a drain electrode 128, and a capacitor C is formed between the drain of MOSTFT-1 and the source electrode 127 of MOSTFT-2 via an insulating film 136. The drain region 121 of the MOSTFT-2 is extended to be connected to the FEC (Field Emission Cathode) of the FED, so that the extension part serves as the emitter region 152. In order to improve the switching characteristics, an LDD part can be formed in the switching MOSTFT-1.

Each MOSTFT is covered with an insulating film 130. On this insulating film 130, the light-shielding metal film 151 is formed using the same process steps and the same material as the FEC gate lead electrode 150, so that each MOSTFT is covered with the light-shielding metal film 151. In FEC, an n-type polycrystalline diamond film 163 is formed on the emitter region 152 formed of a polycrystalline silicon film to serve as a field emitter. The insulating films 118, 137, 136, and 130 are patterned to form openings therein, thereby patterning the emitter region 152 into an mxn emitter. A gate lead electrode 150 is formed in the entire area of the patterned insulating film 130.

The phosphor 156 covered by the black metal layer 155 serving as an anode is formed on a substrate 157 such as a glass substrate, and the substrate 157 is arranged so that the substrate 157 and the FEC face each other. The gap between the substrate 157 and the FEC maintains a high vacuum state.

In this FEC structure, the n-type polycrystalline diamond film 163 formed on the polycrystalline silicon film 152 formed according to the technology of the present invention is exposed through the openings of the gate lead electrode 150, so that each exposed area is used as an emitter. Surface-emitting emitter of electron 154. Since the polycrystalline silicon film 152 located under the emitter is composed of large-size crystal grains (greater than a few hundred nm), when the polycrystalline silicon film 152 is formed on the n-type polycrystalline diamond film 163 by catalytic CVD or the like The lower polycrystalline silicon film 152 is used as a crystal growth seed, so the crystal grains of the polycrystalline diamond film 163 can be grown to a larger particle size. As a result, micro-irregularities 168 that can enhance electron emission are formed on the surface of the emitter.

It is easy to manufacture FEC with a thin-film surface-emitting emitter, and it has stable emission characteristics and long service life.

Because all active elements (including the MOSTFT and diodes in the peripheral driving circuit, and the pixel array area) are maintained at the ground voltage of the light-shielding metal film 151 (it is better to use the same process steps and the same material as the gate lead electrode 150 ( Nb, Ti/Mo, etc.) to form a light-shielding metal film) covering, that is, the insulating layer located above the MOSTFT is covered by the grounded light-shielding metal film 151, so no charging occurs, and therefore no emitter current runaway occurs. In addition, the light-shielding metal film 151 formed on the MOSTFT prevents light from entering the MOSTFT, thereby preventing the MOSTFT from malfunctioning. Therefore, a field emission display (FED) device with high quality and high reliability can be achieved.

The sequence of processing steps for manufacturing FED will be described below. First, as shown in FIG. 26A, after the polycrystalline silicon film 117 is formed on the entire surface through the above-mentioned processing steps, the polycrystalline silicon film 117 is patterned by an etching process and a photolithography process well known to those skilled in the art. To become an island Where MOSTFT-1, MOSTFT-2 and emitter are formed. Then, by plasma-enhanced CVD, catalytic CVD, etc., a protective silicon oxide film 159 is formed on the entire surface.

After that, in order to adjust the impurity concentration of the gate channel of MOSTFT-1 and MOSTFT-2 to reduce V_thThe control becomes the optimal value, and the entire surface is doped 5x10 by ion implantation or ion doping.¹¹ atoms/cm²The dosage is like boron ion 83, so that the doped island has 1x10¹⁷ Atom/cc receiver concentration.

After that, as shown in FIG. 26B, using photoresist 82 as a doping mask, doping 1x10 in the source/drain and emitter regions of MOSTFT-1 and MOSTFT-2¹⁵ atoms/cm²Dosage of phosphorous ions 79 to form a 2x10²⁰ The source region 120, the drain region 121, and the emitter region 152 have a donor concentration of atoms/cc. Afterwards, the protective silicon oxide film in the emitter region is removed by a photolithography process and an etching process that are well-known to those skilled in the art.

Then, as shown in Figure 26C, use monosilane and methane (CH₄) And N-type impurities to form a polycrystalline diamond film 163 with micro-irregularities 168 on the surface of the polycrystalline silicon film 152 in the emitter region by catalytic CVD or bias-catalyzed CVD. The crystalline silicon film 152 serves as a growth seed. During the previous deposition, a thickness of 1 to 5 μm is formed on the silicon oxide film 159 and the glass substrate 111 in other regions.⁺Type amorphous diamond film 170. Specifically, when catalyzed CVD or the like is used to form n⁺In the case of type crystal diamond film, n-type impurity gas (for example, phosphine PH₃, Arsenide AsH to provide arsenic₃Or to provide antimony stibine SbH₃) With methane CH₄Mix so that n⁺Type polycrystalline diamond film 163 has 5x10²⁰To 1x10²¹ atoms/cc impurity concentration (thickness 1000 to 5000 nm). During the previous process, an amorphous form of n is formed on the protective silicon oxide film⁺Type drill film 170. This layer of amorphous diamond film is also called DLC (Diamond Like Carbon) film.

After that, as shown in FIG. 26D, a catalytic AHA treatment is performed to remove the amorphous diamond film 170 by etching the amorphous diamond film 170 by using hydrogen-based active species (such as activated gas ions). Then, the silicon oxide film 159 is removed by etching. After that, a gate insulating film (silicon oxide film) 118 is formed by catalytic CVD or the like. In the previous catalytic AHA treatment, the amorphous diamond film will be reduced and etched by hydrogen molecules/hydrogen atoms/activated gas ions at a high temperature. At the same time, the n formed in the emitter region will be reduced and etched.⁺Type polycrystalline diamond film 163 is an amorphous component, and forms a high crystallinity n⁺Type polycrystalline diamond film 163. Through the reduction and etching process, the n of the emitter region 163⁺A large number of micro irregularities are formed on the surface of the type polycrystalline diamond film 163. During the previous process, the n on the protective silicon oxide film⁺The type amorphous diamond film is reduced and etched to remove it. It is desirable to continuously perform the catalytic CVD process and the AHA process to prevent pollution and achieve high productivity.

After that, as shown in FIG. 26E, using the refractory metal (such as Mo-Ta alloy) deposited by sputtering, the gate electrodes 115 of MOSTFT-1 and MOSTFT-2 are formed, and the gate electrodes connected to the gate electrode of MOSTFT-1 are formed. Polar line. Then, after a protective film (such as a silicon oxide film) 137 is formed, an RTA (Rapid Thermal Anneal) process is performed using an infrared lamp or the like to activate the doped n-type impurities and p-type impurities. Then, a window is formed at a position corresponding to the source of MOSTFT-2, and refractory gold deposited by sputtering is used For example, Mo-Ta alloy, the source electrode 127 and ground wire of MOSTFT-2 are formed. In addition, a protective film (such as a silicon oxide/silicon nitride multilayer film) 136 is formed by plasma enhanced CVD, catalytic CVD, etc.

After that, as shown in FIG. 26F, windows are formed at positions corresponding to the source/drain regions of MOSTFT-1 and the gate region of MOSTFT-2, and interconnects 128 of aluminum containing 1% silicon are formed to make the MOSTFT The -1 drain and the MOSTFT-2 gate are connected to each other via interconnection 128. During this process, the source electrode of MOSTFT-1 and the source line 127 connected to the source electrode are also formed.

After that, as shown in FIG. 26G, a protective film (silicon oxide/phosphosilicate glass/silicon nitride) 130 is formed, and a GND line window is formed. After that, the hydrogenation and calcining process was performed at 400° C. in a synthetic gas environment for a time length of 30 minutes. After that, as shown in FIG. 26H, the Nb film is vacuum-evaporated and then patterned to form the gate lead electrode 150 and the light-shielding metal film 151. In addition, a window is formed in the field emission cathode to expose the emitter electrode 163 through the window, and the activated gas ions generated during plasma treatment or AHA treatment are used for cleaning. Specifically, the titanium/molybdenum film or the niobium film is wet-etched using an acid-based etchant and a photolithography process well known to those skilled in the art. The silicon oxide film and the PSG film are wet-etched using a hydrofluoric acid-based etchant. Use CF₄And so on, the silicon nitride film is removed by plasma etching. The polycrystalline diamond film 163 of the field emission cathode (emitter) is subjected to a catalytic AHA treatment, thereby cleaning. In this process, hydrogen molecules/hydrogen atoms/activated gas ions are used to remove irregular organic pollution, water, oxygen/nitrogen/carbon dioxide adhered to the surface of the film at high temperature, thereby improving the electron emission efficiency.

The following list can be used as the source gas for depositing polycrystalline diamond film 163 Examples of carbon-containing composites.

1) Paraffinic hydrocarbons, such as methane, ethane, propane and butane.

2) Alkyne, such as ethyl and propyne.

3) Olefin hydrocarbons (olefin hydrocarbons), such as ethylene, propylene, butene.

4) Dioefin hydrocarbons, such as butadiene.

5) Alicyclic hydrocarbons, such as cyclopropene, cyclobutene, cyclopentene and cyclohexene.

6) Aromatic hydrocarbons, such as cyclobutdiene, benzene, toluene, xylene and naphtahlin.

7) Ketones, such as acetone, diethyl ketone and benzophenone.

8) Alcohols, such as methanol and ethanol.

9) Amines, such as trimethylamine and triethylamine.

10) Substances composed only of carbon atoms (such as graphite, coal, and coke).

In the above-listed examples, any one can be used alone, or a combination of two or more can be used.

Examples of inert gases usable herein are argon, chlorine, neon, krypton, xenon, and radon. Examples of dopants are boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsine, selenium, beryllium, and any combination of these. The doping concentration may be (for example) 10²⁰ atoms/cc.

Fifth specific embodiment

In this fifth specific embodiment, the present invention is applied to a solar storage battery, which is one of the photoelectric conversion devices. The following explains the manufacture of solar energy storage An example of the sequence of processing steps in the pool.

First, as shown in FIG. 27A, an N-type low-crystalline silicon film 7A with a thickness of 100 to 200 nm is formed on a metal substrate 111 such as stainless steel by plasma enhanced CVD, catalytic CVD, or the like. In this process, by mixing appropriate proportions of monosilane and such as PH₃Frequency doping gas to doping 1x10¹⁹To 1x10²⁰ N-type impurities at atoms/cc concentration.

After that, by plasma enhanced CVD, catalytic CVD, etc., an i-type low-crystalline quality silicon film 180A with a thickness of 2 to 5 μm is formed on the n-type low-crystalline quality silicon film 7A. After that, by plasma-enhanced CVD, catalytic CVD, etc., a p-type low-crystalline silicon film 181A with a thickness of 100 to 200 nm is formed thereon. In this process, by mixing proper proportions of monosilane and e.g. B₂H₆P-type doping gas, doped 1x10¹⁹To 1x10²⁰ P-type impurity with atoms/cc concentration.

Then, as shown in FIG. 27B, a protective insulating film 235 (such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an oxide film) with a thickness of 50 to 100 nm is formed by plasma enhanced CVD, catalytic CVD, etc. Silicon/silicon nitride multilayer film).

The condensing annealing process is performed by irradiating the obtained low crystalline quality silicon films 7A, 180A, and 181A with condensing rays 210 emitted from a lamp, thereby converting the films into polycrystalline films 7, 180, and 181, respectively. During this annealing process, the doping impurities in each film will be activated.

After that, as shown in FIG. 27C, the protective insulating film 235 is removed, and the hydrogenation treatment is performed at 400° C. in a synthetic gas environment for a time length of 1 hour. In addition, a transparent electrode (ITO (Indium Tin Oxide; indium tin oxide) film, IZO (Indium Zinc Oxide; indium zinc oxide) film etc.) 182. After that, by depositing silver or the like through a metal mask, a wave-shaped electrode 183 with a thickness of 100 to 150 nm is formed in a predetermined area on the transparent electrode 182.

The solar storage battery according to this embodiment has a photoelectric conversion film, which is formed by the large-grained polycrystalline silicon film according to the present invention with high mobility and high conversion efficiency. In addition, the solar battery has excellent surface texture and excellent back surface texture, so the photoelectric conversion film has high light confinement efficiency and high conversion efficiency. The technology according to the present invention is not only applicable to solar storage batteries, but also applicable to other types of thin-film photoelectric conversion devices, such as photosensitive drums used in electronic musical instruments.

Although the present invention has been described with reference to the specific embodiment of the present invention, the present invention is not limited to this specific embodiment, and the specific embodiment of the present invention can be modified and changed without departing from the scope of the present invention.

For example, the vapor phase deposition method is not limited to catalytic CVD or plasma enhanced CVD. Parameters such as the number of executions of the focusing annealing process, the irradiation time, and the substrate temperature are not limited to the specified values used in the specific embodiment. In addition, the substrate material and other materials are not limited to the materials used in the specific embodiments.

The present invention is particularly suitable for forming MOSTFTs in internal circuits of displays, peripheral driving circuits, video signal processing circuits or memory. Using the polycrystalline semiconductor film or single crystalline semiconductor film according to the present invention, in addition to this type of MOSTFT, other active elements (such as diodes) and various active elements (such as resistors, capacitors, interconnects and Inductor).

From the foregoing description, it can be known that the present invention has the following advantages (1) to (10). This is because the present invention is characterized by single crystal or polycrystalline thin semiconductor The system is manufactured by using a thin semiconductor film of low crystalline quality formed on a substrate by performing concentrating annealing treatment on the thin semiconductor film of low crystalline quality, thereby melting or semi-melting the thin semiconductor film of low crystalline quality , Or heating the low crystalline quality thin semiconductor film while the low crystalline quality thin semiconductor film maintains a non-melting state, and then cooling the low crystalline quality thin semiconductor film, thereby enhancing the crystallization of the low crystalline quality thin semiconductor film.

(1) In the concentrating annealing process, the light emitted by the ultra-high pressure mercury lamp is focused into a desired form, and a thin semiconductor film of low crystal quality such as an amorphous silicon film is irradiated with focused light to reduce the low crystal quality The thin semiconductor film is heated to a molten or semi-melted state, or when the low crystalline quality thin semiconductor film is maintained in a non-melted state, the low crystalline quality thin semiconductor film is heated, and then the low crystalline quality thin semiconductor film is cooled. That is, in this method, high illuminance energy irradiated on a thin semiconductor film of low crystalline quality will heat the thin semiconductor film of low crystalline quality to a molten or semi-melted state, or when the thin semiconductor film of low crystalline quality maintains a non-melted state The thin semiconductor film of low crystalline quality is heated at time, and then the thin semiconductor film of low crystalline quality is cooled, so as to obtain a large-grained polycrystalline semiconductor with high carrier mobility and high quality, such as monocrystalline silicon or polycrystalline silicon film. membrane. This technology can greatly increase productivity and significantly reduce costs.

(2) In the concentrating annealing treatment according to the present invention, since the zone melting and recrystallization are performed when the melting zone is continuously moved, the pre-added catalytic element (such as Ni) and other impurities used to strengthen the crystallization are isolated It becomes a melted zone, so such catalytic elements or impurities can be easily removed. Therefore, no impurities remain in the resulting annealed film. In this way It is easy to obtain a polycrystalline thin semiconductor film with large particle size, high carrier mobility and high quality. Specifically, if multiple-zone melting and recrystallization are performed by repeatedly performing melting and cooling using a plurality of condensed rays emitted from a plurality of lamps, a polycrystalline thin semiconductor film with larger particle size and high quality can be obtained. The high purity obtained by this technology can produce highly stable and highly reliable devices without degrading semiconductor characteristics. In addition, in the concentrating annealing treatment technology, a simple process is used to perform zone melting and recrystallization or multiple zone melting and recrystallization, which can efficiently remove the catalytic element that has completed the enhancement of the crystallization role, and it can also be highly efficient Remove other impurities. Simplified manufacturing process can reduce costs.

(3) The crystal grains in the polycrystalline silicon film are arranged in the condensing scanning direction. Therefore, if the TFT is formed in this direction, the mismatch and stress at the edge of the crystal grains can be minimized, and the resulting polycrystalline thin silicon film has high mobility.

(4) If the concentrating annealing process is used to form another low-crystalline silicon film on the polycrystalline silicon film by zone melting recrystallization or multiple zone melting recrystallization, and if the concentrating annealing process is used to perform crystallization again By chemical conversion, a thicker polycrystalline silicon film with large particle size, high carrier mobility and high crystal quality can be formed. By repeatedly performing this process, a total thickness on the order of several microns can be obtained. In this way, not only MOS LSI can be manufactured, but also other types of devices such as bipolar LSI, CMOS sensor, CCD area/linear sensor, and solar battery can be manufactured with high efficiency and high quality.

(5) Regardless of whether ultraviolet (UV) lamps or infrared lamps are used, it is easy to The light emitted by the lamp is focused into a linear, rectangular or square shape, and can emit light continuously. In addition, the beam size and scanning pitch can be arbitrarily set. High light intensity can increase melting efficiency and total processing capacity, so cost reduction can be achieved.

(6) It is easy to control the wavelength, light intensity and irradiation time of the lamp used in the concentrating annealing treatment device. In addition, the heating/melting speed and cooling speed can be controlled by controlling the speed of moving the substrate or lamp. By controlling these parameters, a polycrystalline silicon film with desired particle size and purity can be formed.

(7) The lamp used in the concentrating annealing treatment device is cheaper than the excimer laser generator used in the excimer laser annealing treatment device, so a significant cost reduction can be achieved.

(8) In the concentrating annealing process, especially in the annealing process using ultra-high pressure mercury lamps, light with the same wavelength as the XeCl excimer laser (wavelength: 308 nm) can be used to continuously irradiate the entire film surface with a small change in energy. Therefore, the resulting crystallized semiconductor film has uniform characteristics, and the characteristics of the manufactured TFT vary little between devices. Therefore, high total processing capacity and high productivity can be achieved, thereby reducing costs.

(9) Concentrating annealing process can be used at low substrate temperature (200 to 400°C). Therefore, low-strain-point glass or heat-resistant resin can be used as the substrate material, and a large-area substrate can be manufactured at low cost. Therefore, weight and cost reduction can be achieved.

(10) The use of a single crystal or polycrystalline semiconductor film with high carrier mobility formed by concentrating annealing technology can not only manufacture top-gate type TFTs, but also other TFTs , Such as an ante gate Bottom-gate type MOSTFT and dual-gate type MOSTFT. Therefore, high-efficiency semiconductor films can be used to manufacture high-speed and high-current semiconductor devices, electro-optical devices, and high-efficiency solar batteries. Specific examples of devices that can be manufactured by this technology include: silicon semiconductor devices, silicon semiconductor integrated circuits, silicon germanium semiconductor devices, silicon germanium semiconductor integrated circuits, silicon carbide semiconductor devices, silicon carbide semiconductor integrated circuits, composite semiconductors ( Such as GaAs) devices, composite semiconductors (such as GaAs) semiconductor integrated circuits, polycrystalline diamond semiconductor devices, polycrystalline diamond semiconductor integrated circuits, liquid crystal displays, (inorganic/organic) electroluminescent displays, field emission displays (FED) , Light-emitting polymer display, light-emitting diode display, photoreceptor, CCD area/linear sensor, CMOS sensor and solar battery.