EMI shielding for semiconductor chip carriers

Electromagnetic interference (EMI) shielding for semiconductor chip carriers

Background of the invention

1. Field of Invention

The present invention relates to electronic packaging combined with EMI shielding. In particular, the present invention relates to a semiconductor device combined with an integrated circuit chip carrier structure, which has a built-in ground shield, adjusted to reduce EMI emission, and is used for high-speed switching electronic packaging.

When manufacturing electronic packages, especially semiconductor devices combined with wafer carriers or substrates of thin sheets or organic materials or ceramics and similar materials, and supporting one or more semiconductor chips covered by a heat dissipation cover or a top cover structure, it is reliable Performance will be potentially adversely affected by the electromagnetic interference (EMI) encountered, and EMI shielding needs to be provided to resist and eliminate the adverse effects. In addition, EMI shielding must also be used as an emission shielding function; effectively hinder or stop the emitted EMI energy. Often, these semiconductor devices may include a substrate, provide electrical connections to one or more semiconductor chips located on it, and include a heat dissipation structure; for example, a heat spread sheet in the shape of a top cover or a top cover, which is connected by thermal conduction and mechanical bonding. , Arranged on a single chip or several chips in sequence.

Different electrical components and interconnections are generally on both sides of the substrate, and are electrically communicated with a single chip or several chips, as in the known semiconductor or electronic packaging technology. In order to effectively filter out any EMI encountered during the operation of the semiconductor device, it has been suggested to provide a structure that extends to the vicinity of the chip and is sandwiched between the heat dissipation cover structure or the top cover and the substrate, because appropriate Connect or wire to produce EMI shielding for semiconductor devices or electronic packaging. In this connection, many EMI shielding or similar EMI protection structures for electronic packaging or semiconductor devices have been proposed in this technology, which has varying degrees of protection or shielding from electromagnetic interference (EMI). efficient.

2. Discussion of conventional techniques

Therefore, among the numerous documents in the specific technical field that provide EMI shielding for electronic packaging such as electronic devices, Mertol's US Patent No. 5,866,943 discloses a system and method for forming a lattice array device package using electromagnetic shielding, wherein The hardened object is placed between the substrate and the upper cover or the top cover structure, with the semiconductor wafer sandwiched therebetween. The hardened object surrounding the semiconductor chip includes the different electrical connections between the semiconductor chip, the substrate and the thermal display, or it is covered and effectively provided for the necessary EMI shielding, so as to protect from the influence of EMI during the electronic packaging. .

The US Patent No. 5,650,659 of Mostafazadeh et al. discloses a semiconductor component package assembly, which includes an EMI shield sandwiched between a substrate and a heat dissipation structure, and includes an integrated circuit chip to provide electrical connections to form a complete radio frequency/electromagnetic field. Interference (RF/EMI) shielding. In certain embodiments, an adhesive with electrically conductive properties can be sandwiched between the substrate and the necessary EMI shielding structure to provide electrical grounding of the components.

The US Patent No. 5,761,053 by King et al. also discloses a Faraday cage, which is located on the substrate and the housing containing the integrated circuit components, which allows the EMI/RFI energy to be dissipated to obtain an effect that is harmless to the operation of the device. answer.

Similarly, Osorio's US Patent No. 5,317,107 discloses a semiconductor device including a substrate and a housing portion, the housing portion has an integrated circuit chip sandwiched therebetween, and includes a shield to block EMI energy, which would be very unfavorable. Affects the performance of the device.

In addition to the above documents, there are many other patents that provide EMI shielding for different types of electronic structures.

US Patent No. 6,261,251 by Hutchison et al. discloses a wiring connection package for low-cost (radio) applications, using a complex metal-conductive frame structure to provide insulation against splitting frequencies.

Glenn's U.S. Patent No. 5,939,784 discloses a package for wiring and connecting dies, which is used in acoustic wave devices and has an EMI shielding interface.

U.S. Patent No. 5,939,772 to Hurst et al. discloses a wiring connection package that incorporates a metal plate in the surrounding assembly that is adjusted to apply a magnetic shield to the package.

The US Patent No. 5,838,093 of Sakai et al. discloses a piezoelectric unit package, combined with a device with a surrounding metal top cover, which can provide a shielding effect against EMI energy during the packaging operation.

The US Patent No. 5,536,907 of Miyawaki et al. discloses a wiring connection package for a semiconductor device. The semiconductor device includes a metal cover bonded together and a structure that provides EMI shielding.

The US Patent No. 5,254,871 by Benavides et al. discloses a The TAB carrier includes a heat plate that is combined and integrated and a metal plate structure that can activate the EMI shielding function.

Jones US Patent No. 5,227,583 discloses a wiring connection package with a metalized ceramic cover, which is used as a signal shielding component to protect against energy generated by EMI.

In addition, US Patent No. 4,967,315 by Schelhorn; US Patent No. 4,323,155 by Kling; US Patent No. 5,898,344 by Hayashi; US Patent No. 5,635,754 by Strobel et al.; US Patent No. 5,485,037 by Marrs; Bethurum US Patent No. 5,477,421 by Moulton; US Patent No. 5,371,408 by Moulton; US Patent No. 5,313,371 by Knecht; and US Patent No. 5,043,534 by Mahulikar et al., each of which describes a different type to some extent The structure, combined with EMI shielding design, in order to hinder the EMI effect on the performance of different devices or electronic packaging.

Although each of the above documents combines EMI shielding to varying degrees, the present invention focuses on the combination of favorable grounding caps or electronic packaging, especially suitable for adjustment to extremely high-speed electronic switching applications, such as super BGAs', (registered trademark^TM) And the need for high-efficiency type EMI shielding.

Summary of the invention

Therefore, according to an embodiment of the present invention, there is a semiconductor device including an organic substrate or a wafer carrier, in which an upper cover of an electrical and thermal conduction structure is attached to a hardened object, and the hardened object is sandwiched between the substrate and the peripheral area of the upper cover , And the integrated circuit or semiconductor chip is located between the upper cover and the organic substrate. Although it includes a hardened material, it also includes an adhesive with compatible thermal conductivity between the chip and the substrate to improve the reliability of the components. Degree of good thermo-mechanical connection. Built into the organic carrier are conductive ground straps so as to extend near the peripheral area of the carrier and between the top and bottom surfaces of the substrate. The hardened object can be attached to the substrate by using electrically non-conductive bonding material to cover the active circuit area of the chip carrier or the substrate that extends near the integrated circuit chip, and the conductive bonding material can be used to extend to the built-in Near the ground strap inside the substrate.

According to the second embodiment of the present invention, the wafer carrier or substrate may include a hard ceramic unit for arranging a ball grid array (BGA), which is interconnected to the wafer via a solder ball medium built in the encapsulation layer . The electrical and thermal conductive upper cover, such as the heat-dissipating roof structure, is superimposed on the chip and connected together using a suitable dielectric adhesive. A built-in conductive grounding strap is formed near the periphery of the ceramic substrate, and an EMI gasket with conductive characteristics is interconnected to the ground with a heat dissipation upper cover or a top cover structure. The ground ring forms a ground connection to the spherical grid array, creating EMI shielding for the entire design.

According to the third embodiment of the present invention, which is generally similar to the above-mentioned second embodiment, the upper cover or the top cover structure may have a flange area of the dependent sleeve, which communicates with the built-in wiring in an electrical manner, using EMI adhesive , A grounding strap is formed in the periphery of the ceramic substrate. In the previous embodiment, EMI gaskets are used instead of adhesives.

The rigid or essentially rigid substrates used in the second and third embodiments, such as ceramic wafer carriers, eliminate the need to provide a hardened structure, as in the first embodiment, which is less rigid in connection The demand for organic substrates or thin wafer carriers.

Therefore, the object of the present invention is to provide a new electronic package design combined with EMI shielding, which includes a hardened object located between a substrate with organic characteristics and a conductive upper cover or a heat dissipating top cover, and an integrated circuit chip surrounded by the hardened object is placed therebetween, and The substrate has a ground connection to produce EMI shielding, and has a built-in ground ring in the peripheral area of the organic substrate.

A further object of the present invention is to provide an electronic package of the type described, including an EMI barrier layer for incident or incident EMI energy.

Another object of the present invention is to provide an electronic package of the type described, including an EMI shield for emitting or emitting EMI energy.

According to a further object of the present invention, there is provided a design of the described type that adds EMI shielding to a semiconductor package, wherein the EMI gasket is inserted into a ceramic substrate with a built-in strip ground connection on the periphery, and provides It is electrically interconnected with the metal top cover or the heat dissipation top cover structure, and has a spherical grid array on the substrate.

Another object of the present invention is to provide an electronic package or semiconductor structure, which includes an EMI adhesive inserted in the sleeve-dependent flange of the heat dissipation upper cover or the top cover, and includes the EMI adhesive built into the ceramic substrate and connected to the spherical shape Conductive wiring of the grid array in order to form a ground connection to the metal upper cover, generating EMI Shield for this structure.

In addition, another object of the present invention is to provide a method of using EMI shielding, which is installed in an electronic package as described herein.

Now you can refer to the following detailed description of the preferred embodiment of the electronic package or semiconductor device with EMI shielding, combined with related drawings; among them: FIG. 1 shows a partial cross-sectional view of the semiconductor package of the first embodiment in a general diagram. , Including an organic substrate and a hardened structure to form a grounded EMI shield; Figure 2 shows a package with a ceramic substrate of the second embodiment, including a built-in ground ring, which communicates with the upper cover electrically via an EMI gasket; and Figure 3 shows the package of the third embodiment, which is similar to the second embodiment, but uses EMI adhesive instead of a spacer inserted between the electrical grounding wires, extending on the periphery to the ceramic substrate and the conductive top cover or upper cover within.

Detailed description of the preferred embodiment

In more detail, referring to the drawings, especially the embodiment shown in FIG. 1, a semiconductor package 10 including an organic substrate 12 is represented in a schematic diagram, which may be formed of a thin sheet, and an integrated circuit chip 14 is shown therein. Suitable solder balls 16 are inserted between the chip 14 and the substrate 12, and the solder balls 16 can be encapsulated in the encapsulating material 17, as is well known in the art.

The top cover or heat dissipation top cover structure 18 of conductive material is designed to be on the chip 14, facing the side opposite to the side of the substrate 12, and facing out of the chip 14 in a radial shape. Extending, for example, conductive materials include copper, aluminum, tin, chromium, silicon, carbide, carbon, diamond, ceramics with conductive coating layers, their alloys and compositions, and similar materials, but are not limited thereto, as As is well known in this technology, the upper cover or heat dissipation top cover structure 18 is attached to the chip using a thermally conductive compatible adhesive 20 to improve the thermal and mechanical reliability of the interconnection. The adhesive is in the composition It is basically electrically non-conductive or low-conductivity, such as thermal and conductive silver-containing adhesives.

The hardening component 24 is located between the lower surface of the upper cover or the top cover structure 18 and the upper surface of the organic substrate 12, and extends along the peripheral area 22. The hardening component 24 may basically have a central opening 26 on its plane. The central opening 26 extends near the periphery of the wafer 14 in a spatial relationship. The hardening component 24 may be a suitable conductive material similar to the upper cover or the top cover structure 18, as it is made of the above-mentioned metal and non-metal material composition. The top cover or top cover structure 18 is fixed to the hardened object 24 via a conductive adhesive 28 sandwiched therebetween. On the other hand, the adhesive between the chip and the top cover is generally compatible thermally conductive and electrically non-conductive bonding Agent. Alternatively, the adhesive 28 may be electrically non-conductive but has internal conductive units, so as to form an electrical path between the hardened object 24, the upper cover and the substrate 12.

As shown, in accordance with the present invention, shown only in schematic form, the opposite side of the organic substrate 12 may include electrical connections to the solder balls 16, such as electrical paths that make up the array of the BGA 30, and form an interconnection with the chip 14. The electrical interconnection together, as well known in the art.

The area along the periphery of the organic substrate 12 includes a built-in annular electrical grounding strap 32 that extends between the top surface of the organic substrate and the connection area 30 on the opposite side. As previously indicated, the adhesive material for attaching the hardened object 24 to the upper cover or the top cover 18 is a conductive adhesive material, and is on the opposite side of the hardened object facing the substrate, covering the conductive area on the active circuit area of the substrate. Adhesive 34, such as pyrolux, and further conductive adhesive material 36 on the ground strap 32 on the upper surface of the organic substrate 12 to form an electrical connection to the hardened object 24, where the lower part of the substrate The ground straps on the surface are in contact with the spherical lattice array 30. The internal electrical circuit on the upper surface of the substrate has a connection area 38 formed by a ground strap 32 and one or more solder balls 16 on the periphery of the module, so as to produce electromagnetic interference (EMI) shielding for the entire semiconductor package 10 to shield the outside And form a barrier layer to the radiated or incident EMI energy.

Although basically the basic concept of providing EMI shielding for different types of devices is well known in this technology, the ground ring 32 built into the organic substrate 12 in communication with the hardened object 24 is special and specific. The advantageous design produces ultra-high quality and unique EMI shielding in this embodiment, especially for ultra-high-speed switching applications of semiconductor devices, which is currently expected in this technology.

Referring now to the embodiment of FIG. 2, in this example, the hardened material used in the embodiment of FIG. 1 has been removed. Therefore, the substrate 40 includes a hard ceramic material. As a result, it is not necessary to use hardened material components; From Tao The characteristics of porcelain materials come from.

As in the previous embodiment, the integrated circuit chip 42 is on the upper surface of the ceramic substrate 40 with solder balls 44 built in the packaging material 46 inserted. The upper cover or heat-dissipating top cover structure 48, which radiates outward toward the peripheral boundary line of the integrated circuit chip 42 and is made of conductive material, is connected to the upper cover or the top cover structure as described above, and is in electrical communication with the grounding strap 50. The grounding strap is It is composed of wires built in the peripheral area of the substrate 40 and extending between the opposite side surfaces thereof. The EMI gasket 52 representing the conductive path is sandwiched between the upper cover 48 and the upper terminal end of the grounding strap 50. The latter is built into the substrate and located along the periphery of the latter, whereby the gasket 52 is an electrical Ground connection to the spherical grid array 56 on the substrate surface on the far side of the chip, and through one or more solder balls and the adhesive between the upper cover and the ground strap terminal on the upper surface of the substrate 40, and let The wafer has further electrical connections.

For the embodiment of FIG. 3 which is essentially similar to the embodiment of FIG. 2, in this example, the conductive top cover or upper cover structure 48 has a dependent peripheral flange 60 having a lower end surface 62, which is very close to the ceramic substrate 40's upper surface. In this way, the conductive EMI adhesive 64 is used instead of the gasket 52 of the adhesive material in FIG. It communicates with at least one solder ball 44 and the integrated circuit on the chip to form an EMI shielding structure, similar to the EMI shielding structure in the embodiment of FIGS. 1 and 2.

The above structure includes the peripheral areas built in the substrates 12 and 40 of different embodiments The new ground strap inside provides a highly effective EMI shielding or barrier layer that surrounds the entire package or semiconductor structure, thereby reducing or even completely removing any emitted EMI emission and incident EMI energy encountered during module operation. Although the present invention has been specifically shown and described for the preferred embodiments, those skilled in the art will understand that the above and other changes in form and details can be made without departing from the spirit and scope of the present invention. .