Semiconductor integrated circuit device

Semiconductor integrated circuit device

The present invention relates to an effective technique for semiconductor integrated circuit devices, and particularly relates to the application of protruding electrodes such as solder bumps for substrate mounting formed on semiconductor substrates.

Semiconductor integrated circuit devices formed with protruding electrodes such as solder (hereinafter also referred to as flip-chip semiconductor integrated circuit devices), for example, such as Japanese Patent Application Publication No. 5-218042 and Japanese Patent Application Publication No. 8-250498, And U.S. Patent No. 5,547,740, etc. These publications all disclose one of the basic types of flip chip semiconductor integrated circuit devices.

The design of the flip chip semiconductor integrated circuit device described in the above publication, for example, is to arrange and rewiring from the bonding pad of the chip, and then arrange the bump electrode array (array) for the connection and rewiring on the surface of the chip. The bump electrodes arranged in the aforementioned area array are exposed on the surface protection film. In this way, the gap between the bump electrodes can be enlarged, so that the substrate assembly for connecting the bump electrodes to the wiring on the mounting substrate is easy to perform, and a mounting substrate with wide wiring spacing and low cost can be used. However, in this flip-chip semiconductor integrated circuit device, the bump electrode is directly connected to the terminal on the mounting substrate, only the bump electrode is exposed, and the wiring pad of the semiconductor chip is covered by an insulating film or a protective film. Therefore, the above-mentioned bump electrodes will be regarded as external connection terminals for package pins such as QFP.

<p>The above-mentioned flip-chip semiconductor integrated circuit devices are becoming more highly functional, and the circuit scale of their internal circuits tends to increase. In response to the increase in circuit scale, the size of each semiconductor chip has also become larger, and the wiring width of the circuit has become relatively smaller. Therefore, taking a semiconductor integrated circuit device driven by a clock pulse as an example, the clock pulse transmitted from the external terminal When passing through internal wiring, a signal delay will occur, and the clock pulses supplied to each internal circuit will have a phase difference. The timer must absorb the time deviation, which hinders the high frequency of the clock pulse. In addition, in order to meet the goals of low power consumption and miniaturization of components, when the power supply voltage is reduced for the operating voltage of the internal circuit, in order to prevent the voltage loss in the above internal wiring, it is necessary to install several step-down voltage generating circuits. The current consumption of the above-mentioned step-down circuit has increased, and the circuit scale has been increased.</p><p>The purpose of the present invention is to provide a semiconductor integrated circuit device that facilitates the realization of high-speed operation and reasonable circuit configuration. Another object of the present invention is to provide a semiconductor integrated circuit device, which can improve the flexibility of the internal circuit layout of the chip with a simple structure. All the foregoing and other objectives and new features of the present invention are clearly shown in the description and drawings in the specification of this patent application.</p>

<p>The following only lists the representative ones of the inventions disclosed in this specification, and briefly explains the outline: that is, a first electrode is provided on one of the main surfaces of a semiconductor substrate, which connects the circuit elements and wirings constituting the circuit with the above-mentioned Then, an organic insulating film is formed on the circuit after the opening on the surface of the first electrode is removed, and then the first and second external connection electrodes are arranged on the organic insulating film, and finally the organic insulating film is covered With the conductive layer, the first and second external connection electrodes are electrically connected to the first electrode Pick up.</p><p>The following only lists the representative ones of the inventions disclosed in this specification, and briefly describes the outline: that is, on one main surface of the semiconductor substrate, a first electrode and a second electrode are provided, which are connected to the circuit constituting the circuit The components, wiring, and the above-mentioned circuit are then formed with an organic insulating film on the above-mentioned circuit after the openings on the surface of the first electrode and the second electrode are removed, and then the organic insulating film is covered with a conductive layer to make the first and second The electrodes are electrically connected.</p>

Implementation of the invention

FIG. 1 is a schematic structural diagram showing one embodiment of the semiconductor integrated circuit device of the present invention. Fig. 1(A) shows the cross-sectional part, and Fig. 1(B) shows the plane part. In the semiconductor integrated circuit device of this embodiment, one main surface of the semiconductor chip 06 is formed with circuit elements and wiring as shown in the figure. In this wiring, the wiring pad 04 is formed by the uppermost wiring to remove the wiring After the opening of the pad 40 is formed, the first organic insulating film 02 is formed. The organic insulating film 02 is made of polyimide, but it is not a rigid limitation.

On the first organic insulating film formed by polyimide, a rewiring layer 05 is formed, which serves as a conductive layer to electrically connect at least two wiring pads 04 formed on the main surface of the semiconductor wafer 06 . Then, after removing the opening formed by the bump electrode 03 on the surface of the rewiring layer 05, the second organic insulating film 01 is formed. At least two of the above-mentioned bump electrodes are provided for each rewiring 05 corresponding to one.

The rewiring 05 of this embodiment has the function of wiring to connect the two bump electrodes 03 to each other and to the two wiring pads (wiring pads) provided on the semiconductor chip, rather than simply replacing the general IC package. Pin, only from semiconducting The wiring pads of the bulk chip are wound to increase the spacing between the bump electrodes, so that the bump electrodes are connected to the wiring on the mounting substrate. The structure of this rewiring 05 is beneficial to the function of the power supply means described below.

On the main surface of the semiconductor wafer 06, the uppermost wiring layer 07 is formed to connect the two wiring pads 04, but it is not a rigid limitation. With this uppermost wiring layer 07, an operating voltage such as a power supply voltage is applied to a circuit element, for example, a circuit element formed on the main surface of the semiconductor chip 06.

FIG. 2 is a plan view showing an embodiment of the semiconductor integrated circuit device of the present invention. The semiconductor integrated circuit device of this embodiment is suitable for dynamic RAM (random access memory), but it is not a rigid limitation. It shows the layout of rewiring and the bump electrodes and wiring pads connected thereto.

In the same figure, bump electrodes are represented by , and wiring pads are represented by small . These bump electrodes and wiring pads are connected to each other by rewiring. The aforementioned redistribution 05 is divided into two types according to its function: DC voltage and AC signal. An example of a wiring layer 605, which is the same as the rewiring in the traditional chip-level CSP (chip size package), is that a bump electrode and a wiring pad are connected in a one-to-one correspondence for inputting address and Control signals, as well as data input and output, etc. These individual signal lines 605 are capable of high-speed transmission of digital signals flowing in them, reduce parasitic capacity, and correspond to several wiring pads arranged in a high density, using a rewiring layer with a narrow wiring width.

In this embodiment, the aforementioned redistribution layer 05 is used to realize low-impedance power supply. In the same figure, the left end of the semiconductor wafer is extended up and down, and a rewiring layer 105 is provided on the upper and lower sides, which is bent toward the center and has a large wiring width interval to supply the power supply voltage VDD. In this redistribution layer 105, an upper Three bump electrodes at the bottom, one at the center, and three bump electrodes at the bottom receive the power supply voltage VDD supplied from a total of seven external locations. The redistribution 105 includes: a wide part of the wiring with a large interval, which is used as a trunk line; and a connection part, which branches from the wide part of the wiring to the outside, and connects the semiconductor chip at several places through the thinner wiring Several wiring pads. The power supply voltage VDD is supplied from these plurality of wiring pads to the circuit elements via the uppermost wiring such as the foregoing.

The right end of the semiconductor wafer is extended up and down, and a rewiring layer 205 is provided on the upper and lower parts, which is bent toward the center and has a large wiring width interval to supply the ground potential VSS of the circuit. The redistribution layer 205 is provided with two bump electrodes at the top, one at the center, and three bump electrodes at the bottom, which receive the circuit ground potential VSS supplied from a total of six external locations. The rewiring 205 includes: a wide part of the wiring with a large interval, which is used as a trunk line; and a connection part, which branches from the wide part of the wiring to the outside, and connects the semiconductor chip in several places through the thinner wiring. Several wiring pads. The ground potential VSS of the circuit is supplied to the circuit elements from the plurality of wiring pads via the uppermost wiring such as the foregoing. When a rewiring layer with a large spacing wiring width is used to supply such power supply voltages VDD, VSS, etc., it will be contrary to the above-mentioned signal line 605 and form a larger parasitic capacitance. For power supply VDD and VSS, it helps to stabilize the parasitic capacitance between them.

In this embodiment, a power supply path independent of the output circuit is provided to reduce the large power noise generated in the output circuit and transmit it to the external input circuit or internal circuit. That is, the rewiring layer 305 is the one that supplies the ground potential VSSQ of the circuit to the output circuit, which is divided on the semiconductor chip into The four-zone configuration is provided with bump electrodes to supply the ground potential VSSQ respectively. These wiring lines 305 are connected to each other via bump electrodes and through wiring on the mounting substrate, and are supplied at the same ground potential VSSQ.

The rewiring layer 405 used for supplying the power supply voltage VDDQ as the above-mentioned output circuit is arranged to extend up and down toward the central part of the semiconductor chip. The redistribution layer 405 is provided with two bump electrodes at the upper and lower ends, and one bump electrode in the center, which receives the power supply voltage VDDQ supplied from a total of five locations from the outside.

In this embodiment, in addition to using the redistribution layer to supply DC voltages such as those described above, the redistribution layer can also be used for signal lines that transmit AC signals. The rewiring layer 505 is used to transmit the clock pulse CLK. The bump electrode provided in the center of the semiconductor chip provides the clock pulse CLK, and then transmits the clock pulse CLK to the wiring pads provided at the center and the wiring pads at the upper and lower ends. . In this way, in order to obtain a large-sized semiconductor chip with a large memory capacity, a rewiring layer with a low resistance value can be used to distribute the clock pulse CLK, thereby reducing the phase difference of the clock pulse CLK in the internal circuit and realizing the operation Speed up.

The DRAM chip set in the embodiment is a synchronous DRAM with four memory banks or a synchronous DRAM with a DDR structure, and the memory accesses of 64 bits per unit are performed by the above four memory banks, but there is no hard limit. There are 64 I/O circuits in total, which are vertically arranged side by side in the center of the semiconductor chip. Therefore, the I/O circuits driven by the rewiring layers 305 and 405 for supplying the operating voltages VDDQ and VSSQ are arranged as described above.

As mentioned above, 64 I/O circuits are located in the center of the semiconductor chip. Taking a longer distance to disperse the arrangement, therefore, the distance between the input and output circuits arranged at the upper and lower ends becomes longer, resulting in a delay in the transmission of the clock pulse CLK and a phase difference, which hinders high speed. In this embodiment, the bump electrode for supplying the clock pulse CLK is provided in the center of the chip, and the bump electrode is branched upward and downward from there, and the clock pulse CLK is distributed by the rewiring 505, so it can pass through the input and output circuits arranged at the upper and lower ends The clock pulse is distributed one and a half distances, and the low-resistance redistribution 505 is used to shorten the transmission delay of the clock pulse in the supply path. That is to say, the most serious of the phase difference of the clock pulse lies in the circuit that receives the clock pulse from the wiring pads adjacent to the bump electrodes, and the circuit that receives the clock pulses from the wiring pads provided at both ends of the chip. Through the above-mentioned rewiring 505, the phase difference of the clock pulse can be greatly reduced.

FIG. 3 shows a schematic layout diagram of an embodiment of the DRAM used in the present invention. The layout of the DRAM in this embodiment corresponds to the DRAM rewiring and wiring pads in Figure 2 above. In the same figure, the memory array or memory mat 14 is divided into several configurations. In the longitudinal center of the semiconductor chip, the I/O circuits are dispersedly arranged as described above, and corresponding I/O control circuits are provided. There are four input/output control circuits 13 corresponding to the memory array 14, which are arranged in two rows along the longitudinal center of the chip. In this way, each I/O control circuit 13 can be connected to eight I/O circuits.

The above-mentioned four input/output control circuits 13 respectively provided in the corresponding left and right memory arrays are divided into a group of two upper and lower, which are combined into a clock pulse input buffer 11. To correspond to the two clock pulse buffers 11 adjacent to the left and right, one clock pulse input pad CLKU and CLKD are further provided. In addition, a clock pulse input pad CLKC is also provided in the central part of the chip.

These clock pulse input pads CLU, CLKC, and CLKD are connected to each other through a rewiring 12 for clock pulse input, and this rewiring 12 is also connected to a solder bump electrode 10 for clock pulse input. Under this structure, the clock pulse CLK input from the solder bump electrode 10 for clock pulse input can be transmitted to the above-mentioned clock pulse input pads CLK, CLKU, and CLKD via the rewiring 12.

The clock pulse input pads CLKU, CLKC, and CLKD are transmitted from the above-mentioned clock pulse input pads CLKU, CLKC, and CLKD, and then transmitted to the clock pulse input buffer 11 through the uppermost metal wiring layer 15 containing aluminum or the like in the DRAM chip. The internal clock signals formed in these respective clock input buffers 11 are also transmitted to the input/output control circuit 13 via the uppermost metal wiring layer 15 containing aluminum in the DRAM chip, but there is no hard limit. Corresponding to the clock pulse input buffer 11 set by the clock pulse input pad CLKC, it will form an internal clock pulse signal to supply the address input circuit, data input circuit or RAS, CAS, WE, etc. control signal input circuits not shown in the figure Etc., but not a hard limit.

4 is a block diagram showing an embodiment of the clock pulse input part in the semiconductor integrated circuit device of the present invention. This embodiment corresponds to the clock pulse input circuit of the DRAM in FIG. 3 described above.

The bump electrode 10 for clock pulse input is connected to the clock pulse input pads CLKU, CLKC, and CLKD through the rewiring 12. The clock pulse supplied from the clock pulse input pad CLKC is sent to the clock pulse input The input terminal of the buffer 11, from which the clock pulse is input to the internal clock pulse output by the buffer 11, is transmitted to the read/write control circuit 16. The read/write control circuit 16 is read by an instruction not shown in the figure, and forms a read control signal READ according to the designated action.

The above-mentioned read control signal READ is used as the control signal of the clock pulse input buffer 11 corresponding to the clock pulse input pads CLKU and CLKD. When the read control signal READ reaches the effective level, it will pass through the above-mentioned clock pulse. The input pads CLKU and CLKD form output resistor clock pulses QCLK0 and QCLK3 from the input clock signal, which are transmitted to the output resistor circuit 17 included in the input/output control circuit 13. The I/O resistor circuit 17 reads and reads the data data through the above-mentioned output resistor clock pulses QCLK0 and QCLK3, and then transmits the output signal to the I/O wiring pad 19 through the output buffer circuit 18. These I/O wiring pads 19 are connected to bump electrodes for I/O through rewiring not shown in the figure.

Fig. 5 is a schematic cross-sectional view of one embodiment of the semiconductor integrated circuit device of the present invention. This embodiment corresponds to the clock input part of FIG. 3 or FIG. 4, but there is no hard limit.

The semiconductor integrated circuit device of this embodiment is shown in FIGS. 20-24, which will be described later. The rewiring and bump electrodes after the packaging and molding are completed in the wafer process are sometimes also called WPP (Wafer Process Package). Abbreviation) or WPP bump. The following uses the terminology of this WPP wiring layer or WPP bump for description. WPP bumps are formed on the WPP wiring layer for circuit wiring. The WPP wiring layer is covered on the aforementioned organic insulating film not shown in the figure, and the metal PAD (wiring pad) of the chip is connected to the opening of the WPP wiring layer. this The metal PAD is connected to the circuit 1 through the uppermost metal wiring on the chip. The metal PAD corresponds to the aforementioned clock pulse input pad CLKC, and the circuit 1 corresponds to the aforementioned clock pulse input buffer 11, but it is not a hard limit.

The WPP wiring layer corresponds to the circuit 1 and further extends from the metal PAD portion, and the metal PAD corresponding to the circuit 2 is connected to the opening. The metal PAD and the circuit 2 are connected through the metal wiring on the chip as described above. The circuit 2 controls its operation through the aforementioned read control signal READ to form an input buffer 11 that receives a clock pulse signal. The clock pulse signal is input through a clock pulse input pad CLKU or CLKD not shown in the figure.

Fig. 6 is a schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device of the present invention. This embodiment corresponds to the clock input part of FIG. 3 or FIG. 4 described above, but it is not a rigid limitation.

The WPP bumps described above are formed on the WPP wiring layer for circuit wiring. The WPP wiring layer is covered on the aforementioned organic insulating film not shown in the figure, and its opening is connected to the CLK PAD (clock pulse wiring pad) of the chip. The CLK PAD is connected to the clock pulse buffer circuit through the CLK wiring containing the metal wiring on the uppermost layer of the chip, and then connected to the peripheral circuit through the same wiring. The peripheral circuit constitutes the read/write control circuit 16 such as the aforementioned one.

The WPP wiring layer further branches up and down from the CLK PAD portion corresponding to the clock pulse buffer circuit, and connects two CLK PADs corresponding to the CLKU and CLKD at the opening. The two CLK PADs are the same as the previous ones, which are connected to peripheral circuits through the metal wiring on the chip. This peripheral circuit controls its action through the aforementioned read control signal READ to form an output circuit 13, which includes an input buffer 11 that receives a clock pulse signal, and The clock pulse signal is input through the clock pulse input pad CLKU or CLKD not shown in the figure.

FIG. 7 is a block diagram of an embodiment of the semiconductor integrated circuit device of the present invention. This embodiment corresponds to the clock input part of FIG. 3 or FIG. 4 described above, but it is not a rigid limitation.

The WPP bumps described above are formed on the WPP wiring layer for circuit wiring. The WPP wiring layer is covered on the aforementioned organic insulating film not shown in the figure, and the clock pulse signal WPP bumps are connected to the openings thereof. The WPP wiring layer (CLK wiring) is connected to the wiring pad PAD, which corresponds to the clock pulse buffer circuit allocated by the WPP wiring layer.

In this embodiment, since the clock pulse signal WPP bumps, and even between the wiring pads PAD of the clock pulse buffer input part corresponding to the peripheral circuit allocated to it, are constituted by the aforementioned WPP wiring (rewiring) The low-resistance clock pulse wiring is turned on, so the signal delay problem there is less, and the clock pulse phase difference between each other is also small. The above-mentioned wiring pads PAD correspond to the bumps shown in the embodiments of FIG. 3 to FIG. 6. Therefore, each peripheral circuit corresponds to the read/write control circuit 16 and the output control circuit 13.

FIG. 8 is a schematic plan view of an embodiment of the semiconductor integrated circuit device of the present invention. This embodiment is mainly based on an example of external power distribution. For each circuit formed on a semiconductor chip, the power supply path of the power supply voltage VDD and the ground potential VSS of the circuit is displayed.

The left and right ends of the semiconductor wafer are provided with a pair of WPP wires extending up and down. In the above-mentioned pair of WPP wirings, it is set to supply the power supply voltage VDD with the WPP wiring arranged on the left side, but it is not a hard limit. The upper and lower ends of this WPP wiring And the center part is divided into three pieces each toward the center of the chip, and WPP bumps are provided on the protruding parts, and the ground potential VSS of the circuit is supplied from the upper and lower ends and the center part.

In the WPP wiring layer for the power supply voltage VDD, the lower end extends from the WPP bump to the center of the wafer to form the WPP wiring, and then the bump VDDPAD is connected, but this is not a rigid limitation. The bump VDDPAD is connected to the wiring on the chip, and supplies the power supply voltage VDD to the circuit elements formed on the semiconductor chip via the wiring on the chip. The other is to reduce the power supply impedance, and then appropriately branch the thick WPP wiring that constitutes the above-mentioned trunk into thinner WPP wiring to form a structure that connects to the above-mentioned wiring pad VDDPAD, or connects each VDDPAD to each other through the above-mentioned wiring on the chip. It is also feasible.

As described above, in the WPP wiring layer for the ground potential VSS of the circuit, the upper end extends from the WPP bump to the center of the wafer to form the WPP wiring, and then the bump VSSPAD is connected. The bump VSSPAD is connected to the wiring on the chip, and supplies the ground potential VSS of the circuit to the circuit element formed on the semiconductor chip via the wiring on the chip. The other is to reduce the power supply impedance, and then appropriately branch the thick WPP wiring that constitutes the above-mentioned main line into thinner WPP wiring to form a structure that connects to the above-mentioned wiring pad VSSPAD, or connect each VSSPAD to each other through the above-mentioned wiring on the chip. It is also feasible.

Fig. 9 is a schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device of the present invention. This embodiment is suitable for the power supply path of the power supply voltage VDD (or the ground potential VSS of the circuit) of the embodiment of FIG. 7, but not Hard limits.

WPP bumps are formed on the WPP wiring layer (VDD) for circuit wiring. The WPP wiring layer is covered on the aforementioned organic insulating film not shown in the figure, and a total of three WPP bumps are provided on the upper part. The WPP wiring layer is connected to the bump VDDPAD at the opening of the organic insulating film. The bumps VDDPAD are connected through the on-chip wiring, that is, the uppermost metal wiring, and supply the power supply voltage VDD to the circuit elements not shown in the figure through the above-mentioned on-chip wiring.

Fig. 10 is a schematic plan view of another embodiment of the semiconductor integrated circuit device of the present invention. This embodiment is mainly based on an example of external power distribution, and for each circuit formed on a semiconductor chip, the power supply path of the internal voltage VDDI after the externally supplied power voltage VDD is stepped down is disclosed.

The WPP wiring is extended toward the left and right ends and the lower end of the semiconductor chip, and is used as a power wiring for supplying the voltage VDDI of the power section. At the lower end, there is a horizontally extending WPP wiring branch to connect the WPP wiring and the wiring pad VDDI PAD. The wiring pad VDDI PAD transmits the step-down voltage VDDI formed in the step-down circuit through the wiring on the chip. In this way, the WPP wiring layer extending to the left, right and the bottom surrounds the entire semiconductor chip to transmit the step-down voltage VDDI, and to the peripheral circuits that use the above voltage VDDI as the operating voltage, pass through the wiring pads VDDI PAD provided in several places. , The supply of the above-mentioned step-down voltage VDDI is performed.

For the power supply voltage VDD supplied by the above-mentioned step-down circuit, a WPP wiring pad for VDD is provided, and the wiring pad VDD PAD is connected through the WPP wiring layer. this The wiring pad VDD PAD is connected to the wiring on the chip, and the power supply voltage VDD is supplied to the step-down circuit through the wiring on the chip. If a circuit that uses the power supply voltage VDD as the operating dynamic voltage is mounted on the semiconductor chip, other than the one shown in the figure, connect the necessary circuit through the WPP wiring layer connected to the WPP bump for VDD. The wiring pad VDDPAD, as in the above-mentioned step-down circuit, supplies the power supply voltage VDD.

FIG. 11 is a schematic configuration diagram of another embodiment of the semiconductor integrated circuit device of the present invention. In the semiconductor integrated circuit device of the present invention, the WPP wiring layer is not only arranged in a one-to-one correspondence between WPP bumps and pads PAD, but also used as a part of signal lines and power supply lines. In this case, the different wiring must be separated and arranged crosswise. If the above-mentioned WPP wiring is multi-layered, although such circuit separation and cross-arrangement can be achieved simply, the manufacturing process of the WPP wiring is complicated, which will increase the manufacturing cost.

In this embodiment, Fig. 11(A) shows: WPP wiring extending in the horizontal direction and wiring extending vertically in the vertical direction are separated and arranged in a crossed state; Fig. 11(B) shows the cross section In this case, the above-mentioned longitudinally extending wiring is arranged separately and lowered on the chip. That is, in FIG. 11(A), the WPP bumps for external input signals provided above the horizontally extending WPP wiring layer pass through the WPP wiring and pass through the pad PAD, and the WPP wiring layer extends horizontally. The organic insulating film is connected to the wiring on the chip formed underneath. The wiring on the aforementioned chip passes under the horizontally extending WPP wiring layer and leads to the wiring pad PAD, where the WPP wiring is again connected to cross the wiring on other chips, and finally connected to the external input signal. No. PAD.

For example, in FIG. 11(A), even though the above-mentioned laterally extending WPP wiring layer constitutes a power line that transmits the aforementioned internal step-down voltage and external power supply voltage, this embodiment can still be imitated, and the power lines can be cross-arranged as input signal lines. , And can improve the flexibility of the circuit layout formed on the semiconductor chip. In other words, the address signal, data input and data output signal lines that must meet the requirements of high-speed operation should be arranged with a short distance between the WPP bumps and the wiring pads, and high-speed signal transmission must be carried out to switch the operation mode However, the corresponding WPP bumps for signal input should avoid the part formed by the WPP bumps corresponding to the above-mentioned address signals and data input and data output to form a vacant area, and include the WPP wiring on the chip , Just form the above-mentioned intersection.

FIG. 12 is a schematic layout diagram of another embodiment of the DRAM used in the present invention. The DRAM layout of this embodiment corresponds to the rewiring and wiring pads of the DRAM in FIG. 2, but does not include the clock pulse input part. That is, the memory array or the memory pad 14 is arranged in plural divisions as described above. The longitudinal center portion of the semiconductor chip is distributed with 64 input/output circuits as described above, and the corresponding input/output control circuit 114 is provided. Four input/output control circuits 114 are provided along the longitudinal center portion of the chip to correspond to the memory array 14 divided into two rows. In this way, each I/O control circuit 114 is responsible for eight I/O circuits.

Corresponding to the four input/output control circuits 114 respectively provided in the above-mentioned left and right memory arrays, there are wiring pads CLKU1~CLKU4 and CLKD1~CLKD4 for supplying clock pulse input to them, which are transmitted through the rewiring 12. The internal clock pulse is formed in the regeneration circuit 110. The clock pulse CLK input from the solder bump electrode 10 for clock pulse input is transmitted to the wiring pad CLKC through the rewiring 12, and then transmitted to the clock pulse regeneration circuit 110 through the on-chip wiring 15 therefrom. The clock regeneration circuit 110 includes a PLL circuit, a DLL or an SMD circuit, which corresponds to the clock pulse CLK supplied from the outside to form an internal clock pulse signal. The formed internal clock pulse signal is transmitted to the wiring pad CLK2 through the wiring on the chip, and then distributed to the wiring pads CLKU1~CLKU4 and CLKD1~CLKD4 for each clock pulse input through the rewiring 12 therefrom.

FIG. 13 is a block diagram of an embodiment of the DRAM clock pulse input part of FIG. 12. The bump electrode 10 for clock pulse input is connected to the clock pulse input pad CLKC through the rewiring 12. The clock pulse supplied from the clock pulse input pad CLKC is transmitted to the input terminal of the clock pulse regeneration circuit 110 through the wiring on the chip. The clock regeneration circuit 110 includes a synchronizing circuit such as a PLL circuit, a DLL circuit, or an SMD circuit as described above, so that it has a clock pulse supplied from the bump electrode 10 for clock pulse input, and a specific phase Difference, forming a synchronized internal clock signal.

For example, if the externally supplied clock pulse is directly transmitted to the internal circuit, the internal clock pulse will be delayed due to the signal delay of the input buffer circuit that receives the externally supplied clock pulse. To compensate for this phase delay, a PLL circuit and a DLL or SMD circuit are used.

The PLL (Phase Locked Loop) circuit uses a phase comparator to compare externally supplied clock pulses and VCO (Voltage Controlled Oscillator), etc. The voltage controls the phase difference (frequency difference) between the two clock pulses formed in the vibration circuit, and forms a control signal that can make the two coincide to control the above-mentioned VCO. In this PLL circuit, in the above-mentioned PLL loop, in other words, as long as the clock pulse compared by the above-mentioned phase comparator is inserted into the delay circuit formed in the copy circuit corresponding to the above-mentioned input buffer, the external clock pulse can be eliminated The phase difference with the internal clock pulse, or the above delay time is greater than the delay time generated in the input buffer, and the phase of the internal clock pulse is greater than the external clock pulse.

For example, if an internal clock pulse with a relatively large phase is generated, and when the internal clock pulse outputs data, the signal delay in the output circuit can be compensated, and data output can be performed in synchronization with the externally supplied clock pulse. In addition, if the N-division circuit is inserted into the above-mentioned PLL loop in the PLL circuit, an internal clock pulse whose frequency increases by N times relative to the external clock pulse can be formed.

The DLL (Delay Locked Loop) circuit uses a phase comparator to compare the clock pulses delayed by the variable delay circuit and the clock pulses input by one cycle, and control the delay time of the variable delay circuit to make two Those are consistent. It is the same as the above-mentioned PLL circuit. Similarly, inserting the clock pulse compared by the above-mentioned phase comparator into the delay circuit formed in the copy circuit of the above-mentioned input buffer for clock pulse input can eliminate the external clock pulse and the internal clock. The phase difference of the pulse, or make the above-mentioned delay time larger than the delay time generated in the input buffer, and make the phase of the internal clock pulse larger than the external clock pulse.

SMD (Synchronous Mirror Delay, synchronous replication delay) circuit is such as PLL circuit and DLL circuit and other clock pulse synchronization circuits without feedback loop, the synchronization time (Lock Time) is about two to three cycles shorter. In this way, the period of the input clock pulse can be measured as the number of segments of the delay circuit to shorten the above-mentioned phase lock time. This measuring circuit is measured with a delay time equivalent to a period of delay circuit constituent elements as the decomposition energy, which is generally approximately equal to two periods of delay time in a CMOS (Complementary Metal Oxide Semiconductor) circuit. An example of a synchronous circuit using this kind of SMD is disclosed in Japanese Patent Laid-open No. 8-237091.

The internal clock pulse generated in the above-mentioned clock pulse regeneration circuit 110 is transmitted to the wiring pad CLK2 on the wiring layer of the chip, and then distributed through the rewiring 12 to the clock pulse input wiring pad CLKU1 of the I/O control circuit 114 from there. ~4 and CLKD1~4. The I/O control circuit 114 includes, for example, an address input wiring pad 113; an address input buffer 112 for receiving the address signal input from the wiring pad 113; and an address input capacitor 111 for accessing bits. Address input signal. The above-mentioned internal clock pulse is supplied to the address input capacitor 111. At this time, if the external clock pulse is synchronized with the internal clock pulse transmitted to the address capacitor, the signal delay generated in the clock pulse input path can be compensated.

FIG. 14 is a plan view of another embodiment of the semiconductor integrated circuit device of the present invention. The semiconductor integrated circuit device of this embodiment is suitable for static RAM (random access memory), which discloses the circuit layout of rewiring, bump electrodes connected to it, and wiring pads.

The same figure is also the same as before, the bump electrode 20 and the like are represented by , and the wiring pad 22 and the like are represented by small . These bump electrodes and wiring pads are reconfigured The wires 21 and the like are connected to each other. In this embodiment, the redistribution is also divided into two types for DC voltage and AC signal according to its function. Each redistribution layer 25 shown in the example is the same as the redistribution in the conventional wafer-level CSP. A bump electrode and a wiring pad are connected in a one-to-one correspondence, which is used as an address and control signal. Input, and data input and output, etc. These individual signal lines 25 are used for high-speed transmission of digital signals flowing through them. The parasitic capacity is reduced, and several wiring pads with high density are correspondingly arranged, and a rewiring layer with a narrower wiring width is used.

In this embodiment, the aforementioned redistribution layer is used to realize low-impedance power supply. In the same figure, the thickly spaced rewiring layer 21 extending along the periphery of the chip in the upper and lower halves of the semiconductor chip is designed to supply the internal step-down voltage VDDI. In this rewiring layer 21, the center of the chip The step-down voltage circuit 23 marked with a dotted line on the left and right sides of the part, the step-down voltage VDDI formed by it is transmitted via on-chip wiring 24 such as aluminum wiring. For example, if the power supply voltage VDD is set to 3.3 volts, the aforementioned step-down voltage VDDI is reduced to a low voltage of 1.5 volts.

Among the redistributions other than the redistribution 21 described above, except for the thin redistributions for signal input, the redistributions formed with a larger interval of the wiring width, such as those supplied with the ground potential VSS of the circuit, or those supplied with the power supply voltage VDD, are all As mentioned above, it is used as the power supply voltage VDDQ for the output circuit and the ground potential VSSQ of the circuit to reduce the influence of power noise. A number of bump electrodes are arranged in between, and the same voltages such as VSS or VDD are supplied respectively. The SRAM of this embodiment is equipped with peripheral circuits in the vertical center and the horizontal center of the chip, and the memory array is dispersedly arranged on the four sides through related peripheral circuits. Within regions.

Figure 15 is a schematic cross-sectional view to illustrate the above-mentioned rewiring manufacturing method, where (a) is after the circuit on the semiconductor substrate (wafer) is completed, coated with polyimide of an organic insulating film, and then used for photographing Technology (exposure, development) to form an organic insulating film with openings on the aluminum (Al) wiring pad, and then hard-bake it. (b) After the photoresist film is formed, a wiring pattern for rewiring is formed using photographic technology (photolithography). (c) is Cu (copper) electroplating after washing. (d) is the immersion photoresist film removal solution. (e) is the organic insulating film forming the upper layer. That is, the polyimide is coated as described above, and the organic insulating film with openings on the bump electrodes is formed by photolithography (photolithography), and then hard-baked.

16 is a cross-sectional view of another embodiment of the rewiring provided in the semiconductor integrated circuit device of the present invention. The circuit elements and wiring shown in the figure are formed on one main surface of the semiconductor wafer. In this wiring, the wiring pad 04 is formed on the uppermost wiring. After removing the opening of the wiring pad 40, the organic insulating film 02 of the first layer is formed. The organic insulating film 02 is made of polyimide, but it is not a rigid limitation.

On the first organic insulating film containing the polyimide, a rewiring layer 05 as a conductive layer is formed to connect at least two wiring pads 04 formed on the main surface of the semiconductor wafer 06. On the surface of the rewiring layer 05, the part formed by the bump electrode 03 is provided with Cu (copper) terminals, and the remaining part forms the encapsulating resin 101. At least two bump electrodes 03 are provided for each redistribution 05.

FIG. 17 is an example of a logic circuit and an external input/output circuit formed on the semiconductor chip constituting the semiconductor integrated circuit device of the present invention The longitudinal section of the component structure. On the p-type silicon substrate 120 with a resistivity of 10 Ωcm, a p-type deep well region 122 with a depth of 0.8 μm is formed. The aforementioned p-type deep well area 122 is separated by element separation area 125, which is separated by n-type drain area 137, n-type source area 136, gate oxide film 127 with a thickness of 4 nm, and n-type polysilicon with a film thickness of 0.2 μm. A gate electrode with a film and a gate length of 0.2 μm forms an n-channel transistor (also called a MOSFET or MISFET) 4 operating with a power supply voltage of 1.8V.

The aforementioned p-type deep well area 122 is separated by element separation area 125, through n-type drain area 139, n-type source area 138, oxide film 126 with a thickness of 8 nm, and n-type polysilicon with a film thickness of 0.2 μm. A gate electrode 131 with a membrane and a gate length of 0.4 μm forms an n-channel transistor 5 operated by a power supply voltage of 3.3V. Although not shown in the figure, the structure of the p-channel transistor which is combined with the n-channel transistor to form a CMOS circuit is formed on the p-type silicon substrate 120 after the n-type deep well area is formed, and then placed there It forms a p-type source area and a drain area.

The upper part of the aforementioned transistors 4 and 5 is to form a self-integrated contact window. A silicon nitride film 140 with a thickness of 100 nm deposited by the CVD method is arranged, and a contact plug 142 is provided, which is arranged on the planarized surface by the CMP method. The first metal wiring 143 includes an aluminum metal film with a film thickness of 0.5 μm; the first interlayer plug 145 is placed on the flattened layer by the CMP method, at the desired position of the contact layer film 141 with a film thickness of 1 μm. The desired position of the first interlayer film 144 with a film thickness of 1 μm; the second layer of metal wiring 146 includes an aluminum metal film with a film thickness of 0.5 μm; the second interlayer plug 148 is set to be planarized by the CMP method Required for the second interlayer film 147 with a thickness of 1 μm Position; the third layer of metal wiring 149, which includes an aluminum metal film with a film thickness of 0.5 μm; the third interlayer plug 151, which is set at the desired position of the third interlayer film 150 with a film thickness of 0.8 μm; and the fourth layer of metal wiring 152, which includes an aluminum metal film with a film thickness of 1 μm. The fourth metal wiring 152 can also be used as an electrode such as a wiring pad in addition to being used as the uppermost metal wiring.

With the CPU (central processing unit) as the center, several circuit blocks, such as memory circuits and external input/output devices, which constitute its peripheral circuits, are a microprocessor of a chip formed on a semiconductor substrate, constituting these In the system LSI of the structure, the gate oxide film thickness of the MIS (MOS) transistor is divided into two types. Corresponding to the operating voltage of the MIS transistor, it is necessary to ensure a certain degree of withstand voltage (withstand voltage to the destruction of the gate oxide film). For example, use DRAM as an external input/output circuit, analog input/output circuit and memory circuit, such as Memory array address selection uses MOSFETs, analog/digital converters, digital/analog converters, etc. Although there is no hard limit, if 0.2 μm process technology is used, MIS with a gate length of 0.4 μm and a gate oxide film thickness of 8 nm Transistor. In contrast, the circuits that use the stepped down lower internal voltage as the operating power source, that is, logic circuits, SRAM, and CPU, are composed of MIS transistors with a gate length of 0.2 μm and a gate oxide film thickness of 4 nm.

FIGS. 18 and 19 are cross-sectional views illustrating the structure of the device according to an example of the rewiring manufacturing method of the semiconductor integrated circuit device of the present invention. As shown in FIG. 18(A), wiring pads 202 (202a and 202b) are formed on the surface of a semiconductor chip 201 on which a large number of circuit elements are formed on a semiconductor substrate. After removing the opening of the wiring pad 202, a protective layer 203 section of the wafer covered. The one shown in the same figure (A) is equivalent to the traditional wire bonding connection The completion stage with wafers.

As shown in FIG. 18(B), a lower insulating layer 204 is formed on the surface of the wafer. On the lower insulating film 204, the wiring pad 202 (202a and 202b) has an opening.

As shown in FIG. 18(C), when the rewiring 205 is formed between the wiring pad 202a and the electrode formation position, a rewiring layer 295 is also formed on the inspection-dedicated pad 202b.

As shown in FIG. 18(D), after the surface insulating layer 206 is formed, the upper portions of the wiring pads 202 (202a and 202b) of the rewiring layers 205 and 295 and the formation locations of the bump electrodes are exposed.

As shown in FIG. 19(A), when the bump electrode underlayer metal 207 is formed in the bump electrode forming portion, the bump electrode underlayer metal layer 297 is also formed on the wiring pad 202 (202a and 202b) at the same time. The bottom metal layer 297 of the bump electrode directly above the wiring pad 202 (202a and 202b) formed as described above is the inspection pad 209a and the inspection pad 209b. The former corresponds to the wiring pad 202a for power supply or signal input and output, and the latter corresponds to the inspection Dedicated wiring pad 202b.

As shown in FIG. 19(B), the inspection pads 209a and 209b are brought into contact with the tip of the probe 211, and after the probe inspection is performed, the redundancy of the circuit is used to remedy defective products or select functions, and implement the selection of good and defective products.

As shown in Figure 19(C), on the bump electrode bottom metal 207, the bump electrode 208 is formed with solder, and then the completed wafer is cut and divided into individual wafers (dicing) to obtain a flip chip semiconductor product. Body circuit device. The wiring pad 202 and its surface material are usually made of aluminum or aluminum alloy, but copper or other metals can be used depending on the type of wiring material inside the semiconductor element.

In addition to inorganic films such as silicon oxide film or silicon nitride film, the material of the protective layer 203 can also use organic films such as polyimide, as well as these composite materials. The material of the lower insulating layer 204 is designed to relieve the stress (stress, bending state) that acts on the bump electrode 208 due to thermal expansion of the semiconductor integrated circuit device and the mounting substrate after the substrate is mounted, and to reduce the For the capacitance of wiring 205, it is better to use organic materials with low elastic modulus (low modulus of elasticity) and low dielectric constant, such as polyimide, fluorine resin, and various polymer elastomer materials. The polymer elastomer materials exemplified here include rubber materials such as silicon and acrylic, as well as polymer materials with low elastic modulus formed by compounding such rubber materials.

The lower insulating layer 204 is formed by varnish coating, printing, or film bonding. The thickness of the lower insulating layer 204 is preferably about 3 μm or more from the viewpoint of reducing stress and capacitance. Wherein, when an organic film is used for the protective layer 203, the lower insulating layer 204 can be thinner than it, or it can be omitted.

In the aforementioned rewiring 205, for example, a three-layer wiring structure is used, which is formed on the upper and lower sides of copper or steel alloy with a thickness of about 1 to 5 μm, and deposits of chromium, titanium, nickel, and nickel alloys with a thickness of about 0.1 to 0.5 μm. In addition, aluminum and aluminum alloys can also be used.

The material of the aforementioned surface insulating layer 206 is to relieve the stress acting on the bump electrode 208, and it is better to use low-elasticity organic materials such as polyimide, epoxy, fluororesin, or even various polymer elastomer materials. In addition, the lower insulating film (further insulating film) of the aforementioned redistribution is preferably soft in order to absorb the stress applied to the bump electrode. For the upper insulating film 206, from the viewpoint of protection, a material harder than the lower insulating film 204 may be selected. With In general, the upper insulating film 206 and the lower insulating film 204 are formed of a photosensitive polyimide resin film. The final film can be changed by changing the amount of solvent, molecular weight, and filler content before heat treatment (curing). Hardness (elasticity). In addition, the upper and lower insulating films may be formed of different materials. In this case, for example, the upper insulating film 206 may be formed of epoxy resin, and the lower insulating film 204 may be formed of polyimide resin.

For the aforementioned bump electrode base metal 207, it is preferable to use metals with high electroplating barriers such as chromium, nickel, nickel tungsten, nickel copper, etc., with a thickness of about 0.3 to 3 μm. In order to further ensure the wettability of the flux and the electrical connection with the probe, it is better to form a gold film layer with a thickness of about 0.1 μm on the surface. The aforementioned solder bump electrode 208 can be formed by printing flux on the bottom metal 207 of the solder bump electrode, or by transferring a pre-formed solder ball of a certain size, and then performing a reflow process.

As mentioned above, the inspection pads 209 are provided directly above the power supply, signal input/output wiring pad 202a and probe inspection wiring pad 202b. This facilitates the probe inspection after the rewiring process and prevents the wiring pad. The damage of 202 before the rewiring process causes low connection reliability. Especially when the rewiring is used as the wiring for distributing signals as in this embodiment, the probe inspection is more important.

In the above structure, since the probe 211 can be inspected without contacting the solder bump electrode 208 after formation, not only the deformation of the solder bump electrode 208 can be prevented, but also when the probe is in eccentric contact with the curved surface of the solder bump electrode 208, Prevent the probe 211 from being damaged.

In the above structure, since the probe 211 does not need to touch the solder bump electrode 208 The solder bump base metal 207 before formation, therefore, the gold and other metal layers formed on the surface of the solder bump base metal 207 to improve the solder wettability, and the solder barrier metal layer below, will not be damaged. It can prevent the occurrence of the problem of low reliability of solder connection.

In the above structure, by arranging the inspection pads 209 in a row, the probe 211 can use a low-cost cantilever probe as shown in FIG. 19(B), and since no rewiring is applied to the general wire bonding wafer The wiring pad 202 and the inspection pad 209 described in this embodiment have the same position on the chip plane, so the general wire bonding wafer and the probe 211 can be shared.

In the above-mentioned flip-chip semiconductor integrated circuit device, although the inspection pad 209 is included in the projection area of the wiring pad 202, the capacitance added by the additional inspection pad is almost zero. In addition, some of the wiring pads 202b are not provided with corresponding bump electrodes, only the inspection pads 202b are provided, and the probe inspection can be performed after the rewiring process without increasing the number of solder bumps.

20 to 24 are perspective views of various stages of the manufacturing process in the flip chip semiconductor integrated circuit device according to the present invention. FIG. 20 shows the completion stage of the conventional wire bonding wafer. That is, in the state of FIG. 18(A), the whole wafer source 220 is shown. The wiring pads 202 are respectively formed on each chip 210.

When manufacturing a flip-chip semiconductor integrated circuit device, it is formed on the wafer 220 shown in FIG. 20, as shown in the aforementioned examples of FIGS. 18(B), (C), (D) and FIG. 19(A), etc. After the lower insulating layer 204, the rewiring 205, the surface insulating layer 206, and the bump electrode underlayer metal 207, as shown in FIG. 21, a wafer 220 after the bump electrode underlayer metal 207 is formed is obtained. The state in Figure 21, its cross-section is equivalent to Figure 19(A) shows the state.

Next, as shown in FIG. 22, determine the positions where the tips of the several probes 211 contact the several inspection pads 209 (omitted in FIG. 22) on the wafer 220 at the same time, and use the fixed probe card 221 to perform the probe inspection. By means of several probes 221 contacting several inspection pads 209 at the same time, one or several inspection pads 209 of the wafer 210 are inspected at the same time, and the contact positions are moved one by one to inspect all the wafers 210 on the wafer 220. Probe inspection. At this time, the same or the same but separate probe card 221 can be used to perform function selection or defect repair at the same time or continuously.

Next, using FIG. 23, the flux printing method is taken as an example to illustrate the formation process of solder bump electrodes. As shown in the figure, corresponding to the configuration of the bottom metal 207 of the bump electrode on the surface of the wafer 220, the solder printing mask 222 forming the opening 223 is aligned with the position on the wafer 220 and overlapped, and then printed with a wiper (squeegee) 224 Flux 225. The state immediately after the printing is completed is shown in the interrupted view. The flux 225 is printed flatly on a slightly wider area than the underlying metal 207 of the bump electrode. After the wafer is reflowed and heated to melt the flux 225, the solder is condensed into a ball shape to form a solder bump electrode 208.

After the bump electrode 208 is formed, the wafer 220 is as shown in FIG. 24. After the dicing blade 226 cuts and separates the individual wafers 210, the finished flip chip semiconductor integrated circuit device is obtained. The finished product is further subjected to burn-in testing and final inspections of performance and appearance as required, and can be shipped after specific packaging or packaging.

Figure 25 illustrates the manufacturing process after the rewiring formation process of the flip-chip semiconductor integrated circuit device of the present invention through four parts (a), (b), (c), and (d) Sequence flow chart. The manufacturing process shown in the same figure, such as the structure of Figure 19(C) as an example, includes the following steps: rewiring forming step S1, which is to form rewiring 205 on insulating layer 204; surface insulating layer Formation step S2, which is to form an insulating layer such as 206; bump electrode underlayer metal formation step S3, which is to form bump electrode underlayer metal such as 207, and the underlayer metal 297 of the inspection pad 209, etc.; function selection step S4, which It uses the aforementioned anti-fuse 1 program for mode setting, etc.; probe inspection step S5; defect remedial step S6, which uses the aforementioned anti-fuse 1 program to replace bad bits, etc.; bump formation step S7, which is to form bump electrodes; a dicing step S8, which is to cut a single wafer from the wafer; a burn-in step S9, and a final inspection step S10.

The manufacturing process shown in Fig. 25(a) is the manufacturing process of pre-burning S9 after single-chip cutting S8, which is the continuous operation test at high temperature. Due to the use of rewiring in flip-chip semiconductor integrated circuit devices, the spacing between solder bump electrodes (about 60~150μm) is greater than the spacing between wiring pads (about 0.5~1.0mm), such as BGA (Ball Grid Array, ball point) Sockets for burn-in used in array-type CSP (chip size package) are easy to burn-in on a chip basis. That is, before the burn-in process, bump electrodes are formed on the wafer in advance, and the bump electrode array pattern corresponds to the electrode array pattern of the burn-in plug. There is no need to prepare a special specification burn-in plug again. The assembly cost of flip-chip semiconductor integrated circuit devices can be reduced.

In addition, even when a burn-in plug using the bump electrode as a connection terminal is not used, the inspection pad 209 can be used as an electrical connection for burn-in. At this time, on the inspection pad arranged between the bump electrodes, although it is necessary to use The small pitch and expensive burn-in contact terminals that are inspected by probes can prevent the solder bump electrode 208 from deforming under the high temperature contact of the plug.

The manufacturing process of Fig. 25(b) and (c) is in the wafer stage before the single chip cutting process S8, and the burn-in process S9 is performed. Particularly in FIG. 25(b), the above-mentioned inspection pad 209 or solder bump electrode 208 is used before the bump underlayer metal 207 is formed, and the manufacturing process is pre-fired before the solder bump electrode is formed. Since the bump electrode is not used for the electrical connection of the burn-in, it can be contacted under the high temperature environment of the plug-in for the burn-in to prevent the deformation of the solder bump electrode. In addition, since the burn-in is performed in the flat stage before the solder bump electrodes are formed, the contact terminals for burn-in such as plugs can easily come into contact with the inspection pads 209 without disturbing the solder bump electrodes 208. In addition, since the burn-in is carried out in the wafer stage, it is possible to burn-in multiple chips at a time, thereby improving the inspection productivity.

The manufacturing process shown in FIG. 25(c) is after the solder bump electrodes are formed and then burned in. The contact terminal system for the burn-in is in contact with the solder bump electrode 208. When the contact terminal for burn-in is brought into contact with the solder bump electrode 208, although the solder bump electrode 208 is easily deformed, it does not damage the bump electrode base metal 207 or cause problems such as deterioration of the surface quality, so it can be formed with high reliability The bottom metal of the bump and rewiring. At this time, as shown in Figure 25(b), the burn-in can also be performed in the wafer stage, which can improve the inspection productivity.

The manufacturing process shown in Fig. 25(d) is the replacement of the surface insulating layer forming process S2 of each process in Fig. 25(a)~(c) with the bump electrode underlying metal forming process S3, but the function selection process is the following The process is still the same as the manufacturing process in any one of Figure 25(a)~(c). The difference between Fig. 25(a)~(c) and Fig. 25(d) is that in the manufacturing process of Fig. 25(d), the rewiring 205 is combined with the bump underlayer metal 207 It is formed in the same process, so compared with the manufacturing process of Fig. 25(a)~(c), the formation cost of the underlying metal of the bump electrode can be reduced.

When the circuit elements of the semiconductor integrated circuit device are manufactured in a well-established process, and the defect rate is low, the burn-in process may sometimes be omitted. At this time, the manufacturing processes of Figure 25 (a) ~ (c) are exactly the same, and there will be no difference.

The process flow of each manufacturing process in Figure 25, including function selection S4, probe inspection S5, and defect remediation S6, are all implemented continuously. When using anti-fusion wire technology in function selection S4 and defect remedy S6, these three processes are all contacted by probes to the wafer, and can be separately processed through electrical processing (without laser cutting or rewiring. Therefore, it is possible to process the three processes together in one probe test (that is, after the probe test is performed on other wafers, there is no need to perform probe inspection again) to achieve the effect of simplification of the process. At this time, function selection and defect remediation can also be considered in the broad probe inspection.

In the process flow of each manufacturing process in Figure 25, the solder bump electrode formation process S9 is always carried out in the wafer stage before the single chip cutting process S8, and the solder bump electrode formation efficiency is better than that of the traditional BGA or CSP In the manufacturing process, the efficiency of forming solder bump electrodes on each wafer. Furthermore, before the solder bump electrode formation step S7, the three steps of function selection S4, probe inspection S5, and defect remediation S6 are carried out, which can prevent the bumps of solder bumps and facilitate probe testing.

The function selection process S4 can also be implemented after the probe inspection S5 or defect remediation S6. However, if the function selection S4 is implemented before the probe inspection S5, the probe inspection S5 only needs to be checked for the previously selected function, so it can be deleted Reduce inspection items and improve inspection efficiency. Function selection can also be implemented through rewiring, also That is, all the steps until the circuit is formed on the wafer remain unchanged. In the rewiring process, taking DRAM as an example, the bit structure is set to ×16 bits, ×32 bits, or ×64 bits. And so on, re-wiring is used to implement traditional bonding options .

The demand ratio of each product obtained through the function selection of S4 is often changed by the influence of market dynamics. In order to be able to flexibly respond to changes in demand and minimize the inventory of each product, the most ideal way is to keep the inventory in the state before the function selection, and the process after the function selection must be completed in as short a period as possible. The anti-fusion wire technology is used in the function selection to apply the same rewiring pattern to all types, and the inventory can be kept in the state before the bump electrode is formed. In this way, it can be manufactured in a short period of time in response to changes in demand. Must be varieties, and can reduce inventory.

With respect to the manufacturing process illustrated in FIG. 25, it is also possible to reverse to the above, after the bump electrode formation step S7, the function selection step S4 is performed through the aforementioned program element. At this time, in order to select the function, the electrode and the protruding electrode must be exposed on the surface of the semiconductor integrated circuit in order to apply voltage to the program element. However, in addition to the processing associated with function selection, the semiconductor integrated circuit will be able to maintain inventory in a state where almost all wafer processes are completed, so inventory management is easy.

Fig. 26 is a schematic cross-sectional view of another embodiment of the semiconductor integrated circuit device of the present invention. In the semiconductor integrated circuit device of this embodiment, the circuit elements and wirings shown in the figure are formed on one of the main surfaces of the semiconductor wafer as described above. In this wiring, a wiring pad is formed through the uppermost wiring, and it is connected to the bump electrode through the aforementioned rewiring as the conductive layer. Pick up. Although omitted and not shown in the same figure, as in the embodiment of FIG. 1 and so on, after the opening formed by the wiring pad is removed, a first organic insulating film composed of polyimide is formed, and then formed thereon Rewiring.

In this embodiment, FIG. 26(A) is different from the above-mentioned embodiment of FIG. 1 in that a bump electrode and a wiring pad are connected through rewiring. In contrast, although the rewiring of Figure 26(B) is not a rigid limitation, it is intersected with the rewiring of Figure 26(A). The wiring of the upper layer Al (aluminum) wire, etc., makes the redistribution of the connection pad and the redistribution of the bump connected to each other. In this way, the redistribution shown in FIG. 26(A) is arranged on the first organic insulating film, and it is used to connect the uppermost Al wires of the two redistributions, but it is not shown in the figure.

The rewiring of this embodiment is used to connect the wiring pads and bumps in a one-to-one correspondence as shown in the figure. For example, in Figure 26(B), the rewiring is cross-arranged on the uppermost Al line. As in the embodiment of FIG. 11, the signal line or power supply line used as a part of the signal line or power supply line may be, for example, a signal wiring connected to a wiring pad or a power wiring connected to a bump.

FIG. 27 is a schematic structural diagram of another embodiment of the semiconductor integrated circuit device of the present invention. Fig. 27(A) shows a schematic cross-sectional structure; Fig. 27(B) shows a circuit pattern. This embodiment is a modified example of the embodiment shown in FIG. 26. The wiring formed on one main surface of the semiconductor wafer by connecting all the redistributions, together with the uppermost layer (M4) described above, consists of the lower wiring such as the third It is composed of layer wiring M3.

For example, as shown in Figure 27 (A), the connection pad and the connection pad are connected as follows: For example, when there is a cross-extending redistribution between the two as shown in Figure 27(B), and the signal line of the uppermost layer M4 extending in parallel to the above-mentioned connection direction, etc., further use of the third The layer wiring M3 forms an intersection with the above-mentioned M4.

According to Figure 27(A), the wiring pad is connected to one end of the rewiring through the contact window, and the other end of the rewiring is connected to one end of the M4 wiring through the contact window, and the other end is connected to one end of the M3 wiring through the contact window. . The other end of the M3 wiring is connected to one end of the M4 wiring through the contact window. In this configuration, it crosses the signal line for the first time. The other end of the M4 wiring is connected to the other end of the M3 wiring at the intersection of the signal line, etc. through a contact window. The other end of the M3 wiring is connected to one end of the M4 wiring through the contact window. The other end of the M4 wiring is connected to the rewiring connected to the bump, so that an electrical connection is formed between the bump and the bump. In FIG. 27(A), the other end wiring (M4) and redistribution in the above-mentioned intersection are omitted.

FIG. 28 is a plan view of still another embodiment of the semiconductor integrated circuit device of the present invention. The semiconductor integrated circuit device of this embodiment is suitable for memory circuits such as static RAM, but it is not a rigid limitation. It shows the layout of rewiring and the bump electrodes and wiring pads connected thereto.

The same figure is also the same as the previous one. The bump electrodes are represented by , and the wiring pads are represented by small . These bump electrodes and wiring pads are connected to each other through rewiring. In this embodiment, the rewiring is also divided into DC voltage and AC signals according to its functions. The rewiring for AC signals is the same as the rewiring in wafer-level CSP, which is a bump electrode and a wiring pad. One-to-one correspondence connection, used for address and control signal input, as well as data input and output. The rewiring of these individual signals is to reduce the parasitic capacity in order to transmit the signals flowing in it at a high speed, and correspondingly set up several wiring pads with high density, and adopt a rewiring layer with a narrower wiring width.

In this embodiment, the aforementioned redistribution layer can also be used for low-impedance power supply. In the same figure, the rewiring layer with a larger spacing of the wiring width extending along the center of the semiconductor chip and the periphery of the chip is designed to supply the step-down voltage formed in the internal step-down circuit. This redistribution layer transmits a step-down voltage, which is formed by step-down circuits arranged on the left and right sides of the center of the chip, and then distributed to the periphery of the chip through the contact window as the operating voltage of the internal circuit. For example, if the power supply voltage is set to 3.3 volts, the aforementioned step-down voltage is reduced to a low voltage of 1.5 volts.

The two redistributions provided inside the step-down power line in the longitudinal direction of the chip are provided for supplying the ground potential VSS of the circuit. In addition, the power supplied from the outside is transmitted to the above-mentioned step-down circuit through bumps and rewiring not shown in the figure. If there is an input/output interface that operates with an external power supply, power is supplied to it through the above-mentioned bumps, rewiring and internal wiring. These structures are the same as those of the embodiment shown in FIG. 14, so they are omitted here.

Fig. 29 is a plan view of still another embodiment of the semiconductor integrated circuit device of the present invention. The semiconductor integrated circuit device of this embodiment is a modified example of the embodiment shown in FIG. 28 described above. The same figure is an enlarged display of the half of the memory chip shown in FIG. 28. In this embodiment, although it is not a rigid limitation, the rewiring is arranged in a cross, and the rewiring connects a bump electrode and a wiring pad in a one-to-one correspondence.

With this cross arrangement, for example, the same array of bumps and wiring pads is used, and functions can be changed by changing the pattern of rewiring. For example, it can be made to have the same function as the traditional joining option. Or in a specific signal, in order to transmit the signal circulating in it at a high speed, the above-mentioned intersection is used to reduce the parasitic capacity and obtain the shortest distance. Such a crossover technique between rewiring can be achieved by using the uppermost wiring and the lower wiring formed on the semiconductor substrate in the embodiments of FIGS. 26 and 27 described above.

The functions and effects obtained in the above embodiments are as follows:

(1) On one main surface of a semiconductor substrate, circuit elements, wirings and first electrodes that are electrically connected to the above-mentioned circuit are provided, and an organic insulating film is formed on the above-mentioned circuit after the surface portion of the above-mentioned first electrode is removed. Then, first and second external connection electrodes are arranged on the organic insulating film, and finally a conductive layer is coated on the organic insulating film to connect the first and second external connection electrodes and the first electrode. , Not only the above-mentioned conductive layer can also be used as a good power supply path, but also can improve the flexibility of the circuit layout of the power circuit formed on the semiconductor substrate.

(2) In addition to the above, making the area of the first and second external connection electrodes larger than the area of the first electrode not only helps to achieve a high degree of integration of the elements and wiring formed on the semiconductor substrate, but also It can take advantage of external connection mechanisms such as bump electrodes.

(3) In addition to the above, the above-mentioned conductive layer is formed by redistribution, which will be able to complete the manufacture of semiconductor integrated circuit devices in the wafer manufacturing process.

(4) In addition to the above, the conductive layer is formed to be the same or slightly longer than one side of the semiconductor substrate, so that the power supply voltage can be efficiently supplied to the semiconductor substrate. Each circuit element formed on the substrate.

(5) In addition to the above, applying the same voltage to the first and second external connection electrodes can achieve the effect of low impedance voltage supply.

(6) In addition to the above, supplying the power supply voltage from the first and second external connection electrodes can achieve a low-impedance power supply voltage supply and help stabilize the operation of the circuit formed on the semiconductor substrate.

(7) In addition to the above, the ground voltage of the first and second external connection electrode supply circuits can achieve low-impedance ground voltage supply and help stabilize the operation of the circuit formed on the semiconductor substrate.

(8) In addition to the above, a second electrode connected to the circuit is further provided on the one main surface, and the first and second external connection electrodes are electrically connected through the conductive layer, as well as the first electrode and the first electrode. The two electrodes can stably supply an even voltage to the circuit elements formed on the semiconductor substrate.

(9) In addition to the above, solder balls are provided on the first and second external connection electrodes, which can be manufactured in the wafer manufacturing process, and the semiconductor integrated circuit device can be easily and stably mounted.

(10) On one main surface of the semiconductor substrate, the circuit elements, wiring and the first electrode and the second electrode that electrically connect the circuit are provided, and then the surface openings of the first electrode and the second electrode are removed Then, an organic insulating film is formed on the above circuit, and a conductive layer is coated on the organic insulating film to electrically connect the first electrode and the second electrode. In this way, not only the conductive layer can also be used to transmit signals , And can improve the flexibility of the circuit layout of the power circuit formed on the semiconductor substrate, and help to increase the speed of the operation.

(11) In addition to the above, using the above-mentioned conductive layer as redistribution can achieve the effect of high-speed signal path in the wafer manufacturing process.

(12) In addition to the above, a first external connection electrode and a second external connection electrode are further provided on the organic insulating film, and the conductive layer is connected to the first external connection electrode and the second external connection electrode, In this way, the circuit elements formed on the semiconductor substrate can be stably supplied with an even voltage from the outside.

(13) In addition to the above, the above-mentioned first external connection electrode and second external connection electrode are used as bump electrodes, which can not only complete the manufacture of semiconductor integrated circuit devices through the wafer process, but also can be mounted on the substrate To achieve the effect of high-density mounting.

(14) In addition to the above, using the first electrode and the second electrode as wiring pads, the semiconductor chip can be assembled on a semiconductor integrated circuit device with a read terminal to realize a diversified package form of the semiconductor chip.

(15) In addition to the above, making the area of the first external connection electrode and the second external connection electrode larger than the area of the first electrode and the second electrode will not only help achieve the formation of the semiconductor substrate The high integration of components and wiring can also take advantage of external connection mechanisms such as bump electrodes.

(16) In addition to the above, solder balls are provided on the first and second external connection electrodes, which can be manufactured in the wafer process, and the semiconductor integrated circuit device can be easily and stably mounted.

(17) In addition to the above, a first external connection electrode is further provided on the organic insulating film, the conductive layer is connected to the first external connection electrode, and other than the first external connection electrode, the remaining external connection All electrodes are not connected, so only one external terminal is needed to effectively supply voltage and even signals to the circuit elements formed on the semiconductor substrate.

(18) In addition to the above, supplying a clock pulse signal to the first external connection electrode can reduce the phase difference of the clock pulse supplied to the several circuits formed on the semiconductor substrate, and contribute to the speed of the circuit.

(19) In addition to the above, a voltage forming circuit that receives a first voltage is further provided on a main surface of the semiconductor substrate, and a second voltage different from the first voltage is formed through the voltage forming circuit, and then a second voltage different from the first voltage is formed through the voltage forming circuit. The conductive layer transmits the above-mentioned second voltage, which can simplify the power circuit formed on the semiconductor substrate, make the circuit layout simple and easy, and achieve the effect of stable supply of equal voltage.

(20) In addition to the above, a clock regeneration circuit that receives a first clock pulse is further provided on one of the main surfaces of the semiconductor substrate, and a second clock corresponding to the first clock pulse is output through the clock regeneration circuit The pulse is then distributed through the conductive layer to distribute the second clock pulse, so that the internal clock pulse supplied from the outside and synchronized with the clock pulse can be efficiently distributed to the circuits formed on the semiconductor substrate.

(21) In addition to the above, the conductor layer can be connected through a wiring part of which is provided on one main surface of the semiconductor substrate to cross the conductor layer to achieve the effect of easy arrangement of signal lines and power lines.

(22) In addition to the above, using the conductive layer as the connecting wiring to combine the uppermost wiring formed on one of the main surfaces of the semiconductor substrate and the wiring formed on the lower layer will make it easier to achieve signal wiring and Easy power cord The effect of configuration.

(23) On one main surface of the semiconductor substrate, the circuit elements, wiring and the first electrode and the second electrode that are electrically connected to the circuit are provided, and the surface parts of the first and second electrodes are removed. An organic insulating film is formed on the above-mentioned circuit, and first and second external connection electrodes are arranged on the above-mentioned organic insulating film, and then a conductive layer is coated on the above-mentioned organic insulating film to electrically connect the above-mentioned first and second The external connection electrode and the first and second electrodes, and at their intersections, one side of the conductor layer is connected to the wiring provided on one of the main surfaces of the semiconductor substrate. In this way, a signal line and a power supply can be achieved The effect of easy line configuration.

(24) In addition to the above, using the above-mentioned conductive layer as connection wiring to combine the uppermost wiring formed on one of the main surfaces of the semiconductor substrate and the wiring formed on the lower layer will make it easier to achieve signal wiring and The power cord is easy to configure.

In the above, the invention proposed by the inventors and others are described in detail based on the embodiments, but the present invention is not limited to the foregoing embodiments, and various changes can be made without departing from the spirit of the invention. For example, the structure and material of the rewiring formed on the above-mentioned semiconductor wafer can take various different implementation forms. The semiconductor integrated circuit device with the above-mentioned bump electrode can be applied to semiconductor integrated circuit devices of other multi-chip module package structures in addition to the multi-chip module structure mounted on a mounting substrate. For example, two semiconductor wafers are combined in a laminated structure to form a semiconductor integrated circuit device. The invention can be widely applied to semiconductor integrated circuit devices formed before the packaging process in the wafer manufacturing process.

Effect of invention

Among the inventions disclosed in this specification, the most representative effects obtained are briefly described as follows: On a main surface of a semiconductor substrate, the circuit elements, wiring and electrical connection of the above-mentioned circuit are provided on a main surface of the semiconductor substrate. For the electrode, an organic insulating film is formed on the circuit after the surface portion of the first electrode is removed, and then first and second external connection electrodes are arranged on the organic insulating film, and finally the conductive layer is coated on the organic insulating film The upper part is used to electrically connect the first and second external connection electrodes and the first electrode. In this way, not only the conductive layer can also be used as a good power supply path, and the power circuit formed on the semiconductor substrate can be improved. Flexibility of layout.

On one main surface of the semiconductor substrate, the circuit elements, wiring, and the first electrode and the second electrode that electrically connect the circuit are arranged, and the openings on the surface of the first electrode and the second electrode are removed. On the circuit, an organic insulating film is formed, and the conductive layer is coated on the organic insulating film to electrically connect the first electrode and the second electrode. In this way, not only the conductive layer can be used to transmit signals, but also can be improved The flexibility of the circuit layout formed on the semiconductor substrate also contributes to the high-speed operation.

<p>01. . . Polyimide of the first layer</p><p>02. . . Polyimide of the second layer</p><p>03. . . Bump electrode</p><p>04. . . Wiring pad</p><p>05. . . Redistribution layer</p><p>06. . . Chip</p><p>07. . . Top layer wiring</p><p>105. . . Rewiring layer (VDD)</p><p>205. . . Redistribution layer (VSS)</p><p>305. . . Rewiring layer (VSSQ)</p><p>405. . . Rewiring layer (VDDQ)</p><p>505. . . Rewiring layer (CLK)</p><p>605. . . Rewiring (signal line)</p><p>705. . . Rewiring (other wiring)</p><p>11. . . Clock pulse input buffer</p><p>12. . . Rewiring</p><p>13. . . Input and output control circuit</p><p>14. . . Memory array</p><p>15. . . The uppermost metal wiring layer</p><p>16. . . Read/write control circuit</p><p>17. . . Output resistance circuit</p><p>18. . . Output buffer circuit</p><p>19. . . I/O wiring pad</p><p>110. . . Clock pulse regeneration circuit</p><p>111. . . Address input resistor</p><p>112. . . Address input buffer</p><p>113. . . Address input wiring pad</p><p>114. . . Input and output control circuit</p><p>20. . . Bump electrode</p><p>twenty one. . . Rewiring (power cord)</p><p>twenty two. . . Wiring pad</p><p>twenty three. . . Step-down voltage</p><p>twenty four. . . Wiring on chip</p><p>25. . . Rewiring (signal)</p><p>120. . . p-type silicon substrate</p><p>122. . . p-type deep well field</p><p>125. . . Component separation field</p><p>126, 127. . . Gate oxide film</p><p>130, 131. . . Gate electrode</p><p>136. . . n-type source field</p><p>137. . . n-type drain field</p><p>138. . . n-type source field</p><p>139. . . n-type drain field</p><p>140. . . Silicon Nitride Film</p><p>141. . . Contact interlayer film</p><p>142. . . Contact embolism</p><p>143. . . First metal wiring</p><p>144. . . First interlayer film</p><p>145. . . First interlayer embolism</p><p>146. . . Second metal wiring</p><p>147. . . Second interlayer film</p><p>148. . . Second interlayer embolism</p><p>149. . . Third metal wiring</p><p>150. . . The third interlayer membrane</p><p>151. . . Third interlayer embolism</p><p>152. . . Fourth metal wiring</p><p>201. . . Semiconductor wafer</p><p>202 (202a, 202b). . . Wiring pad</p><p>203. . . Protective film</p><p>204. . . Lower insulating layer</p><p>205, 295. . . Rewiring</p><p>206. . . Upper insulating film</p><p>207. . . Bump electrode bottom metal</p><p>208. . . Solder bump electrode</p><p>297. . . Bump electrode bottom metal</p><p>209a, 209b. . . Check the wiring pad</p><p>210. . . Chip</p><p>211. . . Probe</p><p>221. . . Fixed probe card</p><p>220. . . Wafer</p><p>223. . . Opening</p><p>224. . . Wiper</p><p>225. . . Flux</p><p>226. . . Cutting blade</p><p>30. . . WPP wiring layer</p><p>31. . . WPP bump</p><p>32. . . Metal PAD</p><p>33. . . On-chip metal wiring</p><p>34. . . Chip</p><p>35. . . Circuit 1</p><p>36. . . Circuit 2</p><p>37. . . Clock buffer circuit</p><p>38. . . Peripheral circuit</p><p>39. . . CLK PAD</p><p>40. . . CLK wiring on chip</p><p>41. . . WPP wiring layer CLK wiring</p><p>42. . . Clock signal WPP bump</p><p>43. . . PAD</p><p>44. . . WPP wiring layer (CLK wiring)</p><p>45. . . VSS PAD</p><p>46. . . VSS WPP bump</p><p>47. . . VSS WPP wiring layer</p><p>48. . . Wiring on VSS chip</p><p>49. . . VDD WPP bump</p><p>50. . . VDD PAD</p><p>51. . . VDD WPP wiring layer</p><p>52. . . Wiring on VDD chip</p><p>53. . . WPP bump (VDD)</p><p>54. . . VDDI PAD</p><p>55. . . Step-down circuit</p><p>56. . . Internal step-down power supply (VDDI) WPP wiring layer</p><p>57. . . Wiring on chip</p><p>58. . . External input signal WPP bump</p><p>59. . . External input signal PAD</p><p>60. . . WPP solder bumps</p><p>61. . . Photoresist</p><p>62. . . Polyimide film</p><p>63. . . Cu</p><p>64. . . Al wiring pad</p><p>65. . . Bump</p><p>66. . . The uppermost Al line</p><p>67. . . Rewiring</p><p>68. . . Wiring pad</p><p>69. . . Contact window</p><p>70. . . M3 wiring</p><p>71. . . M4 wiring</p><p>72. . . Contact window for connecting M4 and rewiring</p><p>73. . . Connect the contact window of M3 and M4</p><p>74. . . Contact window (rewiring-AL)</p><p>75. . . VSS</p><p>76. . . Step-down power cord (rewiring)</p><p>77. . . Chip size</p><p>78. . . Cross junction</p><p>79. . . Signal line, etc.</p>

1(A) and (B) are schematic structural diagrams of an embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 2 is a plan view of an embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 3 is a schematic layout diagram of an embodiment of the DRAM used in the present invention.

FIG. 4 is a block diagram of an embodiment of the semiconductor integrated circuit device of the present invention.

Fig. 5 is a schematic cross-sectional view of an embodiment of the semiconductor integrated circuit device of the present invention.

Fig. 6 is a schematic plan view of an embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 7 is a block diagram of an embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 8 is a schematic plan view of an embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 9 is a schematic plan view of an embodiment of the semiconductor integrated circuit device of the present invention.

Fig. 10 is a schematic plan view of another embodiment of the semiconductor integrated circuit device of the present invention.

11(A) and (B) are schematic structural diagrams of another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 12 is a schematic layout diagram of another embodiment of the DRAM used in the present invention.

FIG. 13 is a block diagram of an embodiment of the DRAM clock pulse input part of FIG. 12.

FIG. 14 is a plan view of another embodiment of the semiconductor integrated circuit device of the present invention.

Fig. 15 is a schematic cross-sectional view of an embodiment of the rewiring manufacturing method according to the present invention.

16 is a cross-sectional view of another embodiment of the rewiring provided in the semiconductor integrated circuit device of the present invention.

17 is a longitudinal sectional view of the device structure of the present invention, which shows an embodiment of a logic circuit and an external input/output circuit formed on a semiconductor chip constituting a semiconductor integrated circuit device.

18 (A) ~ (D) are cross-sectional views illustrating the device structure of some embodiments of the rewiring manufacturing method in the semiconductor integrated circuit device of the present invention.

19(A)~(C) are cross-sectional views of the device structure illustrating the remaining part of the embodiment of the rewiring manufacturing method in the semiconductor integrated circuit device of the present invention.

20 is a perspective view illustrating a stage in the manufacturing process of the flip-chip semiconductor integrated circuit related to the present invention.

21 is a perspective view illustrating another stage of the manufacturing process in the flip chip semiconductor integrated circuit of the present invention.

FIG. 22 is a perspective view illustrating another stage of the manufacturing process in the flip chip semiconductor integrated circuit of the present invention.

FIG. 23 is a perspective view illustrating another stage of the manufacturing process in the flip-chip semiconductor integrated circuit of the present invention.

FIG. 24 is a perspective view illustrating another stage of the manufacturing process in the flip-chip semiconductor integrated circuit of the present invention.

25 (a) ~ (d) is a flowchart illustrating the manufacturing process after the rewiring molding process in the flip-chip semiconductor integrated circuit related to the present invention.

26 (A) ~ (B) are schematic cross-sectional views of another embodiment of the semiconductor integrated circuit device of the present invention.

27(A)~(B) are schematic cross-sectional views of another embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 28 is a plan view of still another embodiment of the semiconductor integrated circuit device of the present invention.

Fig. 29 is a plan view of still another embodiment of the semiconductor integrated circuit device of the present invention.