Dram cell arrangement with vertical MOS transistors and method for its fabrication

Dynamic random access memory cell configuration with vertical metal oxide semiconductor transistor and its manufacturing method

The preferred specific embodiments of the dynamic random access memory cell configuration and the manufacturing method thereof according to the present invention will be described below with reference to the accompanying drawings, in which:

1a, 2a, 3, and 4 are cross-sectional views taken along the line AA in FIG. 1b to explain the continuous process steps involved in manufacturing the dynamic random access memory cell configuration according to the present invention;

Figures 1b and 2c show plan views of the configuration of dynamic random access memory cells, which are manufactured according to the process steps shown in Figures 1a and 2a of the present invention, respectively;

Fig. 2b is a cross-sectional view of the tangent line BB in Fig. 2c.

The individual process steps for manufacturing the dynamic random access memory cell configuration according to the present invention will be described with reference to FIGS. 1 to 4.

The present invention relates to a dynamic random access memory cell configuration with a vertical metal oxide semiconductor transistor, and to its manufacturing method, wherein the transistor does not have any floating body, more specifically, it is completely depleted.

So far, in the configuration of dynamic random access memory cells, that is, dynamic semiconductor memory, almost all of the memory cells used are single transistor memory cells, which are well known to us and include a metal oxide semiconductor memory cell. The crystal is a transistor and a capacitor. The information in the memory cell is stored in the form of charge in the capacitor. The capacitor is connected to the transistor in a way that when the transistor is driven through the word line, the charge of the capacitor can be read through the bit line.

Generally speaking, it is desirable to be able to manufacture dynamic random access memory cell configurations with high packing density. In this respect, the advantages of designing the metal oxide semiconductor transistor as a vertical transistor are considerable, in which the source, the channel region and the drain are arranged on top of each other. Regardless of the channel length, this type of MOS transistor only occupies a small amount of space. Furthermore, it is desirable to be able to arrange the vertical transistor and the capacitor associated with each memory cell on the semiconductor substrate vertically on top of each other.

For example, a configuration containing a large number of memory cells of this type can be found in German Patent 4430483A1. Each memory cell has a row of selected transistors arranged vertically, which includes a drain region and a source region in the row of the semiconductor substrate. There is a current channel between the drain region and the source region. Also in the vertical direction, the current path is controlled by a control gate electrode, which completely surrounds the substrate row and is isolated by an oxide layer. The control gate electrode of each memory cell is composed of doped polysilicon, which is electrically connected to each other and forms a word line for driving the selected transistor.

The problem with the well-known metal oxide semiconductor transistor is that the row-shaped channel region, which is insulated from the substrate and accumulates charge carriers therein, changes the threshold voltage. The active region, for example, will also appear in SOI (Silicon On Insulator) substrates. Its complete insulation has many advantages, but it also causes negative effects, known as floating body effects. These effects are caused by the inability of the charge carriers generated in the active region to flow out. It is particularly suitable for the charge carriers generated in the channel region of the MOS transistor.

On the other hand, in the well-known MOS transistor, although the gate electrode surrounds the channel region, there is no guarantee that the depletion region will completely extend from the periphery of the row-shaped channel region to its center, that is, it cannot be determined. Whether the metal oxide semiconductor transistor is truly completely depleted, so that the depleted region completely fills the channel region.

This kind of completely depleted metal oxide semiconductor transistors, because of their advantages, so the demand is increasing. It seems that they can only be achieved in some cases. Among them, the P-type doped channel region will be restricted in some directions. In the case of a planar standard metal oxide semiconductor transistor (where it will not be separated from the substrate). For example, this is true for row-shaped channel regions of well-known transistors or planar MOS transistors on SOI substrates. However, in these cases, the channel region is not connected to the substrate for insulation purposes. On the contrary, as described above, it has been found that a floating body may be caused.

German patent 19929211A1 discloses a dynamic random access memory cell configuration and a manufacturing method, in which the metal oxide semiconductor transistor system is designed as a vertical transistor, and the floating body effect can be avoided. The transistor described in this document will form a hump-shaped protrusion in the substrate, which has a laterally adjacent gate electrode, and on the other side of the protrusion, the channel area will penetrate a conductor structure It is electrically connected to the gate electrode, so the charge carriers generated in the channel region can flow out. However, the overall result of this well-known cell configuration is a complex, interlaced structure, which is very difficult to manufacture.

The purpose of the present invention is to provide a dynamic random access memory cell configuration and a manufacturing method thereof, which can provide a completely depleted transistor without generating a floating body as much as possible, and at the same time provide a simple manufacturing method.

According to the present invention, this objective can be achieved by a dynamic random access memory cell configuration with the characteristics listed in item 1 of the scope of patent application.

The present invention provides a dynamic random access memory cell configuration with vertical metal oxide semiconductor transistors, which has a matrix configuration of memory cells, each of which has a metal oxide semiconductor transistor, and the metal oxide semiconductor transistor has an upper source /Drain region, a channel region and a lower source/drain region, which are stacked on top of each other to form a layer, and a capacitor, which is connected to the metal oxide semiconductor transistor,-where the memory The channel regions of the metal oxide semiconductor transistors of the cell matrix are arranged in columns and rows, and the channel regions arranged along one of the rows are parts of a rib that extends horizontally in the substrate, where each of the ribs Will be surrounded by the gate dielectric layer on both sides and the upper source/drain region,-where the gate electrode of the metal oxide semiconductor transistor is arranged along one of the rows of the memory cell matrix, and Each part of the column of parallel strip-shaped character lines is located above the ribs and starts from above the trenches formed between the ribs in the row direction, filling the trenches to exceed the width of the character line, -Therefore, at each intersection of the memory cell matrix, there will be a vertical double gate metal oxide semiconductor transistor, and the gate electrodes of the associated word line are formed in the trenches on both sides of the associated ribs.

The basic idea of the present invention is that, firstly, the horizontal double gate of the vertical transistor is related to the width and doping of the channel region, and the transistor can be easily produced in a completely depleted form; secondly, it can pass through the ribs and the substrate The channel area at the edge is in contact, so the charge carriers can flow out.

A preferred embodiment can provide a dynamic random access memory cell configuration, in which each memory cell has a capacitor, which is stacked under the metal oxide semiconductor transistor and electrically connected to the lower source / Drain region,-and in it, there is a metal bit line on the metal oxide semiconductor transistor, which is arranged along one of the rows, parallel to the row, the metal bit line is located on the word line and electrically It is electrically connected to the upper source/drain region of the associated MOS transistor.

The upper source/drain regions of the rows are formed in a strip-like manner, and there are more advantages in the formation of continuous regions, and they can be connected to the corresponding metal bit lines in a bonding manner.

The present invention also provides a method for manufacturing a dynamic random access memory cell configuration as in the first patent application, which includes the following steps: -a) implanting dopant ions to generate an upper source on the substrate /Drain region array; -b) Use lithography etching mask pattern to etch the trench to produce the channel area, which will be connected to each other to form a rib; -c) Create a cover layer in the trench and on the surface of the rib Generate a gate dielectric layer on the substrate; -d) deposit and pattern the strip character line, and generate gate electrodes on both sides of each metal oxide semiconductor transistor; -e) deposit a second layer on the front surface of the substrate An auxiliary layer, which can be used for wafer bonding, and then the first auxiliary carrier substrate is applied to the first auxiliary layer, and then the substrate is removed; -f) implanting dopant ions to produce a lower surface on the channel region Source/drain region array; -g) Use STI technology to produce shallow isolation trenches. Using the following additional steps, it is especially possible to provide a simple dynamic random access memory manufacturing method; -h) generate a contact structure and a capacitor, which are stacked on the front surface of the first auxiliary carrier substrate, and are associated with the The bottom source/drain region of the metal oxide semiconductor transistor contacts; -i) On the front surface of the first auxiliary carrier substrate, deposit a second auxiliary layer, which can be wafer-bonded, and then the second auxiliary The carrier substrate is applied to the second auxiliary layer, and then the first auxiliary carrier substrate and the first auxiliary layer are removed; -j) on the front surface of the second auxiliary carrier substrate, a structural metal bit line is formed, with So as to directly make electrical contact with the upper source/drain region.

Schematic description

The preferred specific embodiments of the dynamic random access memory cell configuration and the manufacturing method thereof according to the present invention will be described below with reference to the accompanying drawings, in which:

1a, 2a, 3, and 4 are cross-sectional views taken along the line AA in FIG. 1b to explain the continuous process steps involved in manufacturing the dynamic random access memory cell configuration according to the present invention;

Figures 1b and 2c show plan views of the configuration of dynamic random access memory cells, which are manufactured according to the process steps shown in Figures 1a and 2a of the present invention, respectively;

Fig. 2b is a cross-sectional view of the tangent line BB in Fig. 2c.

The individual process steps for manufacturing the dynamic random access memory cell configuration according to the present invention will be described with reference to FIGS. 1 to 4.

Detailed description of the invention

By way of example, Figure 1b shows a configuration (matrix) of four memory cells, in which the striped character line 10 (gate) in the plan view of Figure 1b defines the columns of the matrix and contacts the transistor, the character The lines are arranged adjacent to each other in a column, and the strip-shaped upper source/drain region 4 in each case, which defines several rows, is located above the transistors arranged in one of the rows. Fig. 1a is a cutaway view of the unit configuration of the line AA in Fig. 1b. As will be explained in more detail below, the manufacturing technology that uses the SOI substrate as a starting point has many benefits, that is, starting from the substrate 1, it has a polysilicon layer 3 to be patterned thereon and intervening buried layers.Enteroxide layer 2.

It can be seen from FIG. 1a that an implantation step is first used to generate an upper n-type doped source/drain region 4 array on the SOI wafer, that is, the polysilicon layer 3. At this time, in the manufacturing sequence, further implantation steps (well array, surrounding, etc.) can be performed and the surrounding STI (Shallow Trench Isolation) technology can be used to create trench isolation.

Then, the trenches 5 in the row direction can be (dry) etched by lithographic etching mask patterns, so that continuous polysilicon residual ribs 7 can be maintained, which are defined by the trenches 5 (see FIG. 2b). The channel regions 6 of the transistors arranged adjacent to each other are located in the column direction (see Fig. 1a).

In the next step, by way of example, silicon nitride can be deposited, planarized by the CMP method, and etched back, so that a nitride layer can be produced in the trench 5, which can be used as a capping layer 8 later. Then, gate oxide 9 will be generated on both sides and above the rib 7; if necessary, the transistor process can be performed separately in the cell array and the surrounding. The gate oxide 9 can be produced especially by thermally growing an oxide layer.

The next process steps include depositing, lithographic etching patterning, and etching the strip character line 10. Conductive materials, for example, doped polysilicon, tungsten, silicon nitride, or a layer system with an intermediate tungsten nitride layer will also fill the trench 5, thereby forming gate electrodes 11 and 12. After the word line 10 is etched, SiN deposition and etching steps are further performed, especially for manufacturing spacers. In addition, additional source/drain regions can be implanted around, for example, to fabricate logic circuits on the chip. Finally, a first auxiliary layer 13 can be deposited, which is usually an oxide layer (although it may also be a BPSG layer), which can be used for wafer bonding and can be planarized if necessary, so that the state of FIG. 1a can be produced.

In a further process step, the wafer bonding step, the first auxiliary carrier substrate 14 may be coated or adhesively bonded to the planarized auxiliary (oxide) layer 13. This can be achieved by heating the opposite surface and bonding it.

After the boundary surfaces have been joined and cooled, an indecomposable chemical bond will be formed between the auxiliary (oxide) layer (13) and the first auxiliary carrier substrate 14 after a preset time.

The already (initial) formed structure will be processed from the opposite side for further process steps. To achieve this goal, the entire structure must be "turned over", and the uppermost substrate 1 must be etched by wet etching. The advantage of the buried oxide layer 2 is that it can be used for etching. Furthermore, the buried oxide layer 2 can be removed by chemical mechanical planarization CMP or by a further etching step. The capping layer 8, especially the silicon nitride layer, can be used in the gate electrode. Oxide 9 prevented these processes before.

The doped ions will be implanted into the currently uncovered surface, referring to FIG. 2a, which is the original back surface, so as to generate an array of lower source/drain regions 15 on the channel region 6. Because the lower source/drain region must be electrically isolated, which is different from the upper source/drain region, then, referring to Figures 2b and c, STI technology will be used in the usual way (lithographic etching, etching, oxide Deposition, CMP) to produce shallow isolation trenches 16 in the form of ribbons.

This can produce the state shown in Figure 2. If you refer to the cross-sectional view of any one of the two tangent lines in the plan view of FIG. 2c, the basic concepts of the present invention can be more easily explained in FIGS. 2a and 2b, which are located in mutually perpendicular tangent directions.

FIG. 2a clearly shows the vertical MOS transistor, which each includes an upper and a lower source/drain region 4 and 15, and a channel region 6 extending vertically therebetween, and a gate oxide 9. In each trench 5 to both sides, that is, to the left and right sides of the channel region 6, gate electrodes 11 and 12 are formed, which are connected to each other by a strip character line 10.

Therefore, according to the present invention, a vertical transistor with lateral double gates is provided. Therefore, firstly, depending on the width and doping of the channel region 6, a completely depleted transistor can be easily produced. These transistors are connected to each other in the column direction, so that each transistor in the lateral direction has two gate electrodes 11 and 12, and each gate electrode in the trench 5 can also be regarded as belonging to two adjacent Of transistors.

Secondly, the vertical transistors will be connected to each other in this way in the row direction, referring to FIG. 2b, so that the channel region 6 forms a continuous rib 7. Therefore, the transistor, or more specifically the channel region 6 of the row transistor, does not form individual silicon rows isolated from each other, but forms a wall-like structure, that is, the ribs 7. These structures can adopt characteristics similar to the substrate due to size considerations, or at least make contact at the edge of the substrate. Because the channel area 6 is in contact at the edge of the substrate and grounded, the floating body effect can be significantly reduced or even avoided.

It is suggested to be able to manufacture cell configurations with memory cells, each of which includes a vertical transistor, a capacitor disposed under the vertical transistor, and a metal bit line disposed above the transistor. Essentially, the following additional steps are required: first, a contact structure 17 is generated on the front surface of the first auxiliary carrier substrate 14, and a multilayer capacitor is generated on the contact structure. The contact structure 17 in each case connects the lower source/drain region 15 of each transistor to the first electrode 18 of the capacitor stacked under the transistor. The dielectric material 19 in each case, for example tantalum pentoxide, will isolate the first electrode 18 from the capacitor, and in each case, it will be designed and connected to the opposite electrode of a common capacitor plate 20. In the case of multilayer capacitors, all customary specific embodiments (box shape, cylindrical shape, etc.) can be applied, and various materials can also use customary specific embodiments, but it is preferable to use metal electrodes and super Dielectric with high dielectric constant. Therefore, generally speaking, a simple low-impedance connection capacitor can be produced, and its aspect ratio (aspectratio) will not be restricted due to metallization, as in the case of trench capacitors.

After the multilayer capacitor is manufactured, a second auxiliary (oxide) layer 21 is deposited on the capacitor, and in the wafer bonding step, a second auxiliary carrier substrate 22 is coated or adhesively bonded. Then, the entire structure will be turned over again, so the conventional method steps can now be used to generate metal bit lines 23 and contacts (not shown) on the front surface of the auxiliary carrier substrate 22.

After "flip" twice, the current dynamic random access memory cell configuration according to the present invention, as shown in Figure 4, has the desired configuration (the substrate, the embedded capacitor above it, and then the vertical transistor , And the uppermost is the metal bit line), because of the relationship between the vertical configuration of the selected transistor and the capacitor stacked below it, super-large integration can be carried out. The size of the memory unit is about 4F ² , The smallest lithographic etching characteristic size is F<0.2 microns.

The process for manufacturing the dynamic random access memory cell configuration according to the present invention is very simple, especially in the aspect of lithography (using a ribbon mask), and especially includes a very simple metallization operation.

In particular, wafer bonding is used multiple times in the manufacturing sequence to enable it to combine the main advantages of trench technology (because from the device, the capacitance and metallization are in different directions, so it has a simple metal It is easy to integrate the advantages of vertical transistors) and the main advantages of stacking technology (systems that can reduce thermal budget: devices, capacitors, metalization).