Apparatus for generating random numbers

Random number generating device

<p>100. . .Random number generating device</p><p>101. . .Fast variable frequency oscillator</p><p>102. . .Slow Frequency Oscillator</p><p>103. . .Domain synchronization logic</p><p>104. . .Balance logic</p><p>105. . .Parallel conversion logic</p><p>106. . .buffer</p><p>107. . .Variable frequency logic</p><p>108. . .Variable deviation generating device</p><p>200. . .Timing diagram</p><p>300. . .Domain synchronization logic</p><p>400. . .Balance logic</p><p>401. . .Data register</p><p>402. . .Bit counter</p><p>403. . .Parity logic</p><p>404. . .Gate logic</p><p>405. . .Random bit selection buffer</p><p>500. . .Parallel conversion logic</p><p>501. . .Bit counter</p><p>502. . .Offset register</p><p>600. . .Variable deviation generating device</p><p>601. . .Static analog deviation signal</p><p>602. . .Two-bit digital analog transformation logic</p><p>603. . .Sum logic</p><p>700. . .Variable deviation generating device</p><p>701. . .Static deviation signal</p><p>702. . .Inverter</p><p>703. . .Inverter</p><p>800. . .Slow frequency conversion logic</p><p>801. . .Fast variable frequency oscillator</p><p>802. . .Frequency-driven logic</p><p>803. . .Mutex or logic element</p><p>900. . .Slow Frequency Oscillator</p><p>901. . .Slow ring oscillator</p><p>1000. . .Fast oscillator frequency table</p><p>1100. . .Slow oscillator frequency table</p>

In order to further understand the actual technical content of the present invention, please refer to the following drawings and descriptions.

FIG. 1 is a block diagram of a random number generating device according to the present invention.

FIG. 2 is a timing diagram of the present invention, describing how the control of variable deviation is applied to modify the oscillation frequency according to the present invention.

FIG. 3 is a block diagram of a network synchronization logic in the random number generating device in FIG. 1 of the present invention.

FIG. 4 is a block diagram of a balanced logic according to the present invention.

FIG. 5 is a block diagram of a parallel conversion logic in the random number generating device in FIG. 1 of the present invention.

FIG. 6 is a detailed block diagram of the first embodiment of the variable deviation of the present invention.

FIG. 7 is a detailed block diagram of the second embodiment of the variable deviation of the present invention.

FIG. 8 is a block diagram of a slow frequency conversion logic according to the present invention.

FIG. 9 is a block diagram of a slow variable frequency oscillator according to the present invention.

Figure 10 is a period and frequency table, showing the multi-level function of the analog deviation signal of a typical fast oscillation signal.

Figure 11 is a period and frequency table, which shows the multi-grading function of analog deviation signals for different logic states of randomly changing noise bits that typical slow-oscillation signals have.

Relevant information about the application:

This application is related to the following U.S. patent applications with a common filing date and a common applicant, which are hereby incorporated by reference in this application.

<tables><img file="TW554285B_D0001.tif" /></tables>

(1) Technical Field of Invention:

The invention relates to microelectronics from a macro perspective, especially a random number generating device composed of integrated circuits.

(II) Technical background of the invention:

Today, computer-based applications rely heavily on the random number technique. Nowadays, the field of programming in technology has gradually been commercialized unknowingly.

In the early years, those large and fast computing systems used simulation programs to actually infer the properties exhibited by various phenomena of interest, such as a huge network system containing many computers.

At present, the demand for the generation of random numbers in areas such as efficiency and convenience, and the areas of modeling and simulation has not decreased, because recent technological advances have provided desktop computers with more powerful computing capabilities. You know, the software and hardware that can provide more powerful computers have already been put into the components of these desktop computers. In fact, the processing power of desktop computers has improved the entire new application area, and the reason for this increase is based on the generation of random numbers. For example, random numbers are widely used in many electric toys, such as positioning many star-shaped figures or the position of enemy fighters. In order to allow consumers to accept 'electric toys must simulate the relevant changes in the situation, so that the simulated conditions are the same as the conditions that consumers expect in real life.

Another applicable field of random numbers is encryption technology, and this technical field has higher requirements for the generation of random numbers. In this field, random numbers are applied as an encrypted key. The mathematical algorithm is used to encrypt and decrypt many electronic files or data strings, and then store or transmit the electronic files or data strings. For example, a random key is created to encrypt financial data so that the financial data can be transmitted securely via the Internet. Obviously, more and more embodiments can find the technology to apply encryption, for example, the general email is transmitted between two organizations after being encrypted.

Now most of the random numbers generated in desktop computing systems are done in one application. Regarding such random number generation methods, pseudo-random number generation is more famous because these random numbers are applied to a mathematical algorithm to generate a series of independent variables, and these variables are evenly distributed. The odds are commensurate. Take a typical example: 'When a "seed" number is initially selected, the mathematical algorithm will distort the selected "seed" number and present a random state in a disordered order, and these "seed" numbers are A law of nature. In order to truly achieve a random state, a random number generating device must have the random characteristics of some physical devices, such as thermal noise generated by a diode or a resistor.

Some hardware-based random number generating devices are individual integrated circuits, but to date, there is no hardware technology or existing ones that can generate random numbers by cooperating with their own microprocessor circuits. . Because the microprocessor is the heart of a desktop computer, it is best to generate random numbers directly from the microprocessor.

Therefore, the best condition for a hardware-based random number generating device is that it can be easily incorporated into the design of integrated circuits, especially the latest microprocessors today.

In addition, there is also a need for logic elements required by a random number generating device that are commonly used in integrated circuits in microprocessors.

(3) Brief description of the invention:

The present invention provides a hardware-based random number generation technology. For example, a random number generating device is provided. The device includes a first variable frequency oscillator, a second variable frequency oscillator, and a frequency variation logic. The first variable frequency oscillator generates a first oscillating signal at a first frequency. The second variable-frequency oscillator generates a second oscillation signal, the second oscillation signal is not synchronized with the first oscillation signal, and a second frequency of the second oscillation signal is less than the first frequency. The bits of the random number are configured at the second frequency from the first oscillating signal. The frequency conversion logic is coupled to the second frequency conversion oscillator and generates a noise to guide the second frequency conversion oscillator to change the second frequency. This noise is equivalent to the co-location of a third oscillation signal and a fourth oscillation signal, but these two signals are not synchronized, nor are they synchronized with the first and second oscillation signals.

The present invention is directed to exploring how to have a function of generating a random number device in an integrated circuit. The random number generating device has a fast oscillator, a slow oscillator, network domain synchronization logic and frequency conversion logic. The fast oscillator generates a fast oscillating signal at a first frequency. The slow oscillator generates a slow oscillating signal. The slow oscillation signal is decoupled from the fast oscillation signal, and its signal strength is less than half of the first frequency at the second frequency. The network synchronization logic is coupled with the fast oscillator and the slow oscillator. The network synchronization logic samples the fast oscillation signal, that is, when the fast oscillation signal is synchronized with the slow oscillation signal, a random number of potential bits is obtained. . The frequency conversion logic is coupled to the slow oscillator and changes the second frequency according to the co-location of the two independent oscillation signals.

The present invention is to understand a random number generating device in a microprocessor. The random number generating device includes a slow oscillator, balance logic and frequency conversion logic. The slow oscillator generates a sampling timing signal, and the sampling timing signal is applied to obtain a sampling of a first oscillation signal, and the intensity of the sampling timing signal is less than one-half of the frequency of the first oscillation signal. The balance logic is coupled to the slow oscillator and will reject multiple consecutive sample pairs, and the samples have the same state; the balance logic will also configure a random number of bits, the random number comes from the complex number One of the two consecutive sampling pairs, and the sampling pairs do not have the same status. The frequency conversion logic is coupled to the slow oscillator and changes the frequency of the sampling timing signal in accordance with the same position of the two asynchronous oscillation signals.

Schematic illustration

In order to further understand the actual technical content of the present invention, please refer to the following drawings and descriptions.

FIG. 1 is a block diagram of a random number generating device according to the present invention.

FIG. 2 is a timing diagram of the present invention, describing how the control of variable deviation is applied to modify the oscillation frequency according to the present invention.

FIG. 3 is a block diagram of a network synchronization logic in the random number generating device in FIG. 1 of the present invention.

FIG. 4 is a block diagram of a balanced logic according to the present invention.

FIG. 5 is a block diagram of a parallel conversion logic in the random number generating device in FIG. 1 of the present invention.

FIG. 6 is a detailed block diagram of the first embodiment of the variable deviation of the present invention.

FIG. 7 is a detailed block diagram of the second embodiment of the variable deviation of the present invention.

FIG. 8 is a block diagram of a slow frequency conversion logic according to the present invention.

FIG. 9 is a block diagram of a slow variable frequency oscillator according to the present invention.

Figure 10 is a period and frequency table, showing the multi-level function of the analog deviation signal of a typical fast oscillation signal.

Figure 11 is a period and frequency table, which shows the multi-grading function of analog deviation signals for different logic states of randomly changing noise bits that typical slow-oscillation signals have.

Explanation of main component symbols

100. . .Random number generating device

101. . .Fast variable frequency oscillator

102. . .Slow Frequency Oscillator

103. . .Domain synchronization logic

104. . .Balance logic

105. . .Parallel conversion logic

106. . .buffer

107. . .Variable frequency logic

108. . .Variable deviation generating device

200. . .Timing diagram

300. . .Domain synchronization logic

400. . .Balance logic

401. . .Data register

402. . .Bit counter

403. . .Parity logic

404. . .Gate logic

405. . .Random bit selection buffer

500. . .Parallel conversion logic

501. . .Bit counter

502. . .Offset register

600. . .Variable deviation generating device

601. . .Static analog deviation signal

602. . .Two-bit digital analog transformation logic

603. . .Sum logic

700. . .Variable deviation generating device

701. . .Static deviation signal

702. . .Inverter

703. . .Inverter

800. . .Slow frequency conversion logic

801. . .Fast variable frequency oscillator

802. . .Frequency-driven logic

803. . .Mutex or logic element

900. . .Slow Frequency Oscillator

901. . .Slow ring oscillator

1000. . .Fast oscillator frequency table

1100. . .Slow oscillator frequency table

(5) Detailed description of the invention:

The following description is intended to enable a person skilled in the art to understand and use the specific applications and requirements of the present invention. For the situation where the preferred embodiment is modified in various ways, it will be obvious to those skilled in the art. The general principles defined herein will equally apply to other embodiments. Therefore, the preferred embodiments of the present invention should not be used to limit the scope of the present invention, that is, all equal changes and modifications made according to the scope of the patent application of the present invention should still fall within the scope of the patent of the present invention.

After knowing that the random number generation and related technologies discussed in the technical background of the foregoing invention are applied to integrated circuits that generate random numbers today, the present invention will be described with reference to FIGS. 1 to 11.

Please refer to FIG. 1, which is a block diagram of a random number generating device according to the present invention. The number 100 in the figure is a random number generating device. The device 100 has a fast frequency conversion oscillator 101, and the fast frequency conversion oscillator 101 generates a fast oscillation signal SOS2. The fast oscillation signal SOS2 is provided to the network domain synchronization logic 103. The random number generating device 100 also has a slow variable frequency oscillator 102, and the slow variable frequency oscillator 102 generates a slow oscillation signal BOS. The slow oscillation signal BOS is sent to the network domain synchronization logic 103 and the balance logic 104. The device 100 or the random number generating device 100 further has a variable deviation generating device 108, and the variable deviation generating device 108 generates a random number analog deviation signal BIAS, and the random number analog deviation signal BIAS is provided to the two-frequency oscillationDevice 101 with 102 and variable frequency logic 107. The frequency conversion logic 107 generates a digital noise NOISE, and the digital noise NOISE is provided to the slow-speed variable frequency oscillator 102. The balancing logic 104 outputs a variable-frequency bit signal RNDM, and goes to the parallel conversion logic 105 together with a random bit strobe signal CLKRN. The parallel conversion logic 105 outputs a random bus RN [7: 0] and sends it to a buffer 106 together with a ready signal RDY. The plurality of bits RN [1: 0] from the random bus RN [7: 0] are sent to the variable deviation generating device 108.

In this embodiment, both the fast oscillator 101 and the slow oscillator 102 are configured like ring oscillators 101 and 102, which are like the two timing signal generating devices 101 and 102 currently used in integrated circuits. A person familiar with this technique will know that the typical ring oscillators 101 and 102 will provide the oscillating output signals SOS2 and BOS within a frequency range. The limit of this range depends on the choice of components and the timing signal generating device. 101 and 102 specifications. The special frequencies of the oscillating output signals SOS2 and BOS are generally set according to the amplitude of the analog deviation signal BIAS. The analog deviation signal BIAS is provided to the oscillators 101 and 102 by an external source 108. In many application examples, the ring oscillators 101 and 102 are selected in the range of their output frequencies. Therefore, a special output frequency can be known, and a deviation signal BIAS can be fine-tuned to the special output frequency. In addition to providing fine-tuning functions, today's microelectronics uses variables of other technologies to change the value of the bias signal BIAS with slight differences to compensate for fluctuations in voltage and temperature changes in a system and changes in integrated circuit manufacturing processes.

In operation, although a common deviation signal BIAS is provided to the fast oscillator 101 and the slow oscillator 102, they produce independent and asynchronous outputs SOS2 and BOS. In one embodiment, the fast oscillator 101 generates a frequency range value that is 10 to 20 times the frequency generated by the slow oscillator 102. In another embodiment, the frequency range provided by the fast oscillator 101 is at least twice the frequency provided by the slow oscillator 102. The network domain synchronization logic 103 uses the slow oscillation signal BOS, such as the same sampling timing signal BOS, to obtain a sample of the fast oscillation signal SOS2. The sampling of the fast oscillating signal SOS2 is sampled at the frequency of the slow-talking oscillating signal BOS and is continuously provided to the random bit signal RNDUM as a potential bit of random numbers.

When the variation generated during processing or any other form of variation leads to a condition that affects the generation of potential disorder numbers on the signal RNDUM, the balance logic 104 will come out to compensate for the above situation; so that the signal RNDUM does not have a tendency to a particular Trend of logic state (such as logic 0 or logic 1). Then, the balancing logic 104 checks the successfully paired potentially random bits provided by the RNDUM to determine whether the two bits of each pair have the same logic state. If the two bits have the same logic state, the balance logic 104 will reject the bit pair due to the attribute of the random number. If the two bits do not have the same logic state, the balance logic 104 selects one of the bits as a random number. In one embodiment, the first of the two bits in a bit pair or a potential bit is selected as the random bit. In another embodiment, the second bit is selected. Next, the random number bits are transmitted with a variable-frequency bit signal RNDM, and a corresponding strobe signal CLKRN is generated by the balance logic 104, which indicates that the parallel conversion logic generates an random number bit.

Random bits are clocked in series via signals RNDM and CLKRN and parallel conversion logic 105. The parallel conversion logic 105 aggregates the random number bits generated by the string into an n-bit random number. The n-bit random number is provided by a buffer 106 connected in parallel through a bus [7: 0]. . An instant signal RDY will strengthen the buffer 106 to lock n-bit random numbers, so it can be retrieved. For example, an 8-bit random number can be provided to the bus [7: 0]. In addition, for some other examples, random numbers that can provide selective structures are in contrast to those required for selective applications.

The unpredictability of potential bits used in random numbers is increased by independently changing the frequency of the fast oscillator 101 and the slow oscillator 102. First, the levels of the deviation signals BIAS of the two oscillators 101 and 102 can be changed to conform to the logical state of the plurality of bits of the random number described above, and the random number will be provided to the buffer 106 after configuration. The parallel conversion logic 105 continues to convert the serial random number to the parallel random number, and the state of the bus RN [7: 0] will change to reflect the logical state of each new bit being converted to a new bit position. . For example, the two bits RN [1: 0] from the bus RN [7: 0] are extracted and sent to the variable deviation generating device 108. The deviation generating device 108 is based on the analog value of the deviation signal BIAS of the state changes of the two bits RN [1: 0]. The change of the bias signal BIAS is about a fixed value of BIAS, and the fixed value is determined by the state of a 3-bit fixed-point input signal XRAY [2: 0]. In an integrated circuit embodiment, the state of the 3-bit fixed-point input signal XRAY [2: 0] is fixed when the integrated circuit is manufactured. Therefore, the fixed-point input signal XRAY [2: 0] will prompt the integrated circuit designer to adjust the value of the bias signal BIAS when a certain part is being generated, so as to compensate or compensate for the changes that occur during the processing. Although the embodiment in FIG. 1 only uses two bits from the random bus RN [7: 0] to adjust the bias signal BIAS, those skilled in the art will understand that different embodiments of the present invention can be combined State to extract the other bits of bus RN [7: 0], so it can meet the necessary conditions for selective application.

Another second mechanism to increase the unpredictability of potential bits is through frequency conversion logic 107. The frequency conversion logic 107 will generate digital noise NOISE independently, and the logic state of NOISE will change the frequency of the slow frequency conversion oscillator 102 in a random manner. In addition, the digital noise NOISE is applied to the bias signal BIAS associated with the slow-frequency variable-frequency oscillator 102 to change the frequency of the oscillating signal BOS. Therefore, the sampling frequency of the signal SOS2 will be effectively changed.

According to the invention, a random number generating device is concluded that the output state SOS2 of a first oscillator 101 is sampled by a second oscillator 102 in a certain proportion. The second oscillator 102 has a lower frequency than the first oscillator 101. The balancing logic 104 filters out a plurality of samples having the same logical level. Any one of the accepted bit pairs will be used for the configuration of an n-bit random number. The n-bit random number will be provided to a buffer after the serial and parallel conversion is completed. <img file="TW554285B_D0002.tif" /> . The configured random number of bits RN [1: 0] will be continuously applied by an deviation generating device 108 to change the level of a deviation signal BIAS, and the level will be provided to the first and second oscillations.Device 101,102. Thus, the frequencies of the related outputs SOS2 and BOS will continuously change. The frequency of the second or slow oscillator 102 may have additional and continuous changes, which is based on the logic state of an independently generated random digital signal.

Please refer to FIG. 2, which is a timing diagram of the present invention. The timing diagram 200 describes how the control of variable deviation is applied to modify the oscillation frequency according to the present invention. The timing diagram 200 shows a first oscillating signal SOS, a second oscillating signal BOS2 and a variable analog deviation signal BIAS. These signals SOS2, BOS, and BIAS are nouns representing the relevant output signals discussed in FIG. The amplitude of each signal SOS2, BOS, and BIAS is related to the high (HI) and low (LO) amplitude boundaries, which show the voltage boundary value defined by the amount of voltage applied to the microelectronic circuit and the circuit technology. For example, for a 1.5 volt CMOS integrated circuit, if the voltage amount indicated by HI is large near 1.5 volts, if the voltage amount expressed by LO is large near 0 volts.

According to a preferred embodiment of the present invention, when the signal BIAS is displayed as very high (HI), the two oscillating output signals SOS2 and BOS are both at the highest frequency. The signal SOS2 has a period of 1.0 ns, which corresponds to a frequency of 1 GHz. The signal BOS has a period of 15ns, which corresponds to a sampling frequency of 67MHz. Therefore, when the bias signal BIAS is at the highest level, the speed of the signal SOS2 is about 15 times that of the sampling signal BOS.

When the deviation signal BIAS is at the lowest (LO), the two oscillating output signals SOS2 and BOS are both at the lowest frequency. The signal SOS2 has a period of 2.0 ns, which corresponds to a frequency of 500 MHz. The signal BOS has a period of 45 ns, which corresponds to a sampling frequency of about 22 MHz. Therefore, when the bias signal BIAS is at the lowest level, the speed of the sampling frequency provided by the signal BOS is approximately one-twentieth of the potential bit generation frequency provided by the signal SOS2.

When the amplitude of BIAS is moderate, the signal SOS2 has a period of 1.5ns (667MHz), and the signal BOS has a period of 30ns (33MHz). Under such moderate amplitude conditions, the speed of the sampling frequency is about one-twentieth of the frequency of potential bit generation.

The timing diagram 200 in FIG. 2 is to clarify the change of the bias signal BIAS. Even if each of its oscillating signals SOS2 and BOS shows an almost linear response, the frequency relationship between these two signals SOS2 and BOS is still non-linear of. However, those skilled in the art will know from the timing diagram 200 in the embodiments discussed above that any oscillator in this device does not need to respond linearly, and the bias signal BIAS does not need to be provided to this device. The invention provides a system or integrated circuit whose operating voltage varies over the entire range of the supply voltage. The fast oscillation signal SOS2 does not need to be ten to twenty times faster than the sampling signal BOS.

Please refer to FIG. 3, which is a block diagram of a network synchronization logic 300 in the random number generating device 100 in FIG. 1 of the present invention. The network domain synchronization logic 300 includes two registers 301 and a fast oscillating signal SOS2, and the logic 300 is synchronized with a timing network domain that complies with a slow oscillating signal BOS. In this embodiment, the two registers 301 are a flip-flop 301, and the signal BOS can be input to the two registers 301 like a clock. The first clock edge of a BOS (eg, the rising or falling edge is determined by a special circuit structure). The sampling of the signal SOS2 is selected to generate the output signal SOS2REG. On the clock edge of the next BOS, the second register 301 captures the state of the signal SOS2REG to the output signal RNDUM. Those skilled in the art will understand that at least two serial registers are needed, and they will be used as general purpose to synchronize digital signals from different timing network domains. This can solve the problem of two asynchronous timing network domains. problem. The following is about the 1-clock startup delay. According to the clock edge of each slow-oscillation signal BOS, the network synchronization logic 300 will provide a random number above the output signal RNDUM. New potential bits.

Please refer to FIG. 4, which is a block diagram of the balanced logic 400 of the present invention. The balancing logic 400 has a data register 401 to receive potential bits provided by an random number on the signal RNDUM. The sampling clock BOS is applied by the data register 401 at the same timing, and is applied to the clock potential bit string to the balance logic 400. And the sampling clock BOS is also provided to the one-bit counter 402 and the AND logic 404. The data register 401 provides a latched data output signal RNDUMX, and the latched data output signal RNDUMX is sent to the parity logic 403 and input to a random bit selection buffer 405 according to a prescribed route. The parity logic 403 has a singular parity output signal DIFF, and the singular parity output signal DIFF is provided to the AND logic 404. In addition, the even output signal EVEN of the one-bit counter 402 is provided to the other input terminal of the AND logic 404.

In operation, the data register 401 enables the balanced logic 400 to enter a pair of potential bits of the random number, which is provided by the network synchronization logic 300 in a serial manner, as in the slow-oscillating signal BOS. Sampling of the fast oscillating signal SOS2 in the timing network domain. The signal RNDUM provides access to a first potential bit, and the signal RNDUMX provides access to a second potential bit. The first potential bit and the second potential bit in the pair of potential bits are both provided to the parity logic 403. In this embodiment, the parity logic 403 is a mutually exclusive OR logic gate 403. If the logical states of the potential bits on the signals RNDUM and RNDUMX are different, the parity logic 403 will claim an odd parity output signal DIFF. If the logic states of the two potential bits are the same, the odd-numbered parity output signal DIFF will not be asserted.

One purpose of recapitulating the balance logic 400 is to identify potential bits that have been successfully paired provided by the domain synchronization logic 300. Therefore, the bit counter 402 is used to assert the signal EVEN for each even-numbered circle of the sampling clock signal BOS, and assert the signal ODD for each odd-numbered circle of the sampling clock signal BOS. Therefore, the even bit output signal EVEN of the bit counter 402 is considered to have the function of a reviewer, so that the logic 404 ensures that the potential bits are all considered in pairs, and a single bit is not repeated for more than two of. During this period, the parity logic 403 functioned exactly like a sliding two-bit parity window on the latent bit data string. The use of the output signal EVEN is still used as a reviewer so that the logic 404 confirms that the potential bits are processed in pairs. In this embodiment, the AND logic 404 is an AND logic gate 104.

If the two bits of the potential bit pair are in different states, the first bit of the potential bit will be sent from the signal RNDUMX to the output signal RNDUM according to a prescribed route, and will pass through the buffer 405 on the way. For random numbers, the output signal RNDM is a newly accepted bit state. Therefore, the signal CLKRN will be confirmed to show the next logic, which means that a newly accepted bit is already valid on the output signal RNDM.

Based on the above discussion, those skilled in the art will understand that the selective structure completed by the present invention can achieve the effects discussed above. For example, and as far as the logic 404 is concerned, an odd output signal ODD of the bit counter 402 is just like the same reviewer. Moreover, the second bit of a potential bit pair is more likely to replace the first bit and become a random number.

Please refer to FIG. 5, which is a block diagram of a parallel conversion logic 500 in the random number generating device in FIG. 1 of the present invention. The parallel conversion logic 500 is coupled to the balance logic 400 and receives signals RNDM and CLKRN. The parallel conversion logic 500 includes a one-bit counter 501 and a U-shift register 502 (shift register).

In operation, when a new random bit is accepted, the random bit strobe signal CLKRN is confirmed by the balance logic 400. Furthermore, the new random number bits will be proposed to the offset register 502 through the provision of the signal RNDM, and the timing will be started via the signal CLKRN. The bit counter 501 counts the number of strobes provided by the signal CLKRN. When CLKRN has been selected many times and the number of times is the same as the random number, the bit counter 501 will show that a new n-bit random number on the bus RN [7: 0] is already available. In FIG. 5 of the present embodiment, an 8-bit counter 501 together with an 8-bit offset register 502 is applied to convert eight serial random bits into a parallel 8-bit random number. . Although Figure 5 shows an 8-bit random number, those skilled in the art understand that if there are other bit-random numbers, the structure discussed in the present invention will also be competent, so it is not limited to 8-bit numbers. In FIG. 5, the signal states of the multiple random bits on the bus RN [7: 0] are changed to the bus RN [7: 0] through the register 502. Therefore, a plurality of random number bits from the bus RN [7: 0] are provided to provide a device, which can change an offset signal BIAS according to the present invention and the effect of a variable offset generating device.

Please refer to FIG. 6, which is a detailed block diagram of the first embodiment of the variable deviation generating device 600 of the present invention. The variable deviation generating device 600 includes a 2-bit digital analog conversion logic 602 and a total logic 603. The two bits RN0 and RN1 from bus RN [7: 0] and the data discussed in Figure 5 will be provided to the 2-bit digital analog conversion logic 602, which is like data input to logic 602 .

The 2-bit digital analog interactive conversion logic 602 converts the binary digits RN0 and RN1 to an analog voltage signal NSE (analog voltage signal). The analog voltage signal NSE is provided by a logic zero voltage and a voltage power supply. Twenty percent (VDD / 5). For example, in a 1.5V system, if the value of RN0 is 0 and the value of RN1 is 1, the amplitude of NSE is about 200mV. When RN0 is changed to a logic 1, the value of NSE will become approximately 300mV.

As the random number of bits RN [1: 0] is constantly changing, the value of NSE will also continue to change as they are. The random change signal NSE is then concluded by the summation logic 603 and transferred to a static analog deviation signal 601 to generate a signal BIAS. The bias signal BIAS is provided to the fast and slow oscillators of the random number generating device to randomly change the random bit generation frequency and the sampling frequency. In the embodiment shown in FIG. 6, it is expected that the amplitude of the static analog deviation signal 601 is established after the device selected by the designer. For example, the logic level of the setup signal XRAY [2: 0] is shown in FIG. Those skilled in the art will understand that the expected function of the variable deviation generating device 600 is to report a random analog voltage signal NSE in order to adjust a fixed deviation signal 601 in an additional manner. In this way, an offset signal 601 will be affected, that is, some fixed voltage points will be changed. Therefore, the types of the LO and HI signals input to the digital analog interactive transformation logic 602 and the logic 602 itself can easily meet the requirements of different embodiments according to the present invention.

Please refer to FIG. 7, which is a detailed block diagram of the second embodiment of the variable deviation generating device 700 of the present invention. Another embodiment of the variable deviation generating device 700 includes three P-channel MOS devices P1, P2, and P3, which are connected in parallel to the drain of an N-channel element N1. A static deviation signal XBIAS701 is provided to the N1 gate. The deviation generating device 700 receives the two bits RN0 and RN1 of the bus RN [7: 0]. The two bits RN0 and RN1 are sent to the gates of the respective P-channel elements P4 and P5 via the inverters 703 and 702, on the way. The drains of P4 and P5 of the P-channel element are coupled to the respective sources of P2 and P3, respectively.

In operation, the deviation generating element 700 adjusts the voltage of a deviation signal BIAS in a random manner by using the states of RN0 and RN1. This voltage is provided to a plurality of oscillators in accordance with the present invention to establish a frequency corresponding to the oscillating signal. The analog level of the signal XBIAS of the N-channel element N1 will obtain the voltage portion of the voltage VDD provided by the entire N1 and P1 elements. The signal BIAS is the voltage signal proposed at the drain of the element N1. When RN0 and RN1 are in the logic zero state, components P4 and P5 are turned off, so any current will be blocked from entering P-channel components P2 and P3. When RN0 is in a logic one state, element P4 is turned on, so a path is provided to allow current to pass through element P2, so the voltage value of signal BIAS is increased. In the same situation, when RN1 is in a logic one state, element P5 is turned on, so a path is provided to allow current to pass through element P3, so the voltage value of signal BIAS is also increased. Those familiar with this technology will understand that because the P-channel components P2 and P3 are connected in parallel to component P1, turning on P2 and / or P3 will increase the voltage value of BIAS, and the boost of the BIAS corresponds to the size of P2 / P3 size. On the other hand, those skilled in the art will also understand that the changes in the dimensions of the components N1, P1, P2, and P4 can also provide a larger amplitude of the bias signal BIAS and other multiple applications.

Please refer to FIG. 8, which is a block diagram of a slow frequency conversion logic 800 according to the present invention. Looking back to the embodiment shown in Figure 1, the slow frequency conversion logic 800 (element 107 in Figure 1) can be used to change an additional source of random randomness, so that the slow oscillator, sampling or signal BOS can be changed. frequency. The variable frequency logic 800 includes two independent variable frequency oscillators 801. In this embodiment, the variable frequency oscillator 801 is the same as the random bit generating oscillator 101 discussed in FIG. Its role is for economic considerations. The variable-frequency oscillator 801 provides asynchronous output signals SOS0 and SOS1, and the SOS0 and SOS1 are provided to a plurality of frequency driver logic elements 802 (frequency driver logic elements). The output signals DSOS0 and DSOS1 of each frequency driving logic element 802 are provided to the signal comparison logic 803. The signal comparison logic 803 is here an exclusive-OR (exclusive-OR) 803. The signal comparison logic 803 outputs a randomly changing digital noise NOISE, which will be provided to the slow frequency conversion oscillator 102.

After obtaining the comparison between the two individual and non-synchronous oscillation output signals DSOS0 and DSOS1, the randomly changing digital noise NOISE is generated at . This embodiment includes a mutually exclusive OR logic, which performs a comparison operation via the signal comparison logic 803. If the logic states of signals DSOS0 and DSOS1 are the same (for example, both signals are logic zero or logic one), NOISE will not confirm (such as a logic zero). If the logic states of the signals DSOS0 and DSOS1 are not the same (such as one of the two signals is logic zero and the other signal is logic one), NOISE will confirm (such as a logic one). The mutual exclusion or comparison performed by the signal comparison logic 803 is also known when obtaining the parity of DSOS0 and DSOS1. When the signals DSOS0 and DSOS1 have odd parity (for example, they have different logic states), the noise NOISE is set to logic 1. When the signals DSOS0 and DSOS1 have even parity (for example, they have different logic states), the noise NOISE is set to logic 0. In the embodiment shown in FIG. 8, the two signals DSOS0 and DSOS1 are both obtained by dividing the output signals SOS0 and SOS1 of a variable frequency oscillator 801. In this embodiment, a frequency divider 802 functions to divide signals SOS0 and SOS1 by 8 to obtain signals DSOS0 and DSOS1. The frequency divider 802 is applicable to the embodiment having the oscillator 801. These embodiments are different from the digital noise NOISE caused by the slow oscillator 102 in terms of system response, and the digital noise NOISE is different from the slow oscillation The system response of the device 102 is the same. Those skilled in the art will understand that for a plurality of embodiments using an independent oscillator 801, the divider 802 is not needed, and the system response of the independent oscillator 801 and the sampling timing oscillator 102 is consistent of. On the other hand, those skilled in the art will also understand that because each oscillator 801 operates independently, logical equations of either odd parity or even parity (such as the complement of odd parity) can be used to generate digits. Noise Noise. Therefore, those skilled in the art will understand that the plurality of oscillators 801 need not be identical.

Please refer to FIG. 9, which is a block diagram of a slow variable frequency oscillator according to the present invention. The slow-speed variable-frequency oscillator 900 provides a sampling timing signal BOS. The sampling timing signal BOS is changed by a randomly changing analog deviation signal BIAS and a randomly changing digital noise signal NOISE. The slow variable frequency oscillator 900 includes a slow ring oscillator 901 to generate a slow oscillation signal BOS in a frequency range. The frequency range is changed according to the value of an analog signal FRQDRV provided. In order to generate the analog signal FRQDRV, the slow variable frequency oscillator 900 has two series-connected P-channel elements P1 and P2, which are connected in parallel with another P-channel element P3. The amplitude of the analog signal FRQDRV is determined by its expression, so that the components P1 to P3 are activated.

Returning to Figures 1, 6, and 7 discussed earlier, the signal BIAS is an analog voltage that changes randomly, and the analog voltage changes by a fixed deviation point. Therefore, the device P2 and P3 provide proof to the expression, meaning one An acceptable amplitude is provided to the surround-view oscillator 901 by the analog signal FRQDRV. Furthermore, returning to what was discussed in Figures 1 and 8, the digital signal NOISE will randomly change the logic state. NOISE is connected to the P1 gate and passes a low-pass filter, which is composed of a resistor R1 and a capacitor C1. Therefore, those skilled in the art should understand that some specific embodiments of the present invention can use some selective components to achieve the effects of the resistors and capacitors of the components R1 and C1 shown in FIG. For example, in an embodiment of an integrated circuit, a metal oxide semiconductor device (MOS Device) should be able to provide the effects of resistance and capacitance as described above. The low-pass filters R1 and C1 can provide a twisting function to the logic transition of the signal NOISE. Therefore, the logic transition of the signal NOISE is within the acceptable range of the ring oscillator 901, and the amplitude of the signal FRQDRV is randomly increased or decreased by changing the current passing through the gate of P1. Therefore, those familiar with this technology should understand that because the P-channel elements P1 and P2 in series are connected in parallel with the device P3, the current flowing through P1 can be obtained according to the element specifications of P1 to P3. On the other hand, professionals should also know that the specifications and characteristics of components P1, P2, and P3 are easy to adjust to provide a larger range of vibration amplitudes to meet the plurality of ring oscillators 901 used in the present invention. Demand.

What is currently being discussed is the random variation of the frequency of the SOS2 and BOS signals, which generate a random number of components and independent and unsynchronized oscillators. A detailed description of the 1.5-volt CMOS microcircuit will be discussed in Figures 10 and 11.

Please refer to Figure 10, which shows a period (SOS_period) and frequency (SOS_frequency) table 1000, which shows the relationship between the typical fast oscillation signal SOS_ and the analog deviation signal BIAS. The random bit generation signal SOS2 and the asynchronous oscillation signals SOS0 and SOS1 associated with the fast oscillation and signal SOS_ are used to generate a random noise bit NOISE. The plurality of signals are a fast-frequency oscillator 101 according to the present invention and a fast-frequency oscillator 801 similar to that in the slow-frequency converter logic 800. The logic state of a fixed deviation signal XRAY [2: 0] can be applied through a plurality of variable deviation generating devices 108, 600, 700 to set the value of the signal BIAS, as shown in the technical contents shown in Figs.

In the embodiment shown in FIG. 10, a signal BIAS has a voltage ranging from 766 to 509 millivolts (mV) and is used by the fast oscillators 101 and 801 to generate the oscillating signals SOS2, SOS0, and SOS1. The plurality of signals The range is approximately 500 to 870 MHz. Returning to the technical content shown in Figures 1, 6, and 7, the classification of the signal BIAS changes as shown in Table 1000, as the multiple bits of the variable are shown on the variable bus M [7: 0] Change status.

Please refer to FIG. 11 for a period (BOS cycle) and frequency (BOS frequency) table 1100, which shows the typical deviation signal BIAS of a typical slow-oscillation signal BOS for different logic states of noise bit NOISE and its analog bias signal Multiple grading capabilities. The sampling timing signal BOS related to the slow oscillating signal BOS is provided via the slow variable frequency oscillator 102 of the present invention. The logic state of a fixed deviation signal XRAY [2: 0] is used by a plurality of variable deviation generating devices 108, 600, and 700 to set the value of the signal BIAS, as shown in the technical content shown in Figures 1, 6, and 7. .

As shown in the embodiment shown in FIG. 11, the BIAS voltage used by the sampling oscillator 102 ranges from 766 to 509 millivolts (mV) to generate a sampling timing signal BOS, whose frequency range is about 22 to 63 MHz. Returning to the technical content shown in Figures 1, 6, and 7, the level change of the signal BIAS is shown in Table 1000, as the multiple bits of the variable are shown on the variable bus RN [7: 0]. Change status. Figure 8 shows how the digital noise bit NOISE is generated to provide more random variation of the sampling timing frequency.

The embodiments discussed in FIGS. 10 and 11 are typical examples of coherence provided to fully understand the present invention. Therefore, those familiar with the art should know that the two embodiments are not intended to limit the range of the deviation voltages corresponding to the plurality of frequencies derived here.

Although the object, features, and advantages of the present invention are described in detail in FIG. 11, other embodiments are also included in the present invention. For example, although the present invention is about a random number generating device used in an integrated circuit, such as a microprocessor, the scope of the present invention is beyond the above. The plurality of elements in the applications and embodiments discussed herein can be regarded as individual independent devices or circuits between the plurality of devices.

In addition to the above, the aforementioned oscillators are exemplified by ring oscillators, and other oscillator technologies are not discussed here. Generally speaking, oscillator technology is applied in today's microelectronics to manufacture timing signals, but the oscillator embodiments discussed herein will not represent all oscillator technologies. In fact, the scope of the present invention can be extended to any device or method of generating a non-synchronous oscillating signal alone, the frequency of which can be varied and applied to the above-mentioned related conditions.

In addition, a fast bit generating oscillation signal mentioned in the present invention has a frequency range from about 500 MHz to 1 GHz, and a sampling oscillation signal has a frequency range from about 20 MHz to 65 MHz. The embodiments related to the above two signals are used to introduce the present invention in a known application field. Therefore, anyone familiar with the art will understand that the frequency range of the plurality of elements in the present invention can be expanded or reduced due to the generation of random numbers, the amount of which is equivalent to the requirements of some other applications, and those Other applications do not include the above discussion. By using the parity between the two asynchronously generated asynchronous signals to generate a digital noise bit, the sampling timing signal of the random number generating device can be further deformed, thus providing a designer with a wider and accessible frequency space. The reachable frequency of the random number generating device is changed by using changing technology, such as the thermal noise of a resistor.

The above-mentioned embodiments fully show that the purpose and efficacy of the present invention are deeply implemented and progressive, have great industrial use value, and are new inventions that have never been seen on the market today, and fully comply with the new patents. Progressiveness and novelty requirements, apply in accordance with the law.

However, the above is only for your sincere review, and we ask your reviewers to make a clear reference and pray for your approval.