Production method of III nitride compound semiconductor group, III nitride compound semiconductor element based thereon and III nitride compound semiconductor light emitting element

Method for manufacturing group III nitride-based compound semiconductor, and group III nitride-based compound semiconductor device and group III nitride-based compound semiconductor light-emitting device obtained by the manufacturing method

<p>1. 91. . . Substrate</p><p>2. 92. . . buffer layer</p><p>5. . . Growth space to ensure materials</p><p>5s. . . The growth space after forming ensures the material</p><p>31, 32, 103, 203. . . n-GaN layer</p><p>31. . . The first group III nitride compound semiconductor (layer)</p><p>32. . . The second group III nitride-based compound semiconductor (layer)</p><p>41. . . First screen material</p><p>41m. . . First curtain</p><p>42. . . Second screen material</p><p>42m. . . Second curtain</p><p>104, 204. . . n-AlGaN layer (covering layer)</p><p>105, 107. . . n-GaN guiding layer</p><p>106, 205. . . Luminescent layer</p><p>109, 207. . . p contact layer</p><p>108, 206. . . p cover layer</p><p>900. . . Point of difference</p><p>902. . . Bad row</p><p>93. . . Group III nitride compound semiconductor (layer)</p><p>100. . . Laser diode (LD)</p><p>110A, 208A. . . p electrode</p><p>110B, 208B. . . n electrode</p><p>200. . . Light Emitting Diode (LED)</p><p>G. . . Group III nitride compound semiconductor (layer)</p><p>901. . . Run through</p><p>1000, 2000. . . Wafer</p>

1(a)~(h) are cross-sectional views of the manufacturing steps of the group III nitride compound semiconductor according to the first embodiment of the present invention.

2(a) and (b) are detailed cross-sectional views of the epitaxial growth part in the manufacturing steps of the group III nitride compound semiconductor according to the first embodiment of the present invention.

Figure 3 is a cross-sectional view of a modified example.

4 is a cross-sectional view of the structure of a group III nitride-based compound semiconductor light-emitting device according to a second embodiment of the present invention.

5 is a cross-sectional view of the structure of a group III nitride-based compound semiconductor light-emitting device according to a third embodiment of the present invention.

Fig. 6 is a cross-sectional view of a through-difference row transmitting a group III nitride-based compound semiconductor.

[Detailed Description of the Invention] [Technical Field of the Invention]

The present invention relates to a method for manufacturing group III nitride compound semiconductors. In particular, it is a method for manufacturing group III nitride compound semiconductors using lateral epitaxial growth (ELO). In addition, the so-called group III nitride-based compound semiconductors refer to binary systems such as AlN, GaN, and InN; Al _x Ga _1-x N, Al _x In _1-x N, Ga _x In _1-x Ternary system such as N (all 0&lt;x&lt;1); Al _x Ga _y In _1-xy The general formula A1 of the quaternary system of N(0&lt;X&lt;1,0&lt;y&lt;1,0&lt;X+y&lt;1) _x Ga _y In _1-xy N(0x1,0y1,0X+y1). In addition, if there is no particular limitation in this specification, when the group III nitride compound semiconductor is simply referred to, it also includes group III nitrogen doped with impurities for forming the conductivity type into p-type or n-type. Compound semiconductors.

[Learning Technology]

Group III nitride-based compound semiconductors, for example, in the case of light-emitting devices, direct migration semiconductors whose emission spectrum spans a wide range of red from the ultraviolet region are used in light-emitting diodes (LED) or laser diodes Light-emitting elements such as body (LD). In addition, because of its wide energy band, by using other semiconductor components, it can be expected to perform stable operations at high temperatures. Therefore, the application of transistors such as FETs is also being actively developed. In addition, since the main component is not a stele (As), from an environmental point of view, development and application to various semiconductor devices are also expected. In this group III nitride compound semiconductor, sapphire is usually used as a substrate, and then elements are formed on it.

[Problems to be solved by the invention]

However, when a group III nitride compound semiconductor is formed on a sapphire substrate, the lattice constant between the sapphire and the group III nitride compound semiconductor is misaligned, resulting in a misalignment, resulting in poor device characteristics. . This dislocation-following difference row is the penetration difference row penetrating the longitudinal direction of the semiconductor layer. In the group III nitride compound semiconductor, it will cause transmission 10 ⁹ cm ^-2 The problem of poor ranking occurs. This transfers the layers of group III nitride compound semiconductors with different compositions to the uppermost layer. With this, for example, in the case of light-emitting elements, problems such as the threshold voltage and current of the LD, the life of the LD and the LED element, and other element characteristics become poor. In addition, even other semiconductors are stagnant in semiconductor elements with low mobility (mobility) because electrons are scattered with defects. This is the same when using other substrates.

Related to these situations, use the schematic diagram of FIG. 6 for explanation. The system shown in FIG. 6 has a substrate 91, a buffer layer 92 formed on the substrate 91, and a group III nitride compound semiconductor layer 93 formed on the substrate 91. The substrate 91 is made of, for example, sapphire, and the buffer layer 92 is made of aluminum nitride (AlN). The purpose of providing the aluminum nitride (AlN) buffer layer 92 is to alleviate the dislocation between the sapphire substrate 91 and the group III nitride-based compound semiconductor layer 93. But even so, there is still no way to change the generation of the bad row to zero. From the point 900 where the row is generated, the row passes through the row 901 in the vertical direction, which also penetrates the buffer layer 92 and the group III nitride-based compound semiconductor layer 93. In this way, when various required group III nitride compound semiconductors are to be stacked on the upper layer of the group III nitride compound semiconductor layer 93 to form a semiconductor device, the transfer from the group III nitride compound semiconductor to the group III nitride compound semiconductor The differential row 902 on the surface of the layer 93 will pass through the differential row in the longitudinal direction of the semiconductor element. As such, in this conventional technology, when forming the group III nitride-based compound semiconductor layer, it is potentially impossible to prevent the problem of differential transmission.

In addition, in recent years, in order to prevent the penetration of the differential row, there has been development and adoption of horizontal growth technology. This is to form a mask composed of silicon oxide, tungsten, etc. with partially striped windows formed on the sapphire substrate or the III-nitride compound semiconductor layer, and then use the semiconductor of the window as the core. Grow horizontally. However, because of the transmission and penetration difference row above the window, in order to also prevent this phenomenon, it is convenient to use the horizontal growth to cover the top of the screen, and even make the original screen disappear, and the upper part of the window forms a stripe. The second screen needs to grow horizontally again. That is, it is necessary to switch to perform three group III nitride compound semiconductor steps with completely different manufacturing steps, and a mask forming step with completely different secondary manufacturing steps.

The present invention is to solve the above-mentioned problems, and its object is to produce a group III nitride-based compound semiconductor that has suppressed the generation of through-differences under the switching of the suppression step.

[Means to solve the problem]

In order to solve the above-mentioned problems, the invention described in item 1 of the scope of patent application uses lateral epitaxial growth to form a group III nitride-based compound semiconductor layer that has suppressed penetration of the third-party nitride-based compound semiconductor layer. The manufacturing method; characterized in that it comprises: forming a first mask of island-shaped first masks such as stripes or lattices of group III nitride-based compound semiconductors without epitaxial growth on the layer constituting the base Formation step; a step of securing a growth space for the compound used to form a growth space, and the growth space is to ensure a space for epitaxial growth of group III nitride-based compound semiconductors; group III nitride-based compound semiconductors are not epitaxial The second mask forming step of the growth; the step of removing the compound formed by the growth space securing step; and the epitaxial growth step of passing the group III nitride compound semiconductor through the growth space and growing vertically and horizontally epitaxially; Wherein, the first mask and the second mask form the masks in such a manner that the layers constituting the base cover substantially the entire surface from above the vertical. In the present invention, the "layer constituting the base" refers to all the following cases. That is, (1) a single or composite substrate regardless of composition; (2) a so-called buffer layer regardless of composition is formed on the substrate; (3) a so-called buffer layer is formed or not formed on the substrate, and then the group III nitrogen is formed Compound semiconductor layer. In addition, the so-called island state does not necessarily mean separate regions. For example, a striped or grid-shaped first mask may be formed on the entire surface of the wafer, and the first mask may be continuously formed in a very wide range.

Furthermore, the invention described in item 2 of the scope of patent application is that the second mask forming step includes: partially removing the compound formed by the growth space securing step to make the first mask or the layer part constituting the substrate The step of exposing; connecting to the exposed surface of the first mask or the layer constituting the substrate, and forming the second mask constituent material on the entire surface of the compound; and partially removing the second mask constituent material, and The step of exposing the compound formed in the growth space in the area with the first mask in the lower layer.

Furthermore, the invention described in item 3 of the scope of patent application is the uppermost layer of the layer constituting the base and belongs to the group III nitride compound semiconductor with the same composition as the group III nitride compound semiconductor. In addition, the same composition referred to here refers to those with negligible doping degree difference (mole ratio is less than 1% difference). Furthermore, the case where the layer constituting the base is a single group III nitride-based compound semiconductor substrate is of course also covered by the invention described in item 3 of the scope of patent application.

Furthermore, the invention described in item 4 of the scope of patent application is a group III nitride-based compound semiconductor device formed by using any of the group III described in items 1 to 3 of the scope of patent application. The method for manufacturing a nitride-based compound semiconductor is on the upper layer of the group III nitride-based compound semiconductor layer.

Furthermore, the invention described in item 5 of the scope of patent application is a group III nitride-based compound semiconductor light-emitting device, which uses the group III described in any one of items 1 to 3 in the scope of patent application. The method for manufacturing a nitride-based compound semiconductor is obtained by laminating different group-III nitride-based compound semiconductor layers on the upper layer of the prepared group-III nitride-based compound semiconductor layer.

Furthermore, the invention described in item 6 of the scope of patent application is a method for manufacturing group III nitride-based compound semiconductor substrates, except for the group III described in any one of items 1 to 3 in the scope of patent application. In addition to the manufacturing method of nitride-based compound semiconductors, there is also the use of removing all the parts below the second mask to obtain a group III nitride-based compound semiconductor substrate.

[Function and Invention Effect]

Please refer to FIG. 1 for an overview of the manufacturing method of the group III nitride compound semiconductor of the present invention. Furthermore, in FIG. 1, although the diagram with the substrate 1 and the buffer layer 2 is shown to facilitate understanding, the present invention directly grows the epitaxial crystal, which produces a through-difference row in the longitudinal direction of the combined structure. The base layer of the III-nitride-based compound semiconductor layer and the III-nitride-based compound semiconductor that should be epitaxially grown. Through the unique technology of the present invention, the III-nitride with a region that reduces the vertical penetration difference is obtained. Compound semiconductor layer. The substrate 1 and the buffer layer 2 are not essential requirements in the present invention. Hereinafter, as shown in Fig. 1(a), the first group III nitride-based compound having a penetrating difference in the longitudinal direction (the vertical direction of the substrate surface) formed on the surface of the substrate 1 via the buffer layer 2 is used The semiconductor layer 31 uses an example of the present invention to illustrate the important part of the effect of the present invention. In this case, only the first group III nitride compound semiconductor layer 31 may be considered for the layer constituting the base, or the substrate 1, the buffer layer 2 and the first group III nitride compound semiconductor layer 31 may be combined.

On the surface of the substrate 1, the first group III nitride-based compound semiconductor layer 31 having a penetrating difference in the longitudinal direction (the vertical direction of the substrate surface) formed by the buffer layer 2 is formed on the entire surface of the first mask material 41 (Figure 1(a)). Next, the first mask material 41 is formed into island shapes such as dots, stripes, or grids, and is used as the first mask 41m. At this time, the surface of the first group III nitride compound semiconductor layer 31 is scattered and exposed (FIG. 1(b), the above is the first mask forming step).

Next, a growth space securing material 5 is formed in such a way that the island-shaped first mask 41m and the dispersed first group III nitride compound semiconductor layer 31 are exposed to the surface (FIG. 1(c)). Then, in order to form a growth space for epitaxial growth of the second group III nitride-based compound semiconductor, the growth space securing material 5 is subjected to processing and forming such as etching treatment. Part of the formed growth space securing material 5s contacts the surface of the first group III nitride-based compound semiconductor layer 31 (FIG. 1(d), growth space securing step).

Next, the second mask material 42 is formed on the entire surface (FIG. 1(e)). The second mask material 42 is formed to cover the formed growth space securing material 5s. Then, the second mask material 42 is processed into a desired shape by etching treatment or the like. At this time, using the first mask 41m and the second mask 42m, the first group III nitride-based compound semiconductor layer is formed to cover substantially the entire surface from vertically above (FIG. 1(f)). For example, if the first screen 41m is in the shape of a dotted island, the second screen 42m is in the shape of a grid or mesh. If the first screen 41m is striped, the second screen 42m is formed without the first screen. A striped shape in the 41m area of the mask. The second mask 42m is arranged at a position higher than the first mask 41m, and must constitute a "foot" part. Including the parts that make up the "foot", they are collectively referred to as the second mask 42m.

Secondly, the material for securing the growth space after forming is removed for 5s by using, for example, a wet etching process. In this case, the first group III nitride-based compound semiconductor layer 31 exposes the portion adjacent to the formed growth space securing material 5s, and is surrounded by the first mask 41m and the upper second mask 42m. The curved growth space. The so-called "bend" means that although the first group III nitride compound semiconductor layer is substantially covered from above vertically with the first mask 41m and the second mask 42m, the first group III nitride compound semiconductor layer The surface of the semiconductor layer 31 is partially exposed below the second mask 42m, and above the first mask 41m has the meaning of a region capable of vertical epitaxial growth. That is, although the vertical epitaxial growth from the surface of the first group III nitride compound semiconductor layer 31 may be in a portion where the first mask 41m is not formed, it is prevented by the position of the second mask 42m. Then, below the second mask 42m, lateral epitaxial growth may be above the first mask 41m, and above the first mask 41m in the area without the second mask 42m, vertical epitaxial growth may be possible. Furthermore, above the second mask 42m, in the area without the second mask 42m, the vertical epitaxial growth from below may be lateral epitaxial growth (Figure 1(g)).

In this case, if the second group III nitride compound semiconductor layer 32 is epitaxially grown in the vertical and lateral directions, it will come from the surface of the first group III nitride compound semiconductor layer 31 where the first mask 41m is not formed. The penetration differential row transmitted by the longitudinal epitaxial growth will be blocked at the position of the second mask 42m. By the lateral epitaxial growth without the through row, the first mask 41m is conveniently covered with the second group III nitride-based compound semiconductor layer 32, and the portion where the second mask 42m is not formed above Vertical epitaxial growth is possible. In this case, when the vertical epitaxial growth of the second group III nitride compound semiconductor layer 32 is higher than the second mask 42m, the horizontal epitaxial growth starts to make the second mask 42m The entire upper surface is covered with a second group III nitride-based compound semiconductor layer 32 (FIG. 1(h)). At this time, a very small part of the obliquely transmitted through difference is excluded, because all of them use two masks and are not transmitted to the upper half of G shown in Figure 1(h), so there are very few defects and excellent results can be obtained. The group III nitride-based compound semiconductor layer G.

In this case, in the present invention, a special Group III nitride-based compound semiconductor growth device is used in only two stages to form the two masks necessary for this period. Therefore, the step of suppressing the group III nitride compound semiconductor produced by the penetration difference can be switched, and it can be obtained by suppressing it to two times (the first item in the scope of patent application).

When forming the second mask, as shown in FIG. 1(d), the compound (growth space securing material) 5 formed through the growth space securing step is partially removed, and the part of the first mask 41m or the first mask 41m is exposed. After the group III nitride compound semiconductor layer 31, if the second mask material 42 is formed on the entire surface, the "legs" that constitute the second mask 42m can be easily secured (the second in the scope of patent application) .

If the first group III nitride compound semiconductor and the second group III nitride compound semiconductor are of the same composition, because the lattice constant is consistent with other physical quantities, the epitaxial growth between the double layers can be rapid ( Item 3 of the scope of patent application).

By forming the device on the upper layer of the group III nitride compound semiconductor layer obtained according to the above steps, a semiconductor device with a layer with fewer defects and a larger mobility can be formed (the fourth item in the scope of patent application).

By forming a light-emitting element on the upper layer of the group III nitride compound semiconductor layer obtained by the above steps, a light-emitting element with improved element life or LD threshold voltage can be obtained (the 5th item of the scope of patent application).

Furthermore, by using the above steps to obtain the second mask of the group III nitride compound semiconductor layer, only the upper layer is separated from the other layers, and the crystallinity that can significantly suppress the crystal defects such as differential row can be obtained. Group III nitride compound semiconductor (the 6th item in the scope of patent application). In addition, the so-called "substantially completely removed" refers to the ease of manufacture, and even if the residual part penetrates the poorly arranged part, it is also included in the present invention.

[Invention implementation form]

FIG. 1 shows a schematic diagram of an example of the embodiment of the manufacturing method of the group III nitride-based compound semiconductor of the present invention. The buffer layer 2 and the first group III nitride compound semiconductor layer 31 are formed on the substrate 1, and then the first mask material 41 is formed on the entire surface (FIG. 1(a)). Next, the first mask material 41 is formed into island shapes such as dots, stripes, or grids, and is used as the first mask 41m. At this time, the surface of the first group III nitride compound semiconductor layer 31 will be scattered and exposed (FIG. 1(b)). Next, a growth space securing material 5 is formed in such a way that the island-shaped first mask 41m and the dispersed first group III nitride compound semiconductor layer 31 are exposed to the surface (FIG. 1(c)). Then, in order to form a growth space for epitaxial growth of the second group III nitride-based compound semiconductor, the growth space securing material 5 is subjected to processing and forming such as etching treatment. The formed growth space ensures that a part of the material 5s contacts the surface of the first group III nitride-based compound semiconductor layer 31 (FIG. 1(d)).

Next, the second mask material 42 is formed on the entire surface (FIG. 1(e)). Then, the second mask material 42 is processed into a desired shape by etching treatment or the like. At this time, using the first mask 41m and the second mask 42m, the first group III nitride-based compound semiconductor layer is formed to cover substantially the entire surface from vertically above (FIG. 1(f)). In order to arrange the second mask 42m at a position higher than the first mask 41m, a portion constituting the "foot" is provided. Secondly, the material for securing the growth space after forming is removed for 5s by using, for example, a wet etching process. In this case, the first group III nitride-based compound semiconductor layer 31 exposes the portion adjacent to the formed growth space securing material 5s, and is surrounded by the first mask 41m and the upper second mask 42m. The curved growth space (Figure 1 (g)). In this way, the second group III nitride compound semiconductor layer 32 is epitaxially grown vertically and horizontally. First, on the surface of the first group III nitride compound semiconductor layer 31 where the first mask 41m has not been formed, vertical epitaxial growth occurs. Secondly, it uses lateral epitaxial growth to cover 41m above the first mask. Then, the vertical epitaxial growth is performed in a manner that penetrates the portion where the second mask 42m is not formed. Using lateral epitaxial growth at a position higher than 42 m of the second mask, the entire upper surface of the second mask 42 m is covered with the second group III nitride-based compound semiconductor layer 32.

The above-mentioned embodiments of the invention can be selected from the following.

When the group III nitride compound semiconductor is sequentially laminated on the substrate, the substrate can be made of sapphire, silicon (Si), silicon nitride (SiC), spinel (MgAl ₂ O ₄ ), NdGaO ₃ , LiGaO ₂ , ZnO, MgO or other inorganic crystalline substrates; group III-V nitride compound semiconductors such as gallium phosphide or gallium arsenide, or gallium nitride (GaN), or other group III nitride compound semiconductors, etc.

The method for forming group III nitride-based compound semiconductors is preferably metal-organic vapor growth method (MOCVD or MOVPE), molecular beam vapor growth method (MBE), halide vapor growth method (Halide VPE) , Liquid phase growth method (LPE), etc., and different growth methods can also be adopted for each layer.

For example, when a group III nitride compound semiconductor is layered on a sapphire substrate, in order to form a good crystallinity, it is preferable to form a buffer layer that should correct the lattice mismatch between the sapphire substrate and the sapphire substrate. Even if other substrates are used, it is best to provide a buffer layer. The so-called buffer layer adopts low-temperature group III nitride compound semiconductor Al _x Ga _y In _1-xy N(0x1, 0y1, 0x+y1), especially Al _x Ga _1-x N(0X1) is better. The buffer layer can be a single layer or multiple layers with different compositions. The formation method of the buffer layer can be formed at a low temperature of 380~420°C, and on the contrary, it can be formed by the MOCVD method within the range of 1000~1180°C. In addition, using a DC magnetron sputtering device, high-purity metal aluminum and nitrogen can be used as raw materials, and a reactive sputtering method is used to form a buffer layer composed of AlN. Similarly, the general formula Al can be formed _x Ga _y In _1-xy N (0x1, 0y1, 0x+y1, any composition ratio) buffer layer. In addition, evaporation method, ion plating method, laser burning method, ECR method, etc. can also be used. The buffer layer using the physical vapor deposition method is best implemented at 200-600°C, especially at 300-500°C, and more preferably at 350-450°C. When physical vapor deposition methods such as sputtering methods are used, the thickness of the buffer layer is preferably 100~3000 <img file="TW548720B_D0001.tif" /> , Especially 100~400 <img file="TW548720B_D0002.tif" /> Better, 100~300 <img file="TW548720B_D0003.tif" /> For better. The so-called "multi-layer" refers to a method of forming layers with the same composition at a forming temperature of, for example, 600°C or lower and 1000°C or higher. And the layers with the same composition, such as cross formation made of Al _x Ga _1-x A layer composed of N (0x1) and a GaN layer. Of course, these can also be combined, or more than three types of group III nitride compound semiconductor Al _x Ga _y In _1-xy N (0x1, 0y1, 0x+y1) multilayer. Generally, the buffer layer is amorphous, and the intermediate layer is single crystalline. It is also possible to set the buffer layer and the intermediate layer as one cycle to form a plurality of cycles, and any cycle can be repeated. The more repetitions, the better the crystallinity.

The buffer layer and the upper group III nitride compound semiconductor system can replace part of the group III element composition with boron (B) and thallium (Tl), or replace part of the nitrogen (N) composition with phosphorus (P), Stele (As), antimony (Sb), and bismuth (Bi) are all practically applicable to the present invention. In addition, these elements are doped to such an extent that they cannot be displayed on the composition. For example, Al of group III nitride compound semiconductor without indium (In) and stele (As) in the composition _x Ga _1-x In N (0x1), doped indium (In) with larger atomic diameter than aluminum (Al) and gallium (Ga), or doped with stele (As) with larger atomic diameter than nitrogen (N) ), and the expansion strain of the crystal with the removal of nitrogen atoms is complemented by the compression strain to form a better crystallinity. In this case, because acceptor impurities can easily enter the position of group III atoms, it can also be regarded as growth (As-Grown) to obtain P-type crystals. By using this to improve the crystallinity, and in conjunction with the invention of the present case, the penetration difference can be reduced to about 100 to one-thousandths. When the buffer layer and the group III nitride compound semiconductor layer are used to form the base layer with more than two cycles, each group III nitride compound semiconductor layer is preferably doped with larger atoms than the main constituent element The element of the trail. In addition, when constructing a light-emitting element, it is preferable to use the binary system or the ternary system of the original group III nitride-based compound semiconductor.

When forming an n-type group III nitride-based compound semiconductor layer, n-type impurities of Si, Ge, se, Te, C, and other group IV elements or group VI elements may be added. In addition, p-type impurities such as Zn, Mg, Be, Ca, Sr, Ba and other Group II elements or Group IV elements may be added. A plurality of these impurities can also be doped in the same layer, or n-type impurities and p-type impurities can be doped in the same layer.

Although lateral epitaxial growth is best to make the growth surface perpendicular to the substrate, it can also be grown on an inclined surface of the substrate. The lateral epitaxial growth is best on the {11-20} plane of the group III nitride compound semiconductor.

When the direction of the crystal axis of the group III nitride compound semiconductor layer laminated on the substrate can be predicted, it should be formed perpendicular to the group III nitride compound semiconductor layer a plane ({1-20} plane) or m surface ({1-100} surface), using striped mask is quite useful. In addition, the above-mentioned mask may be arbitrarily designed in an island shape, a lattice shape, or the like. In addition to being perpendicular to the substrate surface, the lateral epitaxial growth surface can also form a growth surface with an oblique angle relative to the substrate surface. On the a-plane of the group III nitride compound semiconductor layer, the (11-20) plane is set as the lateral epitaxial growth surface, for example, the stripe length direction is perpendicular to the m-plane of the group III nitride compound semiconductor layer ( 1-100) noodles. For example, when the substrate is set to the a-plane or the c-plane of sapphire, since the m-plane of both sapphire and the a-plane of the group III nitride compound semiconductor layer formed thereon are usually the same, stripes are performed in accordance with this. When it is set to other island shapes such as dots, grids, etc., it is better to also set the surfaces forming the outline (side walls) as {11-20} planes.

Although the first and second masks can use polycrystalline semiconductors such as polycrystalline silicon and polycrystalline nitride semiconductors; silicon oxide (SiO _X ), silicon nitride (SiN _X ), titanium oxide (TiO _X ), zirconia (ZrO _X ) And other oxides; nitride, titanium (Ti), tungsten (W) and other high-melting point metals; or these multilayer films, but are restricted by the relationship with the compound that ensures the growth space. If the compound that secures the growth space is set to silicon oxide (SiO _X ), the first and second masks are other compounds, and the silicon oxide (SiO _X ), it is better not to be removed in the removal method. If the compound that secures the growth space is set to silicon oxide (SiO _X ), because the removal method can use wet etching using buffer HF, the silicon nitride (SiN) that has not been removed by wet etching _X ) Can be used as the first and second masks. In addition, these film forming methods can be vapor deposition, sputtering, CVD, or other vapor growth methods, or any other methods.

It is possible to form semiconductor elements such as FETs and light-emitting elements on the entire group III nitride compound semiconductor having the above-mentioned suppression of penetration of the differential row region, or centering on the suppressed penetration of the differential row region. In the case of a light-emitting element, the light-emitting layer may have a multi-quantum well structure (MQW), a single quantum well structure (SQW), a homogeneous structure, a heterostructure, a double heterostructure, and a pin junction, pn junction, etc. form.

The above-mentioned group III nitride compound semiconductor having the above-mentioned suppressed penetration difference row region is provided with a substrate 1, a buffer layer 2, a first group III nitride compound semiconductor layer 31, and a first and a second cover The parts of the curtain 41m and 42m (part R in Fig. 1(h)) are removed to form a group III nitride-based compound semiconductor substrate (part G in Fig. 1(h)). A group III nitride compound semiconductor element can be formed thereon, or it can be used as a substrate for forming a larger group III nitride compound semiconductor crystal. The removal method can be chemical mechanical polishing or any other method.

Hereinafter, specific embodiments of the invention will be described. Although the light-emitting elements are mentioned in the examples, the present invention is not limited to the following examples, but discloses a method of manufacturing a group III nitride-based compound semiconductor that can be applied to any element.

The group III nitride-based compound semiconductor of the present invention is produced by vapor-phase growth according to the organometallic compound vapor-phase growth method (hereinafter referred to as "MOVPE"). The carrier gas used is like ammonia (NH ₃ ), carrier gas (H ₂ Or N ₂ ), trimethylgallium (Ga(CH ₃ ) ₃ , Hereinafter referred to as "TMG"), trimethylaluminum (Al(CH ₃ ) ₃ , Hereinafter referred to as "TMA"), trimethyl indium (In(CH ₃ ) ₃ , Hereinafter referred to as "TMI"), and cyclopentadiene magnesium (Mg(C ₅ H ₅ ) ₂ , Hereinafter referred to as "Cp ₂ Mg").

The first embodiment

In this embodiment, the buffer layer 2 and the group III nitride compound semiconductor layer 31 as shown in FIG. 1 are used. Set the a face that has been cleaned by organic cleaning and heat treatment as the main face. On the single-crystal sapphire substrate 1, the temperature is lowered to 400°C, and the H ₂ According to 10L/min, NH ₃ Supply 5L/min and TMA at 20μmOl/min for 3 minutes to form a buffer layer 2 made of AlN with a thickness of about 40nm. Secondly, the temperature of the sapphire substrate 1 is maintained at 1000°C, and the H ₂ According to 20L/min, NH ₃ It is introduced at 10 L/min and TMG at 300 μmol/min to form a GaN layer 31 with a film thickness of about 1 μm. Then, SiN is formed on the whole surface by sputtering treatment _X , And a first mask material 41 with a thickness of 100 nm is formed (Figure 1(a)). It was patterned into stripes with a width of 5 μm and an interval of 5 μm by photolithography (Figure 1(b)). At this time, the longitudinal direction of the stripes is set to the <1-100> direction of the GaN layer 31. SiN _X The constituted first mask 41m.

Secondly, the EB method is formed on the entire surface with a thickness of 500nm made of SiO ₂ The formed growth space ensures material 5 (Figure 1(c)). Then, it will be made of SiO ₂ The formed growth space securing material 5 is processed by photolithography, and the central part of the 5 μm interval where the first mask 41 m is not formed is removed with a width of 1 μm. In this way, an exposed surface of the GaN layer 31 with a width of 1 μm appears on the central part of the 5 μm interval where the first mask 41m is not formed (FIG. 1(d)).

Then, using sputtering treatment, SiN is formed on the entire surface _X , And a second mask material 42 with a thickness of 100 nm is formed (FIG. 1(e)). At this time, a "foot" is formed, and the second mask material 42 is connected to the exposed surface of the GaN layer 31 with a width of 1 μm. Then, using a photolithography process, the second mask material 42 is patterned into stripes with an interval of 5 μm. At this time, the longitudinal direction of the stripes is set to the <1-100> direction of the GaN layer 31, and the second mask material 42 is removed above the formed first mask 41m. That is, above the formed first mask 41m, there is the presence of SiO ₂ The formed growth space ensures the material 5s, but there is no second mask 42m, and above the first mask 41m, there is formed SiO ₂ The formed growth space ensures the state of the material 5s and the second mask 42m. 41m in the first mask with SiO ₂ The formed growth space ensuring material 5s above the GaN layer 31 where none of the materials 5s exist is in a state with a second mask 42m. In this way, it is formed with SiN _x The second mask of the "foot" is 42m (figure 1(f)).

Secondly, using buffer HF, it will be made of SiO ₂ The formed growth space ensures that the material 5s is removed by wet etching. In this way, above the GaN layer 31, an "epitaxial growth space" surrounded by the first mask 41m and the second mask 42m appears.

Secondly, the temperature of the sapphire substrate 1 is maintained at 1150°C, and the H ₂ According to 20Lmin, NH ₃ It is introduced at 10 L/min and TMG at 5 μmol/min to make the GaN layer 32 undergo vertical and horizontal epitaxial growth. As a result, along with the "epitaxial growth space" surrounded by the first mask 41m and the second mask 42m above the buried GaN layer 31, a GaN layer 32 with very few penetration differences is also formed above the second mask 42m. Area G.

From Fig. 1 (g) to Fig. 1 (h), as shown in Fig. 2. On the GaN layer 31, the GaN layer 32 is epitaxially grown longitudinally from the portion where the first mask 41m and the second mask 42m are not formed. When the thickness exceeds the thickness of the first mask 41m, the GaN layer 32 starts to cover the first mask 41m in the lateral direction (the part shown by A in FIG. 2(a)).

In this case, since the second mask 42m is not formed above the first mask 41m, longitudinal growth occurs. Conversely, on the GaN layer 31, the portion where the first mask 41m is not formed, because the second mask 42m forms an eaves state on the upper side, so the growth stops. At this time, the through-difference row that is passed along with the longitudinal growth will stop because it is not passed in the horizontal direction.

Above the first mask 41m, the GaN layer 32 grows vertically in a way that penetrates the part where the second mask 42m is not formed. When the height exceeds the upper end of the second mask 42m, the GaN layer 32 starts to cover the second mask again in the horizontal direction. The second screen is 42m (the part shown by B in Figure 2(b)). For example, even if part of the penetrating row reaches above 41m of the first mask, the density of the penetrating row can be made smaller by using the horizontal growth again.

In this case, through vertical and horizontal growth, the upper part of the second mask 42m is completely covered with the GaN layer 32, and the vertical epitaxial growth continues. The GaN layer 32 above the second mask 42m has obviously been suppressed from penetrating the differential row.

Variations

In the above embodiment, although the first mask 41m and the second mask 42m do not overlap when viewed from above, it can also be shown in FIG. Let it be the first mask 41m, and let the upper side be the second mask 42m. In addition, in the above embodiment, although the "foot" of the second mask 42m is set as a striped GaN layer 31 with a width of 1 μm, the "foot" may be provided on the first mask 41m, or both can be designed "Column" shape. These are all formed by the growth space design of the GaN layer 32. It can also be designed according to the growth space of the GaN layer 32 and be a second mask 42m with any shape of "foot".

Second embodiment

On the wafer formed as in the first embodiment, a laser diode (LD) 100 as shown in FIG. 4 is formed as follows. Among them, when the GaN layer 32 is formed, silane (SiH ₄ ), the GaN layer 32 is regarded as a layer composed of n-type GaN doped with curved silicon (Si). In addition, in order to simplify the illustration, the sapphire substrate 1, the buffer layer 2, the GaN layer 31, and the GaN layer 32 with the height of the mask 41m and 42m are combined and described as a wafer 1000 (R in Figure 1(h)) Part), and the remaining GaN layer 32 is described as the GaN layer 103 (part G in FIG. 1(h)).

On a sapphire substrate, a buffer layer made of AlN, a GaN layer 31, and an n-type GaN layer 32 with a height of 41m and 42m, the wafer layer 1000 and the n-type GaN layer 103 are formed of silicon ( Si) doped Al _0.08 Ga _0.92 N-cladding layer 104 composed of N, n-guiding layer 105 composed of silicon (Si)-doped GaN, light-emitting layer 106 of MQW structure, p-guiding layer composed of magnesium (Mg)-doped GaN 107. Al doped with magnesium (Mg) _0.08 Ga _0.92 The p-cladding layer 108 made of N and the p-contact layer 109 made of GaN doped with magnesium (Mg). Next, on the p-contact layer 109, the electrode 110A made of gold (Au) is partially etched until the n-type GaN layer 103 is exposed to form the electrode 110B made of aluminum (Al). The laser diode (LD) formed in this way will significantly improve the life of the device and the luminous efficiency.

The third embodiment

On the wafer formed as in the second embodiment, on the wafer formed as in the first embodiment, a light emitting diode (LED) 200 as shown in FIG. 5 is formed as follows. At the same time, in order to simplify the illustration, the sapphire substrate 1, the buffer layer 2, the GaN layer 31, and the GaN layer 32 with the height of the mask 41m and 42m are combined and described as the wafer 2000 (R in Figure 1(h)) Part), and the remaining GaN layer 32 is described as the GaN layer 203 (part G in FIG. 1(h)).

On the wafer 2000 and the n-type GaN layer 203 composed of a sapphire substrate, a buffer layer composed of AlN, a GaN layer 31, and a GaN layer 32 with a height of 41m and 42m, and the n-type GaN layer 203, silicon (Si) is formed Doped Al _0.08 Ga _0.92 N cladding layer 204 composed of N, light-emitting layer 205, Al doped with magnesium (Mg) _0.08 Ga _0.92 The p cladding layer 206 made of N and the p contact layer 207 made of GaN doped with magnesium (Mg). Next, on the p-contact layer 207, the electrode 208A made of gold (Au) is partially etched until the n-type GaN layer 203 is exposed to form an electrode 208B made of aluminum (Al). The light emitting diode (LED) formed in this way will significantly improve the life of the device and the luminous efficiency.

Symbol description of main components

1. 91. . . Substrate

2. 92. . . buffer layer

5. . . Growth space to ensure materials

5s. . . The growth space after forming ensures the material

31, 32, 103, 203. . . n-GaN layer

31. . . The first group III nitride compound semiconductor (layer)

32. . . The second group III nitride-based compound semiconductor (layer)

41. . . First screen material

41m. . . First curtain

42. . . Second screen material

42m. . . Second curtain

104, 204. . . n-AlGaN layer (covering layer)

105, 107. . . n-GaN guiding layer

106, 205. . . Luminescent layer

109, 207. . . p contact layer

108, 206. . . p cover layer

900. . . Point of difference

902. . . Bad row

93. . . Group III nitride compound semiconductor (layer)

100. . . Laser diode (LD)

110A, 208A. . . p electrode

110B, 208B. . . n electrode

200. . . Light Emitting Diode (LED)

G. . . Group III nitride compound semiconductor (layer)

901. . . Run through

1000, 2000. . . Wafer

Schematic description

1(a)~(h) are cross-sectional views of the manufacturing steps of the group III nitride compound semiconductor according to the first embodiment of the present invention.

2(a) and (b) are detailed cross-sectional views of the epitaxial growth part in the manufacturing steps of the group III nitride compound semiconductor according to the first embodiment of the present invention.

Figure 3 is a cross-sectional view of a modified example.

4 is a cross-sectional view of the structure of a group III nitride-based compound semiconductor light-emitting device according to a second embodiment of the present invention.

5 is a cross-sectional view of the structure of a group III nitride-based compound semiconductor light-emitting device according to a third embodiment of the present invention.

Fig. 6 is a cross-sectional view of a through-difference row transmitting a group III nitride-based compound semiconductor.