CMOS semiconductor device and apparatus using the same

CMOS semiconductor device and equipment using the device

Figures 1A and 1B are diagrams showing the structure and characteristics of thin film transistors;

Figures 2A to 2E are diagrams showing the steps of manufacturing thin film transistors;

Figures 3A to 3D are diagrams showing the steps of manufacturing thin film transistors;

Figure 4 is a graph showing the relationship between the change of diffusion coefficient and temperature;

Figures 5A and 5B series graphics, shown in Si/SiO ₂ The distribution of dopants at the interface;

Figure 6 is a graph showing the characteristics of thin film transistors;

Figure 7 series graphics, shown in Si/SiO ₂ The distribution of dopants at the interface;

Figures 8A and 8B are other figures shown in Si/SiO ₂ The distribution of dopants at the interface;

Figure 9 is a cross-sectional view showing the silicon gate TFT structure;

Figure 10 is a graph showing the circuit structure of SRAM;

11A to 11H show the structure of the active layer in CMOS;

12A to 12F show the structure of the active layer in another CMOS;

Figure 13 shows the structure of an active matrix display device;

14A to 14C show the structure of the shift register circuit;

15A to 15C show other steps of manufacturing thin film transistors;

Figure 16 is other graphics showing the characteristics of thin film transistors;

Figure 17 is an explanatory diagram showing the energy band structure used to obtain Eg;

Figure 18 is a graph showing the frequency characteristics of the CMOS circuit;

Figure 19 is a graph showing the change of transmitted light with changing wavelength;

And FIGS. 20A to 20E show the application fields of semiconductor devices.

Background of the invention

1. Field of the Invention The present invention relates to semiconductor devices, which use crystalline semiconductors (including single crystals and non-single crystals) formed on insulating substrates such as glass substrates, quartz substrates, silicon wafers, and the like, and to manufacturing methods thereof. More particularly, it is related to the case where a CMOS circuit is constructed by using complementary combination of n-channel type and p-channel type semiconductor devices.

2. Know-how. Recently, the technology of manufacturing thin-film transistors on inexpensive glass substrates has progressed rapidly. This rapid progress is due to the growing demand for active matrix display devices. Active matrix (addressed) type display devices include pixels arranged in a matrix, and TFTs (pixel TFTs) are provided to each pixel to individually control data signals by using the switching function of each pixel TFT.

The gate signals and data signals sent to the pixel TFTs arranged in such a matrix configuration are controlled by peripheral circuits formed on the same substrate. Generally, this control circuit is constructed with the main technology for manufacturing CMOS circuits, that is, a circuit that combines n-channel TFT and p-channel TFT in a complementary configuration.

In addition, when constructing the above-mentioned peripheral driving circuit, a TFT circuit capable of high-speed operation is required. Therefore, the crystalline silicon film is mainly used for the active layer. Since the carriers move faster in the crystalline silicon film than in the amorphous silicon film, the crystalline silicon film can be used to realize a TFT with better electrical characteristics.

In this case, FIG. 1A is a cross-sectional view of the COM circuit composed of top-gate TFTs. Referring to FIG. 1A, the base film 102 will be formed on the surface of the glass or quartz substrate 101. The structure also includes a crystalline silicon film for the active layer 103 of the N-channel TFT, and another crystalline silicon film for the active layer 104 of the P-channel TFT.

The above-mentioned active layer will be covered by the gate insulating film 105, and the gate electrodes 106 and 107 will be further covered by the intermediate layer film 108 which electrically insulates the gate electrodes from the lead wires.

In addition, the source electrodes 109 and 110 and the drain electrode 111 electrically connected to the active layers 103 and 104 through contact holes are provided on the interlayer insulating film 108. Since this case refers to a CMOS circuit, the drain electrode 111 is shared by the n-channel TFT and the p-channel TFT. Finally, the source and drain electrodes 109 to 111 are covered by the protective film 112 to provide a CMOS circuit as shown in FIG. 1A.

The structure shown in FIG. 1A is the simplest composition of a CMOS circuit and is used as an inverter to reverse the polarity of the signal. By combining this simple COMS circuit, NAND circuits, NOR circuits, and more complex logic circuits can be realized. In this way, different types of circuits are designed.

However, as disclosed in Japanese Laid-open Patent Application No. 4-206971 and Japanese Laid-Open Patent Application No. 4-286339, CMOS circuits manufactured using crystalline silicon films suffer from the electrical characteristics of n-channel TFTs tending to be suppressed, and p-channel TFT therefore tends to be biased towards the strengthening direction.

The electrical characteristics (Id-Vg) of the TFT in the above situation are shown in FIG. 1B. In FIG. 1B, the horizontal axis (Vg) shows the gate voltage, and the vertical axis (Id) shows the drain current. The curve indicated by 113 shows the Id-Vg characteristic of the n-channel TFT, and the curve indicated by 114 shows the Id-Vg characteristic of the p-channel TFT.

The fact that the Id-Vg characteristic 113 of the n-channel TFT is biased in the suppression direction and the Id-Vg characteristic 114 of the p-channel TFT is biased in the strengthening direction is shown in FIG. 1B, and they are both shifted to the negative side with respect to the gate voltage Vg.

Therefore, it can be seen that the characteristics of n-channel and p-channel 113 and 114 are asymmetrical with respect to the gate voltage of 0V. The absolute value of the threshold voltage of the n-channel TFT and the absolute value of the threshold voltage of the p-channel TFT will become each other. The difference is huge.

However, as disclosed in Japanese Patent Application No. 4-206971, the output voltage deviation caused by the difference between the threshold voltage (driving voltage) of the n-channel TFT and the threshold voltage of the p-channel TFT causes the operating speed to decrease or The cause of CMOS circuit failure.

In order to overcome the above-mentioned problems, the above reference discloses a method of controlling the threshold voltage by adding impurity elements to apply a single conductivity to the channel region of the TFT.

However, in the above technique (hereinafter referred to as "channel doping"), it is found that the control of the addition amount is difficult to reduce to the tracking amount. According to the inventors experiment, it is found that about 1×10 ¹⁸ /cm ³ It is found that the critical value has not changed under the addition amount, but when this value is exceeded, a small change in the concentration is found to cause the critical value to suddenly change.

For example, if the threshold voltage deviation to be controlled is 1V or lower, an offset of a few tenths of a volt can be obtained with a relatively small amount of addition.

Therefore, in order to control the critical value with high accuracy, the impurity element concentration must be accurately controlled. However, the fine control of impurity elements is technically quite difficult. For example, according to the present inventors experimental experience, it is about 1×10 ¹⁸ cm ³ No change in the critical value was found under the addition amount, but when this value is exceeded, a small change in the concentration will cause the critical value to suddenly change.

Summary of the invention

The invention disclosed in the specification was completed in consideration of the above-mentioned problems. Therefore, the object of the present invention is to provide a technique for finely controlling the threshold voltage by precisely controlling the concentration of added impurity elements.

According to the present invention, a semiconductor device with a CMOS structure is characterized by comprising: an n-channel semiconductor device; a p-channel semiconductor device, which is complementarily combined with the n-channel semiconductor device to form a CMOS structure; and a substrate with an insulating surface on the insulating surface Forming the n-channel semiconductor device and the p-channel semiconductor device; wherein the p-channel semiconductor device has an active layer, and only impurity elements that cause p-type conductivity are deliberately added to a partial area of the active layer including at least a channel formation region; Wherein the concentration of the impurity element is distributed in depth toward the main surface of the active layer near the main surface of the active layer, continuously decreasing; and the impurity element maintained in the vicinity of the main surface of the active layer is used To control the threshold voltage.

In the present invention, by absorbing impurity elements (represented by boron (B) ions) from the active layer into the thermal oxide film (gate insulating film), the surface of the active layer (the inversion layer will be formed on it) is reduced. The concentration of impurity ions used to create p-type conductivity in the surface (represented by boron (B) ions).

That is, in the case of using a thermal oxide film as the gate insulating film, the concentration is 1×10 ¹⁷ To 1×10 ^2O /cm ³ Used B ion.

When an amorphous silicon film is crystallized to form a crystalline silicon film, the use of a catalyst element (metal element) that accelerates crystallization will result in a concentration of 5×10 ¹⁸ /cm ³ Or lower crystalline silicon film of metallic elements. This value is used when thermal oxidation is performed in an atmosphere containing halogen. In this case, the gate insulating film will also absorb metals and halogens. In particular, the 1×10 ¹⁶ To ×10 ²⁰ /cm ³ The concentration of halogen is incorporated into the gate insulating film.

The aforementioned metal element is selected from the group consisting of nickel (Ni), cobalt (Co), platinum (Pt), copper (cu), and iron (Fe), but is represented by Ni. The thermal oxidation treatment is performed at a relatively high temperature in the range of 700 to 1,100°C, and regarding halogens, chlorine (Cl) and fluorine (F) are usually used as halogens. When performing thermal oxidation treatment, the halogen is introduced into the treatment atmosphere in the form of a gas containing halogen as its component; especially HCl and NF are used ₃ , ClF ₃ gas.

According to another aspect of the present invention, a semiconductor device with a CMOS structure is characterized by comprising: an n-channel semiconductor device; a p-channel semiconductor device that is combined with the n-channel semiconductor device in a complementary manner to form the CMOS structure; and a substrate , Having an insulating surface, the n-channel semiconductor device and the p-channel semiconductor device will be formed on the insulating surface; wherein the p-channel semiconductor device has an active layer, and impurity elements that produce p-type conductivity are deliberately added to include at least the channel formation Region of the active layer; wherein the n-channel semiconductor device has an active layer, and an impurity element that produces n-type conductivity is deliberately added to the region of the active layer including at least the edge portion; wherein the impurity element The concentration distribution is continuously reduced in depth toward the main surface of the active layer near the main surface of the active layer; and the impurity elements remaining in the vicinity of the main surface of the active layer are used to control Threshold voltage.

More particularly, it is characterized in that in the region containing at least the channel region in the active layer of the above-mentioned P-channel semiconductor device, the edge portion is not included in the channel region at least.

According to yet another aspect of the present invention, a method of manufacturing a semiconductor device is characterized by including the following steps: forming a first and a second active layer on an insulating substrate, both of which are formed of a crystalline silicon film; Conductive impurity element of the first active layer; and subjecting the first and second active layers to thermal oxidation treatment to apply the impurity element to the inside of the thermal oxide film formed on the surface of the first active layer; wherein the The concentration of impurity elements continuously decreases toward the main surface of the active layer in the vicinity of the main surface of the active layer; and the impurity element remaining in the vicinity of the main surface of the active layer is Used to control the threshold voltage.

The object of the present invention is to use the manufacturing method according to the present invention to manufacture a semiconductor device having a CMOS structure, the CMOS structure including an n-channel type semiconductor device and a p-channel type semiconductor device combined in a complementary manner. In the above structure, the first active layer corresponds to a p-channel semiconductor device, and the second active layer corresponds to an n-channel semiconductor device.

According to yet another aspect of the present invention, a method for manufacturing a CMOS type semiconductor device in which an n-channel semiconductor device and a p-channel semiconductor device are complementarily combined is characterized by including the following steps: forming a first active layer on a substrate with an insulating surface and A second active layer, the first active layer is formed of a crystalline silicon film containing impurity elements that cause p-type conductivity, the second active layer does not contain impurity elements; and the first and second active layers receive heat Oxidation treatment to form a thermal oxide film; wherein the first active layer forms the p-channel semiconductor device, and the second semiconductor device forms the n-channel semiconductor device; wherein the impurity element contained in the first active layer is Is drawn into the inside of the thermal oxide film through the thermal oxidation treatment; wherein the concentration of the impurity element in the main surface of the active layer is reduced; and the impurity remaining in the main surface of the active layer The element is used to control the threshold voltage.

According to yet another aspect of the present invention, a method for manufacturing a CMOS semiconductor device in which an n-channel semiconductor device and a p-channel semiconductor device are complementarily combined is characterized by including the following steps: forming a first active layer on a substrate with an insulating surface and The second active layer is formed of a crystalline silicon film containing impurity elements that cause p-type conductivity; and the first and second active layers are subjected to thermal oxidation treatment to form a thermal oxide film; wherein the first active layer is formed The p-channel semiconductor device and the second semiconductor device form the n-channel semiconductor device; wherein the impurity element contained in the first active layer is absorbed into the thermal oxide film through the thermal oxidation treatment; wherein The concentration of the impurity element in the main surface of the active layer is reduced; and the impurity element remaining in the main surface of the active layer is used to control the threshold voltage.

By implementing the invention constituted as described above, the traditional doping technique can work more precisely. This technology can be achieved by adding B ions to the p-channel semiconductor device, and the technology uses physical phenomena, that is, the concentration of B ions is very close to the Si/SiO2 interface (active layer side) of the channel region reduce.

Detailed description of preferred embodiments

The present invention will be described in detail with reference to preferred embodiments according to the present invention. However, it should be understood that the present invention is not interpreted as or limited to the following examples.

Embodiment 1 The present invention relates to the case of manufacturing a CMOS circuit according to the present invention. The CMOS circuit includes an n-channel type TFT and a p-type TFT combined in a complementary structure. 1A, the CMOS circuit manufactured in this embodiment is an inverter circuit with the simplest structure. In this circuit, B (boron) ions are added to the P-channel TFT to control the threshold voltage.

With reference to FIGS. 2A to 2E and FIGS. 3A to 3D, the circuit is described in detail below.

Referring to FIG. 2A, by deposition, a silicon oxide film is formed on the surface of the substrate 201 as the underlying film 202. Taking into account the subsequent thermal oxidation step, the substrate can be selected from a glass substrate, a quartz substrate, a silicon substrate (wafer), and the like. Therefore, a quartz substrate is selected as the substrate 201.

After that, a crystalline silicon film is formed to provide the active layer of the TFT. There are different methods to obtain a crystalline silicon film. However, in the present invention, a reduced pressure thermal CVD or plasma CVD is used to first deposit an amorphous silicon film with a thickness of 100 to 3,000 , preferably 100 to 1,000 Typically, it is 200 to 500. Then, the amorphous silicon film is crystallized by an annealing process using an excimer laser. Ultraviolet radiation using KrF, XeCl, etc. as the excitation gas can be used as an excimer laser.

Alternatively, the crystallization of the amorphous silicon film can be performed by a heating process or using a heating and laser annealing process. For example, an effective method includes applying a heat treatment at a temperature of about 600° C. to subject the amorphous silicon film to a solid-state growth process, followed by laser annealing to improve its crystallinity.

Once the crystalline silicon film 203 is obtained using the above technique, patterning is performed to form an island-shaped semiconductor layer 204 that will form the active layer of the n-channel TFT, and another island that will form the active layer of the p-channel TFT. Shape semiconductor layer 205.

Then, after removing the photoresist masks (not shown) used to pattern the island-shaped semiconductor layers 204 and 205 using the specified bar resolution, the photoresist mask 206 is formed again to cover what will become n-channel TFTs. The island-shaped semiconductor layer 204 of the active layer. Then, the impurity element B ions that cause p-type conductivity are only added to the island layer 205 (channel doping step).

In the present invention, B ions obtained by mass separation will be implanted into 1×10 ¹⁶ To 1×10 ¹⁹ cm ³ The concentration is planted. This method can choose to add B ions separately, so it is beneficial to control the addition amount (addition concentration). Plasma doping can be used as another method of ion implantation, but mass separation is not used. In the case of using this method, since B ions are added in groups with other atoms and molecules, it must be incorporated into the diffusion step.

Since the optimal addition amount of B ions changes depending on how the critical voltage (Vth) changes, the optimal addition amount (addition concentration) of B ions must be determined experimentally. In the construction according to the present invention, after the thermal oxidation step that occurs later, the SiSiO in the channel formation region is determined ₂ The concentration of B ions very close to the interface. Taking into account this fact, the concentration of addition must be controlled.

The present invention relates to the case where B ions are added by ion implantation. Alternatively, a gas containing B ions (for example, diborane) is used as a gas starting material to add B ions during film deposition of amorphous silicon. However, because the threshold voltage of the n-channel TFT will also shift to the positive side, care must be taken in this situation.

After the step of adding B ions is completed, a thermal oxidation process is performed on the island-shaped semiconductor layers 204 and 205. Regarding the thermal oxidation method, the conventional oxidation technology can be used, such as dry O ₂ Oxidation, wet O ₂ Oxidation, and high temperature oxidation.

Since the thermal oxide film can be obtained at a relatively low temperature of 500 to 700°C, gaseous NF is used ₃ The oxidation method as an atmosphere can be applied to glass substrates.

The purpose of the thermal oxidation step in this embodiment is to reduce (control) SiSiO by introducing B ions into the thermal oxide film ₂ B ion concentration at the interface. Figure 4 shows the variation of the diffusion coefficient of silicon and boron with temperature.

Referring to Figure 4, in silicon, the diffusion coefficient of boron and silicon are not very different (compared to the diffusion coefficient of metal elements). It can be seen from the figure that boron is not a substance that can diffuse easily. For example, if the thermal oxidation process is performed at 950°C, the diffusion coefficient of boron will be as low as about 4×10 ^-14 cm ² /s. This fact shows that in the case of redistribution of B ions occurring at the interface between the silicon film and the thermal oxide film, the concentration gradient can be clearly observed.

Figure 5 shows that after the thermal oxidation process, Si/SiO ₂ How does the B ion concentration distribution in the very close part of the interface change. For comparison, the P ion concentration distribution is also shown in Figure 5.

Referring to FIG. 5, it can be seen that when the oxide film is formed, the ions (B and P) doped in Si will be redistributed. This phenomenon is caused by ion doping in Si and SiO ₂ The difference in dissolution rate and diffusion rate in the world. The equilibrium separation coefficient m is defined as follows: m=[C]Si[C]SiO ₂ Among them [C]Si and [C]SiO ₂ It represents the addition of ions to Si and SiO respectively ₂ Solubility in.

SiSiO ₂ The separation of the added ions very close to the interface depends on the value of m. Generally speaking, the diffusion coefficient of the added ions in Si is large enough; when m is less than 1, the added ions will be introduced into SiO ₂ (Refer to Figure 5A). When m is greater than 1, SiO ₂ The world will reject the addition of ions. As a result, in Si/SiO ₂ The concentration of added ions will increase in the very close vicinity of the interface (refer to Figure 5B).

The m literature value of B ions is about 0.3, and the m literature value of P ions is about 10. Therefore, after the thermal oxidation process, the concentration distribution of B ions as shown in FIG. 5A can be obtained. It can be seen from the figure that B ions will be introduced into the thermal oxide films 207 and 208, and in Si/SiO ₂ The B ion concentration of the island-shaped semiconductor layer 205 very close to the interface becomes quite low.

Because when the island-shaped semiconductor layer 205 is used as the TFT active layer in a later stage, the B ion concentration in this region will be considerably minimized. Therefore, this represents the formation of the region by controlling the channel (really forming the inversion layer). The B ion concentration in the vicinity of the main surface of the active layer on the side of the active layer can be finely controlled by the threshold voltage. Therefore, in the inside of the active layer 205, the B ion concentration tends to decrease as it approaches the interface with the gate insulating film 208.

On the contrary, as shown in Figure 5B, the concentration of P ions is in Si/SiO ₂ It increases very close, so in the case of using P ions as doping ions, fine control of the threshold voltage cannot be achieved. The thermal oxidation process can effectively make the concentration of doped ions (B ions) uniform in the main surface of the active layer. This effect is advantageous in the following points.

Referring to FIG. 8A, for example, the concentration curve 801 of B ions doped by ion implantation or plasma doping shows an uneven distribution state in the depth direction of the active layer. In particular, the plasma doping method can effectively form shallow doped regions, but it is difficult to achieve uniform distribution. Figures 8A and 8B show the distribution depth in the desired in-plane direction at any depth.

More specifically, concentration fluctuations will be formed in the in-plane direction (of course, also in the depth direction) in the very close vicinity of the main surface of the active layer, and this fluctuation will be reflected in the energy band state of the channel formation region, and finally Causes an impact, causing fluctuations in the critical value in the semiconductor device.

However, in the case of this embodiment, since the B ions are diffused to a certain extent when redistributed, after the thermal oxidation process is performed, the concentration fluctuation can be reduced as a whole. That is, referring to FIG. 8B, B ions in the high-concentration region are preferentially introduced into the thermal oxide film to sufficiently reduce the concentration. On the other hand, by ion diffusion, the concentration of B ions in the low-concentration region will increase, and when the concentration becomes higher than a certain level, the ions will be absorbed by the thermal oxide film.

Therefore, as a whole, the concentration curve 802 of B ions remaining on the main surface of the active layer will result in an almost uniform concentration distribution. As mentioned above, the effect of selecting B ions by thermal oxidation can not only effectively improve the uniformity of the concentration distribution, but also contribute to the fine control of the threshold voltage.

In addition, in this embodiment, the 500 thick thermal oxide film formed in the thermal oxidation process is used as the gate insulating film. When thermal oxide film is used as gate insulating film, it can reduce SiSiO ₂ The state of the interface in close proximity to the interface, etc. Therefore, it is possible to obtain a TFT with excellent electrical characteristics. In addition, by changing the temperature, duration, and atmosphere during the thermal oxidation process, the film thickness can be controlled.

In addition, in this embodiment, the thermal oxidation process is performed at a relatively high temperature of 950°C. Therefore, the crystallinity of the island-shaped semiconductor layers 204 and 205 can also be expected to be improved considerably.

Once the state shown in FIG. 2 is obtained by completing the thermal oxidation process, an aluminum film (not shown) used to form a gate electrode in a subsequent step is formed by sputtering or electron beam vapor deposition. 0.2% by weight of scandium is added to the aluminum film to suppress the occurrence of mounds or whiskers.

The mound may be a sharp or needle-like protrusion caused by the abnormal growth of aluminum. Yau may be the cause of short circuit and crosstalk between adjacent lines or overlapping lines.

A film of an anodic oxidizable metal such as tantalum and molybdenum can be used instead of the aluminum film.

A conductive silicon film can also be used.

After the aluminum film is formed, anodization using the aluminum film as an anode is performed in the electrolyte to form a thin and dense anodic oxide film on the surface of the aluminum film. When performing patterning, the anodic oxide film thus obtained will increase the adhesion of the photoresist mask to the aluminum film.

After that, photoresist masks 209 and 210 are formed. Then, by using photoresist masks 209 and 210, the aluminum film (not shown) is patterned to form aluminum film patterns 211 and 212, thereby providing a gate electrode protocol. Thus, the structure shown in FIG. 2D is obtained.

Next, according to the conditions disclosed in Japanese Laid-Open Patent Publication No. 7-169974, porous anodic oxide films 213 and 214 are formed on the aluminum film patterns 211 and 212 sides. In this embodiment, porous anodic oxide films 212 and 214 with a thickness of 0.7 μm are formed. The state thus obtained is shown in Figure 2E. Then, after removing the photoresist masks 209 and 210, dense and strong anodic oxide films 215 and 216 are formed according to the conditions disclosed in Japanese Patent Application No. 7-169974. However, in this embodiment, the target voltage is controlled to obtain a 700 film. Therefore, gate electrodes 21 and 22 are established in this step. The resulting structure is shown in Figure 3A.

Referring to FIG. 3A, P ions, an impurity that causes n-type conductivity, are added to the entire surface. Doped with plasma or ion, with 0.2×10 ¹⁵ To 5×10 ¹⁵ cm ² Doped with P ions in a range of dose, preferably 1×101 ⁵ To 2×10 ¹⁵ Cm ² . By performing the steps shown in FIG. 3A, regions 217 and 220 each containing re-implanted P ions are obtained. These regions will later be used as source/drain regions (Figure 3A).

Then, after removing the porous anodic oxide films 213 and 214 using a mixed acid solution containing mixed acetic acid, nitric acid, and phosphoric acid, a photoresist mask is formed to cover the elements constituting the right p-channel type TFT. Next, in this state, but with 0.1×10 ¹⁴ To 5×10 ¹⁴ Cm ² Lower dose in the range, and then implant P ions, the preferred dose is 0.3×10 ¹⁴ To 1×10 ¹⁴ cm ² Scope (Figure 3B).

More specifically, the dose of the P ions implanted in the step shown in FIG. 3B is lower than the dose of the ion implantation performed in the step shown in FIG. 3A. Thus, lightly doped low-concentration impurity regions 223 and 225 are obtained. The regions 222 and 226 will become high-concentration impurity regions heavily doped with P ions.

Upon completion of this step, the region 222 will become the source region of the n-channel type TFT. Moreover, the low-concentration impurity regions 223 and 225 and the drain region 226 can be obtained through this step. Area 324 is the actual essential passage area. The region 225 is generally referred to as the LDD region (lightly doped drain) region.

Although it is not particularly shown in the figure, the region shielded by the anodic oxide film 215 during ion implantation is formed in the channel region 224 and the low-concentration impurity regions 223 and 225. This zone is called an "offset zone" and is formed at a distance corresponding to the film thickness of the anodic oxide film 215.

The offset gate area does not receive ion implantation and is therefore essential. However, since the gate voltage is not applied, it does not form a channel but serves as a resistor element that can alleviate the intensity of the electric field and suppress the deterioration. However, when the distance (offset width) is short, it will not be used as an actual effective offset area. In this embodiment, since the width is 700 mm, this area is not used as an offset area.

Then, referring to FIG. 3C, the photoresist mask 221 is removed, and another photoresist mask 227 is formed to cover the left n-channel TFT. Next, B ions are implanted as impurities that generate p-type conductivity. B ion is 0.2×10 ¹⁵ To 10×10 ¹⁵ cm ² The dose implantation, preferably 1×10 ¹⁵ To 2×10 ¹⁵ cm ² The dose. The dose in this step is approximately the same as that used in the step in Figure 3A.

By performing this step, the conductivity of the high-concentration impurity regions 219 and 220 is reversed from n-type to p-type to form the source region 228 and the drain region 229 of the p-channel TFT. The channel area 230 is formed at the lower right of the gate electrode 22. The channel forming region 230 contains the B ions added in the channel doping step, but the B ion concentration in the very close area of Si/SiO2 will decrease as it approaches the interface.

When the steps shown in FIG. 3C are completed, the photoresist mask 227 is removed, and the structure caused by the excimer laser irradiation is used to activate the impurity elements (P and B ions) and repair the damage of the island-shaped semiconductor layer . Irradiation energy is between 200 to 250mJcm ² 2. area.

When the excimer laser irradiation is completed, as shown in FIG. 3D, an interlayer insulating film 231 of 4,000 is formed. The interlayer insulating film 231 is formed by using any one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, or by using a multilayer structure thereof. These silicide films can be formed by plasma CVD or thermal CVD. Transparent organic resin (for example, polyimide) films can also be used.

Then, the contact hole is penetrated to form the source electrode 232 of the n-channel TFT and the other source electrode 233 of the p-channel TFT. Therefore, by providing the drain electrode 234 shared by the n-channel TFT and the p-channel TFT in this structure, a CMOS structure can be realized (FIG. 3D ).

Although this embodiment specifically describes the case where a CMOS circuit is formed by forming a TFT on a quartz substrate, the same situation can also be applied to a MOSFET formed on a silicon wafer. More specifically, IC technology is the application field of the present invention.

FIG. 6 shows the electrical characteristics (Id-Vg) of the TFT manufactured according to the embodiment shown in FIG. 3D. With reference to Fig. 6, the solid curves indicated by 601 and 602 show the Id-Vg characteristics of n-channel TFT and p-channel TFT, respectively. The curve shown by the dashed line 603 shows the Id-Vg characteristics of the p-channel TFT obtained without using the structure according to the present invention. In the graph, the horizontal axis shows the gate voltage (Vg) and the vertical axis shows the drain current of the TFT. (Id).

The threshold voltage Vth calculated from the Id-Vg characteristic curve 601 of the n-channel TFT manufactured according to this example, n falls within the range of 0.1 to 0.5V, and from the Id-Vg of the p-channel TFT manufactured according to this example The critical voltage Vth,p calculated from the characteristic curve 602 falls within the range of -0.5 to -0.1V.

Compared with the Id-Vg characteristic curve 603 of the conventional embodiment, the Id-Vg characteristic curve 602 of this embodiment is shifted in the positive direction (the direction indicated by the arrow). The threshold voltage obtained from the Id-Vg characteristic curve 603 is in the range of about -1.5 to -1.0. Therefore, it can be seen that the offset value is only slightly offset by a few tenths of the voltage, and the precise control that cannot be achieved by the traditional channel doping technology can be achieved.

The above facts now illustrate the outstanding feature of the present invention, which can control channel doping quite precisely. In addition, the present invention is particularly effective for TFTs with a sufficiently low threshold voltage without performing channel doping.

In addition, as shown in the structure of this embodiment, only the n-channel TFT is added with B ions alone, which is very meaningful. It will be described in further detail below.

Generally speaking, the gap (difference) between the threshold voltage (Vth, n) of the n-channel TFT and the threshold voltage (Vth, p) of the p-channel TFT is called the "window". In addition, as disclosed in Japanese Patent Application No. 4-206971, it is known that when the right and left sides of the window are not symmetrical with respect to the 0V gate voltage, that is, when the absolute value of Vth,n is different from the absolute value of Vth,p At this time, the CMOS circuit will suffer from reduced operating speed or failure.

In general, when a crystalline silicon film is used as the active layer, the Id-Vg characteristic curve tends to shift to the negative side with respect to the gate voltage. Therefore, generally speaking, the threshold value can be controlled by adding impurities that make the n-channel TFT produce p-type conductivity. However, this method increases the width of the window, thereby increasing the voltage range to be applied to the gate electrode.

The driving voltage of the display gate electrode becomes higher, which increases power consumption. In addition, in order to operate a high-speed CMOS circuit with a high driving voltage, a high-reliability circuit with better resistance to deterioration must be realized. This will require the manufacture of TFTs with higher performance.

However, as described above, by individually controlling the threshold voltage of the p-channel TFT according to this embodiment, the width of the window can be controlled; therefore, power consumption can be reduced. In particular, by following the manufacturing method according to this embodiment, the window threshold can be narrowed in the range of 0.2 to 1V. Therefore, this embodiment not only reduces power consumption, but also realizes a CMOS circuit with high reliability.

As mentioned above, by implementing channel doping, only the threshold voltage of the p-channel TFT will be controlled. Therefore, the width of the window can be narrowed and a well-balanced Id-Vg characteristic can be achieved. In particular, the most prominent feature of this embodiment is to reduce the Si/SiO in the channel formation region by allowing ions to be redistributed after the channel doping step. ₂ The concentration of added ions very close to the interface. This will allow fine control of the critical voltage. Therefore, as mentioned above, this embodiment is a very effective method when the circuit needs to have a very finely controlled threshold voltage and channel doping.

Embodiment 2 In Embodiment 1, after the island-shaped semiconductor layer is formed, the channel doping step is performed immediately. However, the channel doping step can be performed between other steps. For example, the doping can be performed on the amorphous silicon film before it is crystallized, or the crystalline silicon film can be doped before it is patterned into an island-shaped semiconductor layer. Doped. Especially in the case of performing doping on an amorphous silicon film, since the doped ions can be allowed to diffuse uniformly into the film during crystallization, mass separation (in which the ion system to be added) is not used can be performed. The ion implantation method is implanted in the formation of a group without any problems.

Or, for example, ions may be added to the crystalline silicon film before or after patterning, and after the ions are diffused by thermal diffusion or laser annealing, thermal oxidation may be performed.

As mentioned above, by considering other steps, the execution order of the channel doping steps can be appropriately modified. Basically, the concentration of added ions is precisely controlled in the thermal oxidation step. Therefore, the only requirement is that the required amount of added ions will be incorporated into the island-shaped semiconductor layer before the thermal oxidation step.

Example 3 In Example 1, FIGS. 5A and 5B show the redistribution tendency of substances with low diffusion rate. For P and B ions, the diffusion rate is almost the same, and as shown in FIG. 4, it is sufficiently low. However, the behavior during redistribution changes as the diffusion rate of the added ions increases to a sufficiently high value.

For example, when the diffusion rate of B ions becomes higher, the ions will exhibit a different distribution state than that shown in FIG. 5A. In fact, according to the report, when the thermal oxidation step is performed in an atmosphere containing hydrogen, the diffusion rate of B ions will increase.

In the above case, in Si/SiO ₂ The concentration of B ions at the interface will become lower than the concentration shown in FIG. 5A. In addition, it is obvious that the concentration of B ions will be lower than /SiO ₂ In the lower.

Therefore, by using the above facts, the concentration of B ions in the main surface of the active layer can be effectively reduced, and the threshold voltage can be further precisely controlled, because hydrogen ions can compensate for dangling bonds and defects in the crystalline silicon film constituting the active layer. Therefore, in a hydrogen-containing atmosphere, the crystallinity of the crystalline silicon film can be further improved.

Embodiment 4 This embodiment is about the case where the conductive crystalline silicon film is used for the gate electrode, and refer to FIG. 9. This embodiment specifically describes the case of manufacturing a CMOS circuit on a quartz substrate, but it can be formed on a glass substrate or a silicon substrate (including a wafer). On silicon substrates, IC circuits using traditional MOSFETs are fabricated, or structures called SOIs are constructed.

Referring to FIG. 9, a silicon oxide film 902 as a base film is formed on a quartz substrate 901. The active layer with the LDD area is labeled 903 and 904, which will become n-channel TFT and p-channel TFT, respectively. The active layers 903 and 904 are formed in the following manner.

First, a crystalline silicon film is formed on the silicon oxide film 902. By following the method described in Example 1 or by using such as SiH ₄ , Si ₂ H ₆ , Or SiH ₂ Cl ₂ The silane gas is used as the gas starting material by pressure-reducing thermal CVD to directly deposit a crystalline silicon film to form the crystalline silicon film. In this embodiment, an undoped crystalline silicon film is used. Once the crystalline silicon film is obtained, it is patterned into an island-like structure to obtain an active layer agreement in order to perform channel doping. In the same manner as in Embodiment 1, channel doping is performed, that is, B ions are added only to the p-channel TFT.

Next, by performing a thermal oxidation step, gate insulating films 905 and 906 are formed, and Si/SiO ₂ The B ion concentration near the interface, for example, by considering the film quality of the thermal oxide film, the film thickness, and the B ion concentration used to control the critical value, the heat treatment is performed under optimal conditions. Of course, you can also use gas TEOS/O ₂ System or gas SiH ₄ /NO ₂ After depositing the silicon oxide film by plasma CVD of the system, the thermal oxide film thus formed is removed to form a gate insulating film.

After that, gate electrodes 907 and 908 are formed and used as masks to implant impurity ions. This impurity implantation step is necessary for forming source/drain regions, low-concentration impurity regions (LDD), and channel regions in the active layers 903 and 904.

Since the LDD region is to improve the resistance to degradation, this region is necessary for making the p-channel TFT suffer less degradation. In the case of forming a CMOS circuit on a single substrate, since impurities are selectively implanted, the step of forming the LDD region is a bit complicated. Therefore, by omitting the LDD area, a simplified method can be realized. In this embodiment, the LDD region is formed on both n-channel and p-channel TFTs.

Perform the first impurity implantation of P ion and B ion. When the implantation is completed, a silicon nitride film is formed by film deposition, and sidewalls 909 and 910 are formed by using anisotropic etching. Then, the second impurity implantation of P ions and B ions is performed to form the source/drain regions of the n-channel TFT and the p-channel TFT. The regions just below the sidewalls 909 and 910 become low-concentration impurity regions (LDD regions). The area just below the gate electrodes 907 and 908 will provide a channel area.

When the active layers 903 and 904 are completed, a titanium (Ti) film or a cobalt (Co) film is formed on the entire surface by sputtering, so that it will be exposed to the source/drain regions and the gate electrode 907 and The reaction of the silicon film on 908 occurs by performing heat treatment. However, from the viewpoint of easy control of the processing atmosphere and total workload, it is preferable to use the RTA method. This technology is known as the metal silicidation technology.

Therefore, part of the source/drain and gate electrodes 907 and 908 is converted into metal silicide (more specifically, titanium silicide or cobalt silicide is obtained in this embodiment) to provide a region with low resistance. Therefore, the interlayer insulating film 911 formed by film deposition and the connections 912 to 914 are formed by penetrating the contact holes on the interlayer insulating film 911 to obtain the CMOS circuit structure shown in FIG. 9.

Embodiment 5 The present invention can also be applied to different types of semiconductor integrated circuits. This embodiment shows a case where the present invention is applied to SRAM (Static Random Access Memory) according to the embodiment of the present invention. The method will be explained below with reference to FIG. 10.

SRAM is a double-steady-state circuit memory that uses flip-flops as memory elements, and stores the binary information value (0 or 1) based on the two-steady state, that is, the double-steady-state circuit is on and off or off and on. . This type of memory system is conducive to maintaining memory as long as the power supply exists. The memory circuit is composed of NMOS and CMOS circuits. Referring to FIG. 10A, the SRAM circuit is a circuit that uses high resistance for passive load components.

10, the SRAM includes a word line 1001, a bit line 1002, a load element 1003 composed of high resistance, two pairs of driver transistors 1004, and two pairs of access transistors 1005. The SRAM of this structure is characterized by high-speed operation and high reliability, and it can be easily embedded in the system.

Example 6 This example is about the use of the present invention and the use of the technology disclosed in Japanese Patent Application No. 7-176753. For example, B ions are added not only to the p-channel TFT, but also to the n-channel TFT.

More specifically, when the channel doping of the p-channel TFT is performed, B ions of the reverse conductivity type are added to a part of the active layer of the n-channel TFT. This technology includes: preventing leakage current (short-channel leakage current) by forming a high-current region with a high-energy barrier to the part that is easy to form a current path. For example, the part that is easy to form a current path is active The edge part of the layer. Japanese Published Patent Application No. 7-176753 discloses the use of different impurities to achieve different effects, and the present invention uses a part of the structure (using impurities that cause conductivity opposite to that of the active layer).

In the embodiment according to Embodiment 1 with reference to FIGS. 2A to 2E, the channel doping of the active layer 205 of the p-channel TFT is selectively performed by providing the photoresist mask 206 for the n-channel TFT. However, in this embodiment, holes are pre-formed in a part of the photoresist mask 206, and B ions are selectively added to a part of the active layer 204 of the n-channel TFT.

Therefore, any region can be set in the active layer 204 of the n-channel TFT to add B ions therein. Some applications will be explained below.

In the plan view of the CMOS circuit in FIG. 11A, the active layer 101 for n-channel TFTs, another active layer 1102 for p-channel TFTs, gate electrodes 1103 made of crystalline silicon film, and conductive materials are shown in the plan view of the CMOS circuit. The connection (source or drain) 1104.

The shaded regions in the active layers 1101 and 1102 are regions where B ions are added during channel doping. In this embodiment, the area where B ions are not added is essentially the intrinsic I layer, and the area where B ions are added in the channel doping step is regarded as Ph. However, it should be noted that the purpose of channel doping is to add B ions to impart p-type conductivity to the active layer. The active layer acts as N h as a whole, so that the characteristics of the layer are close to those of the I layer. Therefore, in this embodiment, the I layer is substantially a weak N layer (N h), and P h is substantially the intrinsic I layer.

Referring to FIG. 11A, B ions are only added to the edge portion of the active layer 1101 of the n-channel TFT to convert this portion into a P-- layer with reversed conductivity. Since the edge part is easily damaged by plasma, etc., the edge part is easy to form a current channel. Therefore, by providing Ph in this part to form a high-energy barrier, the leakage current can be prevented.

FIG. 11B shows a cross-sectional view of the n-channel TFT of the CMOS circuit along the line AA'. It can be clearly seen from the figure that Ph is formed on the edge portions 1105 and 1106 of the active layer, and the lower right portion of the gate (area 1106) will remain as layer I. On the other hand, Figure 11C shows the extension A cross-sectional view of the p-channel TFT along the line BB'. It can be clearly seen from Fig. 11C that B ions are added to the area below the gate electrode (area 1107), thereby forming a shadow area corresponding to P-.

Figure 11D shows a cross-section of the CMOS circuit along the lateral CC'. In this case, the structure of the active layer for n-channel TFTs is different from that for p-channel TFTs. In an n-channel TFT, the source region 1108 and the drain region 1109 will be strongly n-type (that is, resulting in an N++ layer) from heavily added P ions, while the channel region 1110 is still an I layer.

In the case of a p-channel TFT, B ions will be added to the source region 1111 and the drain region 1112 at a high concentration to create a strong p-type conductive layer (ie, p++ layer), and the channel region 1113 will become the addition of B ions P-layer of the tracking quantity.

11E, 11F, 11G, and 11H are other embodiments in which B ions are added to the active layer of the n-channel TFT. Figures 11E and 11F show the situation where the P- layer is provided to the edge part, and Figure 11G shows the situation where the leakage current in the source/drain is reduced. Figure 11F shows that the edge part is surrounded by the P- layer so as not to further damage the edge part of the active layer damaged in the channel doping step. As mentioned above, when performing channel doping, you can also B ions are added to the n-channel TFT, and in parallel with the method according to the present invention, the technique of suppressing leakage current is selectively used. By simply providing holes to the required area of the photoresist mask, ions can be added to the n-channel TFT. Therefore, this technique is not only effective for this situation, but also widely applicable.

If the channel is doped at the same time, when a structure is used that does not add ions only to the edge part, the part without the addition of ions acts as a region with reversed conductivity, and effectively suppresses leakage current. With reference to FIGS. 12A to 12F, this situation is explained below. Since the structure of the CMOS circuit is the same, the symbols used in FIG. 11A are used in the following.

Referring to FIG. 12A, by adding B ions to the edge portion of the N-channel TFT 1101, a P-- layer is formed therein. Since the details have been described above, the description here only refers to the case where B ions are added to the area shown in FIG. 12A. The difference from FIG. 11A is only the structure of the active layer 1201 of the p-channel TFT.

The cross-sectional view of the n-channel TFT along the line AA in FIG. 12A (FIG. 12B) is not particularly different from the above case, but in the cross-section along the line BB of the p-channel TFT (FIG. 12C), it is shown for the edge portion Part I of 1202. Of course, since the region 1203 of the non-edge portion will receive channel doping, it will be converted into a layer.

As mentioned above, the I layer is essentially the N- layer, and the P layer is essentially the I layer. Therefore, for p-channel TFTs, the I layer (essentially the N- layer) without adding B ions serves as a region for inverting the conductivity. More particularly, since the energy barrier between the P-type and N-type regions thus formed is high, the occurrence of carrier transfer can be prevented.

Referring to FIG. 12D, the source region 1204 and the drain region 1205 of the p-channel TFT will become a P++ layer with strong p-type conductivity, and the channel region 1206 will become P-h84d. Finally, a structure including an I layer is implemented to achieve the effect of reducing leakage current. The I layer is formed at least at the edge of the channel region, and the I layer is substantially imparted with an inverted conductivity type (n-type). An embodiment with this structure can be obtained by retaining the I layer in the area shown in FIGS. 12E and 12F.

Embodiment 7 The CMOS circuit manufactured in Embodiment 1 can be applied to an active display device. Regarding active display devices, generally known ones are active matrix liquid crystal devices. Its construction is shown in Figure 13.

The structure shown in FIG. 13 is an SOG (system on glass) type display device, which has a pixel area and a peripheral drive circuit formed on a single substrate, and is also equipped with a control circuit such as a memory circuit and a CPU circuit.

Referring to FIG. 13, the pixel area 1301 usually includes millions and hundreds of TFTs arranged in a matrix, and controls the voltage applied to the liquid crystal. This structure is also equipped with a vertical scanning drive circuit 1302 and a horizontal scanning drive circuit 1303. These driving circuits include shift register circuits, buffer circuits, sampling circuits, etc., to control gate signals and video signals. The control circuit 1304 is composed of a CPU circuit, a memory circuit, and the like.

In the structure with reference to FIG. 13, a semiconductor device with a CMOS structure is used for the horizontal and vertical scan driving circuits 1302 and 1303, the control circuit 1304, and so on. In addition, since the semiconductor device having the CMOS structure manufactured according to the first embodiment can be driven by a low voltage, it can be designed with considerable tolerance to withstand voltage. Therefore, this device is suitable for the above-mentioned driving circuit and the like that require high reliability.

The present invention can be applied not only to the active matrix liquid crystal display device shown in FIG. 13, but also to other electro-optical devices including other types of active flat panel displays, such as EL display devices and CL display devices. In addition, it can be applied not only to direct-view type displays, but also to projection type display devices.

In active display devices, in particular, from the viewpoint of suppressing flicker by accelerating the display image plane, the peripheral driving circuit requires high-speed operation.

For shift registers and counter appliances that perform timepiece operations, high-speed operation is particularly required.

Figure 14A implements the shift register circuit that forms part of the gate driver. The function of the shift register circuit is to select the gate lines arranged in the pixel area sequentially (or one after another). Therefore, if the operating speed of the shift register circuit should be low, the selection of the gate line will consume time, which will eventually increase the time required to complete the display of a single field (or single frame) in the image plane.

Therefore, flicker occurs on the image plane.

The above-mentioned shift resistor circuit is basically composed of the clock inverter circuit shown in FIG. 14B and the inverter circuit shown in FIG. 14C. Since the circuits with reference to FIGS. 14B and 14C are composed of CMOS circuits, the present invention can be applied to CMOS circuits.

As described in Embodiment 1 above, the CMOS circuit manufactured according to the present invention is composed of n-channel TFTs and p-channel TFTs that cause the absolute value of the threshold voltage to be almost the same and the window is substantially symmetrical to Vg=0V. Therefore, it can be known that the CMOS circuit according to the present invention will produce good balance characteristics and the output voltage can be free from deviation. In addition, since the width of the window is narrow (that is, the absolute values of Vth,n and Vth,p are all small), the power required by the driving circuit is advantageously low.

As mentioned above, by applying the present invention, CMOS circuits with good balance characteristics can be effectively manufactured and used in peripheral driving circuits of other semiconductor devices. Generally speaking, high-speed operating drive circuits are prone to suffer from low withstand voltage and extreme degradation. However, since the power consumption of the TFT manufactured according to Embodiment 1, that is, the driving voltage, can be suppressed at a low voltage, a driving circuit that is relatively resistant to degradation and has high reliability can be realized.

Embodiment 8 This embodiment relates to a semiconductor device with a CMOS structure. The CMOS structure includes an n-channel semiconductor device and a p-channel semiconductor device combined in a complementary manner. Each semiconductor device includes at least an active layer. It is made of a crystalline silicon film on a substrate with an insulating surface; the gate insulating film is obtained by applying thermal oxidation treatment to the active layer; and the inter-electrode is provided on the insulating film; which is used to produce Impurity elements with p-type conductivity are only added to the active layer of the p-channel semiconductor device; the concentration distribution of impurity elements is interrupted at the interface between the active layer and the gate insulating film, and on the active layer side very close to the interface Above, the concentration tends to decrease with the subsequent interface; and the impurity elements remaining very close to the interface on the active layer side are used to control the threshold voltage.

Another embodiment of manufacturing a CMOS circuit according to the present invention will be described below. The CMOS circuit includes an n-channel TFT and a p-channel TFT combined in a complementary manner. The CMOS circuit to be manufactured in this embodiment is an inverter with the simplest structure as shown in FIG. 1A. The threshold voltage is controlled by adding B ions only to the p-channel TFT. Therefore, the present embodiment will be explained with reference to FIGS. 15A to 15C.

Referring to FIG. 15A, a silicon oxide film is formed as a base film 1502 on the surface of a quartz substrate 1501 by deposition. The substrate 1501 can be selected from a glass substrate, a quartz substrate, a silicon substrate (wafer), and so on. However, in the case where the temperature is high in the subsequent thermal oxidation step, that is, more particularly, in the case of an ultra-high temperature of 650°C, it is preferable to use a quartz substrate with good heat resistance and not Use a glass substrate with a low softening point.

After that, a crystalline silicon film is formed to provide an active layer of the TFT. In this embodiment, the amorphous silicon film is crystallized to obtain a crystalline silicon film. Therefore, using step-down thermal CVD or plasma CVD, a 1,000 thick amorphous silicon film is first deposited. Since the film thickness will be reduced in the later thermal oxidation step, the above-mentioned film will be formed to be thicker than the required film thickness.

Once the amorphous silicon film is formed, the resulting film will crystallize by heat treatment, laser annealing, or both. In this embodiment, crystallization is performed by using the techniques described in Japanese Laid-open Patent Application No. 6-232059 and Japanese Laid-Open Patent Application No. 7-321339 published by the inventor. The above technique first applies a metal element such as nickel or copper to the amorphous silicon film and maintains this state at a temperature range of 500 to 700°C, typically 600 to 650°C, and heat treatment for 1 to 24 hours. The duration is typically 4 to 12 hours, so that the silicon film has excellent crystallinity.

By performing the above method, an amorphous silicon film (not shown) is crystallized to obtain a crystalline silicon film 1503. The crystalline silicon film 1503 obtained in this way can exhibit better crystallinity than a crystalline silicon film obtained without using the above method. In addition, according to the inventors' knowledge, applying laser annealing to the silicon film thus crystallized by heat treatment can achieve better crystallinity. The state thus obtained is shown in Fig. 15A.

Then, the crystalline silicon film is patterned to obtain an island-shaped semiconductor layer 1504 that later constitutes the active layer of the N-channel TFT and another island-shaped semiconductor layer 1505 that later constitutes the active layer of the p-channel TFT.

Then, using a specific solution for stripping, remove the photoresist mask (not shown) used in the patterning of the island-shaped semiconductor layer 1504 and 1505, and cover the island-shaped semiconductor layer 1504 which will become the active layer of the n-channel TFT. Another photoresist mask 1506 will be formed again. Then, B ions, an impurity element that causes p-type conductivity, are only added to the island layer 1505 (channel doping step).

In this embodiment, 1×10 ¹⁶ To 1×10 ¹⁹ cm ¹³ Concentration of ion implantation, implantation of B ions obtained by mass separation. In this method, B ions are added in the form of atoms in which ions can be uniformly distributed in the island-shaped semiconductor layer. In the case of performing ion implantation without using mass separation, since B ions are added in groups together with other atoms and molecules, a diffusion step must be incorporated to achieve a uniformly distributed state.

Since the optimal number of B ions (addition concentration) to be added depends on how the threshold voltage (Vth) changes, the optimal number must be determined by experiment. In the configuration according to the present invention, after the thermal oxidation step that occurs later, the Si/SiO in the channel formation region is determined ₂ The concentration of B ions at the interface. Taking into account this fact, the concentration of addition must be controlled.

This example illustrates the addition of B ions by ion implantation. Alternatively, a gas containing B ions (for example, diborane) is used as a gas starting material to add B ions during the deposition of the amorphous silicon film. However, in this case, since the threshold voltage of the n-channel will also shift to the positive side, care must be taken. After the addition of B ions is completed, a thermal oxidation process is performed after removing the photoresist mask 1506. Regarding the method of thermal oxidation, it can contain 1 to 10%, preferably 3% of hydrogen chloride (HCl) to oxygen (O ₂ In an atmosphere of ), heat treatment is performed at a temperature of 800 to 1,100°C, more particularly 950°C (Figure 15c).

The following three objectives are achieved by the thermal oxidation step in this embodiment: First, remove the catalyst element (nickel in this embodiment) used in crystallization by inhalation: second, by By drawing B ions into the thermal oxide film, reducing (controlling) Si/SiO ₂ B ion concentration at the interface; and formation of gate insulating films 1507 and 1508. Particularly necessary for the above purpose is the second, which is to reduce SiSiO ₂ The concentration of B ions in the interface.

It is clear from Figure 4 that boron is less prone to diffuse than nickel. For example, at 950°C, that is, at the temperature at which the above-mentioned thermal oxidation treatment is performed, the diffusion coefficient of nickel is approximately 4×10 ^-8 cm ² s, and is about the diffusion coefficient of boron (4×10 ^-14 cm ² s) 10,000 times.

Therefore, the nickel in the island-shaped semiconductor layers 1504 and 1505 moves quickly to combine with Cl ions to form nickel chloride. Nickel chloride is highly volatile and easily decomposes into the gas phase. Therefore, by inhalation, the nickel in the film is removed.

Similar to the case of Example 1, after the thermal oxidation process, the SiSiO ₂ The concentrations of B ions and P ions caused in the very close vicinity of the interface are shown in FIG. 5.

In this embodiment, the 500 thick thermal oxide film obtained through the above thermal oxidation process is used as the gate insulating film. In the case of thermal oxide film as gate insulating film, due to SiSiO ₂ The interface state etc. in the very close part of the interface will be reduced, so a TFT with quite excellent electrical characteristics can be realized. In addition, by changing the temperature, duration, and atmosphere conditions of the thermal oxidation process, the thickness of the thermal oxide film can be controlled.

In addition, in the case of this embodiment, the thermal oxidation process is performed at 950° C., that is, at a relatively high temperature. Therefore, the crystallinity of the island-shaped semiconductor layers 1504 and 1505 can be greatly improved. More specifically, during the absorption of nickel ions by Cl ions, the Si dangling bonds left during the desorption of nickel will recombine with adjacent Si to form Si-Si bonds. As a result, the defects between the angles or the defects appearing in the grain boundary will be greatly reduced and the crystallinity will be increased.

Once the state shown in FIG. 15C is obtained after the thermal oxidation step, the semiconductor device as shown in FIG. 3D is formed in the same manner as described in the embodiment with reference to FIG. 2D and subsequent steps.

[Explanation of TFT in Example 8] The electrical characteristics (Id-Vg characteristics) of the TFT manufactured according to Example 8 and shown in FIG. 3D are shown in FIG. 16. Referring to FIG. 16, the curve (solid line) indicated by 1601 is the Id-vg characteristic of the N-channel TFT, and the curve indicated by 1602 (solid line) is the Id-Vg characteristic of the p-channel TFT. The curve (dashed line) 1603 is the Id-Vg characteristic of the p-channel TFT constructed not in accordance with the present invention.

In the graph, the horizontal axis shows the gate voltage (Vg) of the TFT, and the vertical axis shows the drain current (Id). The Id-Vg characteristic is the Id-Vg characteristic obtained when the drain voltage Vd is set to 1V. In this embodiment, the threshold voltage Vth obtained by calculating the Id-Vg characteristic 1601 of the n-channel TFT, n is in the range of 0.1 to 0.5V, and is at least suitable for a range of 0.2 to 0.5V.

The threshold voltage Vth obtained by calculating the Id-Vg characteristic 1602 of the p-channel TFT, p is in the range of -0.05 to -0.1V, and at least suitable for the range of -0.5 to 0.2V.

When compared with the Id-Vg characteristic 1603 of the conventional p-channel TFT, the Id-Vg characteristic 1602 of the TFT using the present invention is significantly shifted to the positive direction (the direction indicated by the arrow). The threshold voltage obtained by calculating the Id-Vg characteristic 1603 shown by the dotted line is in the range of -1.5 to -1.0. Therefore, it can be seen that the offset is fine to a few tenths of a volt, and it can achieve extremely precise control that is absolutely uncontrollable by traditional channel doping technology.

The above facts clearly show that by using the present invention, the channel doping can be controlled extremely accurately. In addition, as shown in this embodiment, the present invention is particularly effective for TFTs that have a sufficiently low threshold voltage and do not require special channel doping.

The most impactful feature of the semiconductor manufactured according to the embodiment of the present invention is that the semiconductor has excellent high-speed operation. Therefore, the semiconductor obtained in this embodiment is particularly suitable for situations that require high-speed operation, such as peripheral drive circuits composed of CMOS circuits, especially shift register circuits.

The inventors further fabricated the ring oscillator by connecting odd-numbered pairs of the CMOS circuit shown in FIG. 3D in series. As a result, excellent frequency characteristics as shown in Fig. 18 can be obtained. The measurement includes 9, 19 or 51 pairs of CMOS circuit ring oscillators to obtain the relationship between the power supply voltage and the oscillation frequency. Referring to FIG. 18, in the case where the ring oscillator contains 9 pairs operating with a 10V power supply, an oscillation frequency of 123 MHz can be obtained. As mentioned above, this result is mainly due to the rather low S value. Therefore, in the case of constructing a circuit capable of high-speed operation as shown in FIG. 18, the value of S should be 85 mV/dec or lower, and preferably, 75 mV/dec or lower.

This embodiment relates to the case of using a crystalline silicon film formed on a quartz substrate to manufacture a thin film transistor, and this configuration also helps to achieve high-frequency characteristics.

The explanation for this situation is as follows.

In a MOSFET formed on a silicon wafer, generally speaking, it is known that the operating frequency f is inversely proportional to the time constant τ, that is, f=1τ. Since τ can be represented by the product of the capacitance C and the resistance R, f = 1CR is another representation of f. The capacitor C includes a gate capacitor, a depletion layer capacitor, a connection capacitor, and a connection substrate capacitor, and the resistor R includes a source/drain resistor, a connection resistor, and so on. Therefore, the operating frequency depends on all these capacitances and resistances.

In order to increase the operating frequency, active research has been carried out on how to reduce the connection resistance. However, when the connection becomes finer, you will find that this is quite difficult. Therefore, the technology of reducing the capacitance of the connection substrate has attracted a lot of attention. With SOI technology, this is possible, but the best achievement is to reduce the capacitance.

The feature of the thin film transistor technology that has been greatly improved recently is that the transistor system is directly formed on a glass substrate or a quartz substrate. This is quite conducive to no connected capacitors.

Considering that the performance (ie, electrical characteristics) of the TFT manufactured according to this embodiment is well compatible with the TFT of the SOI structure, it can be expected that the TFT according to the present invention will be superior to the TFT of the SOI structure in terms of frequency characteristics.

In addition, it is known that the operating frequency is inversely proportional to the square of the channel length L. For example, a channel length of 0.35μm in the IC is necessary to achieve a high-speed operation of 200MHz. However, even if the channel length exceeds the above limit, the TFT of the SOI structure can still achieve a high-speed operation of 200MHZ. Since the TFT of the SOI structure according to the present embodiment is superior to the TFT of the SOI structure in terms of connecting the substrate capacitance, the channel length can provide a further limit, and in some cases, it is possible to achieve a higher speed operation of ultra-high 200MHz.

In the structure according to this embodiment, as described above, only the threshold voltage of the p-channel TFT is controlled by the channel doping. Therefore, a narrow window width and balanced Id-Vg characteristics can be obtained. In particular, the most prominent feature of the present invention is that the redistribution is generated after the channel doping step, so as to reduce the concentration of the added ions very close to the Si/SiO2 interface in the channel region.

Therefore, precise control of the critical voltage can be achieved. Therefore, this can be used as a very effective method in the case where the threshold voltage is small and the channel doping is required to be quite precise as described in the present invention.

[Eg description of active layer] The inventors further measured the energy band gap (Eg) of the crystalline silicon film manufactured according to this embodiment at room temperature (10 to 30°C). More specifically, the Eg value as follows is obtained. Measure the absorption spectrum of the crystalline silicon film to obtain the effective transmittance of the silicon film as a function of the light wavelength, and the light wavelength at the absorption edge where the effective transmittance begins to decrease will be converted into energy according to the equation E=hcλ, Among them, E is energy, h is Planck's constant, c is the speed of light, and λ is wavelength.

The experimental data obtained by measuring the absorption spectrum of the crystalline silicon film according to this embodiment is shown in FIG. 19. In FIG. 19, the horizontal axis represents the light wavelength in the general visible region, and the vertical axis represents the effective transmittance of the light intensity ratio before and after passing through the film (the transmittance calculated by omitting the reflected light component at the film plane). The measurement is performed for two films with different film thicknesses, namely 400 and 600.

When light is transmitted through the silicon film, the wavelength components with energy higher than Eg of the silicon film will not pass through the film and will be absorbed by the film, while those corresponding to the wavelength region with energy less than Eg will pass through the film. Therefore, the light energy with the wavelength corresponding to the absorption edge of the absorption spectrum is assumed to be equal to Eg.

Referring to FIG. 19, the transmittance starts to decrease at about 800 nm or less. From this value at 800 nm, it is calculated that Eg is almost 1.5 eV. As mentioned above, obtain Eg from Einstein's photoelectric formula: Eg=hc/λ, where h is Planck's constant, c is the speed of light, and h is the wavelength.

The Eg value thus obtained has a close relationship with the electrical characteristics of the TFT.

For example, since the TFT manufactured in this embodiment is an enhanced type, it should exhibit the characteristic of "normally off" (that is, when it is not selected, the TFT is off). It is important to obtain an Eg of 1.3 eV or higher. The reason will be explained below with reference to FIG. 17.

FIG. 17 is a diagram showing the energy band states of the conductive regions 1701 and 1702 and the channel region 1703 corresponding to the source/drain regions. Because the tracking amount of B ions is added to the channel area of the p-channel TFT, the ΔE of the channel area of the p-channel TFT is slightly smaller than that of the n-channel TFT. However, in the following description, this fineness will be skipped The difference.

Referring to FIG. 17, the energy band gap (ΔE) is formed between the conductive region 1701 (or 1702) and the channel region 1703. If ΔE is not large enough, even if it is not selected, the TFT will be turned on (normally turned on), and it will become a so-called low drop TFT.

For example, in the SOI structure, Eg is equal to about 1.1 eV, and ΔE is as small as about 0.5 eV. Therefore, the TFT appears "normally turned on". Therefore, the only way to achieve "normal shutdown" is to deliberately increase ΔE by applying channel doping.

However, as shown in Fig. 17, ΔE obviously increases with the increase of Eg. According to the inventors' knowledge, if an Eg of 1.3 eV or higher is obtained, ΔE will become large enough to achieve a "normally closed" state. Therefore, when implementing the enhanced TFT according to this embodiment, it is important to obtain an Eg of 1.3 eV.

When Eg is equal to 1.3 eV, the wavelength obtained according to the above photoelectric equation is about 950 nm. Therefore, the high-performance TFT as shown in this embodiment can be obtained in the 800±150 nm wavelength region, that is, the Eg region from 1.3 to 1.9 eV, preferably 1.4 to 1.7 eV.

Embodiment 9 In Embodiment 8, by using gaseous HCl, the inhalation of the catalytic element (Ni) is performed. However, it can also be used such as NF ₃ , ClF ₃ Wait for the fluorine gas, and perform the same catalyst element inhalation. In this case, the dangling bond will be terminated by fluorine during the gettering process, and since the Si-F bond will be stronger than the Si-H bond, this is preferable.

In addition, since gaseous NF3 decomposes at 600 to 800°C, that is, at a temperature lower than the decomposition temperature of gaseous HCl used in Example 1, the heat treatment temperature can be lowered. In this embodiment, the heat treatment will be performed at 700°C for a duration of 30 to 60 minutes in a mixed atmosphere based on 0.1 to 10% by weight of oxygen. The mixed atmosphere contains 0.1 to 10% by weight. Percentage of gaseous HCl (represented by 3%) and 0.1 to 3% by weight of gaseous NF ₃ (Represented by 0.3%).

As mentioned above, since the dangling bonds of silicon will recombine with each other and those that still maintain the dangling bonds will be terminated by fluorine, the defect density can be further reduced. In addition, because the heat treatment temperature is reduced by 200 to 300°C, the total workload of the production method can also be improved.

It contains 3% by weight of hydrogen and 0.3% by weight of gaseous ClF ₃ In an oxygen-based mixed gas atmosphere, a mixed oxidation treatment in the range of 500 to 600°C for a duration of 30 to 60 minutes can also achieve the same effect as the above. This situation is more conducive to the nickel absorption performed by the chlorine and fluorine elements.

Embodiment 10 The invention disclosed in this specification can be applied to an electro-optical device using a semiconductor device (represented by TFT (Thin Film Transistor)). Electro-optical devices include liquid crystal display devices, EL (electroluminescence) display devices, and EC (electrochromic) display devices.

Application examples of commercial products include television cameras, personal computers, car navigation systems, television projection systems, and video cameras. These products will be introduced below with reference to Figure 20E.

FIG. 20A shows a television camera, including a main body 2001, a camera 2002, a display device 2003, and an operation switch 2004. The display device 2003 also serves as a viewfinder.

FIG. 20B shows a personal computer, including a main body 2101, a cover portion 2102, a keyboard 2103, and a display device 2104. The display device 2104, as a monitor, requires a diagonal of more than ten inches.

Referring to FIG. 20C, the car navigation system includes a main body 2201, a display device 2202, operation keys 2203, and an antenna 2204. The display device 2202 serves as a monitor, but its main purpose is to display a map. Therefore, the width of resolution is quite large.

Referring to FIG. 20D, the television projection system includes a main body 2301, a light source 2302, a display device 2303, a mirror 2305, and a screen 2306. Because the image displayed in the display device 2303 is projected to the screen 2306, the display device must have a high resolution.

Referring to FIG. 20E, the camera includes a main body 2401, a display device 2402, an eyepiece 2403, an operation switch 2404, and a tape holder. Since the captured image can be viewed in real time through the eyepiece 2403, the user can take a photo while viewing the image.

As mentioned above, the present invention can be applied to a wide range of fields of view, and is suitable for products using different types of semiconductor circuits.

Compared with the traditional channel doping technology, the present invention can control the channel doping more accurately. More specifically, the critical voltage that was previously controlled at the level of several volts can now be controlled at the level of several tenths of a volt.

In particular, the present invention is particularly effective for TFTs with better characteristics (for example, it has a relatively small absolute value of the threshold voltage and it is difficult to control it); it not only affects the driving voltage of the gate electrode but also affects the power consumption window width can be suppressed to 1V Or lower, more specifically, the range from 0.4 to 1.0V.

Although the present invention has been described in detail, it should be understood that the present invention is not limited thereto, and can have any changes without departing from the scope of the patent application.

Schematic description

Figures 1A and 1B are diagrams showing the structure and characteristics of thin film transistors;

Figures 2A to 2E are diagrams showing the steps of manufacturing thin film transistors;

Figures 3A to 3D are diagrams showing the steps of manufacturing thin film transistors;

Figure 4 is a graph showing the relationship between the change of diffusion coefficient and temperature;

Figure 5A and 5B series graphics, shown in Si/SiO ₂ The distribution of dopants at the interface;

Figure 6 is a graph showing the characteristics of thin film transistors;

Figure 7 series graphics, shown in Si/SiO ₂ The distribution of dopants at the interface;

Figures 8A and 8B are other figures shown in Si/SiO ₂ The distribution of dopants at the interface;

Figure 9 is a cross-sectional view showing the silicon gate TFT structure;

Figure 10 is a graph showing the circuit structure of SRAM;

11A to 11H show the structure of the active layer in CMOS;

12A to 12F show the structure of the active layer in another CMOS;

Figure 13 shows the structure of an active matrix display device;

14A to 14C show the structure of the shift register circuit;

15A to 15C show other steps of manufacturing thin film transistors;

Figure 16 is other graphics showing the characteristics of thin film transistors;

Figure 17 is an explanatory diagram showing the energy band structure used to obtain Eg;

Figure 18 is a graph showing the frequency characteristics of the CMOS circuit;

Figure 19 is a graph showing the change of transmitted light with changing wavelength;

And FIGS. 20A to 20E show the application fields of semiconductor devices.