Magnetic memory device

Magnetic memory device

<p>1~3, 160, 169, 189. . . Word line</p><p>4~6, 69, 89, 160. . . Bit line</p><p>7. . . pn junction diode</p><p>8. . . MTJ</p><p>9. . . MRAM cell</p><p> 10. . . n ⁺ Silicon layer </p><p> 11. . . p ⁺ Silicon layer </p><p>12. . . Tungsten embolism</p><p>13. . . Silicon oxide film</p><p>15. . . Type plate layer</p><p>16. . . Initial ferromagnetic body</p><p>18. . . Diamagnetic body</p><p>20, 126a. . . Ferromagnetic</p><p>twenty two. . . Tunnel barrier layer, soft ferromagnetic layer</p><p>twenty four. . . Soft ferromagnetic layer</p><p>25. . . Contact layer</p><p>26. . . Silicon oxide film</p><p>30. . . Detection current</p><p>31. . . Memory cell array, bit line control circuit</p><p>32. . . Word line control circuit</p><p>33. . . Row read/write control circuit</p><p>36. . . Column read/write control circuit</p><p>41. . . CPU</p><p>42. . . DSP</p><p>43. . . Modulation and demodulation circuit</p><p>44. . . ESD circuit</p><p>51. . . First cache memory, bit line control circuit</p><p>52. . . Second cache</p><p>53. . . I/O controller, word line control circuit</p><p>61, 62, 81, 82, 162, 181. . . AND gate</p><p>64, 83. . . Vice word line</p><p>66, 85, 166, 185, 851. . . MRAM cell array</p><p>67, 84. . . Main word line</p><p>70, 170. . . Memory cell array selection line</p><p>80. . . Main universal decoder</p><p>87. . . Universal word line</p><p>88, 188. . . Address signal line group</p><p>102a, 102b, 102c. . . Semiconductor wafer</p><p>106. . . Resin</p><p>107, 129. . . Package body</p><p>109, 130, 131. . . Internal wiring</p><p>112. . . Welding line</p><p>113. . . External wire</p><p>122, 231, 232. . . Semiconductor wafer</p><p>123. . . Passivation film</p><p>124, 124b. . . Mounting film</p><p>125. . . Stress relief film, solder bumps for shielding</p><p>126, 126b. . . Shield electrode</p><p>127. . . Solder bumps for signal transmission</p><p>128. . . Resin material</p><p>132. . . Wafer electrode</p><p>133. . . Adhesive layer</p><p>134. . . Bottom substrate</p><p>135. . . Stress relaxation film</p><p>136a. . . Ferromagnetic</p><p>161. . . NAND gate</p><p>164, 183. . . (Auxiliary) bit line</p><p>167, 184. . . Thematic line</p><p>187. . . Universal bit line</p><p>211. . . Solder bump forming hole</p><p>219. . . Sheet electrode</p><p>223, 235. . . Stress relaxation film</p><p>224. . . Groove</p><p>236. . . Lower board</p><p>237. . . Outer frame</p><p>238. . . On board</p><p>861, 1861. . . Memory cell array group</p><p>901,1901. . . Memory cell array group selection line</p><p>911, 1911. . . Memory cell array selection line</p><p>BL. . . Bit line</p><p>W1. . . Word line</p><p>WL1a, b. . . Select word line</p><p>BL1b. . . Select bit line</p><p>MA. . . MRAM cell array</p><p>Hk. . . Combined magnetic field</p><p>CAB. . . Row address buffer</p><p>MCA. . . MRAM cell array</p><p>CD, 32. . . Row decoder</p><p>MUX. . . Multiplexer</p><p>CRW1. . . Row read/write first control circuit</p><p>RAB, 34. . . Column address buffer</p><p>RD, 35. . . Column decoder</p><p>RRW1. . . Column read/write first control circuit</p><p>IOB. . . Input/output buffer</p><p>CRW2. . . Row read/write second control circuit</p><p>R. . . Variable resistor</p><p>D. . . Diode</p><p>MN, QN, PN, QM. . . NMOS transistor</p><p>TA. . . Terminal</p><p>PN. . . pn junction diode</p><p>GBL. . . Universal flash bit line</p><p>GWL. . . Universal flash word line</p><p>CP. . . Capacitor</p><p>SB. . . Silicon substrate</p><p>IL. . . Insulating film</p><p>ML. . . Conductor layer</p><p>SF1. . . n-type silicon layer</p><p>SF2. . . P-type silicon layer</p><p>STD. . . Tungsten layer</p><p>TPL. . . Type plate layer</p><p>IFL. . . Initial ferromagnetic body</p><p>AFL. . . Diamagnetic body</p><p>FFL. . . Ferromagnetic</p><p>TBL. . . Tunnel barrier</p><p>FML. . . Soft ferromagnetic layer</p><p>CL. . . Contact layer</p><p>BX. . . Buried oxide film</p><p>SI. . . SOI substrate</p><p>OP. . . Opening</p><p>MC. . . MRAM cell</p><p>ID. . . Inductor</p><p>FBL. . . Flash bit line</p><p>FWL. . . Flash word line</p><p>SHB. . . Masking body</p><p>FM. . . Ferromagnetic layer</p><p>TB. . . Insulation</p><p>AF. . . Antiferromagnetic layer</p><p>BD. . . Substrate</p><p>MC2, MC3. . . MRAM cell</p>

Figure 1 is an oblique view showing the architecture of the MRAM cell.

Figure 2 is a diagram showing the architecture of a commonly used MRAM cell array.

Fig. 3 is a diagram for explaining the operation of a commonly used MRAM cell array.

Fig. 4 is a diagram showing the relationship of the magnetic field required to reverse the spin.

FIG. 5 is a diagram showing the MRAM cell array structure related to the first embodiment of the present invention.

FIG. 6 is a diagram showing the operating state of the MRAM cell array related to the first embodiment of the present invention.

FIG. 7 is a diagram showing the MRAM cell array architecture related to the first embodiment of the present invention.

FIG. 8 is a diagram showing the operating state of the MRAM cell array related to the first embodiment of the present invention.

FIG. 9 is a diagram used to illustrate the working state of a commonly used MRAM cell.

FIG. 10 is a diagram for explaining the working state of a commonly used MRAM cell.

Fig. 11 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 12 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 13 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 14 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 15 is a diagram showing the relationship of the magnetic field required to reverse the spin.

Fig. 16 is a diagram for explaining the working state of a commonly used MRAM cell.

FIG. 17 is a diagram for explaining the working state of a commonly used MRAM cell.

Fig. 18 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 19 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 20 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 21 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 22 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

FIG. 23 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 24 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 25 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

FIG. 26 is a block diagram showing the MRAM architecture related to the second embodiment of the present invention.

FIG. 27 is a circuit diagram showing the MRAM architecture of the second embodiment of the present invention.

FIG. 28 is a timing diagram showing the MRAM architecture of the second embodiment of the present invention.

Fig. 29 is a graph showing the dependence of the change rate of the magnetic tunnel resistance on the applied voltage.

FIG. 30 is a diagram showing the architecture of the dual magnetic tunnel junction.

FIG. 31 is a circuit diagram showing the MRAM architecture related to the second embodiment of the present invention.

FIG. 32 is a timing chart showing the MRAM architecture of the second embodiment of the present invention.

FIG. 33 is a circuit diagram showing the MRAM architecture related to the second embodiment of the present invention.

FIG. 34 is a block diagram showing the structure of dividing the word line of the MRAM according to the third embodiment of the present invention.

35 is a block diagram showing a hierarchical structure of MRAM word lines related to the third embodiment of the present invention.

FIG. 36 is a schematic diagram showing a hierarchical structure of MRAM word lines related to the third embodiment of the present invention.

FIG. 37 is a block diagram showing the structure of dividing the MRAM bit line related to the third embodiment of the present invention.

FIG. 38 is a block diagram showing a hierarchical structure of MRAM bit lines related to the third embodiment of the present invention.

Fig. 39 is a perspective view showing the MRAM architecture related to the fourth embodiment of the present invention.

Fig. 40 is a cross-sectional view for explaining the operation state of the MRAM according to the fourth embodiment of the present invention.

Fig. 41 is a cross-sectional view for explaining the operation state of the MRAM according to the fourth embodiment of the present invention.

Fig. 42 is a cross-sectional view for explaining the operation state of the MRAM according to the fourth embodiment of the present invention.

FIG. 43 is a plan view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 44 is a cross-sectional view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 45 is a cross-sectional view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 46 is a plan view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 47 is a plan view showing the MRAM architecture of the fifth embodiment of the present invention.

Fig. 48 is a plan view showing the MRAM architecture of the fifth embodiment of the present invention.

FIG. 49 is a cross-sectional view showing the structure of a semiconductor substrate according to a sixth embodiment of the present invention.

FIG. 50 is a cross-sectional view showing the structure of a semiconductor substrate according to a sixth embodiment of the present invention.

Figure 51 is a block diagram showing a commonly used MRAM architecture.

FIG. 52 is a block diagram showing the MRAM architecture of the seventh embodiment of the present invention.

FIG. 53 is a block diagram showing the MRAM architecture of the seventh embodiment of the present invention.

FIG. 54 is a cross-sectional view showing the MRAM architecture that is commonly packaged.

FIG. 55 is a cross-sectional view showing the MRAM architecture that is commonly packaged.

FIG. 56 is a cross-sectional view showing the MRAM architecture of the eighth embodiment of the present invention.

Fig. 57 is a plan view showing the MRAM architecture of the eighth embodiment of the present invention.

Fig. 58 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 59 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 60 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 61 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 62 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 63 is a plan view for explaining a partial structure of the MRAM according to the eighth embodiment of the present invention.

64A and B are cross-sectional views for explaining a partial structure of the MRAM according to the eighth embodiment of the present invention.

FIG. 65 is a cross-sectional view showing the MRAM architecture of the eighth embodiment of the present invention.

FIG. 66 is a cross-sectional view showing the MRAM architecture of the eighth embodiment of the present invention.

FIG. 67 is a diagram showing the concept of magnetic tunnel junction.

Fig. 68 is a schematic diagram showing the state density of the transition metal.

Fig. 69 is a schematic diagram for explaining the tunneling magnetoresistance effect.

Fig. 70 is a schematic diagram for explaining the effect of tunneling magnetoresistance.

FIG. 71 is a diagram showing an example of the structure of the magnetic tunnel junction.

FIG. 72 is a diagram showing an example of the structure of the magnetic tunnel junction.

Fig. 73 is a diagram showing a substantial example of a spin valve type ferromagnetic tunnel junction element.

FIG. 74 is a diagram showing the essential characteristics of the spin valve type ferromagnetic tunnel junction device.

FIG. 75 is an oblique view showing the architecture of the previous MRAM cell array.

FIG. 76 is an oblique view showing the architecture of the previous MRAM cell array.

FIG. 77 is an equivalent circuit diagram of the structure of the previous MRAM cell array.

FIG. 78 is a diagram for explaining the working state of the previous MRAM cell array.

[Technical field of the invention]

The present invention relates to a magnetic memory device, which has a non-volatile memory array that uses a magnetic tunnel junction as each memory cell.

[Prior Art] (Tunneling Magnetoresistance Effect)

The structure in which two ferromagnetic materials are sandwiched between the insulators is called "Magnetic Tunnel Junction (MTJ)". Figure 67 is a schematic diagram of MTJ. In FIG. 67, the insulating layer TB is sandwiched and arranged by ferromagnetic layers FM21 and FM22, and has a structure in which a voltage is applied to the ferromagnetic layers FM21 and FM22.

In this structure, by measuring the current passing through the insulating layer TB, it can be observed that the current value will be different according to the different magnetization directions of the two ferromagnetic layers.

This phenomenon is called the tunnel magnetic resistance (TMR) effect. Regarding the TMR effect, use Fig. 68 to Fig. 70 to explain as follows.

Fig. 68 is a schematic diagram showing the state density N(E) of transition metals. In Fig. 68, the abscissa axis represents the state density, and the ordinate axis represents the energy E, plus the electrons classified by the spin direction and showing the atoms possessed. In other words, looking at Fig. 68, the left side shows the state density of atoms with spin-down electrons, and the right side shows the state density of atoms with spin-up electrons.

In addition, in Fig. 68, in the 3d orbital and 4S orbital, in order to display the atoms that are filled with electrons to the Fermi level in a mode, the Fermi level is used as the limit, and the hatching shows that the electrons are filled to reach the Fermi level. Atoms up to the Fermi level.

The transition metal becomes a ferromagnetic body because of the difference in the relationship between the number of spin-up and the spin-down in the 3d orbital in atoms that are filled with electrons until they reach the Fermi level.

In other words, the 4S orbital electron system has the same number of spin-up and spin-down times, so it does not involve magnetism.

Fig. 69 and Fig. 70 are diagrams showing the TMR effect in a mode. In FIG. 69, in the 3d orbital of the atoms constituting the ferromagnetic layer FM21 on the left side of the insulating layer TB, the state density of the atom with the spin-down electron is higher than the state of the atom with the spin-up electron Density, so the direction of magnetization becomes downward as a whole.

The ferromagnetic body F22 on the right side of the insulating layer TB is also downward as the direction of magnetization.

The tunneling effect of electrons is mainly caused by preserving the spin direction of the start state and the end state. In Figure 69, both the start state (in the ferromagnetic layer FM21) and the end state (in the ferromagnetic layer FM22) of the downward spin state density are both large, which increases the tunneling probability, resulting in tunneling. The increase in current. That is, the tunneling magnetoresistance is reduced.

In contrast, in FIG. 70, although the state density of the atoms with spin-up electrons in the starting state (in the ferromagnetic layer FM21) is large, it is because the end state (in the ferromagnetic layer FM22) has the spin-up The atomic state density of electrons is smaller, so the tunneling probability is also reduced, so that the tunneling current is reduced. That is, the tunneling magnetoresistance is increased.

Here, the resistance when the magnetization directions of the two ferromagnetic layers are the same is R _F , And its reverse resistance is R _AF , Its tunnel magnetic resistance ratio (Tunnel Magnetic Resistance Rate: TMRR) can be expressed by the following formula: (Formula 1)

<maths><img file="TW548656B_D0001.tif" /></maths>

Incidentally, in the above formula (1), P _l , P ₂ , Are the spin polarizing ratios of the ferromagnetic body layers FM21 and FM22, respectively. Furthermore, the state density on the Fermi surface of the α spin band is Dσ(E _F ), the spin polarization rate can be expressed by the following formula: (Equation 2)

<maths><img file="TW548656B_D0002.tif" /></maths>

In other words, as the state density between the spin-up and spin-down spins on the Fermi surface increases, the spin polarization rate also increases. In addition, the spin polarization ratio is close to 1, and the TMR also increases. In addition, it is well known that a proportional relationship between spin polarization and magnetization is established. Here, the spin polarization ratios of various magnetic materials are shown in Table 1:

<tables><img file="TW548656B_D0003.tif" /></tables>

The device that utilizes the above-mentioned TMR effect and makes the magnetization direction of the two ferromagnetic layers correspond to 0 or 1 to store data is called MRAM (Magnetic Random Access Memory).

Therefore, if it is desired to change the magnetization direction of only one of the two ferromagnetic layers of the MTJ, applying a magnetic field with the structure of FIG. 67 still changes the magnetization directions of both ferromagnetic layers. Therefore, for the purpose of fixing the magnetization direction of one ferromagnetic layer, a technical proposal has been proposed in which an anti-ferromagnetic layer is formed on one ferromagnetic layer.

In Figure 71, the ferromagnetic layer is used to sandwich the ferromagnetic layer FM21 and FM22, and the anti-ferromagnetic layer AF is arranged on the upper part of the ferromagnetic layer FM21, and the anti-ferromagnetic layer AF is connected to the positive The negative electrode is connected to the ferromagnetic layer FM22.

If the ferromagnetic body and the anti-ferromagnetic body are formed adjacent to each other, the magnetic flux passing through the two is closed to achieve the fixation of the magnetization direction. This structure is called "spin valve type ferromagnetic tunnel junction element".

In addition, the structure of a modified example of the spin valve type ferromagnetic tunnel junction element is shown in FIG. 72. In FIG. 72, the insulating layer TB is sandwiched by ferromagnetic layers FM21 and FM22, and an anti-ferromagnetic layer AF is provided on the upper part of the ferromagnetic layer FM21, and a strong Magnetic layer FM23.

Here, the anti-ferromagnetic layer AF is composed of TrMn containing 20-30 atom.% Ir (iridium). Although the magnetization direction of the ferromagnetic layer FM21 is illustrated, it is better not to The external magnetic field is reversed, so CoFe, which has a large coercive force, is used as the ferromagnetic layer FM21.

In addition, as explained using formula (1), as the spin polarization ratio increases, the tunneling magnetoresistance change rate will also increase, so CoFe is selected as the material with a larger spin polarization ratio.

In contrast, although the same CoFe as the above is also used for the ferromagnetic layer FM22, it is preferable to use a material with a large coercive force so that the smallest possible external magnetic field is used to control the magnetization direction of the ferromagnetic layer FM.

In the architecture of FIG. 72, for the purpose of reversing the magnetization direction of the ferromagnetic layer FM22, Ni with a smaller spin polarization ratio is used. ₈₀ Fe ₂₀ (Permalloy=permalloy) as the ferromagnetic layer FM23. Thereby, a small external magnetic field can be used to direct the magnetization of the ferromagnetic layer FM22.

FIG. 73 shows the actual structure of the spin valve type ferromagnetic tunnel junction element shown in FIG. 72, and FIG. 74 shows the measured characteristics of the TMR in this structure.

In FIG. 73, an insulating layer TB is arranged on the upper part of the deposited body of the antiferromagnetic layer AF and the ferromagnetic layer FM21 which are arranged on the substrate BD in a plane shape, and the insulating layer TB is arranged on the upper part of the insulating layer TB. Ferromagnetic layer FM23. In this structure, the result of applying an external magnetic field to measure the magnetoresistance MR is shown in Figure 74.

In FIG. 74, the abscissa axis represents the magnetic field (1 oersted=approximately 79 A/m in terms of conversion), and the ordinate axis represents the tunneling magnetic resistivity (TMRR). It can be seen from Figure 74 that TMRR has achieved 36%, and the magnetic field required for the reversal of the magnetization direction is about 30 (×79A/m) as low as 30 (×79A/m), plus a hysteresis symmetrical to the magnetic field direction can be obtained. .

(The structure and working principle of MRAM)

In MRAM, in the magnetic tunnel junction element constituting the memory cell, the external magnetic field is used to control the magnetization direction of the two ferromagnetic bodies to be the same, or to reverse the magnetization direction, and to make the magnetization direction the same. Or it is in the reverse state, corresponding to 0 or 1, and then stores the data.

The stored data can be read by passing a predetermined current through the memory cell and detecting the voltage across the tunneling magnetoresistor. In addition, since the larger the rate of change of the tunneling magnetoresistance value (TMRR), the easier it is to detect. Therefore, a ferromagnetic material with a larger spin polarization rate is beneficial to the use of MRAM.

In addition, for data writing, it is sufficient to change the magnetization direction of one ferromagnetic body by using a magnetic field generated after a predetermined current is applied to the wiring (word line and bit line).

(Structure of MRAM cell)

As a prior art of MRAM, the structure and working state of MRAM disclosed in US Patent No. 5,793,697 are described as follows.

Fig. 75 is an oblique view showing the MRAM cell array and cells. In FIG. 75, the bit lines 4, 5, and 6 are arranged in parallel with each other at the upper part of the word lines 1, 2, and 3 arranged in parallel with each other.

In addition, an MRAM cell (hereinafter only referred to as a cell) 9 is formed at each intersection point sandwiched by the word line and the bit line. As shown in an enlarged view in FIG. 75, the MRAM cell 9 is a structure in which a pn junction diode 7 and a magnetic tunnel junction element (MTJ) 8 are deposited on the word line.

FIG. 76 is a schematic diagram showing the cross-sectional structure of the MRAM cell 9. Incidentally, in FIG. 76, the case where the MRAM cell 9 is formed on the word line 3 is shown as an example. The word line 3 is provided on the silicon substrate 80, and n is deposited thereon. ⁺ Si layer 10 and p ⁺ In the silicon layer 11, a pn junction diode 7 is formed. The pn junction diode 7 is covered with an insulating film such as a silicon oxide film 13 or the like.

Next, a tungsten plug 12 is arranged on the upper portion of the pn junction diode 7, and the pn junction diode 7 is electrically connected to the MTJ 8 via the tungsten plug 12. Incidentally, the silicon oxide film 13 is also arranged to cover the tungsten plug 12, and the surfaces of the tungsten plug 12 and the silicon oxide film 13 are planarized using CMP (Chemical Mechanical Polishing).

The MTJ8 system has a laminated structure, which in turn has: a template layer 15 (thickness of 10nm) composed of platinum (Pt); ₈₁ Fe ₁₉ The initial ferromagnetic body 16 (thickness 4nm) composed of permalloy; composed of Mn ₅₄ Fe ₄₆ Diamagnetic body 18 (thickness 10nm) composed of CoFe or Ni ₈₁ Fe ₁₉ Ferromagnetic body 20 (thickness 8nm) made of permalloy with fixed magnetization direction; made of Al ₂ O ₃ The tunnel barrier layer 22 is composed of CoFe with a thickness of 2nm and Ni with a thickness of 20nm ₈₁ Fe ₁₉ A soft ferromagnetic layer 24 composed of a multilayer film; a contact layer 25 composed of Pt.

Incidentally, for the tunnel barrier layer 22, after depositing Al with a thickness of 1 to 2 nm, the plasma oxidation method is used and the pressure is 25W/cm under an oxygen pressure of 100 mTorr. ² The power density is formed by processing for 60 to 240 seconds.

In addition, although not shown in FIG. 76, in fact, a large MTJ is formed on the entire surface of the silicon oxide film 13 on the silicon substrate 80, and a photoresist mask is used for this and argon ion polishing is used. (argon ion milling) to define the pattern to form the majority of MTJ8 shown in FIG. 8. In addition, although not shown in FIG. 76, the contact layer 25 is connected to the bit line.

The magnetic tunnel resistance of the MTJ8 is different from the case where the magnetization direction of the soft ferromagnetic layer 24 is the same as the magnetization direction of the ferromagnetic body 20 as described above. The magnetization direction of the soft ferromagnetic layer 24 can be changed by the magnetic field generated by the current flowing between the bit line and the word line.

In addition, the magnetic tunnel resistance of the MTJ8 greatly depends on the film material characteristics such as the thickness of the tunnel barrier layer 22, the barrier height, and the thickness of the interface under the junction.

The soft ferromagnetic layer 24 is formed so that it has an easy-to-magnetize direction called an easy axis. The magnetization direction along the easy magnetization axis has two directions, so that it can correspond to the two data of 0 and 1 of the memory cell respectively.

In contrast, the ferromagnetic body 20 has the same magnetization direction as the easy magnetization axis of the soft ferromagnetic layer 24, and is formed without changing the direction depending on the operating state of the MRAM.

The direction of magnetization is referred to as the direction of fixed magnetization (unidirectional anisotropy direction). The easy magnetization axis of the soft ferromagnetic layer 24 is determined by adding the intrinsic anisotropy, stress induced anisotropy, and the anisotropy caused by the shape of the MTJ8.

Here, the so-called intrinsic anisotropy means: the physical properties of the ferromagnetic body are originally magnetized anisotropy, and the stress induced anisotropy means: when stress is applied to the ferromagnetic body The resulting magnetization is anisotropic.

In addition, as shown in Fig. 75, the MTJ8 has a rectangular shape with a long side length of L and a short side length of W as viewed in plan. This is because the anisotropy caused by the shape of the MTJ 8 is used to determine the easy magnetization axis of the soft ferromagnetic layer 24.

Next, a method of setting the fixed magnetization direction of the ferromagnetic body 20 will be described. The initial ferromagnetic body 16 deposited and formed on the stencil layer 15 is deposited with the {111} orientation face ({111} face) facing upward in the crystal direction. In addition, the diamagnetic body 18 made of MnFe is deposited on the initial ferromagnetic body 16.

These magnetic layers are all deposited under a magnetic field oriented toward a magnetization axis of the soft ferromagnetic layer 24 to be deposited later, thereby determining the direction of fixed magnetization of the soft ferromagnetic layer 24.

In addition, the magnetic flux is closed between the ferromagnetic body 20 and the diamagnetic body 18. Therefore, the magnetization direction of the ferromagnetic body 20 is difficult to change the direction by an external magnetic field compared with the magnetization direction of the soft ferromagnetic layer 24. Within the range of the magnetic field generated by the current between the word line and the bit line, the magnetization direction of the ferromagnetic body 20 can be fixed. Furthermore, the MTJ8 has a rectangular shape in plan view, so that magnetization anisotropy caused by the shape of the ferromagnetic body 20 is generated. This phenomenon also contributes to stabilizing the magnetization direction of the ferromagnetic body 20.

(Summary of MRAM write/read work)

The MRAM write/read operation is explained as follows.

For the word lines and bit lines used for address selection (referred to as word line selection and bit line selection) to flow a predetermined current, the magnetic field is generated at the periphery of each line, so that at the intersection of the two lines (selection Address) generates a combined magnetic field that joins each magnetic field. Once the magnetic field is applied, the magnetization direction of the soft ferromagnetic layer 24 of the MTJ8 arranged at the intersection of the two lines can be changed within the layer, so that data writing can be performed.

The magnitude of the magnetic field is designed to be larger than the switching magnetic field of the soft ferromagnetic layer 24 (that is, the direction of magnetization starts to change), which is mainly determined by the coercive force and magnetization anisotropy of the soft ferromagnetic layer 24.

In addition, the magnetic field generated at the periphery of the selected word line and the selected bit line must be designed to be relatively small to avoid changing the direction of the fixed magnetization of the ferromagnetic body 20. This is because the magnetization direction of the half select unit is not changed. Incidentally, the so-called semi-selected cell is a cell in which current flows only on one of the word line and the bit line located above and below it.

In this way, for the architecture of the memory cell array, it is designed so that the writing current does not flow directly into the MTJ8, so as to reduce the power consumption during the writing operation.

In addition, the data written in the MRAM cell 9 is detected by detecting the current flowing vertically between the pn junction diode 7 and the MTJ 8 to read it. Incidentally, when it is in the working state, the tunneling current circulates longitudinally in the MRAM cell 9 so that the occupied area of the MRAM cell 9 is reduced.

In MTJ8 by Al ₂ O ₃ The resistance of the formed tunnel barrier layer 22 varies exponentially with respect to the thickness of the film. In other words, if the thickness of the film becomes thicker, the current flowing in the tunnel barrier is reduced, and only the current passing through the tunnel junction can flow perpendicularly to the junction.

Furthermore, the data of the MRAM cell 9 is read by monitoring the voltage of the MRAM cell 9. The voltage is generated when the detection current, which is significantly smaller than the writing current, circulates vertically.

As mentioned above, the tunneling probability of MTJ8 is based on the spin state density of the same polarity as the spin polarity in the soft ferromagnetic layer 24 at the beginning. Increase.

Therefore, the magnetic tunnel resistance of MTJ8 is low when the spin state density of the soft ferromagnetic layer 24 and the ferromagnetic body 20 are both the same, in other words, when the magnetization directions of the two layers are the same, and The direction of magnetization is reversed and higher. Therefore, only by monitoring the resistance of the MTJ8 with a small current, the data of the MRAM cell 9 can be read.

Incidentally, the magnetic field generated by the detection current can also be ignored, and the magnetization state of the MRAM cell 9 should not be involved. In addition, the wiring required to read/write the MRAM cell 9 is only the array of bit lines and word lines shown in FIG. 75, so a memory cell array with high efficiency can be constructed.

(Write work)

For the MRAM writing operation, use Fig. 77 and Fig. 78 to further explain as follows.

FIG. 77 is an equivalent circuit diagram of the memory cell array shown in FIG. 75. The two ends of the word lines 1 to 3 are connected to the word line control circuit 53, and the bit lines 4 to 6 are connected to the bit line control circuit. On circuit 51. Incidentally, in order to facilitate the description of FIG. 78, word lines 1 to 3 are represented by word lines WL1 to WL3, and bit lines 4 to 6 are represented by bit lines BL4 to BL6. Furthermore, at the intersections of word lines 1 to 3 and bit lines 4 to 6, MTJ8 represented by a resistance symbol and a pn junction diode 7 represented by a diode symbol are arranged.

Here, assuming that the word line 1 and the bit line 4 are selected, the MRAM cell 9a located at the intersection of the two is selected.

The selected MRAM cell 9a uses the current I flowing on the bit line 4 _B , And the current I flowing on word line 1 _W The generated combined magnetic field is used to write.

At current I _B And current I _W The magnetic field generated by any one of them in the cell area alone is smaller than the magnetic field required to change the magnetization direction of the soft ferromagnetic layer 24 of the MTJ8.

Therefore, for the MRAM cells 9b-9e as half-selected cells (the cells are the word lines and bit lines, only the current I _B Or current I _W On either side), no writing work has been performed.

However, if the current I _B And current I _W The resulting magnetic fields are combined, and it becomes a magnetic field capable of changing the magnetization direction of the soft ferromagnetic layer 24 of the selected MRAM cell 9a.

Incidentally, the current I _B And current I _W Either one of them is designed to circulate in both directions so that the magnetization direction of the soft ferromagnetic layer 24 of the unit 9a becomes two opposite magnetization directions. In addition, in FIG. 77, the bit line control circuit 51 and the word line control circuit 53 are both formed in pairs, so the current I _B And current I _W Both sides can change the direction of the current.

Fig. 78 is a timing chart showing the voltage and current of bit lines 4~6 (bit lines BL4~BL6) and word lines 1~3 (word lines WL1~WL3).

As shown in FIG. 78, the voltages of the bit lines BL4 to BL6 when writing is performed are designed to facilitate the flow of current in both directions. In addition, the voltages of the word lines WL1~WL3 are all greater than the voltage V _b , And set to positive voltage V _W 。

In addition, these currents are all set to: when in the standby state, a bias voltage is applied to the pn junction diodes 7 of all the cells 9. Therefore, it is possible to prevent the current I from flowing in the memory cell during standby. _B And current I _W Situation.

(Read work)

Secondly, for the MRAM read operation, use FIG. 77 and FIG. 78 to further explain the following. As shown in Figure 78, the voltage of the word line WL1 is changed from V _W Down to V _b , And change the voltage of bit line BL4 from V _b Raise to V _W , To apply a positive bias to the pn junction diode 7 of the selected cell 9a.

When performing a read operation, the non-selected bit lines 5 and 6 are still at the standby voltage V _b Instead of selecting word lines WL2 and 3, both are still at standby voltage V _W middle.

Incidentally, in the half-selected cells 9b-9e, there is no voltage drop from the word line to the bit line (that is, 0V is applied to the pn junction diode 7), so that current flowing in the cell can be avoided.

The magnetic tunnel resistance of the selected cell 9a determines the magnitude of the detection current 30 (see FIG. 77) flowing from the bit line BL4 and through the cell 9a to the word line WL1. In the detection circuit used to form a part of the bit line control circuit 51, the average value of the two predictable current values corresponding to the two states of the cell is used as the reference current for comparison with the detection current . Then, the phase difference between the two currents is amplified to read the data stored in the selection unit 9a.

Incidentally, as shown in the waveform of the detection current 30 in FIG. 77, the detection current 30 exhibits two current waveforms equivalent to the two magnetization states of the MTJ8.

After reading the data, the voltages of the bit line BL4 and the word line WL1 respectively return to the standby value, but the magnetization state of the memory cell 9a can be maintained even after reading.

[Problems to be solved by the present invention]

As described above, when a write operation is performed on the MRAM cell, current flows on the bit line and the word line to generate a magnetic field. Furthermore, for the memory cell of the selected address, a magnetic field larger than the switching magnetic field of the soft ferromagnetic layer used to form the cell must be applied, so a relatively large current must flow. Therefore, there is a problem that the power consumption when performing the writing operation increases.

The present invention is made to solve the above-mentioned problems. The first object is to provide an MRAM, which reduces the power consumption when performing a write operation.

In addition, in the previous MRAM memory cells, there is still a problem: If a memory cell block composed of at least one memory cell is used to perform data erasing or writing together, it will take more time.

The second object of the present invention is to provide an MRAM, which shortens the time required for erasing or writing.

[Means to solve the problem]

Regarding the magnetic memory device of the present invention, it is a magnetic memory device, which has: a plurality of bit lines and a plurality of word lines, which cross in a non-contact manner, and are used to form an array substrate; and a plurality of memory cells are separate It is arranged at the intersection of the above-mentioned plurality of bit lines and the above-mentioned plurality of word lines, and contains at least one magnetic tunnel junction, and it is: the above-mentioned plurality of memory cells are respectively arranged in the above-mentioned plurality of bit lines The magnetic tunnel junction of at least one of the element lines and one of the plurality of word lines mentioned above has a soft ferromagnetic layer whose magnetization direction can be changed, and at least one of the above The magnetic tunnel junction is the easy axis of magnetization in the direction in which the soft ferromagnetic layer is easier to be magnetized. Assume.

Regarding the magnetic memory device of the present invention, in the magnetic tunnel junction, a side parallel to the easy axis of magnetization has a shape in plan view that is longer than a side perpendicular to the easy axis of magnetization and has a rectangular configuration. .

Regarding the magnetic memory device of the present invention, it is a magnetic memory device that has: a plurality of bit lines and a plurality of word lines, which cross in a non-contact manner, and are used to form an array substrate; a plurality of memory cells, In order to be respectively arranged at the intersections of the plurality of bit lines and the plurality of word lines, and include at least one magnetic tunnel junction, it is a first switching device having a plurality of pieces, which are respectively connected to The electrical connection between the first end and the first power supply or the second power supply can be switched at the first end of the plurality of bit lines; the second switching device of the majority is connected to At the second end of the plurality of bit lines, the electrical connection between the second end and the first power source or the second power source can be switched.

Regarding the magnetic memory device of the present invention, it is the above-mentioned first switching device, the first and second MOS transistors having the same conductivity, and each of the first main electrodes is connected to the first end of the plurality of bit lines. And each second main electrode is connected to the first power supply and the second power supply, and the second switching device, the third and fourth MOS transistors with the same conductivity, is each A main electrode is connected to the second end of the plurality of bit lines, and each second main electrode is connected to the first power source and the second power source.

Regarding the magnetic memory device of the present invention, it is the above-mentioned first switching device, the first and second MOS transistors having different electrical conductivity, which are each first main electrode connected to the first end of the plurality of bit lines. And each second main electrode is connected to the first power source and the second power source, and the second switching device, the third and fourth MOS transistors with different conductivity, is for each A main electrode is connected to the second end of the plurality of bit lines, and each second main electrode is connected to the first power source and the second power source.

Regarding the magnetic memory device of the present invention, it further has: a fifth MOS transistor, which is connected to each of the first main electrodes of the first and second MOS transistors, and is equipped with the second MOS transistor The same conductivity; the sixth MOS transistor, which is connected to each of the first main electrodes of the third and fourth MOS transistors, and has the same conductivity as the fourth MOS transistor, and the fifth And the control electrode of the sixth MOS transistor is connected to a third power source for applying a predetermined voltage to make the normal state ON.

Regarding the magnetic memory device of the present invention, there is at least one memory cell array group, which is provided with: a plurality of memory cell arrays, which intersect in a non-contact manner, and are used to form a plurality of bit lines and a plurality of words of the array substrate Lines, and a plurality of memory cells respectively arranged at the intersections of the above-mentioned plurality of bit lines and the above-mentioned plurality of word lines, and containing at least one magnetic tunnel junction, and the like; the main word line is a cross Are arranged in the plurality of memory cell arrays; a plurality of memory cell array selection lines are arranged corresponding to each of the plurality of memory cell arrays, and the plurality of word lines are respectively connected to the plurality of The output of the first combinational logic gate arranged at the intersection of the main word line and the plurality of memory cell array selection lines, and the input of the first combinational logic gate is connected to the plurality of main word lines in the cross state On one of the above-mentioned multiple memory cell array selection lines.

The magnetic memory device of the present invention has a plurality of the above at least one memory cell array group, and further has: a universal word line, which is arranged across the plurality of memory cell array groups; and a plurality of memory cell array group selection lines are Corresponding to each block of the plurality of memory cell array groups, and the plurality of main word lines are respectively connected to the intersections of the plurality of general word lines and the selection lines of the plurality of memory cell array groups. Set the output of the second combinational logic gate, and the input of the second combinational logic gate is connected to one of the plurality of general word lines in the cross state and one of the selection lines of the plurality of memory cell array groups One on.

Regarding the magnetic memory device of the present invention, there is at least one memory cell array group, which is provided with: a plurality of memory cell arrays, which cross in a non-contact manner, and are used to form a plurality of bit lines and a plurality of words of the array substrate Lines, and a plurality of memory cells respectively arranged at the intersections of the above-mentioned plurality of bit lines and the above-mentioned plurality of word lines, and containing at least one magnetic tunnel junction, and the like; the main bit line is The plurality of memory cell arrays are arranged across the plurality of memory cell arrays; the plurality of memory cell array selection lines are arranged to correspond to each of the plurality of memory cell arrays, and the plurality of bit lines are respectively connected to the respective The output of the first combinational logic gate is arranged at the intersection of the majority of the master bit lines and the plurality of memory cell array selection lines, and the input of the first combinational logic gate is connected to the plurality of masters in the cross state. One of the bit lines and one of the multiple memory cell array selection lines mentioned above.

Regarding the magnetic memory device of the present invention, there are a plurality of at least one memory cell array group described above, and further have: a common bit line, which is arranged across the plurality of memory cell array groups; and a plurality of memory cell array group selection lines, It is arranged to correspond to each block of the plurality of memory cell array groups, and the plurality of main bit lines are respectively connected to the plurality of general bit lines and the selection lines of the plurality of memory cell array groups. The output of the second combinational logic gate is arranged at the intersection, and the input of the second combinational logic gate is connected to one of the plurality of general bit lines in the cross state and the selection of the plurality of memory cell array groups On one of the lines.

Regarding the magnetic memory device of the present invention, it has: a memory cell array that crosses in a non-contact manner and is used to form a plurality of bit lines and a plurality of word lines of the array substrate, and are respectively arranged in the plurality of bit lines The intersection of the line and the above-mentioned plurality of word lines, and contains at least one of the magnetic tunnel junctions, and the plurality of memory cells are composed of them; inductors, and the at least one of the above-mentioned magnetic tunnel junctions has the ability to change its The soft ferromagnetic layer in the magnetization direction, and the above-mentioned inductor generates a magnetic field along the easy axis of magnetization in the direction in which the soft ferromagnetic layer is easily magnetized.

Regarding the magnetic memory device of the present invention, at least one of the above-mentioned magnetic tunnel junctions is arranged so that the easy axis of magnetization can coincide with the extending direction of the plurality of bit lines or the plurality of word lines. The inductor, The coil-shaped inductor is arranged along the extending direction of the plurality of bit lines or the plurality of word lines that coincide with the direction of the easy axis of magnetization, and the memory cell array is wound.

With regard to the magnetic memory device of the present invention, there is: at least one memory cell array, which crosses in a non-contact manner, and is used to form a plurality of bit lines and a plurality of word lines of the array substrate, and are respectively arranged in the plurality of The intersection of a bit line and the above-mentioned plurality of word lines, and a plurality of memory cells containing at least one magnetic tunnel junction, and the like are formed; at least one flash bit line in the shape of a flat plate is installed separately Outside of the plurality of bit lines and the plurality of word lines in the at least one memory cell array, and covering the formation area of the plurality of bit lines and the plurality of word lines; at least one flash word line.

With regard to the magnetic memory device of the present invention, there are a plurality of the at least one memory cell array, and the plurality of memory cell arrays are arranged in an array, and the at least one flash bit line and at least one flash The word lines are arranged along the array of the above-mentioned multiple memory cell arrays to form the array base and are respectively arranged.

Regarding the magnetic memory device of the present invention, it has: a memory cell array that crosses in a non-contact manner and is used to form a plurality of bit lines and a plurality of word lines of the array substrate, and are respectively arranged in the plurality of bit lines The intersection of the line and the plurality of word lines, and containing at least one magnetic tunnel junction of a plurality of memory cells, and the like; the inductors are respectively arranged on the plurality of bit lines and the plurality of At two ends of at least one of the word lines, the current flowing on at least one of the selected bit line and the word line is stored by LC resonance; at least one capacitor.

The magnetic memory device of the present invention has a plurality of the above-mentioned at least one inductor and the above-mentioned at least one capacitor, and the plurality of bit lines are two pairs to form a bit line group, and the plurality of inductors The device includes a first inductor, which corresponds to each of the above-mentioned plurality of bit line groups, and is arranged to be electrically connected between the bit lines, and the above-mentioned plurality of capacitors includes the first The capacitor is connected to each of the plurality of bit lines corresponding to the above-mentioned plurality of bit lines with conductivity at the other end of the place where the above-mentioned plurality of inductors are arranged.

Regarding the magnetic memory device of the present invention, the above-mentioned plurality of word lines are composed of two pairs to form a plurality of word line groups, and the above-mentioned plurality of inductors includes a second inductor, which corresponds to the above-mentioned plurality of bit lines. Each group of the group is arranged to be conductively connected between the word lines, and the above-mentioned multi-unit capacitors further include a second capacitor, which is located at the other end of the place where the above-mentioned multi-unit inductors are arranged , Each corresponding to the above-mentioned plurality of bit lines is connected with conductivity.

Regarding the magnetic memory device of the present invention, it has: a shielding body composed of at least one semiconductor chip and a conductor, and used for accommodating the above-mentioned at least one semiconductor chip; The shielding body is accommodated; the bottom substrate is closed and sealed to the opening of the package body; the bumps for signal transmission are arranged on the bottom substrate and perform signal transmission between the at least one semiconductor chip and the outside; shielding The bumps are arranged around the bumps for signal transmission and are electrically connected to the shielding body. The at least one semiconductor chip contains a magnetic memory chip and is equipped with a magnetic tunnel junction. The majority of memory cells form a memory cell array.

Regarding the magnetic memory device of the present invention, it further has: a first stress relaxation film arranged on the inside and outside of the edge of the opening of the shielding body; and a second stress relaxation film arranged on the inner wall surface of the shielding body superior.

With regard to the magnetic memory device of the present invention, the above-mentioned at least one semiconductor chip, further including a circuit chip, is a peripheral circuit including the above-mentioned memory cell array, and the above-mentioned magnetic memory chip and the above-mentioned circuit chip are stacked up and down. Housed in the above-mentioned shielding body.

With regard to the magnetic memory device of the present invention, at least one magnetic tunnel junction is provided with a soft ferromagnetic layer capable of changing the magnetization direction, and the shielding body is composed of a magnetic permeability equal to or greater than that of the soft ferromagnetic layer. It is composed of ferromagnetic material.

Regarding the magnetic memory device of the present invention, the above-mentioned shielding body is composed of an anti-ferromagnetic body.

Regarding the magnetic memory device of the present invention, the aforementioned shielding body is composed of a multilayer film of a ferromagnetic body and an anti-ferromagnetic body.

Regarding the magnetic memory device of the present invention, it has at least a multilayer film, which is arranged on the entire area of its main surface and forms at least one magnetic tunnel junction.

Regarding the magnetic memory device of the present invention, the above-mentioned multilayer film is used as at least one of the above-mentioned magnetic tunnel junctions, and contains a tunnel barrier layer and a soft ferromagnetic layer. It is configured by configuration.

Regarding the magnetic memory device of the present invention, it is the above-mentioned multilayer film, and further contains: a double-layer film, which is arranged at the lower part of at least one of the above-mentioned magnetic tunnel junctions and will be used to form the first conductivity type impurity of the pn junction The layer and the second conductivity type impurity layer are laminated.

Regarding the magnetic memory device of the present invention, the above-mentioned multilayer film is provided on an SOI substrate, and the SOI substrate includes: a substrate portion serving as a base; an embedded oxide film disposed on the substrate portion; an SOI layer, It is arranged on the buried oxide film.

[Embodiment of the invention] (A. First embodiment) (Characteristics of this embodiment)

Regarding the MRAM of the first embodiment of the present invention, it is characterized in that the easy magnetization axis of the soft ferromagnetic layer constituting the MRAM cell is not parallel to the bit line and the word line, and more specifically, is the same as the bit line and the word line. The line is 40-50 degrees and equipped with MRAM cells.

(A-1. Device architecture) (A-1-1. MRAM unit architecture)

First, for the representative architecture of the MRAM cell, use FIG. 1 to illustrate. The MRAM cell MC shown in FIG. 1 has a pn junction diode 7, which is used to make n ⁺ Si layer 10 and p ⁺ The silicon layer 11 is deposited and formed.

In addition, a tungsten plug 12 is arranged on the upper portion of the pn junction diode 7, and the pn junction diode 7 is electrically connected to a magnetic tunnel junction (Magnetic Tunnel Junction: MTJ) 8 through the tungsten plug 12.

The MTJ8 system has a laminated structure, which in turn has: a template layer 15 (thickness of 10nm) composed of platinum (Pt); ₈₁ Fe ₁₉ The initial ferromagnetic body 16 (thickness 4nm) composed of permalloy; composed of Mn ₅₄ Fe ₄₆ Diamagnetic body 18 (thickness 10nm) composed of CoFe or Ni ₈₁ Fe ₁₉ The ferromagnetic body 20 (thickness 8nm) is composed of permalloy and has a magnetization pattern; it is made of Al ₂ O ₃ The tunnel barrier layer 22 is composed of CoFe with a thickness of 2nm and Ni with a thickness of 20nm ₈₁ Fe ₁₉ A soft ferromagnetic layer 24 composed of a multilayer film; a contact layer 25 composed of Pt.

The MRAM cell MC containing the MTJ8 has a rectangular shape in plan view, and the direction parallel to the long side thereof is set as the easy magnetization axis of the electron spin direction of the soft ferromagnetic layer 24. Incidentally, the direction parallel to the short side is the hard axis of the hard magnetization direction.

(A-1-2. Further discussion on the previous MRAM cell array)

The plane structure of the previous MRAM cell array is shown in FIG. 2. As for the MRAM cell MC1, it is shown in an oblique view for easy reference.

As shown in FIG. 2, at the upper portion of a plurality of word lines WL1 arranged in parallel to each other, a plurality of bit lines BL1 arranged in parallel to each other are arranged to cross.

Furthermore, at each point sandwiched by the word line and the bit line, an MRAM cell (hereinafter referred to as a cell for short) MC1 is formed. Incidentally, the arrow displayed in a mode in each MRAM cell MC1 shows the spin direction of the soft ferromagnetic layer 24 of the MRAM cell MC1, and it is in the standby state as shown in FIG. 2 in all the MRAM cells MC1 The spin direction of is to the right. As for the architecture of the MRAM cell MC1, although it is the same as the MRAM cell MC shown in FIG. 1, for example, it is not limited to this architecture.

FIG. 3 is a plan view schematically showing the state of writing in the previous MRAM cell array. Incidentally, in the following, there may be cases where the symbols of MC1a, MC1b, and MC1c are added to the MRAM cell MC1 for easy distinction.

When performing writing, a predetermined current flows on the word line and bit line (called selected word line and selected bit line) used for address selection, according to Biot-Savart's law (Biot-savart) The magnetic field is generated around the current. Here, the magnetic field generated around the bit line is Hx, and the magnetic field generated around the word line is Hy. Next, select the word line and select the bit line, respectively, marked as WL1a and BL1a for easy identification.

Incidentally, the current direction in FIG. 3 is from bottom to top on the selected bit line BL1b, and from top to bottom on the selected word line WL1a.

Once a predetermined current flows on the selected word line WL1a and the selected bit line BL1b, the magnetic field Hx and the magnetic field Hy are combined at the intersection of the two lines (selection address). Once the combined magnetic field is applied, the magnetization direction of the soft ferromagnetic layer 24 of the MRAM cell MC1a at the intersection of the selected word line WL1a and the selected bit line BL1b changes within the plane, and data writing can be performed. In FIG. 3, the spin direction of the MRAM cell MC1a is rotated 90 degrees or more and is displayed.

Then, due to the magnetization anisotropy caused by the cell shape, its spin rotates in the direction of the easy magnetization axis, and finally the spin is reversed (180 degrees).

In contrast, the MRAM cell of 9 is selected (half-select) only for one half of the current flowing on one of the word lines and bit lines located above and below it, that is, on the majority of MRAM cells MC1b shown in FIG. 3, Various currents are set so that the spin of the soft ferromagnetic layer 24 can be rotated, but not reversed.

Incidentally, in the majority of semi-selected cells MC1c formed by the selected bit line BL1a, the magnetic field Hx generated around the selected bit line BL1b is in the same direction as the easy magnetization axis, so only the magnetic field Hx cannot cause the graph 3 larger rotation shown above.

The above-mentioned three magnetic field correlations when the combined magnetic field of the magnetic fields Hx and Hy are used to form the magnetic field Hk required to rotate the spins are shown in FIG. 4. In Fig. 4, the abscissa axis represents the magnetic field Hx, and the ordinate axis represents Hy. In addition, the relationship between these is shown in the formula as follows: (Formula 3)

<maths><img file="TW548656B_D0004.tif" /></maths>

The curve in Figure 4 is called the Asteroid curve. If the magnetic field Hk is expressed by the following formula (4), the spin of the soft ferromagnetic layer 24 can be reversed. (Formula 4)

<maths><img file="TW548656B_D0005.tif" /></maths>

In addition, if the magnetic field Hk is expressed by the following formula (5), the spin direction of the soft ferromagnetic layer 24 can be maintained. (Formula 5)

<maths><img file="TW548656B_D0006.tif" /></maths>

The magnetic flux density B generated around the steady current I is based on Biot-Savarts law and can be expressed by the following formula: (Equation 6)

<maths><img file="TW548656B_D0007.tif" /></maths>

Here, μ is the permeability, and R is the distance from the current I. In addition, between the magnetic field H and the magnetic flux density B, the relationship expressed by the following formula (7) can be established: (Equation 7) B=μH ... (7) Therefore, the following formula (8) can be established: ( Formula 8)

<maths><img file="TW548656B_D0008.tif" /></maths>

From the above formula (8), it can be seen that the magnetic field H and the steady current I are directly proportional. Therefore, in order to reduce the power consumption during the writing operation, it is preferable to reduce the magnetic field Hk required for reversing the spin, that is, to reduce the Hx+Hy as much as possible.

Based on the above-mentioned research of the prior art, the inventors have achieved an MRAM cell array architecture that can reduce the magnetic field Hk.

(A-1-3. Structure and work of MRAM cell array)

The planar structure of the MRAM cell array MA10 related to the first embodiment of the present invention is shown in FIG. 5. As shown in FIG. 5, at the upper part of the plurality of word lines WL1 arranged in parallel to each other, a plurality of bit lines BL1 arranged in parallel to each other are arranged in a crosswise manner.

Furthermore, at each intersection point sandwiched by the word line and the bit line, an MRAM cell MC2 is formed. Incidentally, although the structure of the MRAM cell MC2 is the same as that of the MRAM cell MC shown in FIG. 1, for example, it is not limited to this structure.

As shown in FIG. 5, the easy magnetization axis is inclined at 45 degrees with respect to the bit line and the word line, and each MRAM cell MC3 is installed. Incidentally, in this embodiment, it is arranged at an inclination of 45 degrees with respect to the word line WL1. Therefore, in the standby state as shown in FIG. 5, the spin directions of all MRAM cells MC2 are diagonally upward to the right.

FIG. 6 is a plan view schematically showing the writing state of the MRAM cell array MA10. Incidentally, the symbols of MC2a, MC2b, and MC2c will be added to the MRAM cell MC2 below for easy distinction.

Once a predetermined current flows to the word line WL1a and the bit line BL1b, the magnetic field Hx and the magnetic field Hy are combined at the intersection of the two lines (selecting the address). In addition, the current flow direction in FIG. 6 is from bottom to top on the bit line BL1b, and from left to right on the word line WL1a.

Once the combined magnetic field is applied, the magnetization direction of the soft ferromagnetic layer 24 of the MRAM cell MC1a of the device at the intersection of the selected word line WL1a and the selected bit line BL1b is changed within the plane, and data writing can be performed. In FIG. 6, the spin direction of the MRAM cell MC2a is rotated 90 degrees or more and is displayed.

Then, due to the magnetization anisotropy caused by the cell shape, its spin rotates in the direction of the easy magnetization axis, and finally the spin is reversed (180 degrees).

In contrast, the MRAM cell of 9 is only half-selected for one half of the current flowing on one of the word lines and bit lines located above and below, that is, the majority of MRAM cells MC2b and MC2c shown in FIG. 6 Above, various currents are set so that the spin of the soft ferromagnetic layer 24 can be rotated, but not reversed.

Here, the majority of the semi-selected cells MC2c formed by the selected bit line BL1a are due to the magnetic field Hx generated around the selected bit line BL1a, which crosses the direction of the easy magnetization axis at about 45 degrees, so as shown in Figure 6 The spin of the soft ferromagnetic layer 24 is shown to rotate, but by adjusting the magnitude of each voltage, the spin can be reversed or not. This principle is also the same in the majority of half-selected cells MC2b formed by the selected word line WL1a.

(A-1-4. Other structure examples)

As another example of the architecture of the first embodiment, the planar architecture of the MRAM cell array MA20 is shown in FIG. 7. As shown in FIG. 7, at the upper portion of a plurality of word lines WL1 arranged in parallel to each other, a plurality of bit lines BL1 arranged in parallel to each other are arranged to cross.

Furthermore, at each intersection point sandwiched by the word line and the bit line, an MRAM cell MC3 is formed. Incidentally, although the structure of the MRAM cell MC3 is the same as that of the MRAM cell MC shown in FIG. 1, for example, it is not limited to this structure.

As shown in FIG. 7, the easy magnetization axis is inclined at 45 degrees with respect to the bit line and the word line, and each MRAM cell MC3 is installed. Incidentally, in this embodiment, it is arranged at an inclination of 45 degrees with respect to the word line WL1. Therefore, in the standby state as shown in FIG. 7, the spin direction of all the MRAM cells MC3 is diagonally downward to the right.

FIG. 8 is a plan view schematically showing the writing state of the MRAM cell array MA20. Incidentally, the symbols of MC3a, MC3b, and MC3c will be added to the MRAM cell MC3 below for easy distinction.

Once a predetermined current flows to the word line WL1a and the bit line BL1b, the magnetic field Hx and the magnetic field Hy are combined at the intersection of the two lines (selecting the address).

In addition, the current flow direction in FIG. 8 is from bottom to top on the bit line BL1b, and from left to right on the word line WL1a.

Once the combined magnetic field is applied, the magnetization direction of the soft ferromagnetic layer 24 of the MRAM cell MC3a at the intersection of the selected word line WL1a and the selected bit line BL1b is changed within the layer, and data writing can be performed. In FIG. 8, the spin direction of the MRAM cell MC3a is rotated 90 degrees or more and is displayed.

Then, due to the magnetization anisotropy caused by the cell shape, its spin rotates in the direction of the easy magnetization axis, and finally the spin is reversed (180 degrees).

In contrast, the majority of MRAM cells MC2b and MC2c, which are the semi-selected cells shown in FIG. 8, are set with various currents so that the spin of the soft ferromagnetic layer 24 can be rotated, but not reversed. .

(A-1-5. Optimization of MRAM cell arrangement direction)

Next, using FIGS. 9-25, the optimization of the MRAM cell will be described.

First, the case where the combined magnetic field Hk is used to invert the spin will be described.

The relationship between the spin direction of the MRAM cell MC1a at the selected address during the write operation in the previous MRAM cell shown in FIG. 2 and the direction of the combined magnetic field Hk that it reverses is shown in a model in FIGS. 9 and Figure 10.

In Fig. 9 and Fig. 10, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle between the spin and the combined magnetic field Hk is θ ₁ = 135 degrees.

In addition, the relationship between the spin direction of the MRAM cell MC2a of the selected address during the write operation in the MRAM cell array MA10 shown in FIG. Figure 11 and Figure 12.

In Fig. 11 and Fig. 12, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle presented by the spin and the combined magnetic field Hk is θ ₂ = 90 degrees.

In addition, the relationship between the spin direction of the MRAM cell MC3a at the selected address during the write operation in the MRAM cell array MA20 shown in FIG. 7 and the direction of the combined magnetic field Hk that is reversed is shown in a model Figure 13 and Figure 14.

In Figure 13 and Figure 14, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle between the spin and the combined magnetic field Hk is θ ₃ = 180 degrees.

Again, the relationship between the combined magnetic field Hk and the magnetic fields Hx and Hy is shown in FIG. 15. Although this relationship is the same as that shown in the Asteroid curve in Figure 4, under the condition of "|Hx|+|Hy|=constant", that is, under the condition of a certain write current, the Asteroid curve For the magnetic fields Hx and Hy, the relationship of Hx=Hy=Hk/22 is obtained.

Based on this result, in the previous MRAM cell array shown in FIGS. 9 and 10, the combined magnetic field Hk is used to rotate the spin to approximately 135 degrees, and then the shape-based magnetization anisotropy is used to rotate the spin to 180 degrees. Degree.

On the other hand, in the MRAM cell array MA10 shown in FIGS. 11 and 12, the spin is rotated to approximately 90 degrees with the combined magnetic field of the same magnitude. Therefore, even if the shape-like magnetization anisotropy is used, it is still in a critical state whether the spin will spin at all. Therefore, if the structure of the MRAM cell array MA10 is adopted, it is better to make the magnetic field Hx slightly larger than the magnetic field Hy, so that the spin rotation angle θ ₂ It is 90 degrees or more.

Incidentally, in the MRAM cell array MA20 shown in FIG. 13 and FIG. 14, since the spin is rotated to approximately 180 degrees by the combined magnetic field of the same size, the spin can be accurately rotated.

Secondly, regarding the case where the spin direction is maintained even if the coupling magnetic field is applied, the relationship between the spin direction and the direction of the coupling magnetic field Hk that maintains it is shown schematically in FIGS. 16-21. Incidentally, Figs. 16 to 21 all correspond to Figs. 9 to 14, and therefore repeated descriptions are omitted.

In Fig. 16 and Fig. 17, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle presented by the spin and the combined magnetic field Hk is θ ₁₁ = 45 degrees.

In Figure 18 and Figure 19, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle presented by the spin and the combined magnetic field Hk is θ ₁₂ =0 degrees.

In Fig. 20 and Fig. 21, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle presented by the spin and the combined magnetic field Hk is θ ₁₃ = 90 degrees.

Therefore, in the conventional MRAM cell array shown in FIG. 16, the direction of the spin is substantially maintained. In addition, in the MRAM cell array MA10 shown in FIG. 18, the spin direction is maintained and the write operation is performed. In the MRAM cell array MA20 shown, it is in a critical state of whether the spin will spin, so it is not ideal.

It can be seen from the above research that it is preferable to adopt the structure of the MRAM cell array MA20 shown in FIG. 13 and FIG. 20 to consider the direction of current flowing on the bit line and the word line. This architecture will be described using FIGS. 22-25.

In the structure of the MRAM cell array MA20, as shown in Figure 8, the current flow direction is from bottom to top on the bit line BL1a, and from left to right on the word line wL1a, the selected address when performing a write operation The relationship between the spin direction of the MRAM cell MC3a and the direction of the combined magnetic field Hk that reverses it is shown schematically in FIGS. 22 and 23.

In Figure 22 and Figure 23, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle between the spin and the combined magnetic field Hk is θ ₄ =180 degrees, it can be said that this is a structure suitable for reversing the spin direction to perform data writing tasks.

In addition, in the structure of the MRAM cell array MA20, the current flow direction is from top to bottom on the bit line BL1a, and from right to left on the word line WL1a, the selected address when performing a write operation The relationship between the spin direction of the MRAM cell MC3a and the direction of the combined magnetic field Hk held by it is shown schematically in FIGS. 24 and 25.

In addition, compared with the case of FIG. 22, the direction of the current flowing on the bit line and the word line is changed.

In Fig. 24 and Fig. 25, assuming that the magnitudes of the magnetic fields Hx and Hy are the same, the angle between the spin and the combined magnetic field Hk is θ ₅ =0 degrees, it can be said that this is an architecture suitable for performing data writing tasks by maintaining the spin direction.

In addition, regardless of the architecture of FIG. 22 and FIG. 24, it has the advantage that since the direction of the combined magnetic field is consistent with the easy axis of magnetization, the writing error can be reduced more than the prior art.

(A-2. Effect)

As described above, according to the MRAM of the first embodiment of the present invention, the easy magnetization axis of the soft ferromagnetic layer 24 that constitutes the MRAM cell is inclined 40 to 50 degrees with respect to the bit line and the word line, which is more desirable When configured for 45 degrees, even with a lower current, the spin direction of the MRAM cell at the selected address can be reversed more accurately, thereby reducing power consumption during writing.

In addition, if the spin direction of the MRAM cell of the selected address is reversed and the spin direction is maintained, the direction of the current flowing on the bit line and the word line can be changed to combine the magnetic field direction and The direction of the easy magnetization axis is consistent, which can reduce writing errors.

(B. Second embodiment) (Characteristics of this embodiment)

Regarding the MRAM of the second embodiment of the present invention, there are paired read/write control circuits at both ends of the bit line and the word line of the MRAM cell array, and as the structure of the circuit, it includes The first MOS transistor that connects the bit line to the power supply voltage VDD, the second transistor that connects the bit line to the ground voltage VSS, and further have: The function of bidirectional current flow; the function of outputting the voltage caused by the detection current to the sense amplifier when performing the reading work.

(B-1. Device architecture) (B-1-1. The overall architecture of MRAM)

FIG. 26 is a block diagram showing the MRAM architecture of the second embodiment of the present invention, showing the MRAM cell array MCA and its peripheral circuits.

In FIG. 26, the column address buffer CAB receives the row address signal, inverts or amplifies it, and outputs it to the row decoder CD.

The row decoder CD decodes the row address signal, and then outputs the decoded signal to the multiplexer MUX.

The multiplexer MUX selects bit lines based on the decoded row address signal. At the same time, the signal is also output to the row read/write first control circuit CRW1 connected to one end of the bit line, and according to the read or write operation, the signal from the row read/write first control circuit CRW1 The voltage and current of a control circuit CRW1 are applied to the selected bit line.

The row address buffer RAB receives the row address signal, inverts or amplifies it, and outputs it to the column decoder RD.

The column decoder RD decodes the column address signal, and then selects the word line according to the decoded column address signal. At the same time, the signal is also output to the column read/write first control circuit RRW1 connected to one end of the bit line, and according to the read or write operation, the signal from the column read/write first control circuit RRW1 The voltage and current of a control circuit RRW1 are applied to the selected word line.

In addition, the data read from the MRAM cell array MCA or the data written on the MRAM cell array MCA is through the input/output buffer IOB to perform data input/output with the outside.

In addition, a row read/write second control circuit CRW2 is connected at the other end of the bit line, and a column read/write second control circuit RRW2 is connected at the other end of the word line.

(B-1-2. The detailed structure of MRAM)

In the MRAM shown in FIG. 26, the circuit diagram of the architecture of the multiplexer MUX, row decoder CD, column decoder RD, and input/output buffer IOB will be deleted and shown in FIG. 27. In addition, as for the row address buffer CAB and the column address buffer RAB, the illustration is omitted for identification. Incidentally, the MRAM with the architecture shown in FIG. 27 is called MRAM100.

In FIG. 27, the MRAM cell array MCA has MRAM cells MC11, MC21, MC12, and MC22. Each MRAM cell has a structure in which magnetic tunnel junction (MTJ) and pn junction diodes are connected in series. In Figure 27, the MTJ is represented by a variable resistance and the equivalent circuit is represented Series circuit of diodes.

The reason for expressing MTJ with variable resistance is: in the soft ferromagnetic layer (which can change the direction of electron spin, that is, it can change the direction of magnetization), and the ferromagnetic layer (fix the direction of electron spin, that is, In order to fix the magnetization direction), if the two spins are in the same direction, the tunneling resistance decreases, and if they are opposite to each other, the tunneling resistance increases. Therefore, the variable resistor has two types of resistance.

The MRAM cell MC11 has a variable resistor R11 and a diode D11 connected in series between the bit line BL1 and the word line WL1, and the MRAM cell MC21 has a type connected in series to the bit line The variable resistor R21 and the diode D21 between BL1 and the word line WL2, and the MRAM cell MC12 has a variable resistor R12 and two connected in series between the bit line BL2 and the word line WL1 The polar body D12 and the MRAM cell MC22 have a variable resistor R22 and a diode D22 connected in series between the bit line BL2 and the word line WL2.

The structure of the bit lines BL1 and BL2 is as follows: on the row read/write second control circuit CRW2, the drain voltage V is provided by the NMOS transistors MN11 and MN21, respectively _DD . In addition, the structure is also: on the drain electrodes of the NMOS transistors MN11 and MN21, the drain electrodes of the NMOS transistors MN12 and MN22 are respectively connected, and then the source electrodes of the NMOS transistors MN12 and MN22 are provided with sources Voltage V _SS 。

In addition, the gate electrodes of NMOS transistors MN11, MN12, MN21, and MN22 are provided with outputs of NAND gates ND1, ND2, ND3, and ND4, respectively. The three outputs of NAND gates ND1~ND4 are connected to multiplexers.DeviceMUX.

The structure of the bit line BL1 and the bit line BL2 is: on the row read/write first control circuit CRW1, they are respectively provided by the NMOS transistor MN13, the variable resistors R31 and MN23, and the variable resistor R32 Drain voltage V _DD . Moreover, the structure is also: the drain electrodes of NMOS transistors MN13 and MN23 are connected to the drain electrodes of NMOS transistors MN14 and MN24, respectively, and the source electrodes of NMOS transistors MN14 and MN24 are given source voltages. V _SS 。

In addition, the source electrodes of NMOS transistors MN13 and MN23 are also connected to a multiplexer MUX containing a sense amplifier for detecting current.

In addition, for the gate electrodes of NMOS transistors MN13, MN14, MN23 and MN24, outputs of NAND gates ND5, ND6, ND7 and ND8 are respectively assigned, and the three outputs of NAND gates ND1~ND4 are respectively connected to the multiplexerDeviceMUX.

The structure of word line WL1 and word line WL2 is: column read/write first control circuit RRW1, through NMOS transistors QN11 and QN21, respectively, to provide a drain voltage V _DD . Moreover, its structure is also: the drain electrodes of NMOS transistors QN11 and QN21 are connected to the drain electrodes of NMOS transistors QN12 and QN22, respectively, and the source electrodes of NMOS transistors QN12 and QN22 are given source voltages. V _SS 。

In addition, the gate electrodes of NMOS transistors QN11, QN12, QN21 and QN22 are connected to the column decoder RD.

The word lines WL1 and WL2 are structured as follows: On the column read/write second control circuit RRW2, NMOS transistors QN13 and QN14 are respectively provided with a source voltage V _SS 。

Incidentally, in FIG. 27, although the MRAM cell array MCA has two columns and two rows, the scale of the columns and rows is not limited to this scale.

(B-2. Device work)

Using FIGS. 27 to 29, the operation of MRAM 100 will be described as follows. FIG. 28 is a timing chart of each current and voltage in the MRAM 100 when the read and write operations are performed.

In FIG. 28, there are shown: a timing chart for detecting current; a timing chart for voltages applied to word lines and bit lines when performing writing and reading operations of MRAM cells MC11, MC21, MC12; and at the same time Shows the gate voltage V applied to each gate electrode of the NMOS transistors MN11, MN12, MN13, and MN14 ₁₁ , V ₁₂ , V ₁₃ And V ₁₄ The timing chart; for the gate voltage V applied to each gate electrode of NMOS transistors QN11, QN12 and QN13 _W1 , V _W2 And V _w3 The timing table; for the source voltage V applied to the NMOS transistor MN13 _S1 ofchronological table.

In addition, in FIG. 28, the voltage in the standby state of the word line and the bit line is V _W And V _b 。

Each MRAM cell contains a pn junction diode, and a voltage V is applied to the word line and bit line _W And V _b , It can be used to apply a reverse bias on the diode when it is in the standby state. In addition, as shown in Figure 27, each diode is formed by connecting its cathode to the word line, so it can be set to satisfy V _W >V _b 。

Assuming the voltage is V _b = Source voltage V _SS , The control of the bit line BL1 is described as follows.

(B-2-1. Standby state)

As shown in Figure 28, in the standby state, the voltage applied to all word lines is V _W , And V is applied to all bit lines _b . In order to achieve this, four pieces of NMOS transistors MN11, MN12, MN13, and MN14 shown in FIG. 28 are arranged.

In other words, in the standby state, for the gate voltage V ₁₁ And V ₁₃ Give the source voltage V _SS , So that the NMOS transistors MN11 and MN13 are both OFF, and for the gate voltage V ₁₂ And V ₁₄ Give the source voltage V _CD , So that the NMOS transistors MN12 and MN14 are both in the ON state.

In addition, the source voltage V is applied _W1 , In order to make the NMOS transistor QN11 ON state, and apply the source voltage V _W2 , In order to make the NMOS transistor QN12 OFF, and apply the source voltage V _W3 , In order to make the NMOS transistor QN13 OFF.

Incidentally, since the source voltage of the NMOS transistor QN11 is connected to the drain voltage V _DD , So as the gate voltage V _W1 Apply V _DD +V _DD The voltage. This is to supplement the voltage drop caused by the threshold voltage of the transistor.

As a result, the source voltage V is applied to the bit line BL1 _SS , And the drain voltage V is applied to the word line wL1 _DD 。

(B-2-2. Write status 1 (write 1))

If data "1" is written on the MRAM cell MC (that is, the spin is reversed), current must flow through the selected word line WL1 and the selected bit line BL1. In the MRAM 100 shown in FIG. 27, it is assumed that currents in both directions flow only to the bit line.

In this situation, the NMOS transistors MN11 and MN14 are both in the ON state, and the NMOS transistors MN12 and MN13 are both in the OFF state. However, since the source voltage of the NMOS transistor MN11 is connected to the drain voltage V _DD , So as the gate voltage V ₁₁ Apply V _DD +V _DD The voltage.

As a result, the current I flowing on the bit line BL1 _BT It appears to flow from the top of Fig. 27 to the bottom.

In contrast, by turning both NMOS transistors QN11 and QN13 in the ON state and turning NMOS transistor QN12 in the OFF state, the current I from the left to the right in FIG. 27 flows on the selected word line wL1. _WD . Since the source electrode of the NMOS transistor QN11 is connected to the drain voltage V _DD , So as the gate voltage V _W1 , Then V is applied _DD +V _DD The voltage.

In this way, the current I that flows on the selected word line wL1 and the selected bit line BL1 is utilized _WD And I _BT The resulting magnetic field causes the spin of the soft ferromagnetic layer of the MTJ of the MRAM cell MC11 to rotate, thereby performing data writing.

(B-2-3. Reading status 1 (reading 1))

If you want to read the data "1" written in the MRAM cell MC11, only apply a positive bias to the diode D11 of the MRAM cell MC11 to flow the detection current I _SC . The detection current I _SC Once it flows on the MRAM cell MC11, it causes the voltage of the bit line BL1 to drop. Use the magnitude of the pressure drop to determine whether the data is "0" or "1".

In order to apply a positive bias to the diode D11, the voltage V _b Applied to the selected word line WL1, and the voltage V _W Applied to the selected bit line BL1. In order to achieve this state, the NMOS transistors MN11 and MN13 are both in the ON state, and the NMOS transistors MN12 and MN14 are both in the OFF state.

However, since there are V on the source lines of NMOS transistors MN11 and MN13 _DD , So as the gate voltage V ₁₁ And V ₁₃ , Then V is applied _DD +V _DD The voltage.

At this time, for the pn junction diode D22 of the MRAM cell MC22 of the non-selected address, the reverse bias voltage is still applied (for the word line WL2 with the voltage V _W , For bit line BL with V applied _b ), on the contrary, for the diodes D12 and D21 of the MRAM cells MC12 and MC21 of the half-selected address, no potential difference (0 bias) is given, and no current flows in the MRAM cells MC12, MC21, and MC22. Here, among the two resistance values of the variable resistor R11 (that is, MTJ), the higher one is R _H , The lower is R _L 。

The detection current I flowing in the memory cell of the MRAM cell MC _SC , Is changed according to the resistance value of MTJ (that is, the resistance value of variable resistor R11). Assuming the resistance of MTJ is R _H And R _L The value of the detection current is I _L And I _H , Just as R _H >R _L , So I can be established _H >I _L Relationship.

Since the detection current flows through the MRAM cell MC11, the voltage V of the source current of the NMOS transistor MN13 (connected to the multiplexer MUX) _S1 , Reduce the excessive drain voltage V _DD 。

The voltage step-down is based on the value of the magnetic tunneling resistance, and the step-down voltage is compared with the reference voltage by the sense amplifier contained in the multiplexer MUX to detect the data "1".

(B-2-4. Write status 0 (write 0))

If it is desired to write data "0" (the direction of maintaining the spin) on the MRAM cell MC11, where it is different from the case of writing "1", the direction of the current flowing on the selected bit line BL1 is opposite to it. In order to achieve this state, the NMOS transistors MN11 and MN14 are both in the OFF state, and the NMOS transistors MN12 and MN13 are both in the ON state.

As a result, the current I flowing on the bit line BL1 _BT It flows from the bottom of Fig. 27 to the top.

(B-2-5. Read status 0 (read 0))

If you want to read the data "0" written in the MRAM cell MC11, the working principles of the NMOS transistors MN11, MN12, MN13, and MN14 are all the same as the read state 1 (read 1). However, the source voltage V of the NMOS transistor MN13 when the data to be read is "0" _S1 , And the voltage V when the data to be read is "1" _S1 The voltage difference between V will increase as the rate of change of magnetic tunnel resistance increases. The greater the voltage difference V, the greater the limit of the reference voltage that can be detected by the sense amplifier, which makes it easier to detect.

Here, the applied voltage dependence of the rate of change of the magnetic tunnel resistance is shown in FIG. 29. In Figure 29, the abscissa axis represents the bias voltage applied to the MTJ, and the ordinate axis represents the rate of change of the magnetic tunnel resistance {(R _H -R _L )/R _L }. Incidentally, in FIG. 29, the single magnetic tunnel junction characteristic with respect to the tunneling barrier layer with a single-layer MTJ is shown, and the dual magnetic tunnel junction characteristic with respect to the tunneling barrier layer with a double-layer MTJ is also shown.

It can be seen from Figure 29 that if the applied voltage to the (single and double) magnetic tunnel junction is 0.1V, the magnetic tunnel resistance is the maximum. Therefore, when reading is performed, the voltage V applied to the selected bit line BL1 is _W Compared with the voltage applied to the pn junction diode, it is better to be higher than 0.1V. This voltage is adjusted by adjusting the gate voltage V of NMOS transistors MN11 and MN13 _DD +V _DD The value can be achieved.

Here, using FIG. 30, the structure of the double-layer magnetic tunnel junction is described. As shown in Fig. 30, the double-layer magnetic tunnel junction has an anti-ferromagnetic layer AF1, a ferromagnetic layer FM1, a first tunnel barrier layer TB1, a second tunnel barrier layer TB2, and a second anti-strength The structure of the laminated magnetic layer AF2. In these structures, a voltage V is applied between the terminals TA and TB of the first and second antiferromagnetic layers AF1 and AF2 _X , Just on the first and second tunnel barrier layers TB1 and TB2, V _X /2 voltage.

In contrast, when using single magnetic tunnel junctions, V _X Produced on the tunneling barrier film, but the rate of change of its magnetic tunneling resistance is the smaller the applied voltage, the smaller the rate of change of the magnetic tunneling resistance of the dual magnetic tunnel junction naturally becomes larger, so The characteristics between single magnetic tunnel junction and dual magnetic junction are different, as shown in FIG. 29.

(B-3. Effect)

As described above, according to the MRAM of the second embodiment of the present invention, at both ends of the bit line and the word line of the MRAM cell array MCA, the row read/write first control circuit CRW1 and the row read/write Write the second control circuit CRW2, and in each circuit, contains the bit line and the power supply voltage V _DD The connected first MOS transistor (MN11, MN21, MN13, MN23) is used to make the bit line and the ground voltage V _ss The connected second transistors (MN12, MN22, MN14, MN24) can change the direction of the current flowing on the selected bit line by switching the NOMS transistors, and then can arbitrarily change the soft ferromagnetic layer used to form the MTJ Spin direction. Incidentally, the NMOS transistors MN11 and MN12, MN21 and MN22, MN13 and MN14, MN23 and MN24 can switch the connection objects at both ends of the bit line to V _DD Or V _SS , Can also be called a switching device.

In addition, the above-mentioned first MOS transistor of the row read/write first control circuit CRW1 is connected to a multiplexer MUX containing a sense amplifier, so it can be affected by the detection current when the read operation is performed. The resulting voltage is output to the multiplexer MUX.

(B-4. The first modification)

As a first modification of the second embodiment of the present invention, MRAM 200 is shown in FIG. 31. Incidentally, MRAM200 has a structure that is roughly the same as that of MRAM100 described using FIG. 27. The difference is: PMOS transistors MP11, MP13, MP21, MP23, QP11 and QP21 are provided instead of NMOS transistors in MRAM100 MN11, MN13, MN21, MN23, QN11 and QN21, and for the gate electrode of PMOS transistor MP11 and NMOS transistor MN12, give the output of NAND gate ND11, and for PMOS transistor MP21 and NMOS transistor MN22 The output of NAND gate ND12 is given to the gate electrode, and the output of NAND gate ND13 is given to the gate electrode of PMOS transistor MP13 and NMOS transistor MN14, and the output of NAND gate ND13 is given to PMOS transistor MP23 and NMOS transistor MN24. The gate electrode is given the output of the NAND gate ND14 to achieve common gate input.

In the MRAM100 shown in FIG. 27, for the gates of the NMOS transistors MN11, MN13, MN21 and MN23, V _DD +V _DD , So it is only V compared to the gate voltage _DD The NMOS transistors MN12, MN14, MN22 and MN24 may increase the load generated by the gate insulating film.

However, in the MRAM200 shown in FIG. 31, using PMOS transistors MP11, MP13, MP21, and MP23 can avoid applying a voltage higher than V to the gate. _DD Voltage to reduce the load generated on the gate insulating film.

In addition, the use of PMOS transistors MP11, MP13, MP21 and MP23 can achieve shared gate input with NMOS transistors MN12, MN14, MN22 and MN24, while PMOS transistors MP11 and NMOS transistors MN12, PMOS transistors MP21 and NMOS Transistor MN22, PMOS transistor MP13, NMOS transistor MN14, PMOS transistor MP23, and NMOS transistor MN24 all form inverters (drivers, buffers), which reduce power consumption compared to MRAM100.

Fig. 32 is a timing chart of various currents and voltages in MRAM 200 when performing read and write operations.

In MRAM200, since each gate input of PMOS transistors MP11, MP13, and NMOS transistors MN12, MN14 are shared, the gate voltage V ₁₁ And V ₁₂ The timing table is the same, and the gate voltage V ₁₃ And V ₁₄ The timing table is the same.

In addition, since the gate input of PMOS transistor QP11 and PMOS transistor QP12 are shared (the gate input of PMOS transistor QP21 and PMOS transistor QP22 are also the same), the gate voltage V _W1 And V _W2 The timing tables are the same, but the basic working state is the same as that of MRAM100.

Incidentally, in this embodiment, the voltage V _b = Source voltage V _SS , Voltage V _W = Source voltage V _DD For the imagination. In other words, if the MTJ characteristic is the same as that shown in Figure 29, it is set as: source voltage V _DD It is roughly the same as adding 0.1V to the voltage applied to the pn junction diode of each MRAM cell.

Furthermore, although the read/write control circuits of MRAM 100 and 200 are not shown, they may be shared with adjacent MRAM cell arrays. In this case, it is possible to achieve a reduction in the device area of the shared weight.

(B-5. The second modification)

As a second modification of the second embodiment of the present invention, MRAM 300 is shown in FIG. 33. Incidentally, MRAM300 has a structure that is roughly the same as that of MRAM200 described using FIG. 31. The difference is: PMOS transistor MP11 and NMOS transistor MN12, PMOS transistor MP13 and NMOS transistor MN14, PMOS transistor Between each drain electrode of MP21 and NMOS transistor MN22, PMOS transistor MP23 and NMOS transistor MN24, there are inserted NMOS transistors MN15, MN16, MN25, MN26, and between PMOS transistors QP11 and NMOS transistors QN12, NMOS transistors QN1 and QN2 are inserted between each drain electrode of PMOS transistor QP21 and NMOS transistor QN22.

Incidentally, the gate voltages of NMOS transistors MN15, MN16, MN25, MN26, QN1 and QN2 are all fixed at the direct current voltage V _GG 。

The purpose of these NOMS transistors is to reduce leakage. In other words, the leakage in the MOSFET is caused by: BTBT (Band to band tunneling) TAT (Trap Assisted Tunneling), Impact Ionization and SRH (Schockley-Read-hall) caused by the high magnetic field generated by the drain terminal. process).

In order to reduce the leakage, the magnetic field of the drain terminal can be reduced. For example, the NMOS transistor MN15 is inserted between the PMOS transistor MP11 and the NMOS transistor MN12, and then the gate voltage of the NMOS transistor MN15 is set to a predetermined direct current voltage. (Here is the voltage V _GG ), which can reduce the drain voltage given to the NMOS transistors MN12 and MN15.

For example, the voltage V _GG Set at V _DD /2+V _thn (Threshold voltage of NMOS transistor MN15) is applied to enable NMOS transistor MN15 to be normally ON. Next, when the NMOS transistor MN12 is in the ON state, together with the NMOS transistor MN15, the two resistors are connected in series, and it becomes the result of the resistance splitting on the NMOS transistors MN12 and MN15. Forced voltage (drain voltage V _DD ) Is equal, so the total leakage of MN12 and MN15, if the NMOS transistor MN15 is not inserted, is compared with the leakage of only the NMOS transistor MN12, the leakage can be greatly reduced, resulting in lower power consumption.

In addition, the voltage V _DD For V _DD /2+V _thn It is based on the recognition that the forced voltages generated on the NMOS transistors MN12 and MN15 can be minimized due to the adoption of this setting. However, when implemented, only the power consumption can be reduced, and it is not limited to its voltage.

The above results are the same as in NMOS transistors MN16, MN25 and MN26. In addition, the use of NMOS transistors QN1 and QN2 inserted between each drain electrode of PMOS transistor QP11 and NMOS transistor QN12, PMOS transistor QP21 and NMOS transistor QN22 can greatly reduce leakage and reduce power consumption. .

In addition, in the above description, although it is assumed that bidirectional current flows on the bit line of the MRAM cell array and unidirectional current flows on the word line when writing data is performed, it can also be: A unidirectional current flows on the line, and a bidirectional current flows on the word line.

In addition, a device with ON/OFF characteristics such as MOSFET, TFT (Thin Film Transistor) or bipolar transistor can also be used to replace the pn junction diode of the MRAM cell.

(C. The third embodiment) (Characteristics of this embodiment)

The MRAM of the third embodiment of the present invention is characterized in that the word line or bit line of the MRAM cell array is divided into a plurality of sub word lines or sub bit lines.

In other words, the resistivity of the wiring is ρ, the length of the wiring is 1, and the cross-sectional area of the wiring is S, and the wiring resistance R can be obtained by the following formula (9): (Equation 9) R=ρ <img file="TW548656B_D0009.tif" /> . . . (9) Again, the current flowing on the wiring is I, and its power consumption can be obtained by the following formula (10): (Equation 10) P=RJ ² +ρ <img file="TW548656B_D0010.tif" /> . . . (10) Therefore, it can be seen that shortening the wiring length 1 leads to a reduction in power consumption. For example, if the wiring is divided into two, the power consumption is 1/2. If it is divided into n (but n should be an integer greater than 2), the power consumption is 1/n, which reduces the writing work in MRAM Power consumption at a time.

In addition, if the number of memory cells connected to the same word line increases, the load capacity is increased. As a result, the delay time of the signal used to transmit the word line is increased, resulting in the disadvantage that high-speed access cannot be realized.

However, by dividing the word line into sub-word lines to shorten the wiring length to reduce the number of memory cells connected to the same wiring, the load capacity can be reduced. As a result, compared with the memory device without dividing the word lines, the delay time can be shortened, and high-speed access can be realized. The principle is also the same as the bit line. The specific structure of the MRAM of the third embodiment of the present invention will be described as follows.

(C-1. Division of word line) (C-1-1. Device architecture)

The structure of the divided word line MRAM 400 is shown in FIG. 34 as a block diagram. As shown in FIG. 34, MRAM 400 has a plurality of MRAM cell arrays 66.

Each MRAM cell array 66 has: a column read/write first control circuit RRW1 connected to the first end of a plurality of word lines 64 and a column read/write connected to the second end The second control circuit RRW2; the row read/write first control circuit CRW1 connected to the first end of the plurality of bit lines 69 and the row read/write second control connected to the second end Circuit CRW2.

Incidentally, although each of the above-mentioned control circuits is the same as the MRAM 100-300 described in the second embodiment, and the same component numbers are added, it is not limited to these structures.

Furthermore, corresponding to each MRAM cell array 66, most of them are equipped with memory cell array selection lines 70 connected to a row decoder not shown.

In addition, main word lines 67 are respectively connected to the outputs of the AND gates 62 of the plurality of elements that constitute the column decoder. Incidentally, the number of main word lines 67 is consistent with the number of word lines of the MRAM cell array 66.

At the intersection of the majority of the memory cell array selection lines 70 and the majority of the main word lines 67, a binary input AND gate 61 with the memory cell array selection lines 70 and the main word line 67 as inputs is connected, and the The output is connected to the sub word line 64 via the column read/write first control circuit RRW1. The sub word line 64 becomes the word line of each MRAM cell array 66.

(C-1-2. Installation work)

The working state of MRAM400 is explained as follows.

For example, if one of the memory cell array selection lines 70 and one of the main word lines 67 is activated so as to be connected to the activated memory cell array selection lines 70 and the AND gate 61 on the main word line 67, The sub word line 64 connected to its output can be activated.

In this case, the activated main word line 67 is not directly connected to the MRAM cell, so its capacity does not include the capacity of the MRAM cell that constitutes the MRAM cell array 66. Therefore, compared with a structure that selects MRAM cells by using only one word line across a plurality of MRAM cell arrays, the capacity contained in the word line can be greatly reduced.

Moreover, the sub-word line 64 that only crosses on one MRAM cell array 66 is constructed so that the delay (CR delay) caused by the capacity and resistance can be ignored, so that the time required for the MRAM 400 to select a specific MRAM cell can be reduced. It is substantially shortened, so that the operating rate of MRAM is increased.

Here is an explanation about the capacity of the MRAM cell. Assume that an MRAM cell is constituted by a series connection of MTJ (magnetic tunnel junction) and pn junction diodes as an example of its technical case.

In this case, the MRAM cell capacity C _M As shown in the following formula (11), it becomes the capacity C of the MTJ _TMR And pn junction diode junction capacity C _D The capacity is in series.

(Formula 11)

<maths><img file="TW548656B_D0011.tif" /></maths>

In the MRAM 400 shown in FIG. 34, since only the MRAM cell connected to the sub word line 64 in the selected MRAM cell array 66 is accessed, the current flowing between the sub word line 64 and the bit line 69, Compared with the structure of undivided word lines, the number of MRAM cell arrays is reduced in proportion to the inverse number, so that power consumption is reduced.

Incidentally, in MRAM 400, an AND gate is used as a logic gate for controlling the sub word line 64, but it is not limited to AND gates. For example, other logic gates such as NAND gates, NOR gates, XOR gates, etc. may be used. The logic of "High" or "lOW" representing the memory cell array selection line 70 and the main word line 67, and the opposite logic ("LOW" or "High") are combined, and the aforementioned logic gates are input to achieve the same For MRAM400 effect. Here, the so-called "logic LOW" or "High" is equivalent to either of the high value or the low value of each signal voltage.

(C-2. Hierarchy of word lines) (C-2-1. Device architecture)

The structure of the MRAM 500, which is hierarchical for word lines, is shown in FIG. 35 as a block diagram. As shown in FIG. 35, the MRAM 500 has an n-piece memory cell array group 861 to 86n composed of a m-piece MRAM cell array 85.

Taking the memory cell array group 861 as an example, each MRAM cell array 85 has: a column read/write first control circuit RRW1 connected to the first end of a plurality of word lines 83 and connected to the first control circuit RRW1 Column read/write second control circuit RRW2 on both ends; row read/write first control circuit CRW1 connected to the first end of the plurality of bit lines 89 and connected to the second end The upper row read/write second control circuit CRW2.

Furthermore, corresponding to each MRAM cell array 85, a kind of m memory cell array selection lines 911-91m connected to a row decoder not shown is arranged.

In addition, a main word line 84 is connected to the output of the majority AND gate (sub-universal decoder) 81, respectively. Incidentally, the number of main word lines 84 is consistent with the number of word lines of the MRAM cell array 85.

At the intersection of the memory cell array selection lines 911~91m and the majority of the main word lines 84, there are two items that take any one of the memory cell array selection lines 911~91n or one of the main word lines 84 as input. The input AND gate (local column decoder) 82, and its output, is connected to the sub word line 83 via the column read/write first control circuit RRW1. The sub word line 83 becomes the word line of each MRAM cell array 85.

In addition, all the first inputs of the plurality of sub-universal decoders 81 are commonly connected to the memory cell array group selection line 901 corresponding to the memory cell array group 861.

In addition, each of the second inputs of the sub-universal decoder 81 is connected to the output of the AND gate (main universal decoder) 80 via a universal word line 87 connected to the main universal decoder 80. Output.

The selection lines 901 to 90n of the memory cell array group are a kind of wiring that is different from the general word line 87, and the two are arranged to cross each other.

Incidentally, other memory cell array groups also have the same structure as the memory cell array group 861, which are respectively connected to a plurality of sub-universal decoders 81, and each of the plurality of sub-universal decoders 81 is also Connect to the memory cell array group selection line.

In other words, corresponding to each memory cell array group 861 to 86n, the memory cell array group selection lines 901 to 90n are provided, and they are connected to the second general decoder 81 of the majority of the memory cell array groups 861 to 86n. The two inputs are respectively connected to the output of the main general decoder 80 via the general word line 87.

In addition, most of the main universal decoders 80 are connected to the address signal line group 88.

(C-2-2. Installation work)

The working status of MRAM500 is described as follows.

The memory cell array groups 861~86n are selected by using the memory cell array group selection lines 901~90n. Most of the MRAM cell arrays 85 in the memory cell array groups 861~86n are selected by the memory cell array selection lines 911 ~91m to be selected.

The operation of the memory cell array groups 861 to 86n is also illustrated in FIG. 34 for the MRAM 400. For example, one of the memory cell array selection line 911 and the main word line 84 is activated so as to be connected to the activated memory cell array selection The AND gate 82 on the line 911 and the main word line 84 can activate the sub word line 83 connected to its output.

In this case, the capacity of the activated main word line 84 does not include the capacity of the MRAM cell used to form the MRAM cell array 85, so it is compared with a type that spans a large number of MRAM cell arrays. One word line to select the previous MRAM of the MRAM cell can greatly reduce the capacity contained in the word line.

In addition, for example, one of the memory cell array group selection line 901 and the general word line 87 is activated so as to be connected to the AND gate 81 on the activated memory cell array group selection line 901 and the general word line 87, The main word line 84 connected to its output can be activated.

In this case, the capacity of the activated general-purpose word line 87 does not include the capacity of the MRAM cell array 85 used to form the memory cell array group 861 to 86n, so it is compared to a use of straddle in a large number of devices. One word line on the MRAM cell array selects the previous MRAM of the MRAM cell, which can greatly reduce the capacity contained in the word line.

Therefore, the current flowing between the word line 83 and the bit line 89 is not only proportional to the reciprocal reduction of the number of MRAM cell array groups, but also for the memory cell array compared with the previous MRAM that has not facilitated word line hierarchization. The reciprocal of the number of groups is reduced in direct proportion, so that power consumption is reduced.

(C-2-3. The overall structure of MRAM with hierarchical word lines)

An example of the overall structure of the MRAM with hierarchical word lines is shown in FIG. 36. In FIG. 36, there is shown a MRAM with four MRAM cell arrays 851 to 854 and four memory cell array groups 861 to 864, and corresponds to each of the memory cell array groups 861 to 864, with There are four memory cell array group selection lines 901~904. In addition, in each memory cell array group, corresponding to four MRAM cell arrays 851 to 854, four memory cell array selection lines 911 to 914 are arranged.

Incidentally, in FIG. 36, each structure such as the MRAM cell array 85 is represented by a simpler block, and each wiring path such as the general word line 87 is shown in a pattern using arrows. It can be seen from Fig. 36 that the so-called word lines are hierarchized.

(C-3. Segmentation of bit lines) (C-3-1. Device architecture)

The structure of the MRAM 600 divided by the bit lines is shown in FIG. 37 as a block diagram. As shown in FIG. 37, MRAM 600 has a plurality of MRAM cell arrays 166.

Each MRAM cell array 166 has: a column read/write first control circuit RRW1 connected to the first end of a plurality of word lines 160 and a column read/write connected to the second end The second control circuit RRW2; the row read/write first control circuit CRW1 connected to the first end of the plurality of bit lines 164 and the row read/write second control connected to the second end Circuit CRW2.

Incidentally, although each of the above-mentioned control circuits is the same as the MRAM 100-300 described in the second embodiment, and the same component numbers are added, it is not limited to these structures.

Furthermore, corresponding to each MRAM cell array 166, most of them are equipped with a memory cell array selection line 170 connected to a column decoder not shown.

In addition, the main bit lines 167 are respectively connected to the outputs of the AND gates 162 of the plurality of elements that constitute the row decoder. Incidentally, the number of main bit lines 167 is consistent with the number of word lines of the MRAM cell array 166.

At the intersection of the majority of the memory cell array selection lines 170 and the majority of the main bit lines 167, a binary input NAND gate 161 with the memory cell array selection lines 170 and the main bit line 167 as inputs is respectively connected, and The output is connected to the bit line 164 via the row read/write first control circuit CRW1. The bit line 164 becomes the bit line of each MRAM cell array 166.

(C-3-2. Installation work)

The working status of MRAM600 is described as follows.

For example, if one of the memory cell array selection lines and one of the main bit line 167 is activated so as to be connected to the activated memory cell array selection line and the NAND gate 161 on the main bit line 167, The sub bit line 164 connected to its output can be activated.

In this case, the activated main bit line 167 is not directly connected to the MRAM cell, so its capacity does not include the capacity of the MRAM cell that constitutes the MRAM cell array 166. Therefore, compared with a structure that selects MRAM cells by using only one word line across a plurality of MRAM cell arrays, the capacity contained in the word line can be greatly reduced.

Moreover, the sub-bit lines 164 that cross only on one MRAM cell array 166 are constructed so that the delay (CR delay) caused by the capacity and resistance can be neglected, so that the MRAM 600 can select the specific MRAM cell. The time is substantially shortened, so that the operating rate of the MRAM is increased.

As for the capacity of the MRAM cell, since the formula (11) has been used to explain it, the description will not be repeated. In the MRAM 600 shown in FIG. 37, since only the MRAM cell connected to the sub bit line 164 in the selected MRAM cell array 166 is accessed, the current flowing between the sub bit line 164 and the word line 169 is Compared with the undivided bit line architecture, the number of MRAM cell arrays is reduced in proportion to the reciprocal, so as to reduce power consumption.

Incidentally, in MRAM 600, a NAND gate is used as a logic gate for controlling the sub bit line 164, but it is not limited to NAND gates. For example, other logic gates such as AND gates, NOR gates, XOR gates, etc. can be used. Combine the logic of "High" or "low" representing the memory cell array selection line 170 and the main bit line 167, and the opposite logic ("LOW" or "High"), and input the above logic gate to Achieve the same effect as MRAM600. Here, the so-called logic "LOW" or "High" is equivalent to either the high value or the low value of each signal voltage.

(C-4. Hierarchy of bit lines) (C-4-1. Device architecture)

The structure of the MRAM 700 which is hierarchical for word lines is shown in FIG. 38 as a block diagram. As shown in FIG. 38, the MRAM 700 has an n-piece memory cell array group 1861 to 186n composed of a m-piece MRAM cell array 185.

Taking the memory cell array group 1861 as an example, each MRAM cell array 185 has: a column read/write first control circuit RRW1 connected to the first end of the multi-digit line 189 and connected to the second end The column read/write second control circuit RRW2 on the upper part; the row read/write first control circuit CRW1 connected to the first end of the plurality of bit lines 183 and the first control circuit CRW1 connected to the second end Row read/write second control circuit CRW2.

Furthermore, corresponding to each MRAM cell array 185, a kind of m memory cell array selection lines 1911~191m connected to a column decoder not shown is arranged.

In addition, the main bit lines 184 are respectively connected to the outputs of the majority AND gates (sub-universal decoders) 181. Incidentally, the number of main bit lines 184 is consistent with the number of word lines of the MRAM cell array 185.

At the intersection of the memory cell array selection lines 1911~191m and the majority of the main bit lines 184, there is a connection with any one of the memory cell array selection lines 1911~191n or one of the main bit lines 184 as input The AND gate (local row decoder) 182 of the binary input of, and its output is connected to the sub bit line 183 through the row read/write first control circuit CRW1. The sub bit line 183 becomes the word line of each MRAM cell array 185.

In addition, all the first inputs of the plurality of sub-universal decoders 181 are commonly connected to the memory cell array group selection line 1901 corresponding to the memory cell array group 1861.

In addition, each of the second inputs of the sub-universal decoder 181 is connected to the main universal decoder 180 via a universal bit line 187 connected to the output of the AND gate (main universal decoder) 180. At the output.

The selection lines 1901 to 190n of the memory cell array group are a kind of wiring that is different from the general bit line 187, and the two are arranged to cross each other.

Incidentally, other memory cell array groups also have the same structure as the memory cell array group 1861, which are respectively connected to a plurality of sub-universal decoders 181, and each of the plurality of sub-universal decoders 181 is also Connect to the memory cell array group selection line.

In other words, corresponding to each memory cell array group 1861~186n, the memory cell array group selection lines 1901~190n are provided, and they are connected to the second general decoder 181 of the majority of the sub-universal decoders 181 on each memory cell array group 1861~186n. The two inputs are respectively connected to the output of the main universal decoder 180 via the universal bit line 187.

In addition, most of the main universal decoders 180 are connected to the address signal line group 188.

(C-4-2. Installation work)

The working status of MRAM700 is explained as follows.

The memory cell array group 1861~186n uses the memory cell array group selection lines 1901~190n to select any one of them, and the majority of the MRAM cell arrays 185 in the memory cell array group 1861~186n uses the memory cell array group Select the line 1911~191m to be selected.

The working principle of the memory cell array group 1861~186n is the same as the MRAM 600 described using FIG. 37. For example, one of the memory cell array selection line 1911 and the main bit line 184 is activated, so that it is connected to the activated channel. The modified memory cell array selection line 1911 and the AND gate 182 on the main bit line 184 can activate the sub bit line 183 connected to its output.

In this case, the capacity of the activated main bit line 184 does not include the capacity of the MRAM cell used to form the MRAM cell array 185, so it is compared to a use of straddling a large number of MRAM cell arrays. One of the bit lines to select the previous MRAM of the MRAM cell can greatly reduce the capacity contained in the bit line.

In addition, for example, one of the memory cell array group selection line 1901 and the general bit line 187 is activated so as to be connected to the AND gate on the activated memory cell array group selection line 1901 and the general bit line 187 181, the main bit line 184 connected to its output can be activated.

In this case, the capacity of the activated general-purpose bit line 187 does not include the capacity of the MRAM cell array 185 used to form the memory cell array group 1861~186n, so it is more than a kind of utilization. A bit line on the MRAM cell array is used to select the previous MRAM of the MRAM cell, which can greatly reduce the capacity contained in the bit line.

Therefore, the current flowing between the bit line 183 and the word line 189 is not only proportional to the inverse number of the MRAM cell array group, but also for the memory cell compared to the previous MRAM that does not facilitate the hierarchization of the bit line. The reciprocal of the number of array groups is reduced proportionally, so that power consumption is reduced.

Incidentally, in the above-mentioned third embodiment, the method of dividing and layering each of the word lines or bit lines is described, but it may be a combination of these and the like, and the word lines and bit lines may be combined with each other. A structure in which both bit lines are divided, or a structure in which both word lines and bit lines are layered. By using these architectures, power consumption is reduced and MRAM operating rate is increased.

(D. Fourth embodiment) (Characteristics of this embodiment)

Regarding the MRAM of the fourth embodiment of the present invention, it is characterized by using the magnetic field generated by the inductor to perform batch erasing or batch writing of the stored data of a plurality of MRAM cells.

(D-1. Device architecture)

Fig. 39 is a perspective view showing the structure of MRAM 800 related to the fourth embodiment of the present invention. In Figure 39, the bit lines 4, 5, and 6 are arranged in parallel with each other at the upper part of the word lines 1, 2 and 3, and they are arranged in a cross shape, and they are arranged parallel to each other, and the word lines are used An MRAM cell MC is formed at each intersection point sandwiched by the bit line to form an MRAM cell array MCA1.

As for the structure of the MRAM cell MC, it has been described using FIG. 1 and will not be repeated. The direction of the easy magnetization axis of the soft ferromagnetic layer constituting the MRAM cell MC is the extending direction of each word line, as shown by the arrow in the figure.

In addition, a coil-shaped inductor ID is arranged to surround the MRAM cell MCA1.

The inductor ID is configured by connecting wires in a coil shape, and is wound along the direction in which the word lines 1 to 3 extend.

Moreover, the two ends of the inductor ID are connected to an inductor drive circuit (not shown) that can make the current flow in both directions, and its structure is: and then through the direction of the inductor ID is changed , So that the direction of the magnetic field generated on the area surrounded by the inductor ID is changed. Incidentally, the magnetic field generated by the inductor ID is in line with the direction in which the word lines 1 to 3 extend, in other words, it is roughly in line with the direction of the easy magnetization axis of the soft ferromagnetic layer constituting the MRAM cell MC. Unanimous.

Therefore, if it is desired to perform batch erasing or batch writing of data for most of the MRAM cells MC of the MRAM cell array MCA1, only the current flows from the inductor drive circuit to a predetermined direction, so that the generated magnetic field Let's change the spin direction of the soft wall magnetic body together.

Incidentally, for convenience of description, FIG. 39 shows a memory cell array with three columns and three rows, but the scale of the columns and rows is not limited to this.

In addition, a gas or solid insulator is arranged between each conductor line such as the inductor ID, word lines 1 to 3, and bit lines 4 to 6, but the illustration is omitted in Figure 39 for easy identification.

In addition, in FIG. 39, for convenience of description, the winding pitch of the inductor ID is larger than the pitch of the MRAM cell array MCA1, but it is not limited to this.

Of course, the structure of the MRAM cell MC is not particularly limited. It can also be a structure having a dual magnetic tunnel junction as illustrated in FIG. 30, and only at least one magnetic tunnel junction is required. For example, it can also be a memory cell with a magnetic/non-magnetic/magnetic structure that uses at least one of magnetic tunnel junction and magnetostatic combination to make the magnetic flux return path.

In addition, as long as the inductor can generate a magnetic field that is aligned with the direction of the easy magnetization axis of the soft ferromagnetic layer, it does not need to be coil-shaped.

Here, using FIGS. 40 to 42 of the cross-sectional view taken from AA of FIG. 39, the working principle of MRAM 800 will be described. Among them, the winding pitch of the inductor ID is shown with a pitch different from that of FIG. 39 for ease of description.

Fig. 40 shows an example of a state in which the entire batch of clearing tasks has not been executed. As shown in FIG. 40, the MRAM cell MC has a structure equipped with a magnetic tunnel junction (MTJ) at the upper part of its pn junction diode PN. Moreover, the spin direction of the soft ferromagnetic layer 22 of the MRAM cell MC used to form the lower part of the bit line 5 is facing the pattern toward the left, while the spin direction of the other MRAM cells MC is toward the right. Furthermore, in a state where the batch erasing work and the batch writing work are not performed, in other words, the inductor ID is in a standby state, and the inductor ID is grounded. In this way, the external noise is shielded, so that the effect of protecting the MRAM cell array MCA1 is achieved.

Fig. 41 shows an example of the batch removal status. Once the entire batch of clear signals are input into the inductor drive circuit, the current in the first direction flows through the inductor ID to generate a magnetic field to the right as shown by the arrow. At this time, the narrower the distance between the inductor IDs, the less the magnetic field in the inductor can leak to the outside, so that the magnetic field can be generated more effectively.

Here, if the direction of the spin indicating the removal is the right in the figure, the spins of the soft ferromagnetic layer 22 of all the MRAM cells MC are directed to the right at the same time due to the magnetic field in the right direction generated in the inductor. , So that the entire batch of data is cleared.

Fig. 42 shows an example of a state in which a batch of write tasks are executed. Once the entire batch of write signals are input into the inductor drive circuit, a current in a second direction opposite to the first direction flows through the inductor ID to generate a magnetic field toward the left as shown by the arrow.

Here, if the spin direction indicating the writing is set to the left in the figure, the magnetic field in the right direction generated in the inductor causes the spins of the soft ferromagnetic layer 22 of all the MRAM cells MC to face the left at the same time. , So that the entire batch of data is written.

(D-2. Effect)

If you want to perform batch erasing or write the same data in batches for the stored data of most MRAM cells, if you use a method of erasing or writing data by using each selected address of the word line and bit line, it is better. Time-consuming and power consumption is also large.

In contrast, according to the MRAM of the present embodiment, since the data of a large number of MRAM cells can be erased or written in a batch, the work can be completed in a short time, and the inductor ID can be used to generate a magnetic field more effectively. Make it use less power consumption.

(D-3. Modifications)

In order to perform batch erasing or batch writing of the stored data of most MRAM cells, a non-inductor structure can also be used.

As a modification of the fourth embodiment, MRAM 900 is shown in FIG. 43. Incidentally, for convenience of explanation, although it shows an MRAM cell array MCA2 with four columns and four rows, the scale of the columns and rows is not limited as such.

As shown in FIG. 43, above and below the MRAM cell array MCA2, flash bit lines FBL and flash word lines FWL for performing batch processing of data are arranged.

The flash bit line FBL and the flash word line FWL are respectively designed to correspond to the entire area where a plurality of bit lines BL1 and word lines WL1 are arranged, and their planar shapes in FIG. 43 are all rectangular.

In FIG. 43, on the word line WL1, the bit line BL1 has a cross structure, and between the two lines at the intersection of the word line wL1 and the bit line BL1, an MRAM cell MC is arranged.

Furthermore, the flash word line FWL is arranged at the lower part of the word line WL1, and the flash bit line FBL is arranged at the upper part of the bit line BL1. Incidentally, in FIG. 43, the flash bit line FBL located at the uppermost part is displayed with its part deleted for easy identification.

The cross-sectional structure taken from the AA line and the BB line in FIG. 43 are shown in FIG. 44 and FIG. 45, respectively.

As shown in FIG. 45, the MRAM cell MC is located at the upper part of the pn junction diode PN, and has a structure equipped with a magnetic tunnel junction (MTJ).

In this way, flash bit lines FBL and flash word lines FWL are arranged above and below the MRAM cell MC2, and when performing a batch clear or a batch write operation, for the flash bit lines FBL and flash A predetermined current flows on the flash word line FWL, and the spin directions of the soft ferromagnetic layer of all the MRAM cells MC are directed to the same direction together, so that the entire batch of erasing or the entire batch of writing can be realized.

In addition, in the flash bit line FBL and the flash word line FWL, the current used to execute the batch erasing or the batch writing operation is related to the execution of data erasing or writing for each piece of the MRAM cell MC. It is sufficient that the currents flowing in the bit line BL and the word line WL are in the same direction at the time of entry.

In addition, both the flash bit line FBL and the flash word line FWL may have both ends, or only have a single end. In other words, the generated magnetic field is proportional to the magnitude of the current, so as long as more current flows, even if it is only single-ended, spin reversal can be achieved.

In addition, the use of both the flash bit line FBL and the flash word line FWL, and the use of both tools to generate a magnetic field, can reduce the sum of currents used to invert the spin.

In addition, in the state of not performing the batch clearing and batch writing work, in other words, in the standby state of the flash bit line FBL and the flash word line FWL, the flash bit line FBL and the flash word line FWL are enabled The grounding is used to shield the noise caused by the external magnetic field or electric field, so as to achieve the effect of protecting the MRAM cell array MCA1.

Incidentally, in the above-mentioned MRAM 900, although a structure with one MRAM cell MCA2 is shown, it can also be adapted to a structure with a plurality of MRAM cell arrays. This architecture is shown in Figure 46 as MRAM900A.

As shown in Fig. 46, in the MRAM900A, most of the MRAM cells MCA2 are arranged in an array. The general flash bit lines GBL and the general flash word lines GWL used for batch processing of data are arranged in an array.

The general flash bit line GBL and the general flash word line GWL both have the same functions as the flash bit line FBL and flash word line FWL shown in FIG. 43, and because they are commonly used in most MRAM cells On the array MCA2, the name is changed, but the related description is omitted.

Incidentally, the control circuits of the above-mentioned flash bit line FBL and flash word line FWL, general flash bit line GBL, and general flash word line GWL can be used as illustrated in Figure 27, Figure 31, and Figure 33. Column read/write first control circuit RRW1, row read/write second control circuit RRW2, row read/write first control circuit CRW1, row read/write second control circuit CRW2.

In addition, like the MRAM900A shown in FIG. 46, in an architecture with a large number of MRAM cell arrays MCA2, the non-selected ones located on the same row and column as the MRAM cell array MCA2 that is the target of mass erasing or mass writing Current may flow in the MRAM cell array MCA2. Therefore, for the purpose of reducing power consumption, the divided word lines and divided bit lines as illustrated in FIGS. 34 to 38 may be layered. The technical ideas of the word line and the hierarchical bit line are applicable to the general flash bit line GBL and the general flash word line GWL.

(E. Fifth embodiment) (Characteristics of this embodiment)

The MRAM of the fifth embodiment of the present invention is characterized in that it utilizes the LC resonance of the inductor and the capacitor, and then reuses the current, which is used for at least one rewrite of the stored data.

(E-1. Device architecture)

FIG. 47 is a diagram showing the planar architecture of the MRAM 1000 related to the fifth embodiment of the present invention. In FIG. 47, a multiplexer MUX1 is connected to the first end of a plurality of bit lines BL1 of the MRAM cell array MCA3, and a multiplexer MUX2 is connected to the second end. In addition, a voltage V is applied to the first ends of most word lines WL1 _DD , And NMOS transistor QN1 is connected to the second end of most word lines WL1.

In addition, on the multiplexer MUX1, a plurality of NMOS transistors QM1 designed corresponding to the number of bit lines BL1 are connected, and a capacitor is connected to the source electrode of each NMOS transistor QM1 CP1.

In addition, the multiplexer MUX2 is constituted by connecting a piece of inductor ID1 corresponding to two bit lines BL1. As a result, the multiplexer MUX2 is connected to the total number of bit lines BL1. Half the number of equivalent inductors ID1.

Incidentally, the bit line BL1 and the word line WL1 are connected with the row decoder or the column decoder described using FIG. 26, and the control circuit, but since these are less relevant to this embodiment, In order to simplify the description, the illustration and description are omitted.

(E-2. Device work)

Next, explain the working principle of MRAM1000. Incidentally, in order to facilitate the distinction, there may be cases where BL1a and BL1b are added to the bit line BL1.

First, the word line WL1 containing the selected address is selected, and the direct current I _DC Circulate on the selected word line WL1.

Then, the bit line BL1 containing the selected address is selected by the multiplexer MUX1, and then the current I is written ₁ It flows into the multiplexer MUX2 through the selected bit line BL1a. In this case, using the multiplexer MUX2, select the inductor ID1 connected to the selected bit line BL1a, and write the current I ₁ The energy is stored in the inductor ID1 as a magnetic field.

The bit line BL1 connected to the other side of the inductor ID1 is selected by the multiplexer MUX2, so that the write current I flowing in the inductor ID1 can be made ₁ Flow into the selected bit line BL1b, so that as the current I ₂ To reuse.

The current I ₂ , Through the multiplexer MUX1, the electric charge is stored in the unused capacitor CP1, and then the multiplexers MUX1 and MUX2 are properly connected, and in principle, it can be rewritten unlimited times.

In addition, most of the NMOS transistors QM1 are turned on/off according to the timing of the charge accumulation of the capacitor CP1 and the discharge of the charges from the capacitor CP1, while the majority of the NMOS transistors QN1 are controlled in accordance with the current I _DC The timing of the flow to the word line WL1 is controlled by ON/OFF.

(E-3. Effect)

As described above, the LC resonance of the inductor ID1 and the capacitor CP1 is utilized to reuse the write current on the bit line BL1, thereby reducing the power consumption during the write operation.

(E-4. Modifications)

As a modified example of this embodiment, MRAM 1100 is shown in FIG. 48. In MRAM1100, in addition to the structure of MRAM1100 shown in FIG. 47, a multiplexer MUX3 is connected to the first end of most word lines WL1 in MRAM cell MCA3, and a multiplexer MUX3 is connected to the second end. The multiplexer MUX4 is connected.

In addition, on the multiplexer MUX3, a plurality of NMOS transistors QN1 designed corresponding to the number of the plurality of word lines WL1, and a source electrode of each NMOS transistor QN1 is connected with a capacitor CP2.

In addition, the multiplexer MUX4 is constituted by connecting an inductor ID2 corresponding to the two word lines WL1. As a result, the multiplexer MUX4 is connected to half of the total number of the multiple word lines WL1. Equivalent inductor ID2.

In the MRAM1100 with this structure, in addition to the write current of the bit line BL1, the LC resonance of the inductor ID2 and the capacitor CP2 can also be used to reuse the write current of the word line WL1, thereby further reducing the write work Power consumption caused by current consumption.

Incidentally, as for the current reuse work performed by the LC resonance of the inductor ID2 and the capacitor CP2, since it is the same as the work performed by the LC resonance of the inductor ID1 and the capacitor CP1, the description thereof is omitted.

In addition, the current consumed in the inductor ID1 and the capacitor CP1, the inductor ID2 and the capacitor CP2 is compensated by a well-known current detection type compensation circuit installed on the multiplexers MUX1 to MUX4.

In addition, as the inductors ID1 and ID2, for example, a spiral inductor formed by winding a wire in a spiral shape may be used.

The architecture shown in FIG. 47 and FIG. 48 is only an example of the technical solution. As long as the LC resonance is used to achieve current reuse, it is not limited to the foregoing architecture.

(F. Sixth embodiment) (Characteristics of this embodiment)

The magnetic substrate according to the fifth embodiment of the present invention is characterized in that a multilayer film that becomes a magnetic tunnel junction (MTJ) is formed in advance on the main surface.

(F-1. Substrate structure)

The cross-sectional structure of the magnetic substrate of the fifth embodiment of the present invention is shown in FIG. 49. In FIG. 49, on the entire main surface of the silicon substrate SB, an insulating film IL1 such as a silicon oxide film or a silicon nitride film is disposed, and on it, a conductor that becomes a word line or a bit line is disposed. Layer ML1.

On the upper part of the conductor layer ML1, an n-type silicon layer SF1 with a higher concentration of n-type impurities and a p-type silicon layer SF2 with a higher concentration of p-type impurities are deposited. These two-layer structures later become pn junction diodes.

Furthermore, on the upper part of the p-type silicon layer SF2, there is formed a tungsten layer STD which will become a tungsten plug in the future, and a multilayer film which will become an MTJ in the future is arranged on the tungsten layer STD.

In other words, it has the following in order: a pattern layer TPL made of platinum (Pt); a pattern layer made of Ni ₈₁ Fe ₁₉ The initial ferromagnetic body IFL (thickness 4nm) composed of permalloy; made of Mn ₅₄ Fe ₄₆ Diamagnetic body AFL (thickness 10nm) composed of; made of COFe or Ni ₈₁ Fe ₁₉ Ferromagnetic FFL (thickness 8nm) composed of permalloy; made of Al ₂ O ₃ The tunnel barrier layer TBL is composed of CoFe with a thickness of 2nm and Ni with a thickness of 20nm ₈₁ Fe ₁₉ The soft ferromagnetic layer FML composed of the multilayer film; the contact layer CL composed of Pt.

In addition, on the upper part of the contact layer CL, a conductive layer ML2 that will become a word line or a bit line is arranged, and on the uppermost part, an insulating film IL2 that can serve as an anti-oxidation film of the metal layer is arranged.

As long as this kind of magnetic substrate is sold, the user uses a photoresist mask, and then argon ion milling is used to define the pattern, so that the MRAM cell array MCA1 shown in FIG. 39 is formed.

(F-2. Effect)

In this way, the substrate manufacturer sells a magnetic substrate with a pn junction diode and a multilayer film that can become an MTJ formed on the main surface of the magnetic substrate. The user uses the magnetic substrate, which is compared to a simple substrate. And the technology of forming a multilayer film on the main surface can omit the manufacturing process and reduce the manufacturing cost.

(F-3. Modifications)

A magnetic substrate in which a pn junction diode and a multilayer film that can become MTJ are pre-formed on the main surface of an SOI (Silicon on Insulator) substrate is shown in FIG. 50.

In FIG. 50, the buried oxide film BX is provided on the silicon substrate SB, and the SOI substrate SI is provided on the buried oxide film BX. In addition, a multilayer film similar to that shown in FIG. 49 is arranged on the SOI substrate SI.

As explained using Figure 31 and Figure 33, MRAM requires MOSFETs. Furthermore, forming a MOSFET on the SOI layer can reduce the parasitic capacitance, so that the operating speed of the MOSFET can be improved, and as a result, the operating speed of the MRAM can also be improved.

Incidentally, in the sixth embodiment described above, there is shown a structure in which a multilayer film that becomes a magnetic tunnel junction is deposited on a bulk silicon substrate or an SOI substrate, and will be referred to as a magnetic substrate. The multilayer film of magnetic tunnel junction (multilayer film of thin film magnetic material) can also be deposited on a glass substrate or a resin substrate, and the type of substrate that becomes the base material is not limited to a semiconductor substrate.

Therefore, in the present invention, a structure in which a certain substrate is used as a base material and a multilayer film of a thin film magnetic body is deposited is called a thin film magnetic substrate.

(G. Seventh embodiment) (Characteristics of this embodiment)

The MRAM of the seventh embodiment of the present invention is characterized in that the MRAM is formed on various functional blocks formed on the main surface of the substrate.

(G-1. Device architecture)

First, in order to explain the difference of this embodiment, in FIG. 51, a block diagram of the structure of a conventional general semiconductor memory device is shown.

In FIG. 51, as the peripheral circuits of the memory cell array 31, the row address buffer 31, the row decoder 32, the row read/write control circuit 33, the column address buffer 34, the column decoder 35, and the column The read/write control circuit 36 is arranged around the memory cell array 31.

In addition, as other functional blocks, there are: ESD (ElectricStatic DisCharge) circuit 44, which is an input/output buffer (I/O buffer) used for signal transmission and reception with the outside of the device, and the above-mentioned signals. When it is overshoot or undershoot in the standard value, it is attributed to the standard value; Modulator/Demodulator 43, which has the ability to demodulate the modulated signal or modulate the signal Function; DSP (Digital Signal Processing) 42, which has the function of processing digital signals; the first cache memory 51 and the second cache memory 52, which are used to carry out data between the memory cell array 31 and peripheral circuits Intermediary for transmission and reception (temporary storage of data), or synchronization of data transmission and reception between the peripheral circuit and the memory cell array 31; input/output controller (I/O controller), which is used to control the memory cell array 31 Data input/output; CPU (Micro Processer) 41, which is used for data processing.

Previous semiconductor devices, such as DRAM, SRAM, EEPROM, etc., include MOSFETs in their memory cell arrays. Therefore, they must be formed on the main surface of the semiconductor substrate. As a result, the memory cell arrays are formed on the main surface of the semiconductor substrate. The blocks are the same on the main surface of the semiconductor substrate.

Here, the architecture of the MRAM 1200 related to the seventh embodiment of the present invention is shown in FIG. 52 as a block diagram.

In Figure 52, the MRAM cell array MCA is the peripheral circuit of the MRAM cell array MCA, namely the row address buffer CAB, the row decoder CD, the row read/write control circuit CRW, and the column address buffer The RAB, the column decoder RD, the column read/write control circuit RRW, etc. are arranged to overlap with the arrangement area.

In addition, the structure of the peripheral circuit is the same as that described using, for example, FIG. 26, and the other functional blocks are the same as the previous semiconductor device, so the description is omitted.

(G-2. Effect)

The MRAM cell array MCA, as described with reference to FIGS. 28, 31, and 33, does not contain a MOSFET inside, but contains a pn junction diode as a semiconductor element, so its formation area is not limited to the main surface of the substrate.

Therefore, for structures other than the MRAM cell array MCA, that is, the peripheral circuits containing the MRAM cell array MCA, various functional blocks are formed on the main surface of the substrate, and the MRAM cell array MCA is formed on the upper layer. To reduce the device area.

(G-3. Modifications)

As a modification of this embodiment, MRAM 1300 is shown in FIG. 53 as a block diagram.

As shown in FIG. 53 in the MRAM 1300, the MRAM cell array MCA is arranged so as to overlap the entire upper part of the area where the peripheral circuits and various functional blocks are formed.

In this way, the MRAM cell array MCA, peripheral circuits, and various functional blocks are formed separately, thereby increasing the freedom of the placement and scale of the MRAM cell array MCA, reducing the device area, and improving the device layout. The selectivity.

(H. Eighth embodiment) (Characteristics of this embodiment)

Regarding the MRAM of the eighth embodiment of the present invention, it is characterized by adopting MCP (Multi Chip Package), which is the MRAM cell array, the peripheral circuits of the MRAM cell array, and various functional blocks, which are individually made into different semiconductor chips. And the two chips are modularized and housed in a single package.

(Preface)

The maximum formation temperature during the manufacture of peripheral circuits and various functional blocks of the MRAM cell array is as high as about 1000~1200°C. In contrast, the maximum formation temperature during the manufacture of the MRAM cell array is about 400~700°C, which is determined by Curie temperature.

When the two are formed on the same substrate, in order to avoid problems caused by different forming temperatures, the MRAM cell array is formed in a wiring process with a forming temperature of about 400 to 700°C.

For this reason, in the manufacturing steps of MRAM, the steps are formed continuously, and there is a problem that the manufacturing cost is required.

In contrast to this, in recent years, the MCP structure containing many semiconductor chips in a single package has been gradually used. In view of these current conditions, the inventor has learned that although the MRAM cell array and the peripheral circuits of the MRAM cell array and the Various functional blocks are individually made into different semiconductor chips, and the two chips are modularized and housed in a single package MRAM, which can solve the above-mentioned problem. But in fact, in order to obtain an MCP structured MRAM, it is It is not possible to respond to MRAM with the previous package structure.

Before explaining the problems on the MRAM in order to realize the MCP structure, the structure of the MRAM 2000 of the eighth embodiment will be explained as follows.

(H-1. Regarding the previous MCP structure)

A method for assembling semiconductor wafers containing semiconductor devices. Previously, QFP (Quad Flat Package) was used, but it still has the problem of large assembly area. Therefore, only the CSP (ChipSize Package), which has the same assembly area as the chip area, has begun to be used in recent years. This assembly method only needs to be considerably smaller than the QFP assembly area, so it is used in LSIs in mobile phones or DRAMs in PCs (Personal Computers). An example of the previous CSP architecture is shown in FIG. 54 as a cross-sectional view.

In FIG. 54, the semiconductor chip 122 is housed in a box-shaped package 129, and the lower main surface of the semiconductor chip 122 is covered by a passivation film 123 to protect it from the external environment.

The passivation film 123 is composed of an insulating film such as a silicon nitride film or a silicon oxynitride film, and the passivation film 123 is designed with a large number of openings, which is a chip that can be used as input/output terminals of the semiconductor chip 122 The electrode 132 penetrates the structure of the passivation film 123.

The package body 129 has a box shape with a bottom and no cover, and the semiconductor chip 122 is inserted through the opening thereof. Here, the opening of the package body 129 is finally covered by the bottom substrate 134. The main system of the bottom substrate 134 is made of insulating materials such as polyimide resin, and the main surface facing the outside is provided with many solder bumps 125 for shielding and solder bumps 127 for signal transmission.

The bottom substrate 134 has a plurality of internal wirings 130 and 131 for electrically connecting the solder bumps 125 for shielding and the solder bumps 127 for signal transmission to the inside.

The internal wirings 130 and 131 are both connected to the mounting film 124 arranged on the main surface facing the inner side of the bottom substrate 134. As described later, the mounting film 124 has conductive wiring (including a spacer) and an adhesive layer 133 arranged on the insulating film. The electrical signal from the solder bump 127 for signal transmission is transmitted to the semiconductor wafer 122 via a wafer electrode 132 on the pad connected to the internal wiring 130 and the mounting film 124. In addition, the adhesion layer 133 is used to adhere the mounting film 124 and the semiconductor wafer 122. In addition, although not shown in FIG. 54, the mounting film 124 is adhered by another adhesive layer together with the bottom substrate 134.

In addition, a shield electrode 126 made of a conductor is embedded in the bottom substrate 134. The shielding electrode 126 has a rectangular ring shape in plan view, and has a structure with an opening through which the internal wiring 130 does not contact the shielding electrode 126. FIG. 54 is a cross-sectional view of the opening of the shielding electrode 126 cut at a specified position, and the opening is indicated by a broken line.

The shielding electrode 126 is fixed at the power supply potential or the ground potential via the shielding solder bump 125 and the internal wiring 131 to prevent the internal wiring 130 from being affected by electrical noise.

In addition, the semiconductor wafer 122 is surrounded, and a shielding electrode 126b is arranged on the upper main surface of the mounting film 124. The shielding electrode 126b is a flat plate having a rectangular ring shape in plan view, and is electrically connected to the internal wiring 131 via the conductive wiring on the mounting film 124 so as to be fixed at the power supply potential or the ground potential .

The stress relaxation film 135 is arranged so as to cover the shielding electrode 126b. The stress relaxation film 135 serves to relax the stress between the semiconductor wafer 122 and the bottom substrate 134.

Although the cross-sectional shape of the stress relaxation film 135 is originally rectangular, it is sandwiched between the edge of the semiconductor wafer 122 and the mounting film 124, so that it is deformed and the local thickness becomes thinner. In other words, the stress is concentrated on the part sandwiched between the edge of the semiconductor wafer 122 and the mounting film 124, and the stress can be relieved due to the natural thinning of the thickness.

For the stress relaxation film 135, for example, a thermoplastic elastomer is used. Thermoplastic elastomer, which exhibits rubbery elasticity at room temperature, is hardened at high temperature. It is also a polymer material that can be formed in various ways.

In addition, as for the adhesive material between the semiconductor wafer 122 and the stress relaxation film 135, epoxy resin or the like is used. The volume expansion coefficient of thermoplastic elastomer is about 2.7×10 ^-6 , In contrast to this, the volumetric expansion coefficient of silicon is about 3.1×10 ^-6 , So the difference in volume expansion coefficient is small, and thermal stress can be alleviated.

In the semiconductor package, in order to achieve the simultaneous establishment of the number of terminals and the miniaturization of the package, it is inevitable that there are problems: the internal wiring is longer and thinner, and is more susceptible to noise. Therefore, the shielding electrode 126 and the stress relaxation film 125 are provided. In addition, a stress relaxation film 135 is provided to prevent the thermal stress between the semiconductor wafer 122 and the bottom substrate 134 from increasing, thereby reducing the reliability of the electrical connection.

The function of the shielding electrode 126 is as described above. The shielding electrode 126 is connected to the stress relaxation film 125 via the internal wiring 131. Furthermore, the stress relaxation film 125 is arranged to surround the solder bumps 127 for signal transmission, and has a function of preventing the internal wiring 130 from being affected by noise through the solder bumps 127 for signal transmission. Incidentally, although illustration is omitted, the stress relief film 125 and the solder bumps 127 for signal transmission are both connected to a motherboard designed with wiring.

In addition, the previous MCP structure can only be implemented in QFP. The cross-sectional structure of the MCP structure using QFP is shown in Figure 55. In FIG. 55, three semiconductor chips 102a, 102b, and 102c are arranged overlappingly in a single package body 107, and are packaged with resin 106.

As for an example of its technical solution, specifically, the semiconductor chips 102a and 102c are SRAM, and the semiconductor chip 102b is a flash EEPROM. Each semiconductor chip is connected by an internal wiring 109, and the electrical connection with the outside world is realized by a bonding wire 112 and an external wire 113.

By adopting these structures, compared with the structure in which only one semiconductor chip can be provided in a single package, more memory capacity can be obtained corresponding to the same occupied area. As a result, there are many demands for use on mobile phones.

However, QFP still has problems: the chip area will increase the assembly area, and the external wires are susceptible to noise.

In this way, both CSP and QFP have their own shorts and longs, and in MRAM, there is a need to avoid the spin reversal of the soft ferromagnetic layer caused by the influence of the external magnetic field, and the previous package structure cannot be used directly. .

(H-2. Device architecture)

Using FIGS. 56 to 65, the structure of the MRAM 2000 of the eighth embodiment will be described as follows.

The cross-sectional structure of the MRAM2000 is shown in FIG. 56, and the planar structure viewed from the bottom side is shown in FIG. 57. Still, Fig. 56 shows the cross section of line AA in Fig. 57.

As shown in Figure 56, the semiconductor chip 122 containing the peripheral circuits of the MRAM cell array and various functional blocks is housed in a permalloy (Ni ₈₀ Fe ₂₀ ) In a box-shaped shielding body SHB composed of conductors with high permeability.

As a material for the shielding body SHB, a material having a permeability equivalent to that of a soft ferromagnetic body used in MRAM memory cells, or as a ferromagnetic body having a permeability greater than that of a permalloy, can also be used in addition to permalloy (superalloy). )(Mo ₅ Ni ₇₉ Fe ₁₆ ). A ferromagnetic body with a large coercive force becomes a permanent magnet and may have a vicious influence on the surrounding electrical machinery. Therefore, it is preferable to use a ferromagnetic body with a small coercive force. Permalloy and super alloy, Mn ₅₀ Zn ₅₀ Other ferrites and the like are materials that all satisfy these conditions.

On the inner wall surface of the shielding body SHB, a stress relaxation film 235 made of a thermoplastic elastomer is arranged. The stress relaxation film 235 acts to relax the stress of the semiconductor wafer 122 and the shielding body SHB.

The shielding body SHB is composed of a cylindrical outer frame portion 237 as its main body, an upper plate 238 covering one end of the outer frame portion 237, a lower plate 236 covering the other end of the outer frame portion 237, and a stress relaxation film 235 It is arranged on the inner surface of the upper plate 238 and the outer frame portion 237.

In addition, an opening is designed on the lower board 236, and the internal wiring 130 connected to the semiconductor chip 122 penetrates the opening.

The package body 129 has a box shape with a bottom and no cover, and forms a structure for inserting the shielding body SHB with the semiconductor chip 122 through the opening thereof.

The package body 129 has a size that also accommodates the shielding body SHB without leaving space, and a resin material 128 made of resin such as epoxy resin is arranged between the shielding body SHB and the inner wall of the package body 129.

The opening of the package body 129 is finally covered by the bottom substrate 134. The main system of the bottom substrate 134 is made of insulating materials such as polyimide resin, and the main surface facing the outside is provided with many solder bumps 125 for shielding and solder bumps 127 for signal transmission. In addition, the bottom substrate 134 is fixed with an adhesive applied on the mounting film 124 or the lower plate 236.

The bottom substrate 134 has a plurality of internal wirings 130 and 131 for electrically connecting the solder bumps 125 for shielding and the solder bumps 127 for signal transmission to the inside.

The internal wiring 130 and 131 are both connected to the mounting film 124 arranged on the main surface facing the inner side of the bottom substrate 134, and the internal wiring 131 is connected to the mounting film 124 via the spacer and The conductive wiring is electrically connected to the lower plate 236 of the shielding body SHB.

In addition, the internal wiring 131 is electrically connected to a shielding electrode 126 composed of a conductor embedded in the bottom substrate 134. Incidentally, a certain part of the shielding electrode 126 does not necessarily exist in the same cross section of the internal wiring 130 and the internal wiring 131, so it is shown by a broken line in FIG. 56.

In addition, the shielding electrode 126 is fixed at the power supply potential or the ground potential to prevent the internal wiring 130 from being affected by external electrical noise.

The wafer electrode 132, which becomes the input/output terminal of the semiconductor wafer 122, is directly connected to a pad (sheet electrode) arranged on the mounting film 124, via the sheet electrode and conductive wiring arranged on the mounting film 124 , Is electrically connected to the internal wiring 130. Incidentally, the internal wiring 130 is connected to the solder bump 127 for signal transmission.

The solder bump 127 for signal transmission is a terminal for receiving electrical signals between the outside and the inside, and the stress relief film 125 is a terminal for fixing the potential of the shield SHB to the ground potential.

Moreover, as shown in FIG. 57, the stress relaxation film 125 is arrange|positioned so that it may surround the solder bump 127 for signal transmission.

Incidentally, the solder bumps 127 for signal transmission and the stress relaxation film 125 both have the function of dispersing the stress on the bottom substrate 134 to the mounting substrate (mother board). The stress relaxation film 125 is designed to reduce The stress experienced by each solder bump.

(H-3. Assembly method)

Next, using FIGS. 58 to 62, an overview of the assembly method of MRAM2000 will be described as follows. Incidentally, FIGS. 58 to 62 all show the assembly method of the MRAM 2000 in a schematic manner, and do not accurately represent the architecture shown in FIG. 56.

In FIG. 58, a mounting film 124 is adhered to the upper portion of the bottom substrate 134, and a stress relaxation film 223 is adhered to the mounting film 124.

The stress relieving film 223 has a rectangular ring shape and is arranged to surround the arrangement area of the sheet electrode 219 designed on the mounting film 124. In addition, a rectangular ring-shaped groove 224 is formed on the stress relaxation film 223, and the lower plate 236 of the shielding body SHB is arranged in the groove 224 (FIG. 56 ). In addition, the structure in which the lower plate 236 is arranged in the groove 224 is shown in Fig. 64(a) and Fig. 64(b).

In addition, although the illustration is omitted, in the subsequent manufacturing process, the outer frame portion 237 of the shielding body SHB is arranged along the groove 224 and is connected to the lower plate 236.

Incidentally, because the stress relaxation film 223 has a rectangular ring shape, the stress can be reduced in both the X direction and the Y direction shown in FIG. 58.

The sheet electrode 219 arranged on the placement film 124 of the insulator is connected to the solder bump 127 for signal transmission via the internal wiring 130.

In addition, the sheet electrode 219 and the internal wiring 130 on the mounting film 124 are excessively defined in patterns, so that the connection state between each bump and each wafer electrode can be set arbitrarily.

On the mounting film 124, in addition to the sheet electrode 219, an adhesive layer 133 is more selectively formed. The adhesion layer 133 is used to adhere the semiconductor wafer 122 and the mounting film 124.

Next, in the manufacturing process shown in FIG. 59, each wafer electrode of the semiconductor wafer 122 is in contact with each of the sheet electrodes of the mounting film 124 and the semiconductor wafer 122 is mounted, and the semiconductor wafer 122 is fixed by the adhesive layer 133 .

FIG. 60 shows a state where the bottom substrate 134 in the state shown in FIG. 59 is reversed, and the bottom substrate 134 is provided with a hemispherical solder bump forming hole 211. The internal wiring 130 and the internal wiring 131 (see FIG. 56) reach the inner wall surface of the solder bump forming hole 211. In the subsequent process, the solder bump forming hole 211 is filled with solder bumps to make the solder The bumps are electrically connected to the internal wiring 130, the internal wiring 131, and the like. In addition, conductive polymers can also be used instead of solder bumps.

FIG. 61 shows a state in which the solder bump 127 for signal transmission and the stress relaxation film 125 are arranged on the solder bump forming hole 211.

Next, after covering the semiconductor wafer 122 with a shielding body SHB with a stress-relieving film 235 (in FIG. 56) inside, insert it into the package 129 with a bottom and no lid, and then fill the gap with a sealant such as resin In order to obtain a structure with a signal transmission solder bump 127 and a stress relaxation film 125 on the back, as shown in FIG. 62.

Here, using FIGS. 63, 64(a), and 64(b), the plan view shapes of the lower plate 236 and the stress relaxation film 223 that constitute the shielding body SHB will be described. Incidentally, FIG. 63 shows a schematic cross-sectional structure taken from the line BB in FIG. 56, and FIGS. 64(a) and 64(b) both show the cross-sectional structure taken from the line CC and D in FIG. 63. -Sectional structure of line D.

As shown in FIG. 63, the lower plate 236 is composed of a rectangular flat plate with a rectangular opening OP at the center. On the side of the bottom substrate 134, a rectangular ring shape for electrically connecting to the stress relaxation film 125 is provided. The shielding electrode 126 (Figure 56). Incidentally, the outer size of the shielding electrode 126 is approximately the same as the outer size of the lower plate 236.

In addition, the stress relaxation film 223 is arranged on the inside and outside of the opening edge of the shielding body SHB, and the stress relaxation film 235 (FIG. 56) is arranged on the entire inner side of the shielding body SHB, so that the semiconductor chip 231 and the semiconductor chip can be reduced. 232 is subjected to external stress.

(H-4. Effect)

According to the MRAM 2000 of the eighth embodiment as described above, a shielding body SHB for shielding an external magnetic field is used to surround the semiconductor wafer 122 containing the MRAM cell array to prevent the spin of the MRAM cell from being reversed due to the external magnetic field. Changing the magnetization direction instead, in other words, can prevent the data from being overwritten.

In addition, the stress relaxation film 223 is arranged inside and outside the opening edge of the shielding body SHB, and the stress relaxation film 235 is arranged inside the shielding body SHB, so that it can reduce: the mounting substrate (mother board) when MRAM2000 is installed The stress from the outside caused by bending, temperature cycling and external stress is applied to the semiconductor wafer 122.

(H-5. The first modification)

In the MRAM2000 described above, although only one semiconductor chip is assembled, it is shown that, like the MRAM2100 shown in FIG. 65, it can also be a type of semiconductor including peripheral circuits of the MRAM cell array and various functional blocks. On the chip 122a (circuit chip), a structure of a semiconductor chip 122b (magnetic storage chip) containing an MRAM cell array is placed.

The semiconductor wafer 122a is provided with wafer electrodes on both main surfaces, and the semiconductor wafer 122a and the semiconductor wafer 122b are connected by a thin electrode and electrical wiring on a mounting film 124b arranged between the two. In addition, the semiconductor wafer 122a and the semiconductor wafer 122b are both adhered and fixed by the adhesive layer 133.

Incidentally, the electrical connection between the semiconductor chip 122a and the signal transmission solder bump 127 is the same as the connection state between the semiconductor chip 122 and the signal transmission solder bump 127 shown in 65, except for The mounting film 124 is basically the same as the MRAM2000 except for the mounting film 124a, so its description is omitted.

In addition, both the semiconductor wafer 122a and the semiconductor wafer 122b may be arranged in an up-and-down relationship. In this case, it is only necessary to arrange wafer electrodes on both sides of the semiconductor wafer 122b.

In addition, as for the combination state of the semiconductor wafer 122a and the semiconductor wafer 122b, as long as the MRAM cell array is arranged on at least one of the wafers, any known semiconductor wafers can be combined arbitrarily.

In the MRAM2100 shown in FIG. 65, the semiconductor chip 122a containing the peripheral circuits and various functional blocks of the MRAM cell array, and the semiconductor chip 122b of the MRAM cell array are manufactured separately and combined, so there is no need to Taking into account the difference in the formation temperature, the optimization of the individual formation temperature can be achieved. Furthermore, since the semiconductor wafer 122a and the semiconductor wafer 122b are manufactured separately, the manufacturing process can be performed in parallel, so that the manufacturing time can be shortened.

(H-6. Second modification)

In the MRAM2000 shown in Fig. 56, a ferromagnetic body is used as the material of the shielding body SHB. However, an anti-ferromagnetic body such as IrMn containing 20-30 atom.% of Ir (iridium) is used instead of it. Achieve the same effect.

In addition, like the MRAM 2200 shown in FIG. 66, the shielding body SHB may be composed of a multilayer film of a ferromagnetic body 136a and an anti-ferromagnetic body 136b. In this case, the shielding electrode 126 in the bottom substrate 134 acts as a multilayer film of the ferromagnetic body 126a and the antiferromagnetic body 126b. In addition, the vertical relationship of the multilayer film is not limited to the above-mentioned form.

[Effects of the invention]

According to the magnetic memory device of the present invention, at least one of the magnetic tunnel junctions is the easy axis of magnetization in the direction in which the soft ferromagnetic layer is easier to be magnetized, and is the direction in which most bit lines and most word lines extend It is arranged with an angle of 40 to 50 degrees, so even if a small write current is used, the direction of magnetization can be reversed accurately, so that the power consumption when performing the write operation is reduced.

According to the magnetic memory device related to the present invention, in the planar view shape of the magnetic tunnel junction, one side parallel to the easy axis is longer than one side perpendicular to the easy axis, and is formed in a rectangular shape. shape due to anisotropic, the axis of easy magnetization can easily fixed, and have prevented the easy axis of magnetization changes.

According to the magnetic memory device related to the present invention, the first and second switching devices can be used to switch the first and second ends of the bit line to be connected to the first or second power source, so that it can be connected to the bit line Bidirectional current flows, and the magnetization direction of the magnetic tunnel junction is changed, so that the writing or erasing of data can be realized.

According to the magnetic memory device of the present invention, the first and second switching devices are both composed of the first to the fourth MOS transistors with the same conductivity, so it is easy to manufacture.

According to the magnetic memory device of the present invention, the first switching device is composed of first and second MOS transistors with different conductivity, and the second switching device is composed of third and fourth MOS transistors with different conductivity. It is composed of a transistor, so it is not necessary to apply a voltage higher than the power supply voltage to the control electrode of one of the first and second MOS transistors and one of the third and fourth MOS transistors when it is in the ON state. This reduces the load generated on the gate insulating film.

According to the magnetic memory device related to the present invention, between the first main electrodes of the first and second MOS transistors, and between the first main electrodes of the third and fourth MOS transistors, there is a first normally ON state. 5. The sixth MOS transistor, so it can reduce the forced voltage generated between the first main electrodes of the first and second MOS transistors and between the first main electrodes of the third and fourth MOS transistors, and can reduce The leakage current caused by the forced voltage reduces the power consumption.

According to the magnetic memory device related to the present invention, in a magnetic memory device having a plurality of memory cell arrays, a plurality of main word lines straddling the plurality of memory cell arrays and only straddling a single memory cell array are used. The word line can reduce the number of memory cells directly connected to the same wiring, thereby reducing the load capacity. As a result, the delay time caused by the load capacity can be shortened, enabling high-speed access.

According to the magnetic memory device related to the present invention, in a magnetic memory device having a plurality of memory cell array groups formed by a plurality of memory cell arrays, word lines that only span a single memory cell array are used, and word lines that are spanned across the majority are used. The majority of the main word lines on the memory cell array and the general word lines across the group of memory cell arrays can reduce the number of memory cells directly connected to the same wiring, thereby reducing the load capacity. As a result, the delay time caused by the load capacity can be shortened, enabling high-speed access.

According to the magnetic memory device related to the present invention, in the magnetic memory device having a plurality of memory cell arrays, a plurality of main bit lines straddling the plurality of memory cell arrays are used and only straddling a single memory cell array The number of bit lines can reduce the number of memory cells directly connected to the same wiring, thus reducing the load capacity. As a result, the delay time caused by the load capacity can be shortened, enabling high-speed access.

According to the magnetic memory device related to the present invention, in a magnetic memory device having a plurality of memory cell array groups formed by a plurality of memory cell arrays, a bit line that only straddles a single memory cell array is used to straddle The main bit lines on the most memory cell arrays and the general bit lines straddling the most memory cell array groups can reduce the number of memory cells directly connected to the same wiring, thereby reducing the load capacity. As a result, the delay time caused by the load capacity can be shortened, enabling high-speed access.

According to the magnetic memory device of the present invention, there is an inductor capable of generating a magnetic field along the direction of the easy magnetization axis in the direction in which the soft ferromagnetic layer is easier to be magnetized. Most of the data in the memory unit can be erased or written in batches, thus making it possible to process in a short time.

According to the magnetic memory device related to the present invention, a coil-shaped inductor is used to generate a magnetic field more effectively. Therefore, when performing batch erasing or batch writing of data in a large number of memory cells, it can be completed with less power consumption. .

According to the magnetic memory device related to the present invention, there are flash bit lines and flash word lines outside the most bit lines and most word lines of at least one memory cell, and for these predetermined currents, it is possible to For data of a plurality of memory cells with at least one magnetic tunnel junction, a batch erasing or a batch writing of the data is performed, thereby enabling short-time processing.

According to the magnetic memory device of the present invention, in the magnetic memory device where a plurality of memory cell arrays are arranged in an array, the flash bit lines and flash word lines can also be arranged along the plurality of memory cell arrays. The array is arranged to form the array base, so that batch erasing or batch writing can be performed for the data of a large number of memory cell arrays, thereby enabling short-time processing.

According to the magnetic memory device of the present invention, there is at least one inductor and at least one capacitor. The current flowing on at least one of the selected bit line and the word line is stored by LC resonance. Therefore, the write current can be reused, so that the power consumption when performing the write operation is reduced.

According to the magnetic memory device of the present invention, a specific structure can be obtained that can reuse the write current on the bit line.

According to the magnetic memory device of the present invention, a specific structure can be obtained that can reuse the write current on the word line.

According to the magnetic memory device related to the present invention, at least one semiconductor chip is contained in a shielding body composed of a conductor, so that the magnetization of the magnetic tunnel junction can be prevented in a plurality of memory cells containing at least one magnetic tunnel junction The direction is reversed by the external magnetic field, so that the data is overwritten.

According to the magnetic memory device related to the present invention, at least one semiconductor chip can be held by the first and second stress relaxation films, so that the stress applied to a plurality of semiconductor chips can be reduced.

According to the magnetic memory device of the present invention, it is divided into a magnetic storage chip and a circuit chip containing a peripheral circuit of the memory cell array, so that the two are manufactured separately without considering the difference in the formation temperature, so that the individual formation temperature can be achieved. optimize. Moreover, the manufacturing process can be performed in parallel, so that the manufacturing time can be shortened.

According to the magnetic memory device of the present invention, the shielding body is composed of an anti-ferromagnetic body, so that the external magnetic field can be shielded more effectively.

According to the magnetic memory device of the present invention, the shielding body is composed of a multilayer film of a ferromagnetic body and an anti-ferromagnetic body, so it can more effectively shield the external magnetic field.

According to the magnetic memory device of the present invention, there is at least one multilayer film arranged on the entire main surface and forming at least one magnetic tunnel junction. Therefore, when manufacturing a memory cell with at least one magnetic tunnel junction In the case of a magnetic memory device, compared to the technology of preparing a simple substrate and forming a multilayer film on its main surface, the manufacturing process can be omitted and the manufacturing cost can be reduced.

According to the magnetic memory device of the present invention, a magnetic substrate suitable for a magnetic memory device having a memory unit can be obtained, and the memory unit has a single magnetic tunneling combination.

According to the magnetic memory device of the present invention, a semiconductor substrate suitable for a magnetic memory device having a memory cell can be obtained, the memory cell of which has a pn junction diode at the lower part of the single magnetic tunnel junction.

According to the magnetic memory device of the present invention, at least one magnetic tunnel junction is formed on the SOI substrate that can reduce the parasitic capacitance of the MOSFET, so that the operating rate of the MOSFET can be increased, and as a result, the operating rate of the magnetic memory device can be increased.

Symbol description of main components

1~3, 160, 169, 189. . . Word line

4~6, 69, 89, 160. . . Bit line

7. . . pn junction diode

8. . . MTJ

9. . . MRAM cell

10. . . n ⁺ Silicon layer

11. . . p ⁺ Silicon layer

12. . . Tungsten embolism

13. . . Silicon oxide film

15. . . Type plate layer

16. . . Initial ferromagnetic body

18. . . Diamagnetic body

20, 126a. . . Ferromagnetic

twenty two. . . Tunnel barrier layer, soft ferromagnetic layer

twenty four. . . Soft ferromagnetic layer

25. . . Contact layer

26. . . Silicon oxide film

30. . . Detection current

31. . . Memory cell array, bit line control circuit

32. . . Word line control circuit

33. . . Row read/write control circuit

36. . . Column read/write control circuit

41. . . CPU

42. . . DSP

43. . . Modulation and demodulation circuit

44. . . ESD circuit

51. . . First cache memory, bit line control circuit

52. . . Second cache

53. . . I/O controller, word line control circuit

61, 62, 81, 82, 162, 181. . . AND gate

64, 83. . . Vice word line

66, 85, 166, 185, 851. . . MRAM cell array

67, 84. . . Main word line

70, 170. . . Memory cell array selection line

80. . . Main universal decoder

87. . . Universal word line

88, 188. . . Address signal line group

102a, 102b, 102c. . . Semiconductor wafer

106. . . Resin

107, 129. . . Package body

109, 130, 131. . . Internal wiring

112. . . Welding line

113. . . External wire

122, 231, 232. . . Semiconductor wafer

123. . . Passivation film

124, 124b. . . Mounting film

125. . . Stress relief film, solder bumps for shielding

126, 126b. . . Shield electrode

127. . . Solder bumps for signal transmission

128. . . Resin material

132. . . Wafer electrode

133. . . Adhesive layer

134. . . Bottom substrate

135. . . Stress relaxation film

136a. . . Ferromagnetic

161. . . NAND gate

164, 183. . . (Auxiliary) bit line

167, 184. . . Thematic line

187. . . Universal bit line

211. . . Solder bump forming hole

219. . . Sheet electrode

223, 235. . . Stress relaxation film

224. . . Groove

236. . . Lower board

237. . . Outer frame

238. . . On board

861, 1861. . . Memory cell array group

901,1901. . . Memory cell array group selection line

911, 1911. . . Memory cell array selection line

BL. . . Bit line

W1. . . Word line

WL1a, b. . . Select word line

BL1b. . . Select bit line

MA. . . MRAM cell array

Hk. . . Combined magnetic field

CAB. . . Row address buffer

MCA. . . MRAM cell array

CD, 32. . . Row decoder

MUX. . . Multiplexer

CRW1. . . Row read/write first control circuit

RAB, 34. . . Column address buffer

RD, 35. . . Column decoder

RRW1. . . Column read/write first control circuit

IOB. . . Input/output buffer

CRW2. . . Row read/write second control circuit

R. . . Variable resistor

D. . . Diode

MN, QN, PN, QM. . . NMOS transistor

TA. . . Terminal

PN. . . pn junction diode

GBL. . . Universal flash bit line

GWL. . . Universal flash word line

CP. . . Capacitor

SB. . . Silicon substrate

IL. . . Insulating film

ML. . . Conductor layer

SF1. . . n-type silicon layer

SF2. . . P-type silicon layer

STD. . . Tungsten layer

TPL. . . Type plate layer

IFL. . . Initial ferromagnetic body

AFL. . . Diamagnetic body

FFL. . . Ferromagnetic

TBL. . . Tunnel barrier

FML. . . Soft ferromagnetic layer

CL. . . Contact layer

BX. . . Buried oxide film

SI. . . SOI substrate

OP. . . Opening

MC. . . MRAM cell

ID. . . Inductor

FBL. . . Flash bit line

FWL. . . Flash word line

SHB. . . Masking body

FM. . . Ferromagnetic layer

TB. . . Insulation

AF. . . Antiferromagnetic layer

BD. . . Substrate

MC2, MC3. . . MRAM cell

Schematic description

Figure 1 is an oblique view showing the architecture of the MRAM cell.

Figure 2 is a diagram showing the architecture of a commonly used MRAM cell array.

Fig. 3 is a diagram for explaining the operation of a commonly used MRAM cell array.

Fig. 4 is a diagram showing the relationship of the magnetic field required to reverse the spin.

FIG. 5 is a diagram showing the MRAM cell array structure related to the first embodiment of the present invention.

FIG. 6 is a diagram showing the operating state of the MRAM cell array related to the first embodiment of the present invention.

FIG. 7 is a diagram showing the MRAM cell array architecture related to the first embodiment of the present invention.

FIG. 8 is a diagram showing the operating state of the MRAM cell array related to the first embodiment of the present invention.

FIG. 9 is a diagram used to illustrate the working state of a commonly used MRAM cell.

FIG. 10 is a diagram for explaining the working state of a commonly used MRAM cell.

Fig. 11 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 12 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 13 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 14 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 15 is a diagram showing the relationship of the magnetic field required to reverse the spin.

Fig. 16 is a diagram for explaining the working state of a commonly used MRAM cell.

FIG. 17 is a diagram for explaining the working state of a commonly used MRAM cell.

Fig. 18 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 19 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 20 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 21 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 22 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

FIG. 23 is a diagram for explaining the operation state of the MRAM cell according to the first embodiment of the present invention.

Fig. 24 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

Fig. 25 is a diagram for explaining the operating state of the MRAM cell according to the first embodiment of the present invention.

FIG. 26 is a block diagram showing the MRAM architecture related to the second embodiment of the present invention.

FIG. 27 is a circuit diagram showing the MRAM architecture of the second embodiment of the present invention.

FIG. 28 is a timing diagram showing the MRAM architecture of the second embodiment of the present invention.

Fig. 29 is a graph showing the dependence of the change rate of the magnetic tunnel resistance on the applied voltage.

FIG. 30 is a diagram showing the architecture of the dual magnetic tunnel junction.

FIG. 31 is a circuit diagram showing the MRAM architecture related to the second embodiment of the present invention.

FIG. 32 is a timing chart showing the MRAM architecture of the second embodiment of the present invention.

FIG. 33 is a circuit diagram showing the MRAM architecture related to the second embodiment of the present invention.

FIG. 34 is a block diagram showing the structure of dividing the word line of the MRAM according to the third embodiment of the present invention.

35 is a block diagram showing a hierarchical structure of MRAM word lines related to the third embodiment of the present invention.

FIG. 36 is a schematic diagram showing a hierarchical structure of MRAM word lines related to the third embodiment of the present invention.

FIG. 37 is a block diagram showing the structure of dividing the MRAM bit line related to the third embodiment of the present invention.

FIG. 38 is a block diagram showing a hierarchical structure of MRAM bit lines related to the third embodiment of the present invention.

Fig. 39 is a perspective view showing the MRAM architecture related to the fourth embodiment of the present invention.

Fig. 40 is a cross-sectional view for explaining the operation state of the MRAM according to the fourth embodiment of the present invention.

Fig. 41 is a cross-sectional view for explaining the operation state of the MRAM according to the fourth embodiment of the present invention.

Fig. 42 is a cross-sectional view for explaining the operation state of the MRAM according to the fourth embodiment of the present invention.

FIG. 43 is a plan view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 44 is a cross-sectional view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 45 is a cross-sectional view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 46 is a plan view showing the structure of a modification of the MRAM related to the fourth embodiment of the present invention.

FIG. 47 is a plan view showing the MRAM architecture of the fifth embodiment of the present invention.

Fig. 48 is a plan view showing the MRAM architecture of the fifth embodiment of the present invention.

FIG. 49 is a cross-sectional view showing the structure of a semiconductor substrate according to a sixth embodiment of the present invention.

FIG. 50 is a cross-sectional view showing the structure of a semiconductor substrate according to a sixth embodiment of the present invention.

Figure 51 is a block diagram showing a commonly used MRAM architecture.

FIG. 52 is a block diagram showing the MRAM architecture of the seventh embodiment of the present invention.

FIG. 53 is a block diagram showing the MRAM architecture of the seventh embodiment of the present invention.

FIG. 54 is a cross-sectional view showing the MRAM architecture that is commonly packaged.

FIG. 55 is a cross-sectional view showing the MRAM architecture that is commonly packaged.

FIG. 56 is a cross-sectional view showing the MRAM architecture of the eighth embodiment of the present invention.

Fig. 57 is a plan view showing the MRAM architecture of the eighth embodiment of the present invention.

Fig. 58 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 59 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 60 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 61 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 62 is a perspective view showing the manufacturing process of the MRAM related to the eighth embodiment of the present invention.

Fig. 63 is a plan view for explaining a partial structure of the MRAM according to the eighth embodiment of the present invention.

64A and B are cross-sectional views for explaining a partial structure of the MRAM according to the eighth embodiment of the present invention.

FIG. 65 is a cross-sectional view showing the MRAM architecture of the eighth embodiment of the present invention.

FIG. 66 is a cross-sectional view showing the MRAM architecture of the eighth embodiment of the present invention.

FIG. 67 is a diagram showing the concept of magnetic tunnel junction.

Fig. 68 is a schematic diagram showing the state density of the transition metal.

Fig. 69 is a schematic diagram for explaining the tunneling magnetoresistance effect.

Fig. 70 is a schematic diagram for explaining the effect of tunneling magnetoresistance.

FIG. 71 is a diagram showing an example of the structure of the magnetic tunnel junction.

FIG. 72 is a diagram showing an example of the structure of the magnetic tunnel junction.

Fig. 73 is a diagram showing a substantial example of a spin valve type ferromagnetic tunnel junction element.

FIG. 74 is a diagram showing the essential characteristics of the spin valve type ferromagnetic tunnel junction device.

FIG. 75 is an oblique view showing the architecture of the previous MRAM cell array.

FIG. 76 is an oblique view showing the architecture of the previous MRAM cell array.

FIG. 77 is an equivalent circuit diagram of the structure of the previous MRAM cell array.

FIG. 78 is a diagram for explaining the working state of the previous MRAM cell array.