Correlation and demodulation circuit for a receiver for signals modulated by a specific code

Correlation and demodulation circuit of receiver modulated by specific code

Field of invention:

The invention relates to a correlation and demodulation circuit for a receiver which modulates a signal by a first code that determines the repeat length, the first code defining the source from which these signals are transmitted. The circuit includes an associated stage connected to a control device, which is used in particular to plan the associated stage in a normal operation mode or a test mode. In the normal operation mode, the associated stage is intended to receive an intermediate signal, which corresponds to a modulation signal shaped in the receiver modulation signal receiving device. The first code generated by the code generator is then copied in the correlator control loop of the correlation stage to correlate the intermediate signals.

Conventional technical description:

Signals that are specially modulated to the carrier frequency and transmitted by one or more transmission sources usually include a lot of information, which must be demodulated by correlation and demodulation circuits. The codes that encode these signals to define the transmission source are usually a false random code. The determined repeat length code is unique to each transmission source, and enables identification of which transmission source the signal received by the receiver comes from. For example, it can be a signal in the communication field or a satellite positioning signal, like It is a GPS-like signal.

In the example of a GPS receiver, the radio frequency signals transmitted by several satellites in orbit are distinguished from each other by a unique pseudo-random code, called a golden code, and modulated by a carrier frequency signal. The golden code coefficient bit code is formed by 1023 wafers and repeats every millisecond; these wafers have similar digital values of 1 or 0. All gold codes have orthogonal characteristics, which means that after correlating them with each other, the correlation result is expected. It will be close to 0. This feature allows several RF signals from several satellites to be processed simultaneously, such as independent processing in several correlation channels in the same receiver.

The GPS signal provides the position and time to the receiver to calculate X, Y, Z position, speed, and time; however, in order to determine the position and time, the receiver must obtain data from four visible satellites.

In various areas of signal receivers with specific code modulation, such as frequency setting signals, we must ensure that the receiver can specifically allow information to be removed from the received signal. The parts can work properly before or after assembly. Wait for the receiver parts to perform an operational test. Of course, before undergoing extensive inspections of their operation, such receiver parts must undergo several basic testing steps.

When using a GPS receiver, you must perform a receiver operation test close to the real situation to ensure that the channels of the associated level work properly. If the operation test is successful, for example, the position and speed of the receiver user are guaranteed , And the validity of time calculations.

By way of example, particularly in the field of communications, U.S. Patent No. 4,100,531 discloses a means of measuring the bit error rate of a digital device that uses a pseudo-random code provided by a transmitter and received by a receiver for testing. (PRN code) to test the signal. The receiver under test generates a duplicate PRN code to correlate with the signal modulated by the PRN code of the determined length in the correlation stage.

The disadvantage of this device is that the coded test signal is sent from the external transmitter to the receiver for testing, which cannot significantly reduce the test time. Furthermore, another disadvantage is that the transmission signal must be a reflection of the real communication signal to constitute the receiver operation. In the test state, this inevitably involves additional noise in the test signal, so it is often not easy to generate.

In the field of GPS receivers, US Patent No. 5,093,800 discloses a test device capable of generating GPS-type radio frequency signals. These GPS signals generated by the device are intended to be received by the GPS receiver under test. To this end, the device also contains satellite-related data, enabling the generation and transmission of signals corresponding to the coded signals transmitted to the receiver by several satellites.

The disadvantage of this test device is that in order to check that the receiver's associated stage is working properly, the test signal is a radio frequency signal, which is equivalent to the radio frequency signal transmitted by the satellite. This obviously involves additional noise generated by the radio frequency signal generated by the device. To check that the associated hierarchy is working properly. Furthermore, another disadvantage is that the operation test time of the receiver is quite long, because it depends on the repeat length of the pseudo-random code, that is, the golden code. If the receiver is installed on a device powered by a dry cell or battery, the long test time will also unnecessarily consume the battery or accumulator.

An object of the invention is to be able to provide a receiver correlation and demodulation circuit for signals adjusted by a code that reduces the test time of the circuit operation as much as possible, while overcoming the disadvantages of the prior art test devices or methods. In addition, the parameters that are linked to the noise of the received signal can be taken into consideration by affecting the operation of the circuit.

The objective of the correlation and demodulation circuit described above and other objectives are characterized in that during the test, the code generator is adapted to generate a second repeating code copy via the control device, which is shorter than the first code used for correlation operation, It has an intermediate signal modulated by a second repetitive code that is shorter than the first code and provided by the associated stage, so that the closed-loop operation of the associated stage is performed faster than the signal modulated by the first code.

An advantage of the correlation and demodulation circuit is that the closed-loop test time of the correlation stage is greatly reduced, which allows the operating status of the circuit and the receiver containing it to be quickly known.

In the GPS-type RF signal receiver example, if the pseudo-random code repetition length is equivalent to the golden code, the test time of the correlation and demodulation circuit is also relatively long. In addition, if the circuit includes several related channels in the correlation stage, the test time is also long. This is one reason why the intermediate test signal is supplied to the associated stage of the circuit and has a pseudo-random code with a reduced length for a faster check of the operation of this circuit.

Because radio frequency signals also include noise, the reduced pseudo-random code length can be defined to take this noise into account. The reduced code test signal generated without any noise mode allows to provide the output signal of the correlation level cumulative counter, whose power is close to the real output power including noise. Preferably, the pseudo-random code repeat length of these test signals is 31 chips, while the gold code is 1023 chips.

The intermediate test signal may be generated outside the correlation and demodulation circuit, or preferably in the circuit by an integrated test signal generator. These test signal generators need only a small amount of space for the correlation and demodulation circuits, because they are formed by only about forty logic gates or flip-flops, and the circuit has nearly two million transistors. These test signal generators are turned on by a control device, such as a microprocessor device.

Advantageously, the test signal generating device is turned on during a programming period within the microprocessor device. When the circuit is installed in the receiver, the test signal generating device is turned on to prevent intermediate signals from being sent to the circuit by the receiver's receiving device; therefore, during the test phase, the circuit only receives intermediate test signals originating from the test signal generating device.

These test signals are equally imposed on all channels of the associated stage for simultaneous testing of these channels. The microprocessor controls the code generator of each channel so that it generates a copy of one of the reduced pseudo-random codes for each channel during the test phase.

It should be noted that no test signal is provided from outside the receiver; instead, it is preferable to apply noise-free operation test to check the signal to the correlation and demodulation circuits rather than the conventional intermediate signal.

When this circuit is installed in a modulation signal receiver to quickly perform the test phase, a reduction in the test time of the correlation and demodulation circuits is theoretically necessary. If the receiver is installed in a portable object, such as a watch or phone, the reduction in test time can prevent excessive energy from being consumed in the accumulator or storage battery. However, the correlation and demodulation circuit can also be installed in the receiver and tested with a noise-free test signal supplied to the correlation stage, which corresponds to the conventional intermediate signal.

Users can also perform a complete test of the receiver's correlation and demodulation circuits at any time they want.

The purpose, advantages, and characteristics of the correlation and demodulation circuit will become clearer in the following description of the specific embodiment of the circuit in the figure:

Brief description of the schema:

Fig. 1 schematically shows a radio frequency signal receiver with a correlation and demodulation circuit according to the invention; Fig. 2 schematically shows the electronic components of a test signal generator of a circuit according to the invention; Fig. 3a shows a test signal generating device according to the invention One reduced PRN code generator; Figure 3b shows a PRN code generator that can be planned in normal operating mode and test mode for each channel of the associated stage of the circuit according to the invention; And FIG. 4 schematically shows the elements of a correlator according to the correlation stage of the present invention.

Element main play symbol description:

1 GPS receiver 2 Antenna 3 Receiving device 4 'First electronic circuit 4 "Second electronic circuit 5 Clock signal generator 6 Correlation and demodulation circuit 7 Correlation stage 7' Channel 10 Data transfer bus 11 Buffer register 11 ' Buffer register 12 Microprocessor device 13 Data bus 14 Test signal generator 15 Test signal generator 16 Multiplexer 17 Test selector 18 Storage device 19 Control bus 20 Carrier mixer 21 Code mixer 22 Accumulation counter 23 Code Discriminator 24 Code Numeric Control Oscillator 25 Pseudo Random Code Generator 26 Carrier Discriminator 27 Carrier Numeric Control Oscillator 28 Sine / Cosine Table 30 Flip-Flop 32-34 XOR Adder 40 Flip-Flop 41-45 XOR Adder 46-48 Multiplexer 151 Numerically controlled oscillator 152 Small PRN code generator 153 Numerically controlled oscillator 154 Message generator 155 Signal mixer 156 Signal mixer

Description of the preferred embodiment:

In the following description, specific embodiments of the correlation and demodulation circuit will be explained by a GPS-type radio frequency signal receiver; it should be known that the components of several receivers in this technical field known to those skilled in the art will not be described in detail. .

In such GPS receivers, the received radio frequency signals are modulated by a pseudo-random code called a Gold code, and they also include information demodulated by a correlation and demodulation circuit. The messages from at least four satellites therefore allow the microprocessor device of the circuit to specifically calculate the X, Y and Z positions, the speed and / or time of the receiver. However, the use of this correlation and demodulation circuit may also be applied to other types of receivers for signals modulated by a determined repeat length code. For example, the correlation and demodulation strategy may be used in a communication receiver, or in a measurement receiver using an optical signal carrying a determined code, or in other fields.

Figure 1 schematically shows a GPS-type receiver with a correlation and demodulation circuit. The antenna 2 is used to receive GPS radio frequency signals originating from several satellites, the device 3 is used to receive and shape the radio frequency signals supplied by the antenna 2, and the correlation and demodulation circuit 6 receives signals from the receiving device 3 with a frequency level of 400 thousandHertz's plural form intermediate signal IF.

In the receiving device 3, the first electronic circuit 4 first converts a radio frequency signal, for example, from 1,57542 GHz to a frequency of 179 MHz. The second electronic circuit IF4 "implements double conversion to adjust the GPS signal to a frequency of 4.76 MHz first, and then to a frequency of 400 GHz by sampling at 4.36 MHz. At the level, the intermediate complex signal is sampled and quantified at a frequency of 400 GHz. IF is therefore supplied to the correlation and demodulation circuits. The intermediate complex signal IF therefore has an in-phase signal I and a quarter-phase signal Q, which is shown in the figure by a bold line that defines the two bits intersected by oblique lines. However, if 2-bit conversion is performed in the previous stage, these intermediate signals IF can be defined in 4 or 2n bits (n is an integer greater than 1).

For frequency conversion operation, the clock signal generator 5 is part of the RF receiving and shaping device 3. For example, this generator is provided with a quartz oscillator not shown, calibrated to a frequency of 17.6 MHz. The two clock signals CLK and CLK16 are supplied to the correlation and demodulation circuits to supply clocks to the operation of all circuits. The first clock frequency CLK can be 4.36 MHz, and the second clock frequency can be fixed at 16 times, which is 272.5 MHz, for most of the associated stages to save energy.

It should be noted that the signal supplied by the first circuit 4 is provided. For half of the examples, there are 2 output bits (+1 and -1) and 4 output bits (+3; +1; -1; 3). Signals of different parity; therefore, the parity of the GPS signal demodulation operation in the receiver must be considered.

The correlation and demodulation circuit 6 includes an association stage 7 having 12 channels 7 '; a data transfer bus 10 connecting each channel to a separate buffer register 11; and a data bus 13 to temporarily store each bufferDevice is connected to the microprocessor device 12. The storage device 18 connected to the microprocessor is part of the microprocessor device 12, for example, to store data related to each satellite in orbit, as well as the carrier frequency and pseudo-random code parameters of each satellite. All related and demodulation circuit components can be fabricated on a single semiconductor substrate, such as a silicon substrate.

A test signal generating device 14 including a test signal generator 15 and a multiplexer 16 is placed at the input of the correlation and demodulation circuit 6. Intermediate signal IF and receives the intermediate test signal IF at the other input_r_e_s_t. The multiplexer 16 is controlled by the control signal Test supplied by the control device by controlling the bus 19 and the buffer register 11. The control device is integrated into the microprocessor device 12; if necessary, the multiplexer 16 is also It can be integrated in the test signal generator 15.

In the normal operating mode without the control signal Test, the intermediate signal IF representing the radio frequency signals transmitted by several satellites is transmitted by the multiplexer 16 to the correlation stage 7 to all channels 7 '. Some channels are planned differently by the microprocessor 12 in the normal operating mode, so that they each search for visible satellites by using the intermediate signal IF for demodulating the received GPS messages. In contrast, when the microprocessor 12 orders a test period, the microprocessor 12 sends a test control signal to the test signal generating device 14 in particular via the control bus 19. During this test, the test signal generator 15 is therefore turned on, and the multiplexer 16 receiving the test signal Test transmits only the intermediate test signal IF generated by the generator 15_t_e_s_tGo to correlation stage 7; the test signal generator will be explained in more detail with reference to FIG. 2.

Once switched on, the test signal generator 15 generates an intermediate test signal IF_t_e_s_tInstead of performing the conventional intermediate signal, a test representing the correlation stage in the closed loop is performed. These test signals IF_t_e_s_tIt is modulated with a pseudo-random code with a shorter repetition length than the golden code, in order to perform a closed-loop test quickly. Preferably, the reduced pseudo-random code repeat length is 31 chips, which is 2⁵-1, but the gold code has a repeat length of 1023 wafers, which is 2^l⁰_-1。

Of the 1023 wafers, close to 1,000 wafers, in terms of proportion, they can be considered equivalent to the noise of radio frequency signals. As a result, the reduced code of the 31 chip is selected to provide a noise-free intermediate test signal for the test representing the correlation stage.

Of course, for other fields using correlation and demodulation circuits, the reduced second pseudo-random code repetition length may be 2 (ⁿ^-^m) -1, but the repeat length of the first pseudo-random code of the received signal is 2ⁿ-1. The numbers n and m are integers, and n is greater than 3 and m is a determined value between 1 and n-1.

During the test, the microprocessor 12 sends a test control signal TMS to each of the test selectors 17 disposed on the respective channel 7. Each channel 7 'includes received signal IF or IF_t_e_s_tThe correlator 8 and preferably includes a controller 9 which is set to enter operation through specific data, in particular a signal processing rule for obtaining satellites and tracking satellites detected by the channel. The test selectors 17 are each connected to a respective correlator 8 and have the task of supplying instructions CS to the correlator, in particular the planning of a pseudo-random code generator, which will be explained in more detail with reference to FIG. 3b.

In normal operation, no instruction CS is transmitted to the correlator 8 by the selector 17, which means that the code generator correlator 8 wants to generate a code copy, which has a repeat length equal to the gold code. However, during the test, when encountering the instruction of the microprocessor 12, the selector 17 will send out the instruction CS for planning the configuration code generator so that it will generate a pseudo-random code copy with a shorter repetition length than the gold code. The reduced pseudo-random code must therefore be a pseudo-random code modulated on the intermediate test signal during the test period.

The control signal TMS is theoretically defined as a two-bit control word for normal operation or various test modes. If the TMS is equal to 00 in binary, no test command CS is transmitted for normal operation. If the TMS is equal to 11 in binary, then a closed loop test mode is applied to check that all channels 7 'are working properly with the intermediate test signal as input. If the TMS in binary is equal to 01, the test of the correlator module 8 of each channel can be performed through a test vector generator not shown, which is controlled by the microprocessor 12. If the TMS in binary is equal to 10, the test of the controller module 9 of each channel can be performed through the test vector generator. In the present invention, the signal TMS is preferably a value of 00 or 11.

In other possible specific embodiments not shown, all the selectors 17 may be part of the microprocessor device 12. Moreover, the command CS of each correlator 8 can be transmitted via the buses 10 and 13.

While the selector 17 sends the command CS, the microprocessor 12 transmits the parameters related to the pseudo-random code to be searched and the carrier frequency of the intermediate test signal via the bus bars 13 and 10. These parameters are transmitted to plan all channels 7 'during the test, as they also occur in normal operation, but individually on each channel. However, during the test, those parameters are the same for all channels, so the intermediate test signal IF with a reduced unique pseudorandom code_t_e_s_tAttach all channels simultaneously and in the same way.

As previously shown in normal operation, the register 11 in each channel is capable of receiving configuration data or parameters from the microprocessor 12 and the storage device 18, which are associated with each associated channel 7 '. After being associated and locked to a specific satellite, it can be transmitted to the micro processor via the register 11, the information about the GPS message, the state of the PRN code, the frequency increase with the Doppler-effect, false range and other dataDevice 12. 12.

During the test, the register 11 receives the results of the closed-loop test and messages processed by the microprocessor. After the test, the microprocessor can therefore check whether all associated channels operate correctly, independently and externally, before the correlation and demodulation circuits are embedded in normal operation.

It should also be noted that these registers 11 can accumulate data during the association period, which will be used during satellite acquisition and tracking periods, and need not be automatically transferred to the microprocessor 12.

In other possible specific embodiments, it is conceivable that all the channels 7 of the associated stages have a single block register 11, and a given piece of data placed in the register block is the same for each channel.

Given each channel 7, including the controller 9, for all satellite acquisition and tracking periods, the microprocessor 12 can be reduced. For example, the microprocessor 12 may be an 8-bit CoolRISC-816 microprocessor from EM Microelectronic-Marin SA of Switzerland. However, larger microprocessors can be used to avoid placing the controller 9 in each channel, for example, a 32-bit microprocessor. In this case, the larger microprocessor will be responsible for all satellite acquisition and tracking procedures during normal operation and testing in accordance with the present invention.

FIG. 2 schematically shows different units of the test signal generator 15. This test signal generator is turned on according to a microprocessor instruction, as previously described. Once turned on, it generates an intermediate test signal IF_t_e_s_tIn the closed loop, the correlation level to be tested is introduced. Noise-free intermediate test signal IF_t_e_s_tIntermediate signals must be designed in the same way as shaped RF signals in the receiver. However, the intermediate test signal or the replacement signal must be modulated together with a pseudo-random code of a shorter length than the golden code to reduce the correlation level test time.

The test signal generator 15 includes an 8-bit numerically controlled oscillator (NCO) 151 for use in a code determined by the clock signal CLK, a small PRN code generator 152, a message generator 154, and an 8-bit numerically controlled oscillator (NCO) 153 for a carrier frequency that is timed by a clock signal, and two signal mixers 155 and 156. Two 8-bit oscillators 151 and 153 have a frequency resolution of 17 kHz, which is divided by 4.36MHz by 2⁸The clock frequency is defined by CLK.

During the test, two 8-bit numerically controlled oscillators (NCOs) 151 and 153 each received 8-bit binary words from the microprocessor. The first oscillator 151 receives a code for generating the clock signals PRN-CLKs to increase the timing of subsequent small PRN code generators 152. The second oscillator 153 receives a carrier frequency increment for generating a carrier frequency signal. One of the second oscillator 153 is a same-belt signal, and the other is a quarter-phase signal. The carrier frequency value is not important for closed loop testing. Therefore, this carrier frequency can be 400 Hz or lower like a traditional intermediate signal.

The small PRN code generator 152, shown in more detail in FIG. 3a, receives the clock signal PRN-CLKs from the oscillator 151 to generate a pseudo-random code with a reduced repeat length. The code repeat length is preferably 31. Which is 2⁵-1, explained below.

The frequency of the clock signals PRN-CLKs is a function of the code increment indexed by the input terminal of the numerically controlled oscillator 151. If the code increment is fixed at 24, it is a binary number of 11,000, and the clock frequency PRN-CLKs is equal to 24 times of 17 GHz, which is 408 GHz. The code increment can of course be fixed to a higher value, making it close to the 1.023MHz frequency of the associated level code generator in normal operation. However, the PRN-CLKs frequency of 408 MHz has been selected to allow for true processing of the associated stages during normal operation during the test.

As explained with reference to FIG. 4, the output signal of the correlation stage must be equal to the traditional intermediate signal, including the more useful signal of about 16 dB, or the noise-free intermediate test signal supplied at the input of the correlation stage; It is to consider the inherent noise of the RF signal to use the noise-free test signal to perform a fast test of the correlation level close to the real environment.

In order to provide an intermediate test signal similar to the traditional intermediate signal, the message must be placed on the carrier signal at a frequency of 50 Hz; this allows the microprocessor to check at the end of the test that each channel has processed the correct demodulated message. To this end, the message generator 154 sets the timing with an epoch signal (1 ms) to provide a 50 Hz message (modulates the 20-period signal).

The information from the message generator 154 and the reduced PRN code from the small PRN generator 152 are mixed in the mixer 155; the output of the mixer 155 is also mixed or modulated on the loop carrier in the mixer 156 to generate an intermediate test. Signal IF_t_e_s_t。

Figure 3a shows the small pseudo-random code generator 152 in more detail. The structure of the generator is well known to those skilled in the art. Because it must generate a code length of 31, it is used in the encoder G.₁_SAnd decoder G₂_SIt includes a series of five flip-flops 30, which are defined by the number FF and the number of each flip-flop. The state transition of each flip-flop 30 is generated at each clock edge of PRN-CLKS from flip-flop FF1 to flip-flop FF5.

In the first encoder G₁_sIn the flip-flop 30, FF3 and FF5 each have an output that is added by the XOR adder 34, and the output of the adder 34 is introduced into the flip-flop FF1 so that the output of the flip-flop FF5 is at each clock edge of PRN-CLKS Generate a first coded signal G₁_s。

In the second decoder G₂_sIn the flip-flop 30, each of FF2 to FF5 has an output added to the XOR adder 32, and the output of the adder 32 is led to the flip-flop FF1, so that the output of the flip-flop FF5 is at every clock of PRN-CLKS Edge generates second encoded signal G₂_s。

First and second coded signals G₁_s, G₂_sThe XOR adder 33 is added to generate the coded signal G._s, Which corresponds to the output signal from the small PRN code generator 152.

Figure 3b shows a traditional pseudo-random code generator 25 used in each correlator of the correlation stage. The structure of this generator is well known to those skilled in the art, and it is used to generate the golden code in normal operation. copy. However, the code generator 25 also includes multiplexers 46 to 48 so that the generator can also be planned during the test period. During the test, the code generator 25 must be planned to generate a pseudo-random code copy, which is generated by the test signal generator, that is, the code has 31 (that is, 2⁵-1) repeat length.

The pseudo-random code generator 25 includes a first encoder G₁, Where the ten flip-flops 40 defined by the label FF and the numbers of the flip-flops are arranged in series; and a time offset selector G for defining a specific satellite code₂(TAP selector). In normal operation, the encoder G₁The flip-flops FF3 and FF10 each have an output which is added in the XOR adder 41. If no instruction CS is applied to the multiplexer 46, the output signal from the flip-flop FF10 passes freely through the multiplexer 46 (shown in dotted line in the figure); the output of the adder 41 is introduced into the input of FF1 in the flip-flop 40 to At each clock of PRN-CLK, a first coded signal G is generated at the output of the last flip-flop FF10.₁; In normal operation, the pulse signal PRN-CLK is about 1.023 MHz, and about 408 MHz in the test period, which is a function of the intermediate test signal.

During the test, the instruction CS is applied to the multiplexer 46, so only the outputs of FF3 and FF5 in the flip-flop 40 are added in the adder 41, which is explained with reference to FIG. 3a. This plan corresponds to the encoder G₁_sTo produce an output signal G₁_s。

In decoder G₂In the flip-flops FF2, FF3, FF6, FF8, FF9 and FF10, each has an output which is added by the XOR adder 42. The output of the adder 42 is led to the input of the first flip-flop FF1 in the flip-flop 40 by the multiplexer 4. In normal operation, if no command CS is applied to the multiplexer 47, the output of the multiplexer 42 passes freely (shown by a dotted line in the figure) through the multiplexer 47. Second coded signal G₂Therefore, at each clock of PRN-CLK₂Is generated at the output of the last flip-flop FF10.

The outputs of the flip-flops FF2 to FF5 are introduced into the XOR adder 45, and the output thereof is led to the input of the multiplexer 47. During the test, the instruction CS is applied to the multiplexer 47, so that the output of the adder 45 is directed to the input of the first flip-flop FF1 instead of the output of the adder 42; this plan corresponds to the encoder G₂_s, Explained with reference to FIG. 3a to generate an output signal G₂_s。

In particular, the selector G₂Includes XOR adder 43, which adds signals from two flip-flops, selected from ten flip-flops 40, for example, the second encoder G₂The flip-flops FF3 and FF7 to generate a specific code for one of the predetermined satellites. As known to those skilled in the art, by the selector G₂The addition of the adder 43 also generates a specific delay.

If no instruction CS is applied to the multiplexer 48, the output of this adder 43 passes through the multiplexer 48 freely (shown by the dotted line in the figure). Therefore, in normal operation, the selector G₂The output can be compared with the output G₁They are added together to the XOR adder 44 to generate an output signal G. In this case, the output G defines a copy of the golden code of a determining satellite.

During the test, the instruction CS is applied to the multiplexer 48 so that only the output G₁, G₂Add in the adder 44 to generate a signal G corresponding to the explanation of FIG. 3_sOne signal.

Figure 4 shows the different electronic components of the correlator of the correlation stage, which are well known to those skilled in the art. For more details on the various components of this correlator, the reader can refer to Chapter 5 of "Learning GPS Principles and Applications" by Philip Ward and editor Elliott D. Kaplan (ArtechHouse Publisher, USA 1996 ), ISBN version number 0-89006-793-7, especially Figures 5.8 and 5.13, which roughly show the elements of Figure 4. It should be noted in this figure that the bold lines shown with slashes define a specific number of parallel bits.

During testing, correlators of all associated stage channels are planned for testing in the same way, which represent the operation of the correlation and demodulation circuits. In the following description, for simplicity, only one of the correlators is described.

The correlator includes a carrier mixer 20, a code mixer 21, an accumulation counter 22, a code discriminator 23, a carrier discriminator 26, a numerically controlled oscillator of the code 24 and a carrier 27, a pseudo random code generator 25, and a sine / Cosine table 28.

First, the carrier mixer 20 receives an intermediate signal IF at an input during normal operation, and is shown by a dotted line, or receives an intermediate test signal IF during a test period._t_e_s_t. These intermediate signals are complex signals, that is, they have an in-phase signal I and a quarter-phase signal Q according to the formula (I + iQ). As explained above, the selection of the signals arriving at the mixer 20 is applied by the microprocessor device; these intermediate signals are processed in the PRN code control loop and the carrier control loop.

In the mixer 20, on the one hand the intermediate signal IF_t_e_s_tMultiply by the cosine minus i by the internally generated carrier copy sine to extract the in-phase signal I from the intermediate complex signal; on the other hand, multiply by the negative sine minus i by the internally generated carrier copy to cosine from the middle The complex signal takes a quarter-phase signal Q.

After this carrier correlation operation, the signals I and Q are input to the code mixer 21 to find the PRN code equivalent to the internal generator. On the one hand, the in-phase signal I and the quarter-phase signal Q are each multiplied by the early replica E (early replica) of the PRN code, and on the other hand multiplied by the late replica L (late replica) of the PR N code. To give four output signals I_E, I_L, Q_EAnd Q_L. In each associated level channel, only those early and late copies separated by half-chips are kept, regardless of the exact copy in the middle.

Four correlated signals I_E, I_L, Q_EAnd Q_LThe input counter 22 is a pre-detection element. Four output values I of the counter 22_E_s, I_L_s, Q_E_sAnd Q_L_s, Which is represented by 10 bits, corresponding to one full cycle of the golden code. However, only the eight most significant bits are used in the code and carrier control loop.

In normal operation, after every millisecond or every new period, obtain a complete set of output values I_E_S, I_L_S, Q_E_SAnd Q_L_SBecause the code repetition length is 1023 chips with a code clock frequency of 1.023MHz. In contrast, during the test, the code repetition length was reduced to 31 chips and the code clock frequency of 408 MHz, and a complete set of output values was obtained after approximately every 76 μs. This value of 76 μs corresponds to 31 divided by 408 MHz.

In order to provide a complete output during normal operation or testing, the accumulation counter 22 continues to calculate after the start or end of each code sequence; therefore, it can estimate the time gain used to obtain the output value corresponding to the accumulation time ratio, That is (1ms / 76μs), multiplied by the code repeat length ratio, which is 1023/31. The time gain of the closed-loop test of the correlation and demodulation circuit is about 435 times smaller than the test time to be achieved if the pseudorandom code has a repeat length of 1023. If the code clock frequency is fixed at 1023MHz during the test, this gain can even reach 1000 times, because the accumulation time will change from approximately 76μs to 31μs.

By being I_P_SValue will be I_E_SAnd I_L_SAdd two signals, and Q_P_SValue will be Q_E_SAnd Q_L_STwo signals are added to obtain two other output values I corresponding to the virtual exact value_P_S, Q_P_S。

In the PRN code control loop, four outputs are used as signal I_E_S, I_L_S, Q_E_SAnd Q_L_SThen it is introduced into the code discriminator 23, which performs the energy calculation operation of the output signal. The value accumulation during a certain number of integration cycles, for example 16 cycles, is performed in the code discriminator 23; the discriminator 23, which also includes a filter, supplies the filtered code phase loop increment to the code Numerically Controlled Oscillator (NCO) 24; this phase loop increment allows the phase to be adjusted to produce a code copy; for example, the oscillator 24 thus receives a filtered 28-bit binary word from the discriminator 23.

At the beginning of the search procedure, the code phase increment INCR-C is provided via the microprocessor, parameter input and output registers to fix the starting value of the code clock frequency that the oscillator 24 must provide. Of course, if the circuit is in normal operating mode or during testing, the value of this incremental INCR-C is different.

The clock frequency is supplied to the PRN-CLK system to the PRN code generator 25 to provide timing for the generation of the early and late copy of the pseudo-random code. If the instruction CS is applied to the code generator 25, this means that the generator is planned to generate a code copy with a repeat length of 31 during the test. Similarly, during the test, the incremental INCR-C supplied to the numerically controlled oscillator 24 can make the clock frequency PRN-CLK of the output of the oscillator preferably 408 kHz.

In the carrier control loop, the virtual precision output signals IPS and QPS are input to the carrier discriminator 26. Numeric accumulation is performed at the carrier discriminator 26 during a certain number of accumulation periods, such as 16 periods. The discriminator 26, which also includes a filter, supplies the filtered carrier loop increment to the carrier numerically controlled oscillator (NCO) 27. This carrier loop increment allows the frequency to be adjusted to generate a carrier copy; for example, this oscillator 27 therefore A filtered 24-bit binary word from the discriminator 26 is received.

As for the code control loop at the beginning of the search procedure, a frequency increment INCR-P is inputted via the microprocessor. The frequency increment INCR-P allows the carrier frequency generated by the oscillator 27 to be initially fixed to a comparable value of one of the carrier frequencies of the intermediate signal. Of course, the value of this incremental INCR-P is different during normal operating mode or test of the circuit.

The output signal from the numerically controlled oscillator 27 is supplied to the sine / cosine table 28, which produces two complex signals to the mixer 20, and the complex signals (Cosx-iSinx) and (-Sinx-iCosx) are mixed in the mixer 20 Multiply the intermediate complex signal to provide an in-phase signal I and a quarter-phase signal Q.

As described above, the fact that the repeat length of the 31 chip is selected for the pseudo random code modulated on the intermediate test signal allows the inherent noise in the radio frequency to have the code repeat length of the 1023 chip for consideration during the circuit test .

The traditional intermediate signal IF supplied to the correlation stage includes noise that is approximately 16 decibels larger than the useful signal. Therefore, the noise-to-noise ratio (SNR) of the real signal on the output signal provided by the accumulation counter 22 must be considered to have a value comparable to the intermediate test signal without noise. Normally, when the code copy is in phase with the intermediate test signal code, the output signal has an SNR between 15 and 20 dB.

If the correlation-level test is performed with a noise-free RF signal generated outside the receiver, there will be a risk of saturation with respect to the accumulation counter 22. This is why it is necessary to add noise to these signals in order to use the RF test signals to obtain a test representative of the operation of the correlation stage. In contrast, with the intermediate test signal of the present invention, since the output value accumulation in the accumulation counter is not saturated, it is not necessary to add noise.

The power of the accumulator output signal according to the RF signal received by the receiver is obtained by the following formula: P_s= (C / N₀Tσ²Where (C / N₀) T, where T is lms, represents the signal-to-noise ratio (SNR), and σ²Represents the performance average noise power. Therefore, the intermediate test signal produces a cumulative counter output signal with comparable output power, which can be compared with the output power of a real radio frequency signal including noise. This allows close-to-true closed-loop operation tests to be performed at the correlation level with pseudorandom codes reduced to 31.

At the end of the test period, those intermediate signal messages are demodulated in each output channel of the accumulation counter 22 to supply data to the microprocessor. As a function of receiving test results and data, the microprocessor can check whether each associated channel works properly. As a result of the reduction of the pseudo-random code repetition length, when the closed-loop test system is guaranteed to be comparable to the actual operation test, the test time is greatly reduced. Therefore, more than 90% of the components can be tested in a closed-loop test mode.

This closed loop test operation can be repeated during the decision period, as explained earlier, as a function of the programmed microprocessor device. Of course, this stylization is useful when a receiver with correlation and demodulation circuits is installed in a portable power source provided by a dry cell or battery, where the receiver includes a test signal generator. Of course, this portable may be, for example, a watch or a portable phone, which needs to save power consumption, even during testing.

In any case, it is entirely possible to assume that testing is performed before the correlation and demodulation circuits are set up in the receiver. In such cases, closed-loop testing of the circuit's associated stages may be performed on a test stand or even at the end of the manufacturing line of the circuit on the wafer.

Of course, other specific embodiments of the correlation and demodulation circuit may also be conceived by those skilled in the art, without departing from the scope defined by the scope of patent application of the present invention. The present invention can be planned in normal operation mode and test mode, and can be used in any receiver of the signal modulated by the determination code repetition length. The intermediate test signal may be supplied by a test signal generator, for example, a generator located on a test stand rather than integrated in the circuit. However, since the test signal generator only includes about forty logic gates or flip-flops, and the circuit is already close to two million transistors, the circuit of the present invention only takes up a negligible space.