TW525112B

Liquid crystal display device for displaying the displayed data

Abstract

The present invention relates to a liquid crystal display device for displaying display data, and particularly includes a liquid crystal panel including pixel portions arranged in a matrix, and a step voltage corresponding to the display data is added to the pixel portion. A plurality of data drivers, a box driver that selects the pixel unit to which the aforementioned tone voltage is added, and a liquid crystal control circuit that controls the data driver according to a transmission clock; the data driver, the display data input to the data driver, and the data driver The difference between the load of the transmission clock and the load of the display data output from the data driver and the load of the transmission clock is reduced, and a reproduction circuit for regenerating the transmission clock input to the data driver and generating a latching clock is provided. The lock clock locks a lock circuit that inputs the display data to the data driver.

Term

No projected expiry on record.

9 claims: 8 independent, 1 dependent

1
525112 A 8 B8 C8 D8 六、申請專利範圍 -WX7 第90107775號專利申請案中文申請專利範圍修正本民國91年’ 7月15日修正 (請先閲讀背面之注意事項再填寫本頁) l · 一種供顯示資料顯示用的液晶顯示裝置，其特徵爲：具有：含有呈矩陣狀配置的畫素部之液晶板、及將相對應於前述顯示資料之階調電壓外加於前述畫素部之複數的資料驅動器、及選擇外加前述階調電壓的前述畫素部之匣極驅動器及依據傳送時鐘控制前述資料驅動器之液晶控制電路經濟部智慧財產局員工消費合作社印製前述資料驅動器，爲了使朝前述資料驅動器輸入之前述顯示資料和前述傳送時鐘的負荷、及從前述資料驅動器輸出之前述顯示資料和前述傳送時鐘的負荷之偏差變小，而具有：再生朝前述資料驅動器輸入之前述傳送時鐘且生成閉鎖時鐘之再生電路、及依據前述閉鎖時鐘閉鎖朝前述資料驅動器輸入前述顯示資料之閉鎖電路。 2 ·如申請專利範圍第1項之液晶顯示裝置，其中前述複數的資料驅動器，相互地連接在墊圈。 3 .如申請專利範圍第1項之液晶顯示裝置，其中前述再生電路，具有：比較朝前述賓料驅動器輸入之前述傳送時鐘、及在前述再生電路再生之前述傳送時鐘之比較電路。本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）： Α8 Β8 C8 D8 『25112 六、申請專利範圍 4 ·如申請專利範圍第3項之液晶顯示裝置，其中以前述再生電路再生之.前述傳送時鐘，對於朝前述資料·驅動器輸入之前述傳送時鐘的上升要快t期間上升，且對於朝前述資料驅動器輸入之前述傳送時鐘的下降要慢t期間下降。 5 ·如申請專利範圍第3項之液晶顯示裝置，其中前述再生電路，將與前述顯示資料同步之傳送時鐘的周期當作T 0，且將低水準期間及高水準期間的差當作Τ X的情況時，使快T r期間上升且慢T X - T r期間下降之信號重新生成（但，Τ X gt; 〇的情況時，Τ X gt; T r gt; 〇， Τ X lt; 〇的情況時，〇 gt; T r gt; Τ X )。 6 ·如申請專利範圍第1項之液晶顯示裝置，其中從朝前述:資料驅動器輸入之前述顯示資料和前述傳送時鐘的負荷，係爲：5 0 %。 7 · —種供顯示資料顯示用的液晶顯示裝置，其特徵爲：具有：含有呈矩陣狀配置的畫素部之液晶板、及將相對應於前述顯示資料之階調電壓外加於前述畫素部且相互地連接在墊圏之複數的資料驅動器、及選擇外加前述階調電壓的前述晝素部之匣極驅動器 Λ 及依據傳送時鐘控制前述資料驅動器之液晶控制電路前述資料驅動器，爲了使朝前述資料驅動器輸入之前本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -2 - (請先閲讀背面之注意事項再填寫本頁) 訂經濟部智慧財產局員工消費合作社印製 μ5112 Α8 Β8 C8 D8 六、申請專利範圍述顯示資料的設定/保持時間的界限增加’而具有閉鎖前述顯示資料之閉鎖電路。 8 ·如申請專利範圍第7項之液晶顯示裝置’其中前述資料驅動器，具有將以前述變換電路變換之釗述傳送時鐘2倍增之2倍增電路，而依據被2倍增之前述傳送時鐘進行前述顯示資料的讀取。. 9 .如申請專利範圍第8項之液晶顯示裝置’其中前述資料驅動器，爲了使朝前述資料驅動器輸入之前述顯示資料的設定/保持時間的界限增加，而依據前述傳送時鐘生成閉鎖時鐘，且朝前述閉鎖電路輸出。 (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -3 - 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）

174 paragraphs, as filed

Liquid crystal display device for displaying data

101. . .Data drive102. . .Input transmit clock103. . .Enter display information104. . .Input start signal105. . .Input LCD external signal106. . .Input LCD reference voltage107. . .Clock regeneration circuit108. . .Regenerative transmission clock109. . .Lock clock110. . .Starting control circuit111. . .Block address start signal112. . .Output start signal114. . .Blocking circuit115. . .Show data116. . .Output buffering117. . .Output transfer clock118. . .Output buffering119. . .Output display data120. . .Block address generation circuit121. . .Blocking address122. . .Blocking circuit125. . .Show data500. . .LCD display board502. . .LCD controller503. . .Data drive504. . .Cartridge drive505. . .Data Drive Signal Group601. . .Input buffer602. . .Input transmit clock603. . .Inversion circuit604. . .Inversion circuit607. . .End comparison circuit608. . .End comparison circuit609-up. . .Phase advance signal609-dwn. . .Phase delay signal610-up. . .Phase advance signal610-dwn. . .Phase delay signal611. . .Terminal discrimination circuit612-up. . .Phase advance signal612-dwn. . .Phase delay signal613. . .Supply pump circuit614. . .Offset voltage615. . .Loop filter616. . .Offset voltage617. . .VCO circuit619. . .Compare signals620. . .Compare clock901. . .NOR circuit902. . .Reverse signal1001. . .Inversion circuit1401. . .First delay circuit1402. . .Delayed transmission clock1403. . .Load regeneration circuit1404. . .Regenerative transmission clock1405. . .Second delay circuit1406. . .Exclusive theory and circuits1501. . .Delay circuit1502. . .Delay control signal1503. . .Delayed transmission clock1504. . .Inversion circuit1505. . .Reverse signal1506. . .End comparison circuit1507-up. . .Phase advance signal1507-dwn. . .Phase delay signal1508. . .Delay circuit1509. . .Delayed signal1511. . .Timing signal1512. . .decoder1601. . .Delay circuit1602. . .Delayed signal1603. . .Switch circuit1701. . .Delay circuit1901. . .Delay circuit1902. . .Delay control signal1903. . .Delete signal (reset signal)1904. . .Delayed transmission clock1905. . .End comparison circuit1906-up. . .Phase advance signal1906-dwn. . .Phase delay signal1907. . .Delay circuit1908. . .Delayed signal1910. . .Countdown / Countdown Timer1911. . .Timing signal1912. . .decoder1913. . .Blocking circuit

Fig. 1 is a structural diagram of a data driving device according to a first embodiment of the present invention.

Fig. 2 is a structural diagram showing a liquid crystal display device according to a first embodiment of the present invention.

Fig. 3 is a block diagram showing a clock regeneration circuit according to the first embodiment of the present invention.

Fig. 4 is a block diagram showing a phase comparison circuit according to the first embodiment of the invention.

Fig. 5 is a diagram showing the operation of the phase comparison circuit according to the first embodiment of the present invention.

Fig. 6 is a block diagram showing a terminal discrimination circuit according to the first embodiment of the present invention.

Fig. 7 is a structural diagram showing a VCO according to the first embodiment of the present invention

Fig. 8 is a graph showing the relationship between the offset voltage and the oscillation frequency of the VCO in the first embodiment of the present invention.

Fig. 9 is a timing chart showing a clock regeneration circuit according to the first embodiment of the present invention.

Fig. 10 is a timing chart showing the data driver of the first embodiment of the present invention.

Fig. 11 is a block diagram showing a clock regeneration circuit according to a second embodiment of the present invention.

Fig. 12 is a configuration diagram showing a first delay circuit according to a second embodiment of the present invention.

Fig. 13 is a configuration diagram showing a delay circuit according to a second embodiment of the present invention.

Fig. 14 is a block diagram showing a terminal comparison circuit according to a second embodiment of the present invention.

Fig. 15 is a timing chart showing a first delay circuit of the second embodiment of the present invention.

Fig. 16 is a block diagram showing a load regeneration circuit according to a second embodiment of the present invention.

Fig. 17 is a timing chart showing a load regeneration circuit according to a second embodiment of the present invention.

[Industrial use area]

The present invention relates to a liquid crystal display device for displaying data, and more particularly to a liquid crystal display device containing a plurality of data drivers.

[Previous Technology]

Known technology is disclosed in Japanese Patent Application Laid-Open No. 11-194748: a plurality of data drivers are connected in series by a transmission line, and display data and data transmission frequencies are transmitted. Each data driver is transmitted on the input side and the output side. There are buffer circuits between the lines.

However, in the conventional technique described above, the change of the load ratio of the transmission waveform generated when the phase transmission is performed is not considered. For example, when the buffer circuit is slower than the rising response of the transmission waveform, each time the transmission signal passes through the buffer circuit, the delay of the rise of the transmission signal is degraded due to the reduction of the waveform amplitude.

It is assumed that each time the buffer circuit on the output side driven by the data is used, even if the theoretical level of the transmission signal (transmission of display data and frequency of data transmission) is reversed, the load difference that once occurred will not be resolved. For example: when the load of the first data drive is 50% and the load of the third data drive is 45%, the fifth data drive can be expected to become 40%, and at least it cannot be expected to return to 50% again.

In addition, for the two ends of the data driver for reading the display data with the rising / falling of the transmission clock, the setting / holding time limit of the end of the transmitting clock is different between the rising end and the falling end. In other words, since the maximum frequency of the transmission clock and display data is equal at the two-end drive, the line width of the input and output buffers or transmission line is equal to the transmission clock and display data. Therefore, the slave output buffer of the data driver described above In addition, the difference between the transmission clock and display data of the input buffer, the delay time at the time of rising and the delay time at the time of falling can be reduced. On the one hand, the delay time is different because it rises and falls: Although the set time limit is sufficient on the rising end of the transmission clock, the hold time limit is reduced, on the contrary ， Although the hold time is sufficient at the falling end of the transmission clock, the set time limit is reduced. The limits of the setting / holding time are required for both ends. As a result, the limits of the setting / holding time are reduced together.

[Abstract of the invention]

Therefore, an object of the present invention is to provide a liquid crystal display device capable of suppressing changes in a transmission clock and display data.

And, the object of the present invention ， The purpose is to provide a liquid crystal display device that increases the setting / holding limit of display data.

According to the present invention, in order to reduce the difference between the load of the display data and the transmission clock input to the data driver and the load of the display data and the transmission clock output from the data driver, the transmission clock input to the data driver is regenerated and a latched clock is generated. And the latching circuit that inputs the display data to the data driver is latched according to the aforementioned latching clock.

In addition, in the present invention, in order to increase the limit of the setting / holding time of the display data input to the data driver, a latching clock is generated based on the transmission clock. Preferably, the lock-up clock is generated so that the transmission clock rises faster during the period t, and the transmission clock decreases faster than the period t generated.

[Example]

Here is a graphic illustration of a liquid crystal display device for displaying data which is not invented.

Hereinafter, the first embodiment will be described with reference to FIGS. 1 to 10.

Fig. 1 is a block diagram showing the structure of the data driver of the first embodiment. 101 is a data driver that outputs a stepped voltage corresponding to the display data. In this embodiment, it is a data driver with 384 liquid crystal output lines. 102 is input transmission clock, 103 is input display data, 104 is input start signal. The data driver 101 is a reader who inputs the display data 103 with the rising end and the falling end of the input transmission clock 102 according to the input start signal 104. 105 is an input liquid crystal external signal containing a step voltage that corresponds to the display data, and 106 is an input liquid crystal reference voltage that determines the step voltage to be output to the liquid crystal display panel. 107 is a clock regeneration circuit, 108 is a regeneration transmission clock reproduced by the clock regeneration circuit according to the input transmission clock 102, 109 is a locked clock, and is a doubled signal of the regeneration transmission clock 108. 110 is a start control circuit, 111 is a blocking address start signal, 112 is an output start signal, 113 is an output start signal, and 111 to 113 are generated in the start control circuit 110 according to the input start signal 104 and the input transmission clock 102. . Reference numeral 114 is a latching circuit that locks the input display data 103 on the rising end of the latching clock 109, and 115 is a display data that is latched on the latching circuit 114. 116 and 118 are output buffers. When the output start signal 112 is at a low level, it becomes a high impedance state. 117 is the output transmission clock, and 119 is the output display data. 120 is a blocking address generating circuit, 121 is a blocking address, and the blocking address 121 is generated by the blocking address generating circuit 120 according to the blocking clock 109 and the blocking address start signal 111. 122 is a latching circuit (1), and 123 is display data read by the latching circuit (1) 122 according to the latching address 121. 124 is a blocking circuit (2), which is display data for the blocking circuit (2) 124 according to the input liquid crystal plus signal 105. 126 is a liquid crystal driving circuit, and 127 is a liquid crystal applied voltage generated from the input liquid crystal reference voltage according to the display data 125. 128 is to buffer the output liquid crystal external signal of the input liquid crystal external signal 105, and 129 is the output liquid crystal reference voltage to increase the input liquid crystal reference voltage 106 current.

Fig. 2 is a structural diagram showing a liquid crystal display device of the present invention. 500 is a liquid crystal display panel having pixel portions arranged in a matrix, and 501 is a liquid crystal display device. The size of the display area in this embodiment is, for example, the so-called 1024 × 3 (RGB) × 768 XGA specification. 502 is a liquid crystal controller, 503-1 ~ 503-8 is the data driver shown in the first figure, and 504-1 ~ 504-3 is used for outputting pixels (scanning lines) for selecting externally applied step voltage. The driver between the voltages is selected. The gate driver has 256 output numbers, and the data driver 503-1 ~ 503-8 and the cartridge driver 504-1 ~ 504-3 are glass substrates arranged on the liquid crystal display panel 500. Up. The 505-1 ~ 505-8 series are data driver signal groups, and are connected between the liquid crystal controller 502, the data driver 503, and the data driver in the next stage. The 506-1 ~ 506-3 series are the gate driver signal group, and are connected between the liquid crystal controller 502, the data driver 503, and the data driver of the next stage in the same manner as the data driver signal group.

FIG. 3 is a diagram showing a configuration of the clock reproduction circuit 107. 601 is an input buffer of the input transmission clock 102, and 602 is an input transmission clock output from the input buffer 601. 603 and 604 are inversion circuits, and 605 and 606 are signals for inverting the input transmission clock 602 and the comparison signal 619 in each of the inversion circuits 603 and 604. 607 and 608 are terminal comparison circuits that compare the bit plane differences between the ends of the input signal and output the difference. 609-up and 610-up are phase delay signals of the comparison circuits 607 and 608 at each end. 611 is a terminal discriminating circuit. The terminal discriminating calculation is performed based on the outputs of the terminal comparison circuits 607 and 608, and the results are output as a phase advance signal 612-up and a phase delay signal 612-dwn. 613 is a supply pump circuit, and 614 is an offset voltage. In the figure, it is constituted by CMOS electricity, and the offset voltage 614 is changed corresponding to the phase advance signal 612-up and the phase delay signal 612-dwn. 615 is a loop converter, which removes the high-frequency component of the offset voltage 614 and generates the offset voltage 616. 617 is a VCO (Voltage Controlled Oscillator) that changes the output frequency according to the input potential level. 618 is a frequency dividing circuit, which divides and locks the clock 109 to generate a comparison signal 619. 620 is a regenerative transmission clock 108 for an inversion circuit of the comparison signal 619.

FIG. 4 is a diagram showing the configuration of the end comparison circuits 607 and 608 of FIG. 3. Fig. 5 is a timing chart showing the operation of the terminal comparison circuit, and Fig. 6 is a diagram showing the structure of the terminal discrimination circuit, which includes NOR circuits 901-1 to 901-3 and an inversion signal 902.

Fig. 7 is a diagram showing the structure of the VCO circuit 617. 1001 is an inversion circuit for offset input, 1002 is an output buffer, VCO circuit 617 is connected to the inversion circuit 1001, and the output of the final stage is used as the initial stage. Input to get the oscillation frequency.

FIG. 8 is a graph showing the relationship between the bias voltage and the oscillation frequency of the VCO circuit 617, FIG. 9 is a timing chart showing the operation of the clock regeneration circuit 107, and FIG. 10 is a timing chart showing the operation of the data driver 101. The operation of this embodiment will be described based on the above drawings.

As shown in FIG. 2, the data driver signal group 505-1 generated by the liquid crystal controller 502 is transmitted to the first-stage data driver 503-1. Here, the operation of the data driver 503 will be described. As shown in FIG. 10, the input transmission clock 102 is transmitted from the circuit in the previous stage at the rising / falling end at a time when the input display data 103 can be read. However, as explained in the conventional example, the output buffer of the preceding circuit or the input buffer of this circuit may change the load of the input transmission clock 102 or the input display data 103 by the impedance of the transmission line.

For the data driver 503, the clock regeneration circuit 107 shown in FIG. 1 starts to generate the latch clock 109 and the regeneration transmission clock 108 based on the input transmission clock 102. This process is illustrated using Figures 3-9. As shown in FIG. 3, the input transmission clock 102 of the input clock regeneration circuit 107 is compared with the input comparison circuit 607 after the input buffer 601 and the rising ends of the comparison signal 619 are compared with each other. On the one hand, after the transmission clock 602 and the comparison signal 619 are input, and the inversion circuits 603 and 604 are respectively input and inverted, the comparison circuit 608 for comparing the falling ends with each other is input.

The terminal comparison circuit 607 has a structure shown in FIG. For the timing chart, for example, in the case of the terminal comparison circuit 607, as shown in Fig. 5, when the rising ends of the two input signals are compared, if the rising times of the two are the same, the output 609-up and 609-dwn are both the same. As a low level, when the input transmission clock 602 rises faster than the comparison clock 620, when the input transmission clock 602 is at a high level, the period 609-dwn is regarded as a high level when the comparison clock 620 is at a low level. Conversely, when the input transmission clock 602 rises slower than the comparison clock 620, when the input transmission clock 602 is at a low level, the period 609-up is regarded as a high level when the comparison clock 620 is at a high level.

Therefore, for the clock regeneration circuit 107, for example, for the input transmission clock 602, when the phase of the comparison signal 619 is slightly slower under the same period and load, the terminal comparison circuit 607 is configured to transmit the clock 602 from the input. During the period from the rise of the comparison signal 619 to the rise of the comparison signal 619, the phase delay signal 609-dwn becomes a high level, and for the period from the fall of the input transmission clock 602 to the fall of the comparison signal 619, the phase delay signal 610-dwn becomes a high level. At other times, the phase advance signal 609-up, phase advance signal 610-up, phase delay signal 609-dwn, and phase delay signal 610-dwn are all low-level. In other words, as a result, the phase advance signal and the phase delay signal become clear position difference information including the rise and fall of the input transmission clock 602 and the comparison signal 619.

The phase advance signals 609-up, 610up, and phase delay signals 609-dwn, 610-dwn generated in this way are, for the end discrimination circuit 611, by reading the theory and sum of the phase difference information generated separately during the rise and fall, and The rising and falling phase advance information and phase delay information are regarded as one piece of information, respectively. Furthermore, in order to consider the signal level of the supply pump circuit 613 suitable for the latter stage, when a phase difference occurs in the phase advance signal, the theoretical conversion is performed at a low level. In addition, although the phase difference signal cannot have a phase advance and a phase delay at the same time, it is only possible that, for example, the phase advance signal 609-up and the phase delay signal 610-dwn- may become a high-level period in the theory and calculation. Sex. Therefore, for the phase delay signal, after performing a theoretical calculation on the NOR circuit 901-2, the NOR circuit 901-3 is used as a barrier by using the inverted signal 902 as a phase advance signal with a high action.

The phase advance signal 612-up and phase delay signal 612-dwn generated as described above are input to the pump circuit 613. The supply pump circuit 613, as shown in FIG. 6, the phase advance signal 612-up regards the supply side as a high-potential input to the gate of the PMOS, and the phase delay signal 612-dwn uses the supply side as a low-potential input to the NMOS. Gate. The discharge side of PMOSP and NMOS is connected, and the offset voltage 614 is obtained from the node. Therefore, if the phase advance signal 612-up becomes a low level, the potential of the offset voltage 614 rises by applying a current from the high potential side, and if the phase delay signal 612dwn becomes a low level, the bias is performed by applying a current on the low potential side. The potential of the bit voltage 614 is low. In addition, when 612-up is at a high level and 612-dwn is at a low level, since no current flows to any source side, the bias voltage 614 does not change. The high-frequency component is removed by the loop filter 615 by the bias voltage 614 generated by the above operation, and then input to the VCO circuit 617.

Next, the operation of this VCO circuit 617 will be described. The VCO circuit 617 has linearity between the offset voltage and the oscillation frequency, as shown in FIG. 8. Therefore, for the ranges of the offset voltage 614 and VL and VH, the frequency change when the offset voltage changes from V1 to V2 and the frequency change when the offset voltage changes from V2 to V1 become equal.

The signal generated by the above VCO circuit 617 is regarded as a regenerative transmission clock 108 and is output from the clock regeneration circuit, and is fed back by the end comparison circuit 607, and is also fed back by the inversion circuit 604 via the inversion circuit 604.

As a result of the above operation, when the input clock of the clock regeneration circuit 107 is transmitted to the clock 602 and a signal of a load t0 T0% (T0 is a cycle time of the input signal and t0 is a high-level time) is input, as in the ninth case As shown in the figure, the comparison signal 619 rises trm time faster for the rise of the input transmission clock 602, and decreases tfm time slower for the fall of the input transmission clock 602. At this time, trm and tfm are equal from the characteristics of the VCO circuit 617. Therefore, when trm = tfm = (T0-t0) / 2 and the comparison signal 619 is at 50% load, the input transmission clock 602 only changes the same width before and after the change. The signal of the delay time is the same as the reproduction transmission clock 108 of this inversion.

The data driver 101 operates based on the latch clock 109 and the reproduction transmission clock 108 generated as described above. Here, the data reading method in the case of using the locked clock and the reproduction transmission clock will be described with reference to FIG. 10.

Even if the load of the output transmission clock 117 and the display data 119 output from the data driver in the previous section is 50%, the load of the input transmission clock 102 and the input display data 103 in this section is input by the input or output buffer or the impedance of the transmission line. Will change. However, when the drive capacity of the input and output buffers and the impedance of the transmission line are equal in any transmission path, as shown in Figure 10, the transmission clock becomes tdr seconds for the rise delay and tdf seconds for the fall delay. The display data is also rising delay tdr seconds, and falling delay tdf seconds, that is, for 1 cycle T0, the load is 50%, which changes by (50+ (Tdf-Tdr) T0)%. Here, for the first figure, the input display data 103 is blocked by the blocking circuit 114 with the blocking clock 109. However, if the input transmission clock 102 is blocked, the setting / holding time limit is set to Tdr> Tdf. In Fig. 10, for the falling end of the clock, the limit of the set time is still Trsu, but the limit of the hold time is Trho '= Trho- (Tdr-Tdf). In this regard, for the falling end, the limit of the set time is Tfsu '= Tfsu- (Tdr-Tdf). Because the set / hold time limit must be satisfied at the same time during the rise and fall, the limit of the set time of the circuit becomes Tsu = Tfsu- (Tdr-Tdf), and the limit of the hold time becomes Tho = Trho- (Tdr- Tdf).

In this regard, for the regenerative transmission clock in the case where the first embodiment is applied, the load becomes 50%, and for the rise / fall, compared with the input transmission clock, the rise is fast (Tdr-Tdf) / 2 seconds and rises. Mid-slow (Tdr-Tdf) / 2 seconds fall, so the limits of setting / holding time in the rise are Trsu " = Trsu- (Tdr-Tdf) / 2, Thsu " = Tfsr + (Tdr-Tdf) / 2 = Tfsu- (Tdr-Tdf) / 2, and the limits of the set / hold time during the fall are Tfsu " = Tfsu + (Tdr-Tdf) / 2 = Tfsu- (Tdr-Tdf) / 2, Tfho " = Trsu- (Tdr-Tdf) / 2, the limit of the setting / holding time is no longer the difference between the rise and fall of the clock, and the limit of both sides of the setting / holding time (Tdr-Tdf) / 2 seconds occurs, It enables high-speed transmission of a part of it.

Following the second embodiment, a clock regeneration circuit having a structure different from that of the first embodiment will be described using FIGS. 1, 11 to 17.

Fig. 11 is a block diagram showing the structure of a clock regeneration circuit of the second embodiment. 1401 is the first delay circuit, the delay is only half of the high level width of the input transmission clock 102, and a delayed transmission clock (1) I402 is generated. 1403 is a load regeneration circuit, which is synchronized with the delayed transmission clock (1) 1402 and generates The regenerative transmission clock (1) 1404 with a load of 50%. 1405 is a second delay circuit. By having the same function as the first delay circuit (1) 1401, the delay is only the high level of the regenerative transmission clock (1) 1404. Half of the phase, the regenerative transmission clock 108 is generated. 1406 is an exclusive theory and circuit. By performing the exclusive theories and calculations of the regenerative transmission clock 1404 and the regenerative transmission clock 108, a locked clock 109 is generated.

FIG. 12 is a diagram showing the structure of the first delay circuit 1401. 1501-1-1 are delay circuits composed of the same structure, all of which delay the input signal according to the delay control signal 1502. here ， The delay circuit 1501-1 produces a delayed transmission clock by delaying the input transmission clock 102 (11402, and the delay circuit 1501-2 produces a delayed transmission clock (2) 1503 by delaying the transmission clock (1) 1402. 1504 series 1505 is an inversion signal of the input transmission clock 102 generated by the inversion circuit 1504. It is a terminal comparison circuit and determines the phase of the delayed transmission clock (2) 1503 and the rising ends of the inversion signal 1505. And the results are output as phase advance signal 1507-up and phase delay signal 1507-dwn. 1508 is a delay signal for the delay circuit 1509 is a delay signal for the inversion signal 1505. 1510 is a pre-count / count-down counter, and The delay signal 1509 is synchronized and counts up when the phase advance signal 1507-up is valid and counts down when the phase delay signal 1507-dwn is valid. The result is generated as a timing signal 1511. 1512 Series For the decoder, the timing signal 1511 composed of n bits is transformed into only 2 ︿ One of the n bits becomes the effective delay control signal 1502.

FIG. 13 is a diagram showing a configuration of the delay circuit 1501. Delay circuit 1501, which consists of 2 ︿ Delay circuit composed of n 1601-1-1 ~ 1601-2 ︿ n, will delay the input transmission clock 102 for the input by 2 ︿ n stages, and generate 1601-1 ~ 1601-2 ︿ n. 1603-1 ~ 1603-2 ︿ n is a switching circuit, and at most one switching circuit is turned on according to a delay control signal 1502 composed of 2n bits, and a delayed transmission clock (1) 1402 is obtained as an output. The delay circuit 1501-1 and the delay control signal 1502-1 are composed of equivalent circuits.

Fig. 14 is a diagram showing the structure of a comparison circuit on the display side, 1701-1, 1701-2 are delay circuits, and 1702-1, I702-2 are latch circuits. With the structure shown in FIG. 14, the terminal comparison circuit 1506 for the delayed transmission clock (2) 1503, when the inverted signal 1505 is ahead of the phase of the delay portion of the delay circuit 1701-1, the phase advance signal 1507-up It becomes a high level. Conversely, when the delayed transmission clock (2) 1503 is ahead of the delay signal 1701-2 in the inverted signal 1505, the phase delay signal 1507-dwn becomes a high level.

Fig. 15 is a timing chart showing the operation of the first delay circuit.

Fig. 16 is a diagram showing the structure of a load regeneration circuit 1403.

1901-1, 2 are delay circuits composed of the same structure, all of which delay the input signal according to the delay control signal 1922. Here, the delay circuit 1921-1 generates a cut-off signal 1903 by delaying the delayed transmission clock (1) 1402, and the delay circuit 1501-2 performs a cut-off signal 1923 by delay to generate a delayed transmission clock (3) 1904. 1905 is a terminal The comparison circuit, for example, has the same function as the circuit shown in FIG. 17, and compares the phase difference between the delayed transmission clock (3) 1904 and the delayed transmission clock (1) 1422, and uses the result as a phase advance signal. -Up, 1 phase delay signal 1926-dwn output. 1927 is a delay circuit, and 1908 is a delayed signal of a clock (1) 1402 transmitted with a delay of the delay circuit. 1910 is a countdown / countdown counter, which is synchronized with the delay signal 1908. When the phase delay signal 1906-dwn is valid, it counts down and generates a timing signal 1911. 1912 is a decoder and will consist of n bits The timing signal 1911 is converted into 2 ︿ Only one of the n bits becomes the effective delay control signal 1902. 1913 is a blocking circuit with a terminal cut-off function, which locks the high-level voltage synchronously with the delayed transmission clock (1) 1402, and proceeds with the drop of the cut-off signal 1903. Asynchronous erasing operation generates a reproduction transmission clock 128.

Fig. 17 is a diagram showing the operating time of the load regeneration circuit. Based on the above drawings, the operation of the second embodiment will be described in detail.

As in the first embodiment, the input transmission clock 102 is changed after the input load of the data driver 101 is changed. The input transmission clock 102 for the data driver 101 from the aforementioned external input is transmitted to the clock regeneration circuit 107 of the data driver 101 of this embodiment shown in FIG. 11. Here, the operation of the clock regeneration circuit will be described using FIGS. 12 to 17.

With reference to Fig. 12, the input transmission clock 102 is transmitted to the delay circuit 1501-1. The delay circuit 1501-1 is a structure shown in FIG. 13, by using 2 ︿ n delay circuits 1601-1-1601-1-2 ︿ n, delay input transmission clock 102 by 2 ︿ n stages. 2 generated from the above circuit ︿ n-stage delayed signal 1602-1-160.2-2 ︿ n, using the delay control signal 1502 to select the switching circuit 1603-1 to 1603-2 ︿ In n, the only switch circuit is generated by delaying the transmission clock (1) 1402. The delay transmission clock (1) 140 thus generated is input to the delay circuit 1501-2. Here, the delay circuit 1501-2 is exactly the same circuit as the delay circuit 1501-1. Since the delay control signal is common, the delay time of the delay circuit 1501-1 is equal to the delay time of the delay circuit 1501-2. In this way, a delay transmission clock (2) 1503 is generated through the delay circuit 1501-2. The delayed transmission clock (2) 1530 and the aforementioned inversion signal 1505 are input to the comparison circuit 1506. The comparison circuit 1506 has a structure as shown in FIG. 14. The phase difference between the input signals is determined by the delay circuit 1701. In the range of the delay time determined by 1 and 1701-2, the phases of the delayed transmission clocks 1503 and 1505 are considered to be a multiple of the period, and the phase advance signal 1507-up and the phase delay signal 1507-dwn are both It becomes a low level. When the delayed transmission clock (2) 1503 is delayed by the delay circuit 1701-1-1 for the inverted signal 1505, it becomes a high level. When the inverted signal 1505 is delayed for the delayed transmission clock (2) 1503 by the delay circuit 1701 If -2 is ahead of the delay time, the phase delay signal 1507dwn becomes a high level. In addition, although this circuit has substantially the same meaning as the end comparison circuits 607 and 608 of the first embodiment, since the information about the wide phase difference in this embodiment does not have a large meaning, FIG. 14 can be used. The circuit shown.

The phase advance signal 1507-up and the phase delay signal 1507-dwn are input to the pre-count / count-down counter 1510 together with the delay signal 1509. The countdown / countdown counter 1510 counts down according to the delay signal 1509 when the phase advance signal 1507-up is high, and counts down according to the delay signal 1509 when the phase delay signal 1507dwn is high. Therefore, as shown in the action time chart in FIG. 15, when the phase advance signal 1507-up is at a high level, the timing signal 1511 performs the pre-counting action at 3, 4, and 5, when 1507 － If up and 1507-dwn become low level together, stop the timing operation and keep the count value. The n-bit timing signal 1511 generated as above is decoded into 2 in the decoder 1512 ︿ n bits, and a delay control signal 1502 is generated. With the above operation, when the rising edge of the input transmission clock 102 is considered to coincide with the rising edge within the rising edge of the delayed transmission clock (3) 1503, the state can be maintained.

Here, since the delay circuits 1501-1 and 1501-2 are the same circuit, the rising end of the delayed transmission clock (1) 1402 generated by the delay circuit 1501-1 becomes half of the high level time of the input transmission clock 102. position.

Next, the load regeneration circuit 1403 will be described using FIGS. 16 and 17. In FIG. 16, the delayed transmission clock (1) 1402 is transmitted to the delay circuit 1901-1 together with the latch circuit 1913. The delay circuit 1901-1 is the same as the delay circuit 1501-1 in the structure shown in FIG. 13, and a unique switch circuit is selected by using the delay control signal 1902 to generate a reset signal 1903. The reset signal 1903 thus generated can be applied as a cut-off signal of the latch circuit 1913, and is input to the delay circuit 1901-2.

Here, the delay circuits 1901-1 and 1901-2 are completely equal circuits. Because the delay control signals are common, the delay time of the delay circuit 1901-1 and the delay time of the delay circuit 1901-2 are equal. The method of generating the delay control signal 1902 is the same as that in the case of using the first delay circuit 1401 described with reference to FIG. 15. The blocking circuit 1913 blocks the high level at the rising end of the delayed transmission clock (1) 1402, and the low level is removed at the rising of the cut-off signal 1903, and the regeneration transmission clock 108 for its output is the input shown in FIG. 17 The transmission clock 102 has the same cycle and the load becomes a signal of 50%. Further, since the delayed transmission clock (1) 1402 is shifted from the input transmission clock 102 by a phase of a half-period portion of a high level width, the phase of the half-period portion of the high-level width of the regeneration transmission clock 108 or the input transmission clock 102 is also shifted. Make a signal that can generate targets. The regeneration transmission clock 108 thus generated is input to the second delay circuit 1405. The second delay circuit 1405 has exactly the same function as the first delay circuit 1401, and outputs a signal shifted from a high-level half-period portion of the input signal. Here, the regenerative transmission clock 1404 which is the input signal of the second delay circuit 1405 has a load of 50%, so the regenerative transmission clock 108 becomes a signal having a phase shift of 1 to 4 cycles with respect to the regenerative transmission clock 1404. The signal performs an EXOR operation on the exclusive theory and circuit 1406 to generate the lock clock 109.

From the above, it can be seen that, for the input transmission clock 102, the period is the same and the load is 50%, and it only rises fast (or slowly) half the time of the load difference of the input transmission clock 102, so that a slow (fast) falling signal can be generated. It is possible to construct a reproduction transmission clock having the same effect as that of the first embodiment by using only digital circuits.

And ， The liquid crystal display device of the present invention is specifically described with reference to the washer connection of the data driver. However, the present invention is not limited to this, and can also be applied to a method of connecting the data drivers in parallel. Furthermore, the present invention is not limited to a liquid crystal display device, and needless to say, it can be applied to all devices in which a load may be changed by having a transmission line or an input / output buffer.

According to the first embodiment and the second embodiment of the present invention, the data driver has a reproduction circuit provided with a transmission clock, and the driver of this paragraph makes it easy to read display data, and it does not need to be changed. The transmission signal and load of the display data towards the driver of the next stage can be transmitted. In addition, it becomes a setting / holding limit for increasing display data. In addition, the transmission frequency can be increased. In addition, the liquid crystal display device of the gasket type which can realize a low price can realize large screen and high definition.

Schematic illustration