Method for manufacturing bonded wafer

Manufacturing method of bonded wafer

<p>1. . . Bonded wafer</p><p>3. . . Oxide film</p><p>5. . . Stripping wafer</p><p>2. . . Base wafer</p><p>4. . . Micro bubble layer (injection layer)</p><p>6, 7. . . SOI wafer</p>

Figure 1 is an exemplary diagram of the method for manufacturing a bonded SOI wafer according to the present invention; wherein the process (A) is a method of forming an oxide film only on the side of the base wafer where ions are not applied; and the process (B) is on the bonded wafer After the oxide film is formed, ion implantation is performed.

The present invention relates to a so-called ion implantation stripping method in which a wafer implanted with hydrogen or rare gas ions is subjected to heat treatment and then peeled off to produce a bonded wafer, especially the bonding surface is not prone to produce voids ( void) is a method of manufacturing bonded SOI wafers with poor bonding.

In terms of the method of manufacturing a bonded SOI (SILicon On Insulator) using the bonding method, for example, as shown in Japanese Patent Publication No. 5-46086, the technology of bonding two silicon wafers through a silicon oxide film is also That is, the method of forming an oxide film on at least one wafer and making the bonding surfaces close to each other so that no foreign matter is trapped, and then performing a heat treatment at a temperature of 200 to 1200°C to increase the bonding strength is well known.

The bonded wafer with improved bonding strength through heat treatment can be subsequently cut and polished. Therefore, it is possible to reduce the thickness of the wafer on the component production side to the desired thickness by cutting and polishing. The SOI layer is used to make components.

The laminated SOI wafer produced in this way has excellent crystallinity of the SOI layer, and the embedded oxide film directly under the SOI layer also has the advantage of high reliability. However, the thin film is formed by cutting and polishing. It is very time-consuming and wasteful of materials. At the same time, the film thickness uniformity is at best only ±0.3μm of the target film thickness.

On the other hand, with the increasing integration and speed of semiconductor devices in recent years, there is an increasing demand for further thinning of SOI layer thickness and improvement of film thickness uniformity. Specifically, the film thickness must be 0.1± The degree of 0.01μm, and must have uniformity.

To construct thin SOI wafers with such film thickness and film thickness uniformity from bonded wafers, conventional thickness reduction processing techniques using cutting and polishing methods cannot be achieved. Therefore, there is Japanese Patent Publication No. 5-211128 The so-called ion implantation stripping method or hydrogen ion stripping method (also known as "smartcut" (registered trademark) method) disclosed in the No. Bulletin has been developed and completed.

The SOI wafer manufacturing method using this ion implantation lift-off method is to form an oxide film on at least one of two silicon wafers, and at the same time inject hydrogen ions or rare gas ions from a silicon wafer, and in the silicon wafer A fine bubble layer (encapsulation layer) is formed inside the circle, and then another wafer is attached to the ion implantation surface along with the oxide film, and then heat treatment (peeling heat treatment) is applied, and the fine bubble layer is used as the cut surface (peeling surface) ), the wafer is peeled off into a thin film, and further heat treated (combined heat treatment) to obtain a firmly bonded SOI wafer.

In addition, recently, a method of manufacturing an SOI wafer that uses hydrogen ions to excite a plasma state to perform ion implantation without special heat treatment, that is, to perform peeling at room temperature has also been known.

In this method, the cut surface is an excellent mirror surface, it is easier to obtain SOI wafers with extremely high SOI layer uniformity, and the stripped thin film wafers can be reused, so there is an advantage that materials can be used effectively.

Moreover, this method can directly bond silicon wafers to each other without intervening an oxide film. Therefore, it can be used not only in the case of bonding silicon wafers to each other, but also by implanting ions into silicon wafers and combining with quartz , Silicon carbide, aluminum oxide and other insulating wafers with different thermal expansion coefficients, or injecting ions into insulating wafers and combining them with other wafers to produce wafers with these films.

However, when the bonded wafer is manufactured by the above-mentioned ion implantation lift-off method, the organic matter or particles attached during the ion implantation step will cause the original problem of so-called void bonding defects on the bonding interface. Therefore, in general, the ion-implanted wafer is cleaned by RCA or organic removal and then combined with the wafer on the other side. The so-called RCA cleaning spares SC-1 (NH ₄ OH/H ₂ O ₂ /H ₂ O mixed liquid) and SC-2 (HCI/H ₂ O ₂ /H ₂ O mixed liquid) and other two kinds of cleaning liquids are based, and it is the cleaning method in the semiconductor manufacturing process, which can mainly remove particles, organic matter, metal pollution, etc.

However, when the ion-implanted wafer is cleaned using the conventional cleaning method such as the above to produce a bonded wafer, the occurrence of voids may not be suppressed to a satisfactory level. Especially after bonding or peeling heat treatment, even if no voids are observed, the peeling surface will be slightly researched after the bonding heat treatment or bonding heat treatment. The so-called touch polishing (touch polishing) step can be observed. Small (less than 1mm) voids, so it is necessary to reduce the occurrence of voids.

The present invention has conducted a detailed investigation on the pores that are still generated even after the above-mentioned ordinary cleaning step, and found that the cause is that the particles or organic matter attached during the ion implantation step cannot be completely removed in the conventional chemical cleaning. Removed, and will remain, or the surface roughness of the wafer surface due to ion implantation will also produce particles or organic matter. Therefore, when researching and developing the removal of such residual fibrous particles or other impurities or surface roughness, the use of physical removal means is considered, thereby completing the present invention.

In terms of physical removal of impurities, for example, CPM technology can be used, whereby CMP polishing can physically remove impurities such as particles or organics that exist on the ion implanted surface and cannot be removed by chemical cleaning. At the same time, the surface roughness generated in the ion implantation step is also improved, so the cause of the voids can be removed.

The "CMP" technology of the present invention is defined below.

Among the technologies that have received much attention in semiconductor process technology in recent years is the so-called CMP (Chemical and Mechanical Polishing) technology. CMP technology in a broad sense is not a particularly novel technology. General chemical and mechanical research has been used for mirror research of silicon wafers since ancient times. On the other hand, the narrow-sense CMP technology that has attracted much attention in recent years is one of the planarization technologies of semiconductor manufacturing processes. It is a physical planarization method that planarizes interlayer insulating films such as oxide films or metal films such as wiring. As the main body's representative animal technology.

In the present invention, when simply written as "CMP", it means CMP in a narrow sense. In the following, referring to Fig. 1(A) and Fig. 1(B), an example in which silicon wafers are bonded to each other to produce an SOI wafer is described as an embodiment of the present invention, but the present invention is not limited thereto.

In step (a), two silicon wafers 1 and 2 are prepared, and both wafers are cap crystalline silicon wafers that are mirror-polished at least on the surfaces to be bonded. Among them, 1 is the bonded wafer (the first wafer), and 2 is the base wafer (the second wafer).

Step (b) is to form an oxide film 3 on any one of the two silicon wafers 1 and 2. The oxide film is used as the embedded oxide film of the SOI wafer, so its thickness is set according to the application.

Step (c) is a step of implanting ions into the bonded wafer 1 as the SOI layer, which is to inject at least hydrogen ions or rare gas from above on one side of the bonded wafer 1 (the surface bonded to the base wafer 2) A sort of. In this step, hydrogen ions are implanted to form a fine bubble layer 4 parallel to the surface at the average penetration depth of the ions. Therefore, the wafer temperature during implantation is preferably below 450°C, especially below 200°C; and implantation The energy is appropriately determined according to the target thickness of the SOI layer of the SOI wafer to be fabricated. Furthermore, when ion implantation is to be performed on a bare silicon crystal without an oxide film formed on the surface, in order to prevent channelling effect, the implantation is performed at a certain tilt angle with respect to the crystal axis of the bonded wafer 1 in a non-parallel manner. Better.

After step (c), in the past, the cleaning step (chemical cleaning method) was used, and the two wafers 1 and 2 were bonded together. However, in the present invention, the impurity removal treatment (d) is used as the surface treatment before bonding. , To remove impurities attached to the surface of the bonded wafer 1 implanted with ions. The impurity removal treatment (d) uses physical means. Specifically, general chemical mechanical polishing or physical removal that combines both physical removal and chemical removal has mainstream CMP or brushing, and it can also be used in conjunction with conventional chemical cleaning methods. Furthermore, after the physical removal, when the chemical cleaning is performed again, due to the impurity removal effect of the physical removal step, even if the concentration of the chemical cleaning solution is lower than usual, a sufficient cleaning effect can be obtained. Therefore, the chemical cleaning is caused The roughness of the wafer surface can be reduced, and the cost of cleaning liquid production can also be reduced.

In general CMP, for example, rigid foamed urethane can be used as a polishing cloth, and for grinding slurry, potassium hydroxide or ammonia can be added to a slurry of smoked silica. As for scrubbing, you can rinse with pure water or alkaline aqueous solution while scrubbing with a brush (materials can be polyvinyl alcohol, etc.).

The physical method to remove the particles attached to the surface of the wafer can be applied regardless of whether the surface is a silicon crystal surface (process (A) in Figure 1) or an oxide film surface (process (B) in Figure 1) , Will effectively remove the source of the hole. In particular, CMP can physically remove pollutants such as particles on the surface of the wafer as well as the silicon or oxide film of the substrate, so the surface roughness caused by the ion implantation step can also be improved.

Furthermore, step (e) is a step in which after physical removal of impurities (e) is performed on the surface of the wafer implanted with ions by CMP or the like, the wafer 2 (base wafer) on the other side is overlapped and tightly bonded. In a clean gas environment, the surfaces of the two wafers can be brought into contact with each other, and the two wafers can be bonded without the need for adhesives. At this time, in the process (B) of Figure 1, another wafer 2 (base wafer) can also be pre-formed with an oxide film on its surface as needed.

Step (f) uses the encapsulation layer formed by ion implantation as the interface to perform ww to separate the separation wafer 5 and the SOI wafer 6 (SOI layer 7 + embedded oxide film 3'+ base wafer 2) into a peeling heat treatment step. If heat treatment is applied in an inert gas environment or an oxidizing gas environment at a temperature of about 400-600°C, it can be separated into the stripped wafer 5 and the SOI wafer 6 by the rearrangement of crystals and the aggregation of bubbles. At the same time, the contact surface at room temperature is also firmly bonded to a certain extent. In addition, the peeled wafers 5 and 5'in the process (A) and (B) of Figure 1 can be reused if the oxide film on the surface is removed as needed and the peeling surface is polished for regeneration.

To use the SOI wafer 6 in a semiconductor device, the bonding force produced by the peeling heat treatment in step (f) is not sufficient, so the high temperature heat treatment in step (g) is used as the bonding heat treatment to sufficiently improve the bonding strength. The heat treatment system can be carried out in the range of about 30 minutes to 5 hours at a temperature of 1000°C to 1200°C under, for example, a bridging gas ring stirring or an oxidizing gas environment. Furthermore, if the rapid heating/rapid cooling device of the lamp heating device is used, sufficient bonding strength can be obtained in a short time of about 1 to 300 seconds at a temperature of 1000°C to 1350°C.

In addition, if the peeling heat treatment of step (f) is also used for the bonding heat treatment of step (g), step (f) may be omitted.

Next, step (h) is a mirror polishing process to remove the damaged layer and surface roughness existing on the surface of the SOI layer as the cleaved surface (peeling surface). This step can be accomplished by a so-called tauch polish (tauch polish), a polishing method with a very small thickness, or by applying heat treatment in a hydrogen-containing reducing gas environment after the contact polishing. When the heat treatment is performed in the reducing gas environment of hydrogen, the damaged layer and surface roughness can also be removed, so it can also be used as the combined heat treatment of step (g), and the efficiency is better.

Through the above-mentioned steps, a bonded SOI wafer with a very low incidence of voids or no voids at all can be produced.

In addition, the present invention is not limited to the above-mentioned embodiment. For example, in the above embodiment, although the steps of using ion implantation lift-off method to bond two silicon wafers through an oxide film to produce an SOI wafer have been described, the present invention can also be applied to other bonding wafer production methods. In other words, not only can it be used to directly bond silicon wafers to each other to form a bonded wafer after ion implantation without using an oxide film, but it is also suitable for implanting ions into the silicon wafer and then making the wafer Directly with SiO ₂ , SiC, Al ₂ D ₃ The process of combining insulating wafers to produce SOI wafers.

Furthermore, in the above-mentioned embodiment, although the case where the stripping is performed after the heat treatment in the hydrogen ion stripping method is described, the present invention is also suitable for exciting hydrogen ions to perform ion implantation in a plasma state, and then Stripping at room temperature without special heat treatment by hydrogen ion implantation stripping method.

In the embodiment, SOI wafers were fabricated under the following conditions, and the occurrence of voids was compared.

<tables><img file="TW511141B_D0001.tif" /></tables>

<CMP> device: MIRRA model made by APRID and MATERIAL Company <empty observation> device: Bright Iight 200 made by Irvine Company Observation size: Hole as large as 1mmΦ. Hole observation referred to in this article is exposed after touch polishing In the part of the bonding surface, voids larger than 1mmΦ are not present in any wafer.

As mentioned above, in the present invention, when the bonded wafer is fabricated by the ion implantation lift-off method, after ion implantation, the impurities attached to the surface of the wafer are physically removed, so generally RCA cleaning or organic removal cleaning cannot be removed. The organic matter and particles can be completely removed, and at the same time, the surface roughness produced by the ion implantation step can also be improved by research. Moreover, after physical removal (CMP), the concentration of the chemical solution can be reduced during chemical cleaning. Therefore, compared with the prior art, the surface roughness can be suppressed even lower.

Therefore, the thickness of the void defect can be completely eliminated, so the yield of the product can be improved.

Schematic description

Figure 1 is an exemplary diagram of the method for manufacturing a bonded SOI wafer according to the present invention; wherein the process (A) is a method of forming an oxide film only on the side of the base wafer where ions are not applied; and the process (B) is on the bonded wafer After the oxide film is formed, ion implantation is performed.

Symbol description of main components

1. . . Bonded wafer

3. . . Oxide film

5. . . Stripping wafer

2. . . Base wafer

4. . . Micro bubble layer (injection layer)

6, 7. . . SOI wafer