Manufacturing method for semiconductor device

Manufacturing method of semiconductor device

<p>1. . . Low-pressure CVD device</p><p>2. . . Semiconductor wafer</p><p>3. . . Quartz Chamber</p><p>twenty one. . . Lamp annealing device</p><p>twenty three. . . Quartz glass tube body</p><p>twenty four. . . Infrared light</p><p>25. . . Heating means</p><p>201. . . Semiconductor substrate</p>

Fig. 1 is a schematic diagram of a low-pressure CVD apparatus using this embodiment.

Figure 2 is a schematic diagram of the lamp annealing device using this embodiment.

Fig. 3A is a temperature program showing the first example of lamp annealing treatment related to this embodiment. The B series temperature program represents the second example of lamp annealing treatment related to this embodiment. The C series temperature program represents the third example of lamp annealing treatment related to this embodiment.

FIG. 4 is a cross-sectional view illustrating an example of using a semiconductor substrate in this embodiment mode.

Figure 5 shows the temperature program and gas program of the low-pressure CVD device used in this embodiment.

6A~D are the manufacturing engineering drawings of the sample substrate with the heteroepitaxial layer related to this embodiment.

FIG. 7 is a graph showing the concentration distribution of boron (B) and germanium (Ge) in the sample matrix of this embodiment.

Fig. 8 is a temperature program showing a specific example of lamp annealing treatment related to this embodiment.

Fig. 9 is a temperature program showing a specific example of lamp annealing treatment related to the comparative example.

Figure 10 is a graph of the evaluation results of this implementation type.

Fig. 11 is a graph showing the wavelength dependence of Si emissivity.

[Technical Field of Invention]

The present invention relates to a method of manufacturing a semiconductor device, in particular to a light irradiation heat treatment method after heteroepitaxial growth.

[Previous Technology]

The minimum size of semiconductor substrates, especially bidirectional integrated circuits formed on silicon semiconductor substrates, has continued to shrink. Correspondingly, the barrier frequency (fT) and maximum transmission frequency (f _max ), and transmission delay (τ _pd ) Gradually became difficult. This is because the parasitic factor associated with the transistor increases while the minimum size is reduced.

High performance of bidirectional junction transistor (BJT), especially blocking frequency f _T In terms of the improvement, the carrier operating time in the base area is shortened, and the pn junction area of the parasitic formed in the transistor is reduced, and the parasitic capacitance is reduced as much as possible to achieve a substantial improvement.

The minimization of these parasitic factors, unfortunately, it has harm to the common emitter along the current increase rate (h _fe ) And collector emitter yield voltage (BV _Ceo ) Tendency. For example, as the base width becomes narrower, the base doping must be increased to maintain the collector-emitter yield voltage (BV _Ceo ). This will not only reduce the common emitter forward current increase rate (h _fe ), it will also shorten the high temperature exposure time during the subsequent processing of this device. Therefore, the actual two-way junction transistor is basically limited to a blocking frequency of about 20~30GH (f _T )superior.

In order to solve this problem, in recent years, it has been proposed to form emitter-base junctions by different junctions. In the case of a structure with a wide junction width on the emitter and a narrow junction width on the base, the difference in junction width can prevent holes from being injected from the base to the emitter, so the efficiency of electron injection from the emitter to the base Can be relatively improved. Therefore, there are advantages that can ensure the current increase rate of the bidirectional transistor.

There are two combinations of different junctions: an emitter method with a wide junction and a base method with a narrow junction. The former method uses materials with a wide range of emitters such as GaAS, SiC, and silicon (refer to 1987 IEDM, Tech. Digpp186-193). The latter is based on MBE (Molecular Wire Epitaxy) and MOCVD (Metal Organic Chemical Vapor Growth) and other methods using Si-Ge mixed crystals and other materials with a narrow bonding width (refer to the 35th Applied Physics Association in Spring 1970). Lecture 29aZ12/I).

In particular, heterobipolar transistors (HBT) using GaAS and other group III-V compound semiconductors have been most researched and developed, but in recent years, SiGe-based materials of group IV-IV compounds that can be fabricated on inexpensive silicon substrates have been used. And focus on HBT.

The electron affinities of Si and Ge are 4.05 eV and 4.0 eV, respectively, and their values are almost the same, and the bonding difference is 1.1 eV and 0.66 eV, respectively. In addition, Si-Ge mixed crystals are reported to have an intermediate bond width of Si or Ge (refer to Band alignments of coherently strained Ge _X Si _1-X /Si heterostru ctures on<011>Ge _Y Si _1-Y substrates Applied PhySical Letter S48, 24 February 1986). Combining these materials can form Si on the emitter, Ge or Ge-Si mixed crystal layer on the base, and Si and other bidirectional transistors on the current collector.

On the transistor of this composition, because the pn junction is formed at the interface between the Si-Ge mixed crystal layer of the emitter and the base, the energy barrier for holes is larger than the energy barrier for electrons, and the pn junction is diffused and flows. The carrier is mainly electrons. Therefore, the emitter injection efficiency of the bidirectional transistor using this heterojunction is greatly improved.

Furthermore, by suppressing the injection of holes from the base into the emitter, the delay caused by the holes accumulated in the emitter can be eliminated. The low concentration of the emitter reduces the junction capacity between the emitter and the base to form a high-speed bidirectional Transistor is an extremely effective method.

[Problems to be solved by the invention]

However, in the aforementioned materials with a narrow bonding width on the base, for example, MBE, MOCVD, and LP-CVD are used to form Si-Ge mixed crystals (Si ₁ - _X Ge _X ), due to the difference in the number of crystal lattices on the Si and Si-Ge mixed crystals, the Si-Ge mixed crystal layer and the underlying Si single crystal substrate are not in conformity with the crystal lattice, and when the Si-Ge layer with a certain thickness is deposited, Crystal defects such as migration and cracking may occur. Therefore, the problem is that the Si-Ge mixed crystal layer cannot be deposited thickly on the Si substrate.

As mentioned above, in order to improve the emitter injection efficiency, the junction width of the emitter-base junction must be changed rapidly. When the emitter base is joined, the emitter only needs to suppress the ingress of holes, so the Si single crystal of the emitter electrode on the base Ge or Si-Ge mixed crystal layer can be thin (for example, 5-10nm). Therefore, there can be hetero-epitaxial growth between the base and the emitter without defects.

However, if the base layer is thinned, there will be an exchange relationship that the base resistance increases, so it needs to be about 10 to 100 nm, and the Si-Ge mixed crystal layer needs to be thicker. In addition, in order to make the emitter have sufficient bonding difference between the base, Si ₁ - _X Ge _X The composition must be X=0.1 or more. Therefore, a Si~Ge layer of 50nm~300nm must be deposited on the Si substrate.

For example, the Si _1-X Ge _X When a film with a composition of about X=0.5 is formed on a silicon substrate at 10nm, there are reports that _1-x Ge _x There will be a transfer (refer to SILICON MBE: FROM ST RAINED-LAYE REPITAXY TO DEVICE APPLICATION: Journal of Crystal Growth 70 (1984) 444-51). In addition, if a film with X=0.5 or more is grown on a si substrate of 50nm or more, due to the unconformity of the crystal lattice, there will be mismatch transfer on the Si-GE mixed crystal layer, and crystal defects will occur in the base area.

This crystal defect becomes the recombination center of the carrier, which makes the emitter injection efficiency low and forms the cause of penetration between the emitter current collectors. Therefore, it will form a big obstacle when obtaining normal transistor characteristics. In the base area, the current situation is that in order to ensure poor bonding, increase the Ge concentration, and ensure a certain level of base thickness to thicken a single si-Ge mixed crystal layer to meet the aforementioned two requirements at the same time has not yet been established.

Some reports have pointed out various ways in which the transfer of the heteroepitaxial growth layer on silicon can be removed or suppressed. The famous one is thermal annealing after growth to reduce defects. For example, refer to JW Lee and other papers in 50 Appl. Phys. Lett. 31 (1987), Chai and other papers in 50 Appl. Phys. Lett. 992 (1987), and 49 Appl. Phys . N. Zhang De and other papers recorded in Lett. 815 (1986).

The post-grown annealing itself has proven to have the effect of reducing a wide range of defects in the heteroepitaxial layer on the silicon substrate. However, the introduction of impurities into the emitter silicon layer is generally performed by diffusing n-type impurities generated by the polysilicon film deposited on the emitter silicon layer. In order to achieve a shallower junction formation, a halogen lamp is used to quickly heat the lamp annealing device .

At this time, the difference in the thermal expansion coefficient between the Si layer and the Si-Ge mixed crystal layer will cause thermal deviation, and the problem of dislocation and increase in order to alleviate the deviation. In particular, the emissivity of Si is shown in Figure 11. The short-wavelength migration absorption range of 1.1 eV or more (1.4μm or less) of the poor junction and the vibration absorption range generated by the long-wavelength lattice vibration of 10μm or more are Existing, the wavelength range in between is called a window, and there is a range that depends on impurities and temperature. The emissivity in the wavelength range outside the window is not dependent on the temperature and wavelength and is 0.7 (1.0 for blackbody), but the window area obviously depends on the temperature lower than 600°C. The lower the temperature, the more infrared rays penetrate, especially above 600°C. Above 700°C, the wavelength range outside the window is almost the same as the emissivity.

Since the Si-Ge mixed crystal layer has an intermediate junction difference width of Si or Ge, the migration and absorption area is biased to the long wavelength side. The temperature rise during heating during lamp annealing is different on the Si layer and the Si-Ge mixed crystal layer. , So it generates thermal stress and promotes the growth of dislocation.

In view of the above-mentioned points, the present invention provides a method for manufacturing a semiconductor device, especially annealing technology, which can form a heterojunction device such as a heterojunction transistor with few defects and high yield.

[Means to solve the problem]

The method of manufacturing a semiconductor device according to the present invention is that when a substrate having a semiconductor layer different from that of the underlying semiconductor is heat-treated with light, the temperature is temporarily set at an intermediate temperature between the starting temperature and the maximum temperature. Maintain the temperature of the substrate.

The temperature of the substrate is temporarily maintained at an intermediate temperature between the starting temperature and the maximum temperature. At the intermediate temperature, the temperature of the underlying semiconductor and the above heterogeneous semiconductor layer can be the same, so that the thermal stress during the subsequent temperature rise is suppressed.

The manufacturing method of the semiconductor device according to the present invention is that when a substrate having a semiconductor layer different from that of the underlying semiconductor on the underlying semiconductor is heat-treated with light, the intermediate temperature between the starting temperature and the maximum temperature is as high as that The temperature rise speed before reaching the maximum temperature, the temperature rise speed before the intermediate temperature is set to be small.

Compared with the temperature rise rate between the intermediate temperature and the maximum temperature, the temperature rise rate before the intermediate temperature is set to be smaller. At the intermediate temperature, the temperature of the underlying semiconductor and the above heterogeneous semiconductor layer are temporarily consistent, so that the subsequent temperature The thermal stress during ascent is suppressed.

[Implementation Type of Invention]

The method of manufacturing a semiconductor device related to the present invention is to temporarily hold the substrate at an intermediate temperature between the starting temperature and the maximum temperature when heat-treating a substrate with a semiconductor layer different from the underlying semiconductor on the underlying semiconductor by light irradiation temperature.

The intermediate temperature at which the substrate temperature is maintained is the temperature at which there is no light absorption deviation between the dissimilar semiconductor layers. The intermediate temperature to maintain the substrate temperature can be set at 600°C~800°C, 700°C~800°C. If it is a high temperature exceeding 800°C, the temperature difference between the different semiconductor layers cannot be ignored, the thermal stress becomes large, and it is difficult to reduce the transfer of dislocations.

The method of manufacturing a semiconductor device related to the present invention is to heat a substrate having a semiconductor layer different from the underlying semiconductor type on the underlying semiconductor by light irradiation, from the intermediate temperature between the starting temperature and the maximum temperature to the maximum temperature. Set the temperature rise rate before the intermediate temperature to be smaller.

The intermediate temperature is the temperature at which no light absorption deviation occurs between the above-mentioned dissimilar semiconductor layers.

The intermediate temperature is set at 600°C to 800°C, 700°C to 800°C, and the temperature rise rate before the intermediate temperature can be set below 20°C/sec.

An example of the implementation type of the present invention will be described with reference to the drawings.

Fig. 1 is a schematic configuration diagram of a low-pressure CVD apparatus using this embodiment.

This low-pressure CVD apparatus 1 has a substrate 2 for vapor-phase growth of a semiconductor layer, such as a quartz chamber (the so-called reaction chamber) 3 for arranging semiconductor wafers, and a light irradiation heating means for heating the quartz chamber 3 to a desired temperature. In this example Among them are the heating means 5 having a plurality of infrared lamps (for example, halogen lamps) 4, and the conveying unit 6 that conveys the substrate 2 to the quartz chamber 3.

The quartz chamber 3 can be rotated by a motor 7, and a susceptor 8 is arranged on the surface to coat the SiC film with CVD. The reaction gas is supplied into the chamber 3 through the gas supply system 9, and is exhausted through the exhaust system 10. An internal purifier (not shown) is installed in the gas supply system 9. The transport unit 6 has a so-called cleaning chamber 12 of an exhaust system 13, and a gate valve 11 is provided at the connection portion of the quartz chamber 3 between the substrate transport side and the substrate transport side of the cleaning chamber 12.

Fig. 2 is a schematic composition diagram of a light irradiation heating device using this embodiment, that is, a lamp annealing device.

In this lamp annealing device 21, in addition to the substrate 201 that needs to be heat-treated in the peripheral 22, for example, a tube body (so-called heating furnace) 23 composed of quartz glass inserted into a semiconductor substrate (wafer) for growth of the heteroepitaxial layer In addition, a heating means 25 composed of a plurality of infrared lamps (for example, halogen lamps) 24 for irradiating light sandwiched between the quartz glass tube body 23 up and down is arranged. The quartz glass tube body 23 has high permeability to infrared rays. The upper and lower infrared lamps 24 are arranged opposite to the gold-plated inner wall surface of the peripheral 22.

The inserting side of the base body 201 of the quartz glass tube body 23 is opened and closed when the base body 201 is inserted and taken out, and a door 26 is installed, which keeps the inside of the quartz glass tube body 23 airtight when the quartz glass tube body 23 is sealed. Resin compression (O-ring) 27. The peripheral 22 has a water-cooled structure 29 and a gas inlet 30, for example, N ₂ Air or air-cooled structure.

The quartz glass tube body 23 is provided with a quartz truss 31 supporting the base body 201. The base body 201 is horizontally supported by the front end portions of the two quartz pins 32 and the contact thermocouple 33 protruding from the quartz truss 31. The temperature measuring part (alloy part) of the thermocouple 33 is covered with SiC with superior thermal conductivity. Thereby, the heat conduction of the base 201 is improved, and the reduction of the surface area for direct absorption of light is suppressed as much as possible, and the thermal responsiveness is improved to form a structure with a small heat capacity. In addition, the wires outside the temperature measuring part (alloy part) are covered by quartz with good infrared penetration. The coating material other than the temperature measuring part has a structure that suppresses direct light absorption as much as possible. The substrate temperature measured by the contact thermocouple 33 is used to control the substrate temperature by the closed loop feedback when the infrared lamp 24 is output.

During the heat treatment, it should be noted that the atmospheric gas is supplied from the gas inlet 36 at one end of the quartz glass tube body 23, and discharged from the gas outlet 37 at the other end. 34 is a pyrometer for measuring the temperature of the infrared lamp 24, and 35 is a guard ring arranged on the quartz glass tube body 23.

A semiconductor wafer such as a Si wafer is used on the substrate of this embodiment type. The low-pressure CVD device 1 of FIG. For example, the Si-Ge mixed crystal layer 15 is heteroepitaxially grown on the Si-Ge mixed crystal layer 15 (refer to FIG. 4). That is, transport the cleaned Si wafer 2 into the N ₂ In the cleaning chamber 12 for cleaning, after the cleaning chamber 12 is exhausted, the gate valve 11 is opened, and the Si wafer 2 is transported on the receiver 8 in the quartz chamber 3. In the quartz chamber 3, the Si-Ge mixed crystal is supplied to the reaction gas necessary for heteroepitaxial growth through the gas supply system 9, and a thicker Si-Ge mixed crystal layer 15 is heteroepitaxially grown on the Si wafer 2. Next, Si is supplied to the reaction gas necessary for heteroepitaxial growth, and the Si layer 16 is heteroepitaxially grown on the Si-Ge mixed crystal layer 15.

This Si wafer 2 has a heteroepitaxial growth layer grown on the semiconductor substrate (semiconductor wafer) 201 shown in FIG. 4 of the Si-Ge mixed crystal layer 15 and the Si layer 16. Dislocations (crystal defects) are generated on the Si-Ge mixed crystal layer 15. When the Si layer 16 is formed thinner, heteroepitaxial growth without defects can occur.

Next, the semiconductor substrate 201 is subjected to a heat treatment after the hetero-epitaxial growth using the lamp annealing device 21 of FIG. 2 to reduce the dislocation of the hetero-epitaxial layer 15.

Then, in this embodiment, when the semiconductor substrate 201 is subjected to lamp annealing, especially the temperature program is shown in FIG. 3, for example, as shown in FIG. 3A, when the temperature reaches the maximum temperature T ₄ Low temperature, which is the starting temperature T ₁ And reach the highest temperature T ₄ The required intermediate temperature T ₃ When setting the program steps, the semiconductor substrate 201 from the starting temperature T ₁ Heating to intermediate temperature T at a specific temperature rise rate ₃ After that, use the intermediate temperature T ₃ Temporarily maintain the temperature of the semiconductor substrate 201 for a specific time, and then heat it at a specific temperature rise rate until it reaches the maximum temperature T ₄ until. This intermediate temperature T ₃ It can be set to a temperature where the infrared absorption in the window range shown in FIG. 11 is almost the same as the wavelength range outside the window. When the hetero-epitaxial growth layer is grown on a silicon wafer, the above intermediate temperature T ₃ Set to 600°C~800°C, 700°C~800°C.

Maintain intermediate temperature T ₃ The time can be set when the temperature of the Si-Ge mixed crystal layer is stable at the intermediate temperature T ₃ More than the time, the so-called exceed the time when it starts to converge.

For example, when the lamp annealing is performed based on the temperature program in Figure 3A, the temperature of the semiconductor substrate can only be temporarily maintained for a specific time when the intermediate temperature T3 is reached. _， Therefore, the holding time is used to wait for the Si temperature rise which is slower than the Si-Ge temperature rise. That is, the intermediate temperature T at which the light absorption rate of Si and Si-Ge is the same ₃ When the temperature of the Si substrate 2, the Si layer 16 and the Si-Ge mixed crystal layer 15 are the same, the temperature rises the same after that, and the maximum temperature T can be suppressed ₄ The thermal stress at the time of the previous temperature rise. Therefore, the lattice deformation caused by thermal stress can be suppressed, and the dislocation transmission of the Si-Ge mixed crystal layer 15 can be reduced.

In this embodiment, the lamp annealing can be performed based on the temperature program of FIG. 3B.

That is, compared to the above intermediate temperature T ₃ The temperature rise rate until reaching the maximum temperature T4 can be changed from the starting temperature T ₁ To intermediate temperature T ₃ The temperature rise rate up to this point is set to be small, and the semiconductor substrate 201 is set from the starting temperature T ₁ Slowly heat to intermediate temperature T ₃ , And then heated to the maximum temperature T at a general temperature rise rate ₄ until. Starting temperature T ₁ To intermediate temperature T ₃ It is better to set the temperature rise rate up to 20°C/sec or less.

In addition, in this embodiment, the lamp annealing can also be performed based on the temperature program shown in FIG. 3C.

That is, from the starting temperature T ₁ To the above intermediate temperature (that is, the second intermediate temperature) T ₃ Low temperature first intermediate temperature T ₂ The temperature rise rate up to this point is lower than the above-mentioned intermediate temperature (second intermediate temperature) T ₃ With the temperature rise rate until the maximum temperature T4 is reached, the first intermediate temperature T ₂ To the above-mentioned intermediate temperature (that is, the second intermediate temperature) T ₃ The temperature rise rate up to this point is set to be smaller. Then, the semiconductor substrate 201 is reduced from the starting temperature T at a general temperature rise rate ₁ Heat to the first intermediate temperature T ₂ , From the first intermediate temperature T ₂ To the second intermediate temperature T ₃ It is heated slowly, and then heated to the maximum temperature T at a general temperature rise rate ₄ until. This first intermediate temperature T ₂ To the second intermediate temperature T ₃ It is better to set the temperature rise rate up to 20°C/sec or less.

When the lamp annealing is performed based on the temperature program of Fig. 3B and Fig. 3C, as illustrated in Fig. 3A, when the intermediate temperature T is reached ₃ During the stage, the temperature of the Si substrate 2, the Si layer 16 and the Si-Ge mixed crystal layer 15 are the same, and then the maximum temperature T can be suppressed ₄ The thermal stress during the previous temperature rise reduces the dislocation transfer of the Si-Ge mixed crystal layer 15.

Then, explain specific examples.

FIG. 5 shows an example of the gas introduction and temperature program of the low-pressure CVD apparatus 1. In this example, a semiconductor wafer such as a Si(100)CZp type wafer is used as the substrate 2. As shown in Figure 6, this semiconductor wafer is cleaned with HF, for example, NH ₄ OH/H ₂ O ₂ /H ₂ O, solution and HClH ₂ O ₂ /H ₂ After the O solution is cleaned, a thermal oxide film is grown on the main surface of the semiconductor wafer to a specific film thickness, for example, 200 nm. After that, the required photoresist pattern is formed on the thermal oxide film, and the thermal oxide film at the opening of the photoresist is removed by HF treatment to produce a sample wafer with many thermal oxide films with a square pattern of 105μm×105μm. 2 (Refer to Figure 6A).

For this sample wafer 2, clean it with HF, NH ₄ OH/H ₂ O ₂ /H ₂ O solution and HClH ₂ O ₂ /H ₂ O solution cleaning, and then HF (0.5%) cleaning and pure water cleaning and drying before the sample wafer is transported to the low-pressure CVD device 1. Use a rotary dryer when drying.

Then, the sample wafer 2 is transported to the low-pressure CVD apparatus 1 of FIG. 2. Send to N at the beginning of wafer 2 transfer ₂ After the cleaning chamber 12 has been cleaned, the gate valve 11 after exhausting the cleaning chamber 12 is opened, and the wafer 2 is transported to the receiver 8 in the quartz chamber (reaction chamber) 3. The inside of the quartz chamber 3 is evacuated to a required vacuum degree, for example, 80 Torr.

The wafer 2 is heated by the infrared lamp 4.

After the wafer 2 is transported into the quartz chamber 3, in order to remove the natural oxide film formed during pure water cleaning and transport in the atmosphere, the H ₂ bake. Carrier gas (H ₂ ) Supply 20slm. Secondly, the required temperature is set at, for example, 685°C or 700°C, and the SiH ₄ The gas is used as a buffer layer to grow the Si layer 42 at a required flow rate, for example, 50 sccm, and a specific film thickness, for example, about 15 nm (refer to FIG. 6B). Control SiH afterwards ₄ , B ₂ H ₆ , GeH ₄ The gas flow rate makes the maximum concentration of boron become 1×10 ¹⁹ atomscm ² , Ge concentration becomes 15%, for example, 20sccm of SiH is supplied ₄ ,1~8sccm of B ₂ H ₆ ,GeH of 30~50sccm ₄ , The temperature is set at, for example, 610°C or 650°C, and the Si-Ge layer 43 is grown to a desired film thickness, such as about 100nm (refer to FIG. 6C). After that, the Si layer (the upper cap layer) 44 that originally formed the emitter is deposited to, for example, 80 nm. At this time, set the temperature at, for example, 640°C or 670°C, and supply 100sccm of SiH ₄ , 0.9sccm of B ₂ H ₆ . In this way, the sample matrix 201 as shown in FIG. 6D can be obtained.

7 is the SIMS boron (B) and germanium (Ge) concentration data of the sample substrate 201 where the capping layer 44/Si-Ge layer 43/buffer layer 41 is grown.

In addition, the dislocation generation density during heteroepitaxial growth strongly depends on the growth temperature of the capping layer 44/Si-Ge layer 43/buffer layer 42.

Next, in order to confirm that the dislocation transfer caused by the annealing process using lamp annealing is different, the lamp annealing device 21 shown in FIG. 2 is used to perform heating treatment. In this example, the annealing treatment of the sample base 201 (refer to FIG. 6D) is performed by using the two procedures shown in FIG. 8 and FIG. 9. Supply 2s1m of N ₂ The gas is inside the quartz glass tube body 23. The evaluation level is shown in Table 1.

The lamp annealing process in Figure 9 is for example 2slm N ₂ Gas becomes N in the quartz glass tube body 23 ₂ Atmosphere, the heat treatment start temperature T ₁ Set at about 200°C, the sample substrate 201 is transported into the quartz glass tube body 23. After a certain time has passed, the temperature rises at a rate of 50°C/sec from the temperature T ₁ Warm up to the highest temperature T ₄ Keep it for about 10sec until the temperature reaches 1000°C, and then decrease the temperature to T at a temperature drop rate of 50°C/sec ₅ ,500°C, keep the temperature T for the necessary time ₅ After the heat treatment is completed, the sample base 201 is transported out. The program starts at temperature T ₁ To reach the highest temperature T ₄ There is no stage annealing procedure.

The lamp annealing process in FIG. 8 is to supply the atmosphere in the quartz glass tube body 23, for example, to N of about 2 slm. ₂ The gas becomes the atmosphere, and the heat treatment start temperature T ₁ Set at about 200°C, the sample substrate 201 is transported into the quartz glass tube body 23 and the temperature T ₁ Raise the temperature to the intermediate temperature T at a temperature rise rate of 50°C/sec ₃ , 750°C degree and keep 10sec degree, then with the temperature rising speed 50°C/sec from the intermediate temperature T ₃ Warm up to T ₄ , Hold for 10sec at 1000°C, then cool down to T at a temperature drop rate of 50°C/sec ₅ ,500°C degree, keep temperature T for a specific time ₅ After the heat treatment is completed, the sample base 201 is transported out. The program starts at temperature T ₁ To reach the highest temperature T ₄ In between is a staged annealing procedure.

<tables><img file="TW511129B_D0001.tif" /></tables>

<tables><img file="TW511129B_D0002.tif" /></tables>

For the sample substrate 201 in Table 1, the crystalline defects were selectively etched by the etching method of a mixture of hydrofluoric acid: nitric acid (61% concentration): acetic acid: water=1:15:3:1 and observed under a microscope. The number of patterns with dislocations in the 105μm×105μm square pattern at 1300 positions in the longitudinal and lateral directions of the sample matrix was calculated separately, and the dislocation generation at the growth temperature and the dislocation transfer during the subsequent annealing treatment were investigated.

The evaluation results are summarized in Table 2 and Figure 10. The yield (Yield) shown here is the ratio of square patterns without dislocation in the observed square pattern at 1300 (the number of patterns without dislocation × 100/1300).

<tables><img file="TW511129B_D0003.tif" /></tables>

From the results in Table 2 and Figure 10, it can be seen that the amount of dislocation produced by the lamp annealing process after the heteroepitaxial growth is different. For example, when the process in Figure 8 is set with steps of about 750°C and 10sec, it does not greatly depend on the growth temperature of the heteroepitaxial layer, and only slightly increases the dislocation. However, the process of Figure 9 without a stage produces significant Dislocation increases.

In addition, Table 2 does not show that the lower growth temperature of the hetero-epitaxial layer has less dislocation after growth.

In this way, when the temperature of the substrate 201 reaches about 750° C. during the lamp annealing heat treatment, the amount of dislocation can be suppressed by temporarily maintaining the temperature of the substrate 201 for a required time (for example, 10 sec). This is because when the temperature is lower than 600°C, there is a difference in light absorption between the Si-Ge layer and the Si layer, so the temperature rise rate is different between the Si-Ge layer and the Si layer, resulting in thermal stress caused by the difference in thermal expansion coefficient.

Therefore, when the wafer is heated to about 1000°C in one go without providing a step-by-step process, the lattice deformation caused by the thermal stress is relaxed, and a significant dislocation occurs. In contrast, in the temperature range of 750°C or higher, the Si-Ge layer absorbs light similarly to the Si layer. Therefore, the wafer can be maintained at a temperature of about 750°C, and the temperature is the same at one time while suppressing the subsequent temperature rise. Thermal Stress.

In fact, it is evaluated under keeping the temperature of 600°C~800°C, but the occurrence of dislocation in this temperature range is the same as that at 750°C. Furthermore, the same effect can be obtained when the temperature rise rate of the intermediate temperature between 600°C and 800°C is set below 20°C/sec (equivalent to the procedures in Figure 3B and Figure 3C).

In the above example, although the present invention is generally applied to the SiGe series of IV-IV group compounds on the silicon substrate and the lamp annealing treatment of the semiconductor substrate after the Si heteroepitaxial growth thereon, the other forms IV-IV group on the silicon substrate. The semiconductor substrate lamp annealing treatment of the compound SiGe-based heteroepitaxial layer, and the use of GaAS and other group III-IV compound semiconductors for heteroepitaxial growth (including when heteroepitaxial growth is made on a semi-insulating compound semiconductor substrate), etc. It is also applicable to the lamp annealing treatment of semiconductor substrates after various heteroepitaxial growth.

[Effects of the invention]

According to the present invention, during light irradiation heat treatment of a substrate of a so-called heteroepitaxial growth layer on a heterogeneous semiconductor layer on the underlying semiconductor, the relaxation of lattice deformation caused by thermal stress is suppressed, and the dislocation of the heteroepitaxial layer can be prevented from being transferred.

Therefore, it is possible to manufacture hetero-epitaxial junction transistors and other hetero-junction devices with few defects and high yield.

Schematic description

Fig. 1 is a schematic diagram of a low-pressure CVD apparatus using this embodiment.

Figure 2 is a schematic diagram of the lamp annealing device using this embodiment.

Fig. 3A is a temperature program showing the first example of lamp annealing treatment related to this embodiment. The B series temperature program represents the second example of lamp annealing treatment related to this embodiment. The C series temperature program represents the third example of lamp annealing treatment related to this embodiment.

FIG. 4 is a cross-sectional view illustrating an example of using a semiconductor substrate in this embodiment mode.

Figure 5 shows the temperature program and gas program of the low-pressure CVD device used in this embodiment.

6A~D are the manufacturing engineering drawings of the sample substrate with the heteroepitaxial layer related to this embodiment.

FIG. 7 is a graph showing the concentration distribution of boron (B) and germanium (Ge) in the sample matrix of this embodiment.

Fig. 8 is a temperature program showing a specific example of lamp annealing treatment related to this embodiment.

Fig. 9 is a temperature program showing a specific example of lamp annealing treatment related to the comparative example.

Figure 10 is a graph of the evaluation results of this implementation type.

Fig. 11 is a graph showing the wavelength dependence of Si emissivity.

Symbol description of main components

1. . . Low-pressure CVD device

2. . . Semiconductor wafer

3. . . Quartz Chamber

twenty one. . . Lamp annealing device

twenty three. . . Quartz glass tube body

twenty four. . . Infrared light

25. . . Heating means

201. . . Semiconductor substrate