Semiconductor device

Semiconductor device

<p>WL. . . Character line</p><p>SWD. . . Secondary character drive</p><p>DL. . . Data line</p><p>SA. . . Sense amplifier</p><p>MC. . . Memory grid</p><p>ACT. . . Active area of MOS transistor</p><p>SNCT. . . Storage node contacts</p><p>DLCT. . . Data line contact</p><p>TG. . . Choose Transistor</p><p>CS. . . Unit capacitor</p><p>PL. . . Screen pole</p><p>SN. . . Lower electrode of unit capacitor</p><p> MWLB. . . Main character line _㊣</p><p>FX. . . Sub-character driver selection line</p><p>SHR. . . Total SA selection line</p><p>CSP. . . PMOS common source</p><p>CSN. . . NMOS common source</p><p>BLEQ. . . Data line compensation line</p><p>VBLR. . . Data line reference power</p><p>SIO, SIOB. . . Vice IO line</p><p>M2, M3. . . Wiring layer</p>

Fig. 1 shows the layout and circuit diagram of the first word line noise reduction array of the present invention.

Figure 2 is a diagram showing the structure of a DRAM wafer.

FIG. 3 is a circuit diagram showing the first sub-character driver used in the character line noise reduction array of the present invention.

Figure 4 shows the noise reduction principle of the first word line noise reduction array of the present invention.

Fig. 5 shows the layout and circuit diagram of the second word line noise reduction array of the present invention.

Fig. 6 shows the layout and circuit diagram of the third word line noise reduction array of the present invention.

FIG. 7 is a layout and circuit diagram showing the fourth word line noise reduction array of the present invention.

FIG. 8 is a circuit diagram showing the second sub-character driver used in the character line noise reduction array of the present invention.

Figure 9 shows the circuit of the third sub-character driver used in the character line noise reduction array of the present invention.

Figure 10 shows the layout and circuit diagram of the DRAM memory array after the case has been reviewed in advance.

Fig. 11 is an enlarged view showing the layout and circuit diagram of the memory cell in Fig. 10.

Fig. 12 is a cross-sectional view showing the main part of the memory of the memory array of Fig. 11

FIG. 13 is a diagram showing the principle of generating word line noise in the memory array of FIG. 10.

Fig. 14 is a circuit diagram and operation waveforms of the sense amplifier of the memory array shown in Fig. 10.

[Technical Field of Invention]

The present invention relates to noise reduction of a memory array of a semiconductor device containing a memory array.

[Technology of learning]

The documents referenced in this manual are as follows.

[Document 1]: Ultra LSI memory pp.214-217, by Kiyoo Ito, Peifukan, first edition issued on November 5, 1994.

[Document 2]: K. Itoh, IEEE Journal of Solid State Circuit. Vol. 25, No. 3, (1990), pp.778-789.

[Document 2] is the original document cited in [Document 1].

[Document 1] describes the noise intervening in the word line when dynamic random access memory DRAM is amplified. In addition, it records the situation that the noise voltage on the non-selected character line caused by the combined capacity of the data line and the character line causes noise in the data pair line. The influence of this noise is dependent on the data-to-line structure (open data-to-line structure, or foldback data-to-line structure), and the data line pre-charging method (VD pre-charging method, or VD2 pre-charging method). As a result, this noise will be reduced if it is the foldback data alignment structure and the VD/2 pre-charge method.

[Problems to be solved by the invention]

The inventors conducted a detailed review of the relationship between the structure of the 1Gb DRAM array and the noise caused by the combined capacity of the data line and the word line using the ultrafine processing technology of 0.16~0.13μm in this case. FIG. 10 shows a part of the planar layout of the DRAM array and the corresponding circuit diagram that have been reviewed before in this case. Among them, in the planar layout of Figure (a), a memory cell (MC) is arranged at the predetermined intersection of the data line (DL) and the word line (WL). This data line structure is a so-called reentrant data line structure. Here, only the DL that reads the signal from the memory cell is displayed, the WL that forms the gate of the selective transistor, the diffusion layer area (ACT), the data line contact (DLCT) connecting ACT and DL, and the connection between ACT and capacitor The storage node contact (SNCT) of the lower electrode, and the lower electrode of the capacitor connected to the SNCT is omitted. In addition, upper and lower sub-character driver rows (SWDA-U) and lower sub-character driver rows (SWDA-D) are arranged above and below the memory array, and two character lines WL are alternately connected to the upper and lower sub characters. Meta drive column. The sub-character driver is referred to as SWD for short to meet the requirements below. In addition, the left and right sense amplifier rows (SAA-L) and the right sense amplifier rows (SAA-R) are arranged on the left and right sides of the memory array, and two data lines DL are alternately connected to the left and right sensor rows. As required below, the abbreviated sense amplifier is SWD.

The reason why SWA and SA are alternately configured in this way is to ease the layout spacing between SWA and SA. For example, from the perspective of SWDA-U and the memory array, WL will form those who pass through the boundary and enter SWD (WL1, WL2, WL5, WL6) and those who end in the boundary (WL0, WL3, WL4, WL7) ) Two duplicates of each. If WL and SWD are connected in this way, the layout pitch in the data line direction of one SWD can be reduced to a pitch of two WLs. The same layout of the'SA' is also an alternate arrangement, and by this, the pitch in the direction of the character line is relaxed to a pitch of 2 pairs of DL (4 DL). In the case of DRAM, the spacing between WL and DL is very small due to the miniaturization of memory cells. Therefore, it is not easy to lay out SWD and SA with a predetermined pitch, so interactive configuration is extremely important.

Here, if you focus on the connection relationship between the WL and SWD columns, that is, if you focus on the two adjacent memory cells (MCO and MC1) connected to DLOT, these memory cells will have a total of 1 DLCT, but in WL (WL0, WL1) connected to these memory cells will be connected to SWDA-U. On the other hand, if you focus on two adjacent cells (MC2 and MC3) connected to DLOB, these cells will also have a total of 1 DLCT, but in the WL (WL2, WL3) connected to these cells ) Will be connected to SWDA-D. Therefore, in the layout of the memory array in FIG. 10, the WLs connected to the two memory cells sharing the DLCT will be connected to the same SWD row. Also, if the memory array is viewed as a whole, since the pattern shown in Fig. 10(a) is repeated vertically and horizontally, it is connected to the WL (WLO, WL1, WL4 in the figure) of MC (the MC is connected to DLOT) WL5) will all be connected to SWDA-U, and WL (WL2, WL3, WL6, WL7 in the figure) connected to MC (the MC is connected to DLOB) will all be connected to SWDA-D. Therefore, the character lines connected to the memory cell (the memory cell is connected to one data line) will all be connected to the sub-character driver row in the same row.

If it is displayed as a circuit diagram, it is shown in Figure 10(b). In the composition of the return data line, half of the intersections of the data line and the character line are connected to the memory cell. For example, the memory cell MC0 is connected between DL0T and WL0, but MC is not connected between DL0B and WL0. MC is composed of selective transistor, TG and unit capacitor CS. One electrode of CS is the screen PL, which is commonly connected with other memory cells in the array. The other electrode of CS is connected to one of the source or drain of TG, and the other source or drain of TG is connected to DL. DL0T and DL0B are a pair of SA0 connected in SA column L, and DL1T and DL1B are a pair of SA1 connected in SA column R. These SAs amplify the small and medium voltage difference generated in the DL pair based on the signal from the memory cell, that is, amplify the DL of one side to a high-level voltage, and amplify the DL of the other side to a low-level voltage.

Next, expand the parts of MC0, MC1, MC2, and MC3 in FIG. 10 to show the layout in FIG. 11(a) and the circuit diagram in FIG. 11(b). It also shows the parasitic capacitance generated between the WL and DL of these MCs. Parasitic capacitances C00 and C01 are generated between WL0, WL1 and DL0T, respectively. Parasitic capacitances C00B and C01B are generated between WL0, WL1 and DL0B, respectively. Parasitic capacitances C02 and C03 are generated between WL2, WL3 and DL0B, respectively. Parasitic capacitances C02B and C03B are generated between WL2, WL3 and DL0T, respectively.

Here, the cross-sections A-A', B-B', and C-C' of the parts indicated by the arrows in the layout of Fig. 11(a) are shown in Figs. 12(a), (b), (c) )middle. The cross-sectional view of FIG. 12 shows a cross-section near the two character lines WL0 and WL1 in the arrow direction shown in FIG. 11(a). The ACT area on the substrate is the active area of the MOS transistor, and the other part is the component separation area. In addition, WL, DL, and DL are configured on the top to connect with ACT through elliptical DLCT. SN is the lower electrode of the cell capacitor CS, and is connected to ACT through SNCT. In addition, the upper electrode PL of the CS is commonly connected to the cells in the array, and two layers of metal wiring M2 and M3 are arranged on the upper part.

Here, compare the sizes of C00 and C00B. As shown in the cross-sectional view AA' of Fig. 12(a), DLCT0 connected to DLOT will pass very close to between WL0 and WL1. The distance between DLCT0 and WL0 is about 30mm when the memory cell is made by fine processing of 0.13μm. Therefore, the capacitance between DL0T-WL0 (C00) is almost determined by the part between DLCT0-WL0. On the other hand, as shown in the cross-sectional view B-B' of Figure 12(b), DL0B will only pass through the upper part of WL0. The capacitance between DL0B-WL0 (C00B) is determined by the distance between DL and WL, which is 0.13μm It is about 250mm under micro processing. Therefore, C00B is very small compared with C00. According to the detailed capacitance simulation results, if C00 is 100%, then C00B is about 1%. That is, as shown in Figure 11(b), in the structure of the foldback data line, the coupling capacitance of WL0 of DL0T and DL0B seems to have a balance between C00 and C00B at a glance, but in a highly integrated DRAM using micro-memory grids , C00 will form very large, and produce non-equilibrium. Similarly, C01, C02, and C03 are very large for C01B, C02B, and C03B. In other words, the DL-WL coupling capacitor will appear larger when there is MC between DL and WL, and its existence can be almost ignored when there is no MC.

The imbalance of the DL-WL coupling capacitance is due to the high integration of DRAM, which results in the thinning of the thickness of the insulating film in the direction parallel to the substrate (for the interlayer insulating film in the direction perpendicular to the substrate). Lead to new problems. Therefore, as described below, in such an array substrate with unbalanced DL-WL coupling capacitors, WL noise will cause problems.

FIG. 13 shows a data pattern when the memory array and word line noise of FIG. 10 are formed at the maximum. WL0~WL7 are respectively connected to SWD0~SWD7, and SWD0, SWD1, SWD4, SWD5 are configured in SWDA-U, and SWD2, SWD3, SWD6, SWD7 are configured in SWDA-D. In addition, DL0T and DL0B are connected to SAO in SA column L, and DL1T and DL1B are connected to SA1 in SA column R. Here, the circuit diagram of SA is shown in FIG. 14(a), and the operation waveform of the array is shown in FIG. 14(b).

In FIG. 13, considering that WL0 is selected, WLs other than WL0 in the array will be connected to VSSU or VSSD through the N-channel MOS transistor in the SWD, respectively. As shown in Figure 14(b), all SWDs will output 0V in WL during standby. Secondly, in MC, the selected transistor will form an OFF state, and the voltage of VDL (for example, 1.8V) or VSS (for example, 0V) will be written in the capacitor according to the information. In SA, SHRU and SHRD will form VPP (such as 3.5V), CSP, CSN will form VBLR (such as 0.9V), BLEQ will form VPP, YS will form 0V, and DL will be charged to the potential of VBLR.

When the active command and address of the memory are input into the DRAM to select the memory array in the figure, in SAO, SHRL and BLEQ will drop to 0V, and the pre-charging will be interrupted. Then, in SWD0, WL0 will be activated. In this way, the selective transistor connected to the MC of WL0 will be in the ON state, and the signal will come out of the unit capacitor in DL0, DL1, etc., which are precharged to 0.9V. At this moment, for example, in 1024 pairs (2048) of DL, in addition to DLnT, a low level (L) signal appears in all DLs on the T side from DL0T to DL1023T, and only high level (L) signals appear in DLnT. H) signal. At this moment, since there is no signal from the other party's DL to DL1023B, it maintains 0.9V. This mode or the mode in which the H and L are reversed is the worst-case condition when the WL noise is at its maximum. Then, if the CSN is driven to 0V and the CSP is driven to 1.8V to activate SA, that is, from DL0T to DL1023T other than DLnT will be amplified to 0V, and from DL0B to DL1023B other than DLnB will be amplified to 1.8V.

Here, this situation is shown in FIG. 13. In the figure, at the low level (L) on DL0T and DL1T, DL0T and DL1T will be amplified to OV, and at the high level (H) on DLOB and DL1B, DLOB and DL1B will be amplified to 1.8V. At this moment, the noise generated in the WLO will form the following general. WLO will receive the negative noise from the data line from DLOT except DLnT to DL1023T through the coupling capacitor. On the other hand, WLO will receive positive noise from the data line from DLOB other than DLnB to DL1023B through the coupling capacitor. Although the noise generated in the WLO will form the sum of all the noises, as mentioned above, since the WLO is connected to the MC (the MC is connected to the DL on the T side from DLOT to DL1023T), for example, in WLO-DLOB The coupling capacitance between WLO and DLOT is about 1% of the coupling capacitance between WLO and DLOT. That is, the coupling capacitance between the WLO and the data line on the B side is small enough to ignore its existence compared to the coupling capacitance between the WLO and the data line on the T side. Therefore, in WLO, negative noise is almost never canceled and generated. Here, it is represented by the negative (-) sign on WLO. Similarly, negative noise will be generated in WL1, WL4, and WL5. Conversely, since WL2, WL3, WL6, and WL7 are connected to MC (the MC is connected to the DL on the B side from DLOB to DL1023B), for example, the coupling capacitance between WL2-DLOT is higher than that between WL2-DLOB The coupling capacitance is small, about 1%. That is, the coupling capacitance between WL2 and the data line on the T side is small enough to ignore the existence of the coupling capacitance between WL2 and the data line on the B side. Therefore, positive noise will be generated in these WLs, which is represented by the positive (+) sign on the WL. The waveform in Fig. 14(b) also shows the WL noise to WLO, WL1, WL2.

Here, the noise generated in the WL flows into the VSS wired on the SWD through the N-channel MOS transistor in the SWD. Since the VSS wiring is formed on the SWD from the power pad in the center of the chip to the chip end in the DRAM, the impedance is high. In this way, the noise generated in the word line will remain in the VSS on the SWD.

If the WL noise comes from the entire WL of the array, positive noise will be generated in half of the WL, and negative noise will be generated in the remaining half of the WL. SWD, therefore, negative noise will be generated in all WLs connected to SWDA-U, and positive noise will be generated in all WLs connected to SWDA-D. Therefore, the negative noise generated in the VSS wiring (VSSU) on SWDA-U will act in the mutually reinforcing direction, and the positive noise generated in the VSS wiring (VSSD) on SWDA-D will be Act in the direction of mutual enhancement, and cause these noises to become very large. According to the detailed circuit simulation results, it can be known that they will form 100mV respectively. In addition, since the noise generated in the WL will not be cancelled until it reaches the power pad in the center of the chip, the decay time is long.

The WL noise during the DL amplification will return to the DL through the coupling capacitor between WL and DL again, resulting in malfunction. As shown in Figure 13, when the H-level signal is only output on DLnT, the negative noise from WL0, WL1, WL4, WL5, etc. will return to the DLnT. Also, the positive noise from WL2, WL3, WL6, WL7, etc. will return to the DLnB. That is, from the DLn pair, the noise that is in the opposite direction to the original signal will come back, and the amount of signal will be reduced. If the charge in the cell capacitor of the memory cell at the intersection of WLO and DLnT is reduced due to leakage, etc., when WLO is activated, the H-level signal from DLnT will decrease, and the data will be corrupted by WL during amplification. Information and form an antiphase. This situation is shown in Figure 14. When the WL is activated, DLnT and DLnB will be amplified in the opposite direction to the tiny potential difference generated in DLnT and DLnB, causing data to be read incorrectly.

That is, in the case of the memory array of FIG. 10 reviewed previously in this case, in the worst case, since the word line WL noise will act in the direction of mutual enhancement in the sense amplifier driver SWD, WL noise will become bigger. This will degrade the signal read by the sense amplifier, thus causing the memory to be unstable.

Therefore, the object of the present invention is to provide a highly reliable memory array in a highly integrated DRAM pursuing microfabrication, which can reduce the noise generated in the word line when the data line is enlarged.

[Means to solve the problem]

The representative means of the present invention are as follows. A plurality of character lines connected to a plurality of memory cells (the plurality of memory cells are connected to a data line) can be connected to the sub-character drive row (the sub-character drive row) at intervals of one or more It is arranged on the opposite side of the memory array). If such a configuration is formed, in addition to the above-mentioned set of noticeable data line pairs, in the worst-case mode of so-called character line noise in which data of other data line pairs are read out opposite to all the noticed data line pairs, Since half of the character lines connected to the sub-character drive row (the sub-character drive row is arranged on one side of the memory array) will receive positive noise, the remaining half will receive negative noise. Therefore, these word line noises will cancel each other out and reduce the ground power wiring in the sub-character driver row. Similarly, in the row of sub-character drivers arranged on the other side of the memory array, since the connected half-digital lines will receive positive noise, the remaining half will receive negative noise, so these characters The cell line noise will cancel each other out and reduce the ground power wiring in the sub-character driver column.

[Implementation of the invention]

The following uses the drawings to describe the embodiments of the present invention in detail. The circuit elements constituting each block of the embodiment are not particularly limited, and can be formed on a single semiconductor substrate such as single crystal silicon by using integrated circuit technology such as known CMOS (Complementary MOS Transistor). MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is an N-type MOSFET (NMOS) without an arrow, and a P-type MOSFET (PMOS) with an arrow. However, in Figures 3, 8, and 9, in order to clearly distinguish between NMOS and PMOS, an arrow opposite to PMOS is added to NMOS. Hereinafter, MOSFET may also be referred to as MOS for short. However, the present invention is not limited to a field effect transistor including an oxide insulating film provided between a metal gate and a semiconductor layer, and can also be applied to circuits using general FETs such as MISFET (Metal Insulator Semiconductor Field Effect Transistor).

(Example 1)

FIG. 1 shows a part of the planar layout and corresponding circuit diagram of the first word line noise reduction array of the present invention. In the planar layout of Figure (a), a memory cell (MC) is arranged at the predetermined intersection of the data line (DL) and the character line (WL). Here, only the DL that reads the signal from the memory cell is displayed, the WL that forms the gate of the selective transistor, the diffusion layer area (ACT), the data line contact (DLCT) connecting ACT and DL, and the connection between ACT and capacitor The storage node contact (SNCT) of the lower heavy pole, and the lower electrode of the capacitor connected to the SNCT is omitted. Originally in an array, for example, the number of DL is about 2048, and the number of WL is about 512, but only a part of it is shown here. In addition, upper and lower sub-character driver rows SWDA-U and lower sub-character driver rows SWDA-D are arranged above and below the memory array, and two character lines WL are alternately connected to the upper and lower sub-character driver rows. In addition, the left and right sense amplifier rows SAA-L and the right sense amplifier rows SAA-R are arranged on the left and right sides of the memory array, and two data lines DL are alternately connected to the left and right sensor rows.

So it will configure SWA and SA interactively, that is to ease the layout space between SWA and SA. For example, from the perspective of SWDA-U and the memory array, WL will form those who pass through the boundary and enter SWD (WL1, WL2, WL5, WL6) and those who end in the boundary (WL0, WL3, WL4, WL7) ) Two duplicates of each. If WL and SWD are connected in this way, the layout pitch in the data line direction of one SWD can be reduced to a pitch of two WLs. In addition, when patterning the WL, although super-resolution photolithography imaging methods such as phase shifting or tyre illumination are required, if two connected WLs are connected to the SWD, the phase of the light can be connected to the SWD. Two WLs in reverse phase make the layout of SWD easy.

Similarly, the layout of the SA is also alternately arranged, whereby the pitch in the direction of the character line is relaxed to the pitch of 2 pairs of DL (4 DL). In the case of DRAM, the spacing between WL and DL is very small due to the miniaturization of memory cells. Therefore, it is not easy to lay out SWD and SA with a predetermined pitch, so interactive configuration is extremely important.

Here, if we focus on the connection relationship between the WL and the SWD column, the present invention has a specialty in the connection relationship between the SWD column and the WL after the alternate arrangement. That is, if you focus on two adjacent memory cells (MC0 and MC1) connected to DLOT, these MCs will have a total of 1 DLCT, but among the WLs connected to these memory cells, WL0 is connected to SWDA -U, in contrast, WL1 is connected to SWDA-D. On the other hand, if you focus on two adjacent memory cells (MC2 and MC3) connected to DLOB, these MCs will also have a total of 1 DLCT, but in the WL connected to these memory cells, WL2 is connected In SWDA-U, on the other hand, WL3 is connected to SWDA-D. Therefore, in the layout of the word line noise reduction array of the first embodiment, the WLs of the two memory cells connected to the shared DLCT are connected to different SWD rows.

In this example, if we look at the entire memory array, because the pattern shown in Figure 1(a) is repeated vertically and horizontally, half of the WL connected to the MC (the MC is connected to the DLOT) (Figure 1) Middle WL1, WL5) are connected to SWDA-U, and the remaining half (WL0, WL4 in the figure) are connected to SWDA-D. Also, half of the WLs connected to the MC (the MC is connected to DLOB) (WL2 and WL6 in the figure) are connected to SWDA-U, and the remaining half (WL3 and WL7 in the figure) are connected to SWDA-D . Therefore, in the character line connected to the cell (the cell is connected to a data line), half of the character line will be connected to the sub-character drive row of one row, and the remaining half will be connected to the other The auxiliary character drive column of the column. In addition, the SWD in the SWDA-U is connected to the common VSS wiring VSSU. Similarly, the SWD in SWDA-D is connected to the common VSS wiring VSSD. If the VSS is wired in this way, the WL noise can be canceled in the VSS.

If it is displayed as a circuit diagram, it is shown in Figure 1(b). In the composition of the return data line, half of the intersections of the data line and the character line are connected to the memory cell. For example, the memory cell MC0 is connected between DL0T and WL0, but MC is not connected between DL0B and WL0. MC is composed of selective transistor, TG and unit capacitor CS. One electrode of CS is the screen PL, which is commonly connected with other memory cells in the array. The other electrode of CS is connected to one of the source or drain of TG, and the other source or drain of TG is connected to DL. DL0T and DL0B are a pair of SA0 connected in SA column L, and DL1T and DL1B are a pair of SA1 connected in SA column R. These SAs amplify the small and medium voltage difference generated in the DL pair based on the signal from the memory cell, that is, amplify the DL of one side to a high-level voltage, and amplify the DL of the other side to a low-level voltage.

If it is connected in this way, it will be described later, that is, DL0T is amplified to a low level by SA0, and DL0B is amplified to a high level, although negative noise is added to WL0 and WL1. Positive noise is added to WL2 and WL3, but the positive and negative noise added to WL1 and WL2 on the power supply wiring (VSSU) on SWDA-U will be reduced. Similarly, the positive and negative noises attached to WL0 and WL3 on the power supply wiring (VSSD) on SWDA-D will be reduced. Since the WL noise from a pair of data lines in the memory array of the present invention is mutually reduced, no matter what data pattern is generated in the other data line pairs in the array, the noise cancellation effect will be produced.

The following describes the structure of a DRAM using an uninvented character line noise reduction array. Fig. 2 is a diagram showing the structure of a DRAM wafer. In the center of the wafer, bonding pads (PAD) and indirect peripheral circuits (PERI1, PERI2) are arranged in the longitudinal direction. Here, the address and data output and input circuit, power supply circuit, updated control circuit, main amplifier, etc. will be configured. In addition, an array control circuit (A-CTL) for controlling SWD or SA is arranged in the short-side direction. In addition, the chip is divided into 4 blocks according to the above-mentioned circuit and surrounded by a row decoder (R-DEC) connected to the main character line and a column decoder (C-DEC) connected to the column selection line Each block. The memory array (MA) shown in Figure 1 divides each block into a sense amplifier column (SAA) and a sub-character driver column (SWDA) according to the row direction and column direction, respectively, surrounded by the SA column and the SWD column Part.

FIG. 3 shows the first sub-character driver used in the character line noise reduction array of the present invention in FIG. 1. In this SWD, all SWDs in the same SWD column are connected to the common ground wiring VSSU. In addition, since SWD is alternately arranged on the memory array, from the perspective of SWDA-U and the boundary of the memory array, the WL (WL1, WL2, WL5, WL6) that enters the SWD through the boundary and ends in the boundary The WL (WL0, WL3, WL4, WL7) will be formed by repeating 2 each. The feature of the character line noise reduction array of the present invention is that WL(WL1, WL5) connected to MC (the MC is connected to DLOT in Fig. 1) and WL( WL2, WL6) half of them are connected to the SWD in SWDA-U.

If SWD1 is taken as an example, two N-channel MOS transistors MN1, MN2 and one P-channel MOS transistor MP1 are used to form one SWD. For MN1 and MN2, the source is connected to VSSU, and the drain is connected to WL1. Also, connect the gate of MN1 to the main character line (MWLB), and connect the gate of MN2 to FX1B. In addition, as shown in the figure on the substrate (back gate or well potential), MN1 and MN2 can also be connected to VSSU or to a VBB wiring provided separately. Regarding MP1, the source is connected to FX1, the drain is connected to WL1, and the gate is connected to MWLB. The substrate (back gate or well potential) of MP1 is connected to VPP (for example, 3.5V). In addition, the WL of the memory array arranged on the upper side of the SWDA-U and the WL of the memory grid array arranged on the lower side are connected to each other via the SWDA-U.

Here, we will explain the actions when MWLB and FX1 are activated and WL1 is selected. In this case, MWLB will form 0V, FX1 will form 3.5V, FX2, FX5 and FX6 will form 0V, FX1B will form 0V, and FX2B, FX5B and FX6B will form 3.5V. In SWD1, MP1 will be in the ON state, MN1 and MN2 will be in the OFF state, and WL1 will be activated at 3.5V. On the other hand, in SWD2, SWD5 and SWD6, the transistor corresponding to MN1 will be in the OFF state, the transistor corresponding to MN2 will be in the ON state, and WL2, WL5 and WL6 will be connected to VSSU (0V). In addition, although the gate of the transistor corresponding to MP1 is 0V, since the source is also 0V, the ON state is not formed. Therefore, the non-selected WL (WL2, WL5 and WL6) will only be connected to VSSU in the transistor equivalent to MN2.

For other WL1 operation modes, (1) MWLB, FX1 are all non-selection, (2) MWLB is non-selection, FX1 is selection; etc., in the case of (1), MNL and MN2 It will also be in the ON state and connected to VSSU. In the case of (2), only MN1 will be in the ON state and then connected to VSSU. It is the same in other SWDs.

Secondly, the word line noise reduction array related to the present invention is a WL noise reduction effect that represents the worst-case mode when the WL noise is formed at the maximum. As shown in Figure 4, in 1024 pairs (2048 lines) of DL, in addition to DLnT, low-level (L) signals appear in all DLs on the T side from DL0T to DL1023T, and only high-level signals appear in DLnT. Level (H) signal. This mode or the mode in which the H and L are reversed is the worst-case condition when the WL noise is at its maximum. If SA is activated, DL0T other than DLnT to DL1023T will be amplified to 0V, and DL0B other than DLnB to DL1023B will be amplified to 1.8V. In the figure, at the low level (L) on DL0T and DL1T, DL0T and DL1T will be amplified to 0V, and at the high level (H) on DL0B, DL1B, DL0B and DL1B will be amplified to 1.8V. At this moment, the noise generated in WLO will form the following general. WL0 will receive negative noise from the data line from DL0T other than DLnT to DL1023T through the coupling capacitor. On the other hand, WL0 receives positive noise from the data line from DL0B to DL1023B other than DLnB through the coupling capacitor. Although the noise generated in WL0 will form the sum of all noises, as mentioned above, since WL0 is connected to MC (the MC is connected to the DL on the T side from DL0T to DL1023T), for example, in WL0-DL0B The coupling capacitance between WL0 and DL0T is about 1% of the coupling capacitance between WL0 and DL0T. That is, the coupling capacitance between WLO and the data line on the B side is small enough to ignore its existence compared to the coupling capacitance between the WLO and the data line on the T side. Therefore, in WLO, negative noise is almost never canceled and generated. Here, it is represented by the negative (-) sign on WLO. Similarly, negative noise will be generated in WL1, WL4, and WL5. Conversely, since WL2, WL3, WL6, and WL7 are connected to MC (the MC is connected to the DL on the B side from DL0B to DL1023B), for example, the coupling capacitance between WL2 and DL0T is higher than that between WL2 and DL0B. The coupling capacitance is small, about 1%. That is, the coupling capacitance between WL2 and the data line on the T side is small enough to ignore the existence of the coupling capacitance between WL2 and the data line on the B side. Therefore, positive noise will be generated in these WLs, which is represented by the positive (+) sign on the WL.

As shown in FIG. 4, the character line noise reduction array of the present invention is different from the memory array previously reviewed in this case shown in FIG. 13, and negative noise will be generated in half of the WL connected to SWDA-U. , Produces positive noise in half of WL. Therefore, the positive and negative noise will be cancelled in the power supply wiring (VSSU) on SWDA-U, and the WL noise will be reduced. Similarly, negative noise will be generated in half of WL connected to SWDA-D, and positive noise will be generated in half of WL. Therefore, the positive and negative noise will be cancelled in the power supply wiring (VSSU) on SWDA-D, and the WL noise will be reduced.

In this way, in the character line noise reduction array of the present invention, no matter what form of signal appears on the data line, when the data line is amplified, the positive and negative character line noise will cancel each other out in the sub-character driver. It works in the direction of, so it can reduce the word line noise. Thereby, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

In addition, if we focus on the amount of signal from the memory cell, since even a signal smaller than that of the memory array with a poor balance of coupling capacity between the data line and the character line can be sensed accurately, the memory can be expanded. The range of action when the cell capacity is insufficient or the charge stored in the memory cell capacitor decreases due to leakage current.

In addition, in this array, in a pair of operating data lines, the coupling capacitance between one data line and one character line and the coupling capacitance between the other data line and the same character line have a large tolerance. Therefore, as shown in FIG. 1, the storage node contacts of the memory cell can be formed into an elliptical shape, and since the diffusion layer can be laid out in a straight line, the manufacturing process is easy.

That is, if the array of the present invention is used, the refresh characteristics of the DRAM can be improved. In addition, the DRAM manufacturing process can be simplified.

(Example 2)

FIG. 5 is a layout and circuit diagram showing the second hand element line noise reduction array of the present invention. In this embodiment, in the boundary between the SWD column and the memory array, the WL ending in the boundary and the WL connected to the SWD column are repeated as one respectively. This is different from the first embodiment.

Similarly, in this example, we also focus on the connection relationship between the WL and SWD columns. If you focus on two adjacent memory cells (MC0 and MC1) connected to DLOT, these MCs will have a total of 1 DLCT, but among the WLs connected to these memory cells, WL0 is connected to SWD column U, In contrast, WL1 is connected to column D of SWD. On the other hand, if you focus on the two adjacent memory cells (MC2 and MC3) connected to the DLOB, these MCs will also have a total of 1 DLCT, but among the WLs connected to these memory cells, WL2 is connected to SWD column U, in contrast, WL3 is connected to SWD column D. Therefore, in the layout of the word line noise reduction array of the second embodiment, the WLs connected to the two memory cells that share the DLCT are also connected to different SWD rows.

In this example, if we look at the entire memory array, because the pattern shown in Figure 5(a) is repeated vertically and horizontally, there will be half of the WL connected to the MC (the MC is connected to the DLOT) (Figure 5). Middle WLO, WL4) are connected to SWD column U, and the remaining half (WL1, WL5 in the figure) are connected to SWD column D. Also, half of the WLs connected to the MC (the MC is connected to DLOB) (WL2 and WL6 in the figure) are connected to SWD column U, and the remaining half (WL3 and WL7 in the figure) are connected to SWD column D . Therefore, in the character line connected to the cell (the cell is connected to a data line), half of the character line will be connected to the sub-character drive row of one row, and the remaining half will be connected to the other The auxiliary character drive column of the column. In addition, the SWD in the SWD column U is connected to the common VSS line VSSU. The SWD in the same SWD column D is connected to the common VSS line VSSD. If the VSS is wired in this way, the WL noise can be canceled in the VSS.

Therefore, the second word line noise reduction array of the present invention can also cancel each other's positive and negative WL noise during data line amplification in SWD, thereby reducing WL noise. Thereby, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

(Example 3)

6 is a layout and circuit diagram showing the third word line noise reduction array of the present invention. In this embodiment, in the boundary between the SWD column and the memory array, the WL connected to the SWD column and the WL ending in the boundary are repeated in four respectively, which is different from the first and second embodiments.

Similarly, in this example, we also focus on the connection relationship between the WL and SWD columns. That is, WL0 and WL1 of MCO and MC1 connected to DLOT and connected to two adjacent memory cells will be connected to SWD row U together. On the other hand, WL2 and WL3 of MC2 and MC3 connected to DL0B and connected to two adjacent memory cells will be connected to SWD column D together. Therefore, the noise generated in WL0 and WL1 in this embodiment can be canceled on VSSU by the noise generated in WL2 and WL3. Similarly, the noise generated in WL4 and WL5 can be canceled on VSSD by the noise generated in WL6 and WL7.

In this example, if we look at the entire memory array, because the pattern shown in Figure 6(a) is repeated vertically and horizontally, half of the WL connected to the MC (the MC is connected to the DLOT) (Figure 6) Middle WL0, WL1) are connected to SWD column U, and the remaining half (WL4, WL5 in the figure) are connected to SWD column D. Also, half of the WLs connected to the MC (the MC is connected to DLOB) (WL2 and WL3 in the figure) are connected to SWD column U, and the remaining half (WL6 and WL7 in the figure) are connected to SWD column D . Therefore, in the character line connected to the cell (the cell is connected to a data line), half of the character line will be connected to the sub-character drive row of one row, and the remaining half will be connected to the other The auxiliary character drive column of the column.

Therefore, the third word line noise reduction array of the present invention can also cancel each other's positive and negative WL noise during data line amplification in SWD, thereby reducing WL noise. Thereby, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

(Example 4)

FIG. 7 is a layout and circuit diagram showing the fourth word line noise reduction array of the present invention. In this embodiment, although the boundary between the SWD row and the memory array is the same as that shown in FIG. 11, the direction of the data line contacts DLCT of the memory grid arrays MC4, MC5, MC6, MC7 can be changed, so that the diffusion layer is juxtaposed in the DL direction The point that the memory grid of is alternately connected to different DLs is different from Embodiment 1, 2, and 3.

MCO and MC1 WLO connected to DLOT and connected to two adjacent memory cells, WL1 will be connected to SWDA-U together. On the other hand, WL2 and WL3 of MC2 and MC3 connected to DLOB and connected to two adjacent memory cells will be connected to SWDA-D together. In addition, MC4 and MC5 of the two adjacent memory cells are connected to DLOB by arranging the elliptical DLCT below the diffusion layer, but the connected WL4 and WL5 are connected to SWDA-U. Similarly, adjacency. MC6 and MC7 of the two memory cells are connected to DLOT by placing the elliptical DLCT below the diffusion layer, but the connected WL6 and WL7 are connected to SWDA-U.

Therefore, the noise generated in WL0 and WL1 in this embodiment can be canceled on VSSU by the noise generated in WL4 and WL5. Similarly, the noise generated in WL2 and WL3 can be canceled on VSSD by the noise generated in WL6 and WL7.

In this example, if we look at the entire memory array, because the pattern shown in Figure 7(a) is repeated vertically and horizontally, half of the WL connected to the MC (the MC is connected to the DLOT) (Figure Middle WL0, WL1) are connected to SWDA-U, and the remaining half (WL6, WL7 in the figure) are connected to SWDA-D. Also, half of the WLs connected to the MC (the MC is connected to DLOB) (WL4 and WL5 in the figure) are connected to SWDA-U, and the remaining half (WL2 and WL3 in the figure) are connected to SWDA-D . Therefore, in the character line connected to the cell (the cell is connected to a data line), half of the character line will be connected to the sub-character drive row of one row, and the remaining half will be connected to the other The auxiliary character drive column of the column.

Therefore, the fourth word line noise reduction array of the present invention can also cancel each other's positive and negative WL noise during data line amplification in SWD, thereby reducing WL noise. In this way, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

(Example 5)

This embodiment is for the second secondary character driver (SWD) used in the character line noise reduction array of the present invention. Here, although it is shown when combined with the first word line noise reduction array of the present invention, it can also be applied to other word line noise reduction arrays.

As far as the SWD shown in Figure 8 is concerned, the MWLB in Figure 3 is divided into MWLBO and MWLB1, and the number of FX is reduced to half. If this method is used, the layout area of the SWD can be reduced. Here, the SWD configuration is divided into upper and lower sections, and VSS is divided into VSSU1 and VSSU2.

When using such SWD, in order to cancel the WL noise, it is necessary to connect SWD to each VSSU. This SWD corresponds to the WL connected to the MC (the MC is connected to DLOT) and the MC (the MC is connected to DLOB) ) Of the two parties. That is, in FIG. 8, as in FIG. 1, WL1 and WL5 are connected to MC (the MC is connected to DLOT). Also, WL2 and WL6 are connected to MC (this MC is connected to DLOB). In this case, SWD1 connected to WL1 and SWD6 connected to WL6 are connected to VSSU1, so that the WL noise in these WLs can be canceled in VSSU1. In addition, SWD2 connected to WL2 and SWD5 connected to WL5 are connected to VSSU2, so that WL noise in these WLs can be canceled in VSSU2.

Therefore, the combination of the sub-character driver of the present invention and the character line noise reduction array of the present invention can cancel each other's positive and negative WL noise during data line amplification in SWD, thereby reducing WL noise. Thereby, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

(Example 6)

This embodiment is the third sub-character driver (SWD) used in the character line noise reduction array of the present invention. Here, although it is shown when combined with the first word line noise reduction array of the present invention, it can also be applied to other word line noise reduction arrays.

As far as the SWD shown in FIG. 9 is concerned, SWD1 and SWD6 share MN2 equivalent to SWD1 in FIG. 8 and are connected between WLs of each other. If this method is used, since the number of transistors used in SWD can be reduced, the layout area of SWD can be reduced. Here, dividing the configuration of the SWD into two upper and lower sections, and dividing the VSS into VSSU1 and VSSU2 are the same as in FIG. 8.

When using such SWD, in order to cancel the WL noise, it is necessary to connect SWD to each VSSU. This SWD corresponds to the WL connected to the MC (the MC is connected to DLOT) and the MC (the MC is connected to DLOB) ) Of the two parties. That is, in FIG. 9, as in FIG. 1, WL1 and WL5 are connected to MC (the MC is connected to DLOT). Also, WL2 and WL6 are connected to MC (this MC is connected to DLOB). This situation. It is assumed that SWD1 connected to WL1 and SWD6 connected to WL6 are connected to VSSU1, so that the WL noise in these WLs can be canceled in VSSU1. In addition, SWD2 connected to WL2 and SWD5 connected to WL5 are connected to VSSU2, so that WL noise in these WLs can be canceled in VSSU2.

Therefore, the combination of the sub-character driver of the present invention and the character line noise reduction array of the present invention can cancel each other's positive and negative WL noise during data line amplification in SWD, thereby reducing WL noise. Thereby, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

[Effects of the invention]

Regarding the character line noise reduction array DRAM of the present invention, no matter what form of signal appears on the data line, when the data line is amplified, the positive and negative character line noise will cancel each other out in the sub-character driver. It works in the direction of, so it can reduce the word line noise. Thereby, the degradation of the signal read by the sense amplifier can be prevented, and the reliability of the memory operation can be improved.

In addition, if we focus on the amount of signal from the memory cell, since even a signal smaller than that of the memory array with a poor balance of coupling capacity between the data line and the character line can be sensed accurately, the memory can be expanded. The range of action when the cell capacity is insufficient or the charge stored in the memory cell capacitor decreases due to leakage current. Therefore, if the present invention is used, the refresh characteristics of DRAM can be improved. And can make the DRAM manufacturing process easier.

Schematic description

Fig. 1 shows the layout and circuit diagram of the first word line noise reduction array of the present invention.

Figure 2 is a diagram showing the structure of a DRAM wafer.

FIG. 3 is a circuit diagram showing the first sub-character driver used in the character line noise reduction array of the present invention.

Figure 4 shows the noise reduction principle of the first word line noise reduction array of the present invention.

Fig. 5 shows the layout and circuit diagram of the second word line noise reduction array of the present invention.

Fig. 6 shows the layout and circuit diagram of the third word line noise reduction array of the present invention.

FIG. 7 is a layout and circuit diagram showing the fourth word line noise reduction array of the present invention.

FIG. 8 is a circuit diagram showing the second sub-character driver used in the character line noise reduction array of the present invention.

Figure 9 shows the circuit of the third sub-character driver used in the character line noise reduction array of the present invention.

Figure 10 shows the layout and circuit diagram of the DRAM memory array after the case has been reviewed in advance.

Fig. 11 is an enlarged view showing the layout and circuit diagram of the memory cell in Fig. 10.

Fig. 12 is a cross-sectional view showing the main part of the memory of the memory array of Fig. 11

FIG. 13 is a diagram showing the principle of generating word line noise in the memory array of FIG. 10.

Fig. 14 is a circuit diagram and operation waveforms of the sense amplifier of the memory array shown in Fig. 10.

Symbol description of main components

WL. . . Character line

SWD. . . Secondary character drive

DL. . . Data line

SA. . . Sense amplifier

MC. . . Memory grid

ACT. . . Active area of MOS transistor

SNCT. . . Storage node contacts

DLCT. . . Data line contact

TG. . . Choose Transistor

CS. . . Unit capacitor

PL. . . Screen pole

SN. . . Lower electrode of unit capacitor

MWLB. . . Main character line _㊣

FX. . . Sub-character driver selection line

SHR. . . Total SA selection line

CSP. . . PMOS common source

CSN. . . NMOS common source

BLEQ. . . Data line compensation line

VBLR. . . Data line reference power

SIO, SIOB. . . Vice IO line

M2, M3. . . Wiring layer