Power saving for ethernet mac control logic

Power saving of media access control network control logic

A full understanding of the present invention and one of its advantages will now be achieved with reference to the following description and drawings, in which:

FIG. 1 is a block diagram illustrating a specific embodiment;

2 is a flowchart describing general event action processing according to a specific embodiment disclosed;

FIG. 3 is a more detailed flowchart describing power saving characteristics according to a reception event; FIG.

4 is a more detailed flowchart describing power saving characteristics according to a transmission event;

FIG. 5 is a block diagram depicting such a clock source when using multiple media independent interfaces;

FIG. 6 is a logic circuit diagram illustrating a RMII implementation according to the disclosed new embodiment; and

FIG. 7 is a block diagram illustrating a system having a plurality of power saving MAC controllers.

The technical scope of the invention

The present invention relates to a media access controller, and more specifically, it relates to a method for an idle mode during a low-packet operation to access a media by placing one or more clocks of the controller. The controller implements a power saving feature.

Art background

The Internet has seen a significant increase in commercialization in order to develop a potentially large customer base. Billions of dollars continue to invest in hardware, software, and infrastructure to drive sales in this potential market. The basic hardware includes routers and switches to re-transmit data packets through the data network line, so that the operator can contact the client and vice versa. When these data networks fail due to hardware failure, or any other possible reason, customers and operators are even more important.

One of the main causes of hardware failure is heat. As the data transfer speed increases, the amount of power required to process the data increases. The highest-speed microprocessor has a cooling fan to prevent the device from processing a large amount of data and making the temperature too high. However, other devices are installed to send data from the Internet or LAN.

With Gigabit Ethernet, network interface devices currently carry significantly larger data streams, and the use of mechanical cooling methods can be a problem. A power saving structure can extend the life of these devices by providing more efficient power consumption.

Summary of invention

One aspect of the invention disclosed and patented herein is a media access controller with power-saving features. The controller includes a receiving logic circuit for receiving incoming data from a physical interface device and processing outgoing data transmitted to a frame processor; and a transmitting logic circuit for receiving outgoing data from the frame processor And process data sent to the physical interface device. The operation of a power management control logic is connected to each of the reception logic circuit and the transmission logic circuit so as to control the reception logic circuit and the transmission logic circuit in a first mode or a second mode. The power management control logic can control the media access controller in the first mode to conserve power by stopping substantial operations of the receive and transmit logic circuits, and in a second mode of the full power mode, it can perform receive and transmit Logic circuit.

Schematic illustration

A full understanding of the present invention and one of its advantages will now be achieved with reference to the following description and drawings, in which:

FIG. 1 is a block diagram illustrating a specific embodiment;

2 is a flowchart describing general event action processing according to a specific embodiment disclosed;

FIG. 3 is a more detailed flowchart describing power saving characteristics according to a reception event; FIG.

4 is a more detailed flowchart describing power saving characteristics according to a transmission event;

FIG. 5 is a block diagram depicting such a clock source when using multiple media independent interfaces;

FIG. 6 is a logic circuit diagram illustrating a RMII implementation according to the disclosed new embodiment; and

FIG. 7 is a block diagram illustrating a system having a plurality of power saving MAC controllers.

Detailed description of the invention

FIG. 1 is a general block diagram illustrating a MAC controller 100 and a general interface connected to a frame processor (FP) 102 and a physical (PHY) interface 104. The MAC controller 100 can process the basic data flow between the FP 102 and the PHY interface 104. Generally, when initially in a power saving (or idle) mode, the MAC controller 100 is placed in the entire operation (or execution mode) in response to one or more detected "events". The reception logic and transmission logic of the MAC controller 100 may be activated in response to detection of a reception event or a transmission event. Similarly, when a reception event or a transmission event is not detected, the reception logic and the transmission logic are placed in a power saving mode. Therefore, when initially in the power saving mode, detecting the incoming packet from any of the FP 102 or the PHY interface through the MAC controller 100 can change the MAC controller 100 from a power saving mode to a full operation mode.

In the specific embodiment disclosed herein, the receiving section of the MAC controller 100 is discussed from the viewpoint that the data received from the physical interface 104 is sent by the MAC controller 100 to the FP 102, and the MAC controller 100 starts from an idle state. . In order to process incoming data from the PHY interface 104 to the FP 102, the MAC controller 100 must change from a power saving mode to an execution mode. This change in operation occurs in response to an event signal from the PHY interface 104. For responding to this event signal, the MAC controller 100 can start a corresponding "action" and complete this action before deciding whether to change to the idle state. This event is based on the carrier sense signal of the PHY interface 104 used by the general protocols of carrier sense multiplexed access / collision avoidance (CSMA / CA) and carrier sense multiplexed access / collision detection (CSMA / CD). . (Note that these local area network (LAN) protocols are not used. The disclosed specific embodiment system can be used with other protocols. These protocols can provide information on whether the communication action on the LAN or communication media has started, and whether the data packets are sent. Come). The carrier sensing signal is placed on the network medium through a transmission network device that transmits data packets, and is detected by the PHY interface 104, causing a corresponding signal to be sent from the PHY interface 104 across one or more receiving interface lines 106. MAC controller 100. The receiving PHY interface line 106 can provide data and control signals between the MAC controller 100 and the PHY interface 104.

The data has been received and sent to the buffer 108 before the receiving logic portion of the MAC controller 100 "wake-up" in response to the carrier sense signal. The buffer 108 can always operate (when it receives pulses from a continuous execution of the system clock 109), and can temporarily retain the data packets sent from the PHY interface 104 until the receiving logic of the MAC controller 100 changes from the power saving mode to full Operation execution mode (for example, one or two clock signals). The buffer 108 includes a series of inertia flip-flops (not shown in the figure), which can provide sufficient buffer action until the receiving logic becomes the operation, and then provide the data to the internal control receiving logic of the MAC controller 100 for processing. . The buffer 108 can be connected to the system clock 109 on one or more clock lines 112. The system clock 109 is on the board of the MAC controller 100, and continuously executes the operation of the buffer 108 to receive the slave PHY continuously. A data packet sent by the interface 104. The system clock can also drive part of the FP102 logic, and is connected across the FP system clock line 113.

A power management logic block 114 implemented in the MAC controller 100 can be used to perform a power saving function, and can be connected to one or more receiving PHY interface lines 106 to sense a carrier sensing event signal of the PHY interface 104. The power management logic 114 may perform logic functions required to wake up the MAC controller 100 (ie, from an idle mode to an execution mode) in response to the event signal. More specifically, the power management logic 114 is always operational and determines the type of PHY interface 104 to use to receive the clock from one or more clock sources. The connection of selector logic 116 (eg, a multiplexer) selects the appropriate clock source corresponding to the particular type of interface used. For example, in a case of reducing the use of a Media Independent Interface (RMII), the reference clock 110 of the PHY interface 104 can be used to drive the internal TXCLK118 and RXCLK130. If a MII or universal serial interface (GPSI with a 7-bit interface) is implemented, an original clock source 111 can be used. The original signals can be the original TX clock signal and the original RX clock signal from the PHY interface 104. . The original TX clock signal can drive TXCLK118, and the original RX clock signal can drive RXCLK130. Since TXCLK118 more closely follows the original TX clock signal, it can be used as the source clock implemented in MII or GPSI. However, the system clock 109 is available, it requires more synchronization device logic, and there is potentially more delay between when the event is detected and when the MAC logic 100 is functional. If a SMII (Serial MII), or G MII (Gigabit MII), or XG MII (Extended GMII) implementation is used, the original RX clock portion of the reference clock 110 and the original clock source 111 can be used. The reference clock signal can output the generated TX clock to the PHY interface 104, and can also generate the TX CLK of the MAC control logic 100. When additional clock signals are used (refer to the clock 110 signal and the original clock source 111), the control logic becomes more complicated in order to synchronize the signals between the clock sources (110 and 111). The selector 116 crosses one or more clock lines 122, the original clock source 111 crosses one or more clock lines 120, and transmits the clock (TX CLK) 118 is connected to the external PHY reference clock 110 across one or more clock lines 124. The output of the selector 116 is connected to the power management logic 114 across one or more clock lines 128. The implementation of the selector 116 can operate independently to select the clock source corresponding to the selected special type of PHY interface 104, or it can also operate according to the power management logic 114 (phase wiring is not shown in the figure), so that if the power management logic 114 By sensing the type of the PHY interface 104, the selector 116 can be controlled to select an appropriate clock source.

The wake-up function in the receiving part of the power management logic 114 can be gated through a gate logic that receives one or more clock lines 132 and a TX CLK 118 that crosses one or more clock lines 134 While executing. The RX CLK 130 can provide a clock signal to a receiving FIFO control block (RX FIFO control) 136 and a receiving control logic block (RX control) 138. The RX control logic 138 that receives data from the buffer 108 across the buffer interface line 140 can format the data for insertion into an asynchronous receive FIFO (asynchronous RX FIFO) 142 and check the status and integrity of the data. The RX control logic 138 may also interface with the RX FIFO control logic 136 to provide control signals to it. The RX FIFO control logic 136 may synchronize data input to the asynchronous RX FIFO 142 via the RX control logic 138 in response to a control signal received from the RX control logic 136.

The data control transmitted from the asynchronous RX FIFO 142 to the FP 102 is a control interface line 144 across the RX FIFO control 136 of the MAC controller 100 to the FP 102. Data is transmitted from the asynchronous RXFIFO 142 of the MAC controller 100 to the FP 102 along one or more receive data interface lines 146. When the power management logic 114 determines that all actions related to the receiving and transmitting operations on the MAC control logic 100 are completed, the RX CLK 130 and TX CLK 118 are turned off. However, since the asynchronous RX FIFO 142 is asynchronous, it can continue to coordinate operation with the FP 102 until the FP 102 reads the frame end data and the asynchronous RX FIFO 142 notifies it that it is blank.

When acting as a clock source, the reference clock 110 can also provide timing pulses across one or more clock lines 148 to a small portion of the RX FIFO control logic 136 and a small portion of the transmission FIFO control on the clock line 152 Some registers of logic (TX FIFO control) 150, and asynchronous RX FIFO 142 and an asynchronous transmission FIFO (asynchronous TX FIFO) 154 (the clock line is not shown later in the two sets of logic).

The operation of the transmission logic of the MAC controller 100 may receive the "output" data from the FP 102 and process it for transmission to the PHY interface 104. When the FP 102 starts transmitting the frame packet to the PHY interface 104, the FP 102 may transmit a transmission signal to the transmission logic of the MAC controller 100. This transmission signal can be sensed by the power management logic 114 as a second type event. In response to the second event signal, the power management logic 114 can wake up the transmission logic of the MAC controller 100 by gating the TX CLK 118. In addition, in response to this signal, a second action can begin the general processing of preparing to transmit the packet from the FP 102 to the physical interface 104. This second action includes outputting data to the asynchronous TX FIFO 154 of the MAC controller 100 across one or more transmission interface lines 156, and passing the data across one or more through control signals communicated between the MAC controller 100 and the FP 102. The plurality of FP transmission control interface lines 158 are transmitted to the TX FIFO control logic 150. The data packet transmission timing is provided through the gated TX CLK 118, which can receive the start and stop signals from the power management block 114 across one or more transmission clock lines 134. TX CLK118 provides timing signals to TX The FIFO control logic 150 and a transmission control logic block (TX control) 160. The TX control logic 160 may provide the data path from the asynchronous TX FIFO 154 to the PHY interface 104 across the physical interface transmission line 162 and the control signal to the TX FIFO control logic 150 to synchronously insert data from the FP 102 into the asynchronous TX FIFO 154 . The control signal from the TX control logic 160 can also communicate the data transmission status with the power management logic 114. The implementation of RXCLK130 and TX CLK118 are in accordance with the Ethernet reception and transmission rates, respectively. When the frame transmitted from the FP102 ends, the second action (transmission) ends. The method used to determine when this occurs is when the frame gap time exceeds a predefined limit and the asynchronous TX FIFO 154 is blank.

As mentioned above, in order to obtain maximum power saving benefits, the MAC controller 100 may utilize a separate clock domain. Since the RX / TX FIFOs (142 and 154 respectively) are asynchronous and the control of the RX TX clock logic (130 and 118 respectively) is gated, a substantial part of the MAC controller 100 logic can be placed in idle mode (That is, stop). When a valid connection is detected between the MAC controller 100 and the PHY interface 104, the disclosed power saving method can save power by shutting down during the idle time between extended packet transmissions. However, some traditional implementations decide on a link pulse to determine when to use a power saving technology. The disclosed structure includes a more robust application that can be triggered on unreceived or transmitted data packets to indicate whether the power consumption of the MAC circuit is obviously decrease. For example, a GIGA Ethernet MAC controller can operate at a high system speed of 125 MHz. Its high speed has an impact on the life of a chip. This life is affected by the power consumption and the cooling mechanism implemented. During the low-packet action, the selective shutdown capability of the MAC controller 100 can extend the life of the MAC circuit without affecting the packet throughput. The disclosed structure can also be applied to 10G Ethernet.

The disclosed embodiment can provide a power saving method, so that the power management logic 114 of the MAC controller 110 can simultaneously start RX CLK130 and TX CLK118 in response to a detected event, and then turn off both when no action is processed. Clock (RX CLK130 and TX CLK118). In another specific embodiment, thanks to the power management logic 114 can be implemented to individually control the RX CLK130 and TX CLK118, so that when TX CLK118 and its combined transmission logic are idle (ie, there is no data from FP102 to PHY interface 104 (Available for processing), the RX CLK 130 and its receiving logic are operable to process the packet data sent from the PHY interface 104. Similarly, since no packet is sent, the RX CLK 130 and its receiving logic can be placed in the idle mode, while the TX CLK 28 and its transmission logic are in the execution mode to process the packet sent to the PHY interface 104. Finally, as disclosed in the foregoing specific embodiment, the receiving and transmitting portions may be in an idle mode or an execution mode simultaneously.

Note the implementation of CSMA / CD, the transmitting end also needs to monitor the packet movement on the network media to determine the packet transmission time. This is needed in a half-duplex environment to determine the minimum frame gap time. The transmission side supervision of the network packet action is not required in a full multiplexed Ethernet system. Therefore, a more robust logic design includes three capabilities: the MAC controller 100 receives logical RX drive events, the MAC controller 100 transmits logic TX drive events, and the RX / TX drive events, which are part of Network media logic to monitor packet actions (implemented in CSMA / CD). When in a full multiplex structure, RX / TX drive events can only be driven by TX events.

FIG. 2 is a flow chart illustrating the general appearance of a preferred embodiment. The discussion of the general flow begins with the assumption that the system is in an idle state (ie, the power management logic 114 has the RXCLK 130 and TXCLK 118 of the MAC controller 100 in a stop mode) operation. The process starts with a start block, and moves to a decision block 200 to determine whether a predefined event occurs. The number of events that can be detected will only be limited by the prudence of the designer of the MAC controller 100. If not, the flow will execute the "No path to a function block 202, where RXCLK130 and TXCLK138 are maintained in a stop mode, where the stop mode can turn off a substantial part of the functions of all the circuits of the MAC controller 100. The process may then return from the function block 202 to the input of the decision block 200 to continuously sense the occurrence of an event. On the other hand, if a predefined event occurs, the process will execute the "yes path of decision block 200 to a function block 204 to start receiving the transmission clock (130 and 118 respectively).

The process may continue with a decision block 206 to determine whether the detected event is related to receiving data from the PHY interface 104. If so, the process executes the "Yes" path to a function block 208 to begin processing the corresponding action of the received event. The process may continue with a decision block 210 to determine when these receiving actions are completed. If the action is not completed, the flow executes the "No" path to a function block 212 to continuously execute the receive / transmit clock (130 and 118), and the action can be completed. The output of the function block 212 may then be looped back to the input of the decision block 210 to continuously monitor whether all actions are completed. If all the receiving / transmitting actions are completed, the flow will execute the "yes" path of the judgment function 210 to a function block 214 to stop the receiving / transmitting clock (130 and 118). Save mode.

If the event first detected in decision block 200 is not a reception event, the flow will execute a "No" path of decision block 206 to a function block 216 to determine whether the event is a transmission event. If so, the process executes the "yes" path to a function block 218 to begin processing the corresponding action. The process may continue to determine block 210 to determine whether all actions are completed. Process processing can then continue as described above. On the other hand, if the detected event is not a transmission event, the flow will execute the "No path of decision block 216 to a function block 220 in order to take action based on a possible error detection. This action can include sending a resend frame request, or entering a ready state, or setting a flag to indicate whether a frame detection error has occurred, or any other action that can be taken. The process may then proceed to function block 214 to stop RXCLK130 and TXCLK118. Note that the process describes only two events that can be detected. However, in terms of designer's caution, the method of disclosure is not limited to these two events, but has more events that can be detected. As shown in function block 214, after the clock stops, the process can return to the input of decision block 200 to continuously monitor whether a receive / transmit event occurs.

Thanks to the operation of the system, multiple different events can be detected simultaneously. For example, a detected reception event may put the MAC controller 100 into an execution mode. When in the execution mode, a transmission event from the FP 102 can be detected, which can also enable the power management logic 114 to maintain the reception / transmission clock in the execution mode. The detection of a receive event and a transmit event has the same final effect as the start of the receive / transmit clock (130 and 118). Therefore, multiple events and corresponding actions can be processed simultaneously.

In terms of operations, an event can trigger an action to complete a job. When an event is detected, the receive / transmit clocks (130 and 118) can begin and are maintained by the completion of the corresponding action. Since a network communication can move normally per second (and possibly in both directions) and can fit many frames, multiple transmission / reception events and actions can occur simultaneously. Therefore, before completing an action to stop receiving / transmitting the clock, an overall check must determine whether other events or actions are still in progress. If so, the clock must be maintained in execution mode until all events and actions are completed. After all actions are completed, the clock will stop (ie, set back to idle mode) in order to save power and wait for another event.

In the specific embodiment disclosed herein, the logically detectable events and corresponding actions of the MAC controller 100 are described below. When the PHY interface 104 senses a carrier signal on the network medium, the power management logic 114 can interpret this as an event indicating that the frame is to be sent. The corresponding action performed by the MAC control logic 100 can transmit the received frame to the FP 102. When the FP 102 reads the end-of-frame (EOF) data from the asynchronous RX FIFO 142, the action can be completed. When the MAC control logic 100 receives a frame transmission request signal from the FP 102, another event occurs. The corresponding actions performed by the MAC control logic 100 can process the packets of the FP 102 and send them to the PHY interface 104. When the frame is transmitted and the minimum frame gap time has expired, the action is complete. The expiration of this time means that another frame follows the first frame, and subsequent frames should appear within the specified time. If not, it is generally assumed that no frame was sent. A further requirement is that when the asynchronous TX FIFO 154 is blank, an indication of whether this action is complete can be provided.

FIG. 3 is a more detailed flowchart describing one of the receiving events and corresponding actions of the MAC controller 100 according to the disclosed new features. This discussion is based on the assumption that the MAC controller is currently in an idle state. The process starts at a starting point and moves to a decision block 300 to determine whether a reception event occurs. The detection of the reception event is to detect a carrier sensing signal from the PHY interface 104. If it does not happen, the process will execute a "No" path and loop back to the input of decision block 300 to continuously monitor whether a receiving event occurs. If an event is detected, the process will execute the "yes" path of decision block 300 to a function block 302 to start RX CLK 110 (and TX CLK 118). When the RX CLK 110 starts, one or more data frames can be reached from the PHY interface 104 and buffered in the buffer 108. The process then proceeds to a function block 304, where the received packets can be processed by the receiving logic of the MAC controller 100. This process includes keeping the data in the RX control logic 138 to check the data status and data integrity, and then formatting it to insert into the asynchronous RXFIFO 142. The MAC controller 100 may then transmit the frames to the FP 102. This can be achieved by communicating with the FP102 through the RX FIFO control 136 to coordinate frame transmission from the asynchronous RXFIFO 142.

In order to detect the completion of the receive event action, at least two standards must be met, 1) an end of frame (EOF) signal must be detected by the FP102, and 2) the asynchronous RXFIFO142 must be blank. For this purpose, when the packet processing is complete, the flow will go to a function block 306 in order to write the EOF data into the asynchronous RXFIFO 142, and the EOF data can be detected by the FP102. The flow goes to function block 308 to clear the receive pipeline signal of the receive logic. The process then goes to a decision block 310 to determine whether another reception event is detected. If so, the flow executes the "yes" path to the input to function block 304 to continue the packet processing cycle. If no more receive events are detected, the process will execute the "No path to a function block 312 and stop the RXCLK 130. However, as mentioned above, RXCLK130 and TXCLK118 can operate together. Therefore, if a decision is made that no more packets are received from the PHY interface 104, so that RXCLK 130 is turned off, the power management logic 114 can also perform an overall action check to ensure that no other action can be turned off at two clocks (130 and 118) Performed before. If no other event or action is performed, the two clocks (130 and 118) can be stopped, and the process can continue from the output of the function block 312 to the input of the decision block 300 to continuously monitor the reception of events. The power management logic 114 may supervise the processing of packets between receive logic and transmit logic. The absence of packet processing in the receive or transmit logic can trigger the power management logic 114 to perform a complete check of any active events and actions before closing the two clocks (130 and 118).

FIG. 4 is a more detailed flowchart describing power saving characteristics according to a transmission event. The process starts at a starting point and continues to a decision block 400 to determine whether the full multiplex operation can be guaranteed by sending and receiving data through the receiving logic. Since the receiving logic can trigger the operation without relying on the transmitting logic, and vice versa, thanks to the transmitting operation, a complete operation without the receiving logic can begin. Therefore, the decision block 400 can also test a reception event. If a reception event is not detected without the need for a full-duplex operation, the flow executes the "No path of decision block 400 to another decision block 402 to determine whether a new job starts in the asynchronous TX FIFO 154. If no frame data is written to the asynchronous TX FIFO 154, the flow will execute the "No" path to the input of the decision block 400 to continue any event (receive or transmit). The FP102 can start transmission processing by writing frame start data to the asynchronous TX FIFO 154. When this is detected in decision block 402, the flow executes the "Yes" path to a function block 404 to start TX CLK 118. By default and above, RX CLK 130 can also start. The flow then goes to a function block 406 where the MAC controller 100 processes the data from the FP. The data of 102 can be written into the PHY interface 104. The process may continue with a decision block 408 to determine whether the writing process is completed. If it is not completed, the flow will execute the "No path to the input of the function block 406 to continuously write data to the PHY interface 104.

If the writing procedure is completed, the flow executes the 408 "yes" path of the judgment block to a function block 410 to measure and load the frame gap (IFG) time into a register. The process then proceeds to a decision block 412 to determine whether the IFG time has expired. The expiration of this time indicates that there may be no more packets flowing from the FP 102 and the transmission (or write) process of the PHY interface 104 will be interrupted. IFG time can be measured at each frame pair processed by the transmission logic. If the IFG time has not expired, the flow executes the "No" path of decision block 412 and enters the function block 410 to continuously measure the IFG time and load it into a register for query processing. If the IFG time expires according to the predetermined value, the flow executes the YES path of decision block 412 to another decision block 414 to determine whether a new frame is inserted into the asynchronous TX FIFO 154. If so, the flow executes the "yes" path to the input to function block 406 to begin processing the incoming frame data and writes it to the PHY interface 104. This procedure can continuously write each frame of data into the asynchronous TXFIFO 154. If no new frame data is inserted into asynchronous TX FIFO 154, the process executes the "No" path of decision block 414 to a decision block 416 to re-supervise the entire processing of events and actions. If other events and actions are being processed, the flow executes the "Yes path to the input of the function block 410 to continuously process the IFG time. If there are no more events and actions to process, the flow executes the "No" path to a function block 418 to stop the TX CLK 118. The flow then returns to the input of decision block 400 to begin supervising the processing of any event. If the determination block 400 does detect an event, the flow executes the "Yes path to a function block 420 to start TXCLK118. The output of function block 420 then flows to the input of function block 410 to start the measurement and loading of the IFG time.

FIG. 5 is a block diagram illustrating a clock source when using multiple media independent interfaces. In the case where the interface is RMII, the source clock of the power management logic 114 is the reference clock 110 from the PHY interface 104. In the case where the interface is a MII or GPSI, the source clocks of the power management logic 114 are the original TX clock signal 500 and the original RX clock signal 502 from the PHY interface device 104. In the case where the interface is, for example, a GMII or XGMII, the source clock of the power management logic 114 can be obtained from the reference clock 110 and the original RX clock signal 502 of the PHY interface 104. When a transmission clock output 504 controlled by the power management logic 114 is GMII or XGMII in the MII interface, it can also return to the PHY interface 104 without stopping. Regardless, the power management logic 114 has controllable RXCLK 130 and TXCLV 118. Clock field line 506 indicates that the receive FIFO logic 508 and the transmit FIFO logic 510 are timed through the relative RXCLK130 and TXCLCK118 during operation, and these parts of the receive and transmit logic circuits (508 and 510) can receive signals from the system clock 109. pulse.

FIG. 6 illustrates a RMII implementation gate control circuit according to the disclosed new embodiment. As mentioned above, the RMII reference clock signal 600 referring to the clock 110 is implemented in this device and can be used as a clock source for power management control. The RXCLK signal 602 and the TXCLK signal 604 may be synchronized with the RMII reference clock signal 600 on the opposite clock lines 606 and 608. The RMII reference clock signal 600 is also connected on the relative clock lines 614 and 616 to time a received power saving flip-flop (RX save) 610 and a transmission power save flip-flop (TX save) 612. The wake-up control signal of the RX saving device 610 is connected to a RX wake-up input 618, and when the input action from the PHY interface 104 to the FP102 does not detect an input packet, the shutdown control input (RX action completion) 620 can provide shutdown control. Similarly, when a write frame signal is detected from the FP102, the TX saving device 612 may have a TX wake-up input 622 when the transmission logic is placed in the execution mode, and when no input packet is being processed from the FP102 to the PHY interface 104 When transmitting motion detection, a shutdown control input (TX action completed) 624 provides shutdown control. A full multiplex input allows full multiplex operation control.

FIG. 7 is a block diagram of a system using multiple subsystems, where each subsystem can execute in a power saving mode. A system (eg, a network switch) 600 includes multiple subsystems (702, 704, 706, and 708), which are common in network devices such as routers, switches, hubs, etc., each of which includes the aforementioned power savings characteristic. For example, system 700 is operatively configured on a network medium 710 to route data routes to one or more subnets (also known as "subnets"), each unique subnet is Relative to one of the subsystems (702, 704, 706, or 708). The system 700 is constructed using a central system power management controller 712 as shown to control the gated clock of each subsystem (702, 704, 706, and 708) on a subsystem data and control bus 714. In this particular embodiment, the system power management module 712 is implemented without the need to implement another power management logic block 114 in each subsystem (702, 704, 706, and 708).

In operation, the data frame placed on the media can be addressed to a predetermined subnet, which requires only one of these subsystems (702, 704, 706, or 708) to be woken up to process data. For example, if the data placed on the media 710 can be addressed to a first sub-network related to the first subsystem 702, a first subsystem physical interface 716 can detect the carrier sense signal, and a system PHY The interface bus 718 communicates the detection of the signal with the system power management logic 712. The system power management logic 712 can then gate the receive clock of a MAC controller 720 of the first subsystem 702 (not shown in the figure, but similar to RX CLK 110) to operate the receive logic (not shown in the figure, but similar to The aforementioned reception logic RX control 130, RX FIFO control 136, and asynchronous RX FIFO 142 related to FIG. 1). The MAC controller 720 may then send a message to the relevant frame processor 722 of the frame data preparation frame processing and transmit the data to the frame processor 722. The operation can continue in the same manner as the transmission part as disclosed in FIG. 1, and for the entire power saving operation, the system management controller 712 shuts down or executes the gated reception / transmission of the MAC controller 720 based on the presence or absence of data pulse.

As the aforementioned MAC controller 100 of FIG. 1 operates, many events and actions can occur simultaneously. Likewise, in the disclosed embodiment of the system, not only events and actions occur simultaneously in the subsystems, but also events and actions can occur simultaneously in each subsystem (702, 704, 706, and 708). For example, although the receive / transmit logic of the MAC controller 720 of the subsystem 702 may be in idle mode, the receive / transmit logic portion of a MAC controller 724 of the system 704 may begin in response to an event requiring its receive logic operation. Therefore, when the other parts of each subsystem are in power protection mode, each subsystem can operate at full power from a different perspective.

In another specific embodiment, such as the previously disclosed power management logic 114, since each subsystem (702, 704, 706, and 708) contains its own individual power management logic, the system 700 may omit the central system power management logic 712. Each subsystem module is then independently operable based on predetermined events.

In a further specific embodiment, the system includes a central power management block 712 and each subsystem (702, 704, 706, and 708), which can coordinate communication operations with each other to help the disclosed power saving characteristics.

As previously mentioned, the new features revealed have found applications in many different types of physical interfaces. For example, this power saving feature can be applied to the GPSI7 bit interface, MII, RMII, SMII, and GMII interfaces. MII is part of the Fast Ethernet specification and replaces the AUI (or accessory unit interface) of 10Base-T Ethernet. MII can be used to connect the MAC layer 100 to the PHY layer 104. RMII can reduce the interface between the application of the special integrated circuit of the MAC controller 100 and the transceivers with 16 to 7 pins per port, while SMII can further reduce the interface to only 2 pins per port.

Although the preferred embodiment has been described in detail, it can be understood that various changes, substitutions, and changes do not depart from the spirit and scope of the present invention as defined in the appended patent application.