Three dimensional device integration method and integrated device

Three-dimensional device integration method and integration device

A more complete understanding of the present invention and many of its benefits will be better understood with reference to the accompanying drawings and the following detailed description _， Where:

Figure 1 shows a cross-sectional view of a step in the method according to the present invention;

Figure 2 shows a cross-sectional view of a step in the method according to the present invention;

Figure 3 shows a cross-sectional view of joining two substrates according to the present invention;

Figure 4 shows a cross-sectional view of a connecting device according to the present invention;

Figure 5 shows a cross-sectional view of a bipolar transistor with multiple junctions;

Fig. 6 shows a cross-sectional view of the transistor of Fig. 4 connected according to the present invention;

Figure 7 shows a cross-sectional view of a connecting device according to the present invention;

Figure 8 is a cross-sectional view showing the steps of joining two devices together according to the present invention;

Figure 9 is a cross-sectional view showing the steps of joining two devices together according to the present invention;

Figure 10 shows a cross-sectional view of connecting two devices according to the present invention;

11A and 11B show cross-sectional views of two devices to be connected according to the present invention;

Figure 12 shows a cross-sectional view of the device connecting Figures 11A and 11B;

Figure 13 shows a cross-sectional view of the steps of internally connecting the devices of Figures 11A and 11B;

FIG. 14 is a cross-sectional view showing the steps of connecting the connecting device of FIGS. 11A and 11B to another device;

Figure 15 shows a cross-sectional view of connecting and internally connecting three devices;

Figures 16A-16D show the connection of three integrated circuits;

Figure 17A is a laminated internal connection structure;

FIG. 17B is a diagram of connecting the internal connection structure of the stack of FIG. 17A to a substrate with an integrated circuit;

Figure 18 is one of the circuit elements of the -2D array;

Figure 19 shows the circuit elements of the 2D array connected and internally connected;

Figures 20A-20F show the integration method according to the present invention;

Figure 21 shows an exploded view of the integrated device according to the present invention;

Figure 22A shows the backside package;

Figure 22B shows the top surface package;

Figures 23-34 show cross-sectional views of a method for integrating solar cells according to the present invention;

Figures 35 and 36 show the integration of devices with holes;

Figures 37A-37D show the connection of a plurality of molds or devices to a substrate according to the present invention;

Figures 38A and 38B show the connection of a connecting device to a circuit board or package.

Background of the invention Scope of invention:

The present invention relates to a three-dimensional integrated semiconductor device, and particularly relates to a semiconductor device vertically connected together to form a three-dimensional structure.

Background discussion:

The ability to integrate determines the success of the semiconductor industry. This can first be seen from the invention of integrated circuits (IC). IC basically consists of manufacturing electronic components on the surface of the semiconductor wafer, and then metalizing the components to interconnect these components. Good results for cost reduction and performance increase caused by this integration ^， It has already had a considerable economic shock.

Because of the invention of IC, the semiconductor industry has continued to grow rapidly due to the continuous improvement of the integration of different electronic components (ie, transistors, diodes, resistors, capacitors). For most parts, this improvement in integration has been reduced by minimizing the repeatability of feature sizes, allowing more components to be integrated in a given area. It can be improved by increasing the wafer size.

These integrated improvements are basically two-dimensional, in which the volume occupied by the integrated components is basically on the surface of the semiconductor wafer. Although a substantial improvement in printing technology can already result in a substantial improvement in this 2-D integration, there are physical limitations on the density that can be achieved by 2-D. One of these limitations is that the size required to form these components can be minimized. Another limitation is that when the size of the components is reduced, the interconnection requirements between the components will be greatly increased.

Efforts to achieve a degree of integration that exceeds that of 2-D has resulted in improved chip memory and further growth in the semiconductor industry. For example, the trench capacitor uses a large amount of semiconductor volume below the wafer surface and allows more functions to be achieved in a given wafer area. At present, other efforts have continued to increase in a given chip area to directly achieve higher integration by increasing the volume of use. One way is to rewind the integration process to add semiconductor material on top of the interconnect metallization, followed by additional interconnect metallization. Although this may result in more components per chip area, it will cause other problems, which include a large increase in heat load. In addition, this effort and other differences are that it uses only one substrate and only processes one surface of that substrate. In order that the device does not need to undergo heat treatment when manufacturing the internal connection, it will be simpler and improve the manufacture of the device.

Another problem is that compared to reducing the size of the device, the ability to scale the size of the internal connection is relatively weak. Ideally, it requires that the critical size of a via will be the same as the size of a gate. However, because the scaling of the vias lags behind the scaling of the device, it limits the integration density.

A further problem is trying to integrate different forms of technology into a single circuit or wafer. BiCMOS is an example. basically _， Special processing technologies must be designed to be able to combine these technologies. The process required for one technology usually forms an interface with other required processes. Therefore, there must be a compromise. The overall development of this combination of technologies has been suspended, making it very difficult to make flexible combinations of technologies that may be integrated. In other words, the most advanced "best seed" technologies have not been combined, nor can they be developed. Another problem with the development of combined technologies is that they must be customized first. It must first design the manufacturing process to combine the technology, which will limit the device. Again, because it needs to redesign the manufacturing process, it cannot get the benefits of development and the improvement of technology.

Summary of the invention

The purpose of the present invention is to provide a method and device with high integration density. Another object of the present invention is to provide a method and device that can integrate different types of materials.

A further object of the present invention is to provide a method for integrating devices of different forms, and a structure including the integrated device.

Another object of the present invention is to provide a method and device that can integrate different types of technologies.

Yet another object of the present invention is to be able to avoid or minimize the heat load in the internal connection device.

Another object of the present invention is to allow the integration of the best available technology without the need for many process compromises.

Yet another purpose is to provide an improved connection device, the internal connection between the device and the substrate, the card and/or the substrate.

These and other objectives can be achieved by a method of forming an integrated device, which includes the following steps: forming a first bonding material on a first semiconductor device with a first substrate, and forming a first element on a first device with a second substrate A second connecting material is formed on the upper surface, and the first and second connecting materials are directly connected. A part of the first substrate can be removed to expose the remaining part of the first semiconductor device, and the integrated device can be installed in a package.

The first semiconductor device may be the exposed side of the remaining part of the first semiconductor device. The first semiconductor device can have a substrate on its upper and bottom, and an active area can be formed on the upper side, and the package is connected to the first semiconductor from the bottom. A second element with a third substrate can be connected to the rest of the first semiconductor device, and the first element can be removed _， Or substantially removed, and the semiconductor device can be connected to the package from the upper part.

The first semiconductor device may have a plurality of interconnection poles, and the connection may be formed by at least one degree of interconnection from a side of an exposed remaining portion. A plurality of internal connections can also be formed by an exposed remaining part side. It can directly constitute a device element area connected to the first semiconductor device.

According to the method of the present invention, it may also include the following steps: connecting a first thermal diffusion substrate to a first semiconductor device having a device substrate, and removing a part of the device substrate to expose a portion of the first semiconductor device The remaining part connects a second thermal diffusion substrate to the remaining part of the first semiconductor. A plurality of internal connection levels can be formed in the first semiconductor device, and the first or second thermal diffusion substrate can be used to form a connection to at least one of these internal connection levels. Connections to different levels of internal connections can be formed using a real contact method, and they can be directly connected to the device element area of the semiconductor.

According to the method of the present invention, it may also include the following steps: directly connecting a first semiconductor device having a first substrate to a device, and removing a part of the first substrate to expose the first semiconductor device after the connection The remaining part of the component can include a substrate for thermal diffusion and impedance matching, or for RF isolation, an antenna, or a matching network including passive components. The remaining part of the first semiconductor device can be connected to the device, and a part of the remaining part can be removed to expose a part of the device. The method according to the present invention may also include: directly connecting a part A first element of the system is connected to a second element of the system, and the first and second elements are internally connected. The first element can be connected to a second element having a substrate, at least a part of the substrate can be removed, and the first and second elements can be formed from the side of the second element from which the part has been removed Internal connection. A shielding component, an isolation component or an antenna can be connected to at least one of the first and second components. An optical device can be connected to an electronic device, or a low-speed high-density semiconductor device can be connected to a high-speed low-density semiconductor device. The first and second semiconductor devices may be of different technologies. E.g _， A microprocessor can be connected to a high-density memory device, or in another example, the first and second solar cells can be connected together.

The method according to the present invention may also include attaching a plurality of first elements to the surface of a substrate to form a second element, and directly connecting the second element to a third element from the side to which the first element is attached. The attaching step may include directly connecting each of the plurality of first components to a surface of the substrate. A part of the second element can be removed after joining. The first element can be internally connected with the third element, the first element can be internally connected by using the second element, and the first element and the third element can develop at least one of the second and third elements Internal connection. A recess may be formed in the second element, and the first element may be connected to the second element in the recess.

As another embodiment, a method may include the following steps: forming a first bonding material on a first semiconductor device, and forming a second bonding material on a second device. The first and second bonding materials can be directly connected, and a conductor array with a plurality of contact structures can be formed on an exposed surface of the first semiconductor device. A via can be formed to pass through the first semiconductor device to the device area, and an internal connection can be formed between the device area and the contact structure. The conductor array may include a peg grid array. The method may further include combining the peg grid array and forming a plate _， The conductor area on the card or substrate.

The device according to the present invention may include a first device portion having a first device, which includes a first substrate, and wherein the first substrate has been removed to form a first bonding material on the first device portion On the upper side, a first element having a second connecting material is formed thereon, and the first connecting material is directly connected to the second connecting material. The first device part may include a first solar cell part ^， The first element may include a second solar cell with a substrate. An internal connection may be formed between the first solar cell part and the second solar cell, which is connected to the side of the first solar cell from which the first substrate has been removed.

The first device part may include a semiconductor device with active components _， The first element may include a substrate for thermal diffusion and impedance matching _， Or used for RF isolation, an antenna, or a matching network containing passive components. The first device part may have a first side and an opposite second side, which may constitute an internal connection to the device part, which may be either the first side or the second side. A shielding component or an isolation component can be directly connected to one of the first device part and the first element. An antenna can be directly connected to one of the first device part and the first device element, and an internal connection can be formed between the antenna and at least one of the first device part and the first element.

The first device part may include an optical device, and the first element may include an electronic device. The first element may also include a low-speed high-density semiconductor device, and the first device part may include a high-speed low-density semiconductor device. The integrated device according to the present invention may also include a plurality of first elements, each of which is directly connected Ground is connected to a surface of a substrate to form a second element, and a third element is directly connected to the second element, which is connected to the side where the first element is connected to the surface of the substrate . The internal connection can be formed between the third element and a selected one of the plurality of first elements, and the internal connection can be formed between the selected one of the first elements. The first element may be placed in a recess formed in the substrate.

As another embodiment, the device according to the present invention may include a device part including a semiconductor device with opposite upper and bottom sides, a first substrate may be directly connected to the upper side of the device part, and a second The substrate is directly connected to the bottom side of the device part. Internal connections can be formed to the device portion to pass through one or both of the first and second substrates. The power and ground connections can be formed to the device part through only one of the first and second device substrates, and the signal and clock intra-board connections can be formed through the other of the first and second device substrates. The device part.

The integrated device according to the present invention may also include a plurality of first elements, each of which is directly connected to a surface of a second element. The first element and the second element may include at least one of a semiconductor device, a patterned conductor, an antenna element, and an impedance matching element. A via window may be formed in the first element, and a conductive material may be formed in the via window to internally connect the first element and the second element.

The device according to the present invention may also include a first bonding material disposed on a first semiconductor device, and a second bonding material disposed on a first element. The first and second connecting materials are directly connected. A conductive array can be arranged on an exposed surface of the first element having a plurality of conductive regions, and internal connections can be formed between the conductive region of the array and the conductive region of the semiconductor device. The conductive array may include a peg grid array. The second conductive area can be fitted in the conductive area, which is formed on at least one of a board, a card or a substrate.

Schematic description

A more complete understanding of the present invention and many of its benefits will be better understood with reference to the accompanying drawings and the following detailed description _， Where:

Figure 1 shows a cross-sectional view of a step in the method according to the present invention;

Figure 2 shows a cross-sectional view of a step in the method according to the present invention;

Figure 3 shows a cross-sectional view of joining two substrates according to the present invention;

Figure 4 shows a cross-sectional view of a connecting device according to the present invention;

Figure 5 shows a cross-sectional view of a bipolar transistor with multiple junctions;

Fig. 6 shows a cross-sectional view of the transistor of Fig. 4 connected according to the present invention;

Figure 7 shows a cross-sectional view of a connecting device according to the present invention;

Figure 8 is a cross-sectional view showing the steps of joining two devices together according to the present invention;

Figure 9 is a cross-sectional view showing the steps of joining two devices together according to the present invention;

Figure 10 shows a cross-sectional view of connecting two devices according to the present invention;

11A and 11B show cross-sectional views of two devices to be connected according to the present invention;

Figure 12 shows a cross-sectional view of the device connecting Figures 11A and 11B;

Figure 13 shows a cross-sectional view of the steps of internally connecting the devices of Figures 11A and 11B;

FIG. 14 is a cross-sectional view showing the steps of connecting the connecting device of FIGS. 11A and 11B to another device;

Figure 15 shows a cross-sectional view of connecting and internally connecting three devices;

Figures 16A-16D show the connection of three integrated circuits;

Figure 17A is a laminated internal connection structure;

FIG. 17B is a diagram of connecting the internal connection structure of the stack of FIG. 17A to a substrate with an integrated circuit;

Figure 18 is one of the circuit elements of the -2D array;

Figure 19 shows the circuit elements of the 2D array connected and internally connected;

Figures 20A-20F show the integration method according to the present invention;

Figure 21 shows an exploded view of the integrated device according to the present invention;

Figure 22A shows the backside package;

Figure 22B shows the top surface package;

Figures 23-34 show cross-sectional views of a method for integrating solar cells according to the present invention;

Figures 35 and 36 show the integration of devices with holes;

Figures 37A-37D show the connection of a plurality of molds or devices to a substrate according to the present invention;

Figures 38A and 38B show the connection of a connecting device to a circuit board or package.

Description of preferred embodiments

Now please refer to the drawings, especially FIG. 1, which shows a first specific embodiment of the method and device according to the present invention. A substrate 10 has an upper surface 11 having a surface flatness. The substrate 10 is preferably a first-generation substrate or an integrated circuit wafer. The non-flatness of the surface 11 shown in FIG. 1 is for illustrative purposes, and does not mean that the actual surface flatness is described. The substrate 10 preferably has a relatively smooth and flat surface 11. The required flatness and flatness of the upper surface can be achieved by polishing. Chemical mechanical polishing or CMP is a method to achieve the required flatness and planarity. The CMP process can be optimized by appropriately selecting the polishing pad, slurry, and polishing conditions to achieve the required surface roughness and flatness.

On the surface 11, a thin film 12 with a thickness greater than the surface non-planarity of the surface 11 is deposited. The film 12 must have good thermal conductivity and a high dielectric constant, such as SiO ₂ , Diamond, or diamond-like carbon (DLC). Preferably, the thermal conductivity is 1 _－ 10wCmK range, and the relative dielectric constant is in the range of 1-3. The preferred range of the thickness of the film 11 is 1-10 times the non-planarity of the surface of the film 11. Then the upper surface 13 of the film 13 is ground into a flat surface with a roughness of 5-15, preferably between 5-10. A flat surface with a roughness5 is the best flat surface, which can enhance the connection characteristics of the film.

It is also possible to deposit the thin film 12, grind the upper surface 13, then deposit other thin films (14 in Figure 2), and grind the second thin film to achieve the flatness required for the upper surface (15 in Figure 2) Spend. Three or more films, which can repeat the deposition and polishing operations for each or at least the upper film _， It can be used to achieve the required surface roughness and flatness.

The substrate 10 is now ready for wafer bonding. Any type of substrate can be connected to the substrate 10. 3, a substrate 16 is preferably an integrated circuit wafer containing active devices, which is prepared in the same manner as the substrate 10, by forming a thin film 17 that exposes the surface 18 _， Its surface roughness is in the same range as the surface 13 of the film 12 (or the surface 15 of the film 14). A higher degree of planarity can further constitute the joining process. The film 17 can be formed into one or more stacks using one or more grinding operations, as described above. The surfaces 18 and 12 can be brought into contact with each other (as shown by the arrows in Figure 3). A connection like Van der Waals can be formed between surfaces 18 and 13 (Figure 4). A stronger connection can be achieved by subsequently heating the bonded substrate and film.

The best way to connect is to connect directly _， There is no need to apply pressure, voltage and temperature. If the substrate has a SiO ₂ The upper surface (or other connecting materials), it does not need to deposit other SiO ₂ Lamination to grind the surface, which assumes SiO ₂ The upper surface has enough thickness to achieve a sufficient surface roughness and flatness, such as CMP.

example

This example uses an example of attaching a material such as GaAS, InP or GaN to a diamond substrate when it needs to optimize thermal packaging and dielectric performance. A substrate connected to a material with high thermal conductivity allows better management of heat transfer. The diamond substrate, after preparing its connection, has a relatively flat upper surface. Basically because the diamond substrate has a relatively rough surface, a relatively flat and flat upper surface can be achieved by grinding. However, grinding is expensive and it is difficult to consistently obtain a very smooth surface. It is also possible to use a copper susceptance material to form the diamond substrate. The diamond film basically removes the copper susceptibility after the deposition when the temperature is lowered, and it leaves a fairly smooth and flat surface when the growth starts, and a rougher surface when the growth ends.

A thin layer of silicon dioxide is deposited on the upper surface of the upper surface. The thin layer of silicon dioxide must be thicker than the non-planarity of the diamond surface, for example: 1 to 10 times, but it should be as thin as possible to optimize performance. Then the silicon dioxide layer is ground into a flat surface suitable for wafer bonding, such as 5. The diamond substrate with a thin silicon layer is now ready for wafer bonding.

At this time, any device formed on any type of substrate can be connected to the surface of the silicon dioxide layer. For this example, a multiple junction bipolar transistor (HBT) can be used, as described in the patent application serial number 09165,203 _， This document is cited here as a reference. The HBT system is processed to such a degree that it can be prepared to attach a first-generation substrate ^， As shown in Figure 5. Basically, this will include the steps of forming the emitter metallization, and performing base etching, performing base metallization, performing a passivation/planarization stage, and applying a thermal shunt. In FIG. 5, a collector layer 22 is formed on a GaAS substrate 20, a planarizing material 21, a base region 23, a base contact 24, and an emitter 25 reflecting a pole contact 26. It should be noted that the single device shown in Figure 5 is not a limitation. A wafer containing several devices or an integrated circuit can also be connected in the same way.

Another very thin layer of silicon dioxide 27 is deposited on the flattened surface of the HBT. The thickness of the silicon dioxide layer 27 is larger than the non-planarity of the planarized surface of the HBT (eg, 1 to 10 times), but it must be as thin as possible to optimize performance. The surface of the silicon dioxide layer 27 is polished to a flatness sufficient for wafer bonding, for example, 5. The stacks 27 and 12 are then joined by placing them together. The surface is preferably placed relatively close after a wet cleaning process, which is followed by a drying process to drive off the liquid between the stacks 27 and 12. It forms a Van der Waals connection. A stronger bond can be achieved by subsequent heating and bonding of the laminated layers 27 and 12.

When laminates 12 and 27 are heated after bonding _， It generates stress, which can cause some toxic effects in the formed device and substitute substrate. It is possible to form a stress relief layer between the diamond substrate and the silicon dioxide layer, and between the HBT device and the silicon dioxide layer 27. These are the films 28 and 29 of FIG. 6. The stress relief layer is a composite layer of homogeneity or material, that is, Young's modulus, so that this laminate will yield stress applications before other laminates.

When the connection has been described using a silicon dioxide film polished to a desired surface roughness, other films may also be used. For example _， Silicon or DLC can also be used. When silicon is used, oxygen can be implanted into the bonding layer below its opposite surface to form a conforming layer. The conforming layer is a stack equivalent to the stress relief layer. It is better to use Si, Sic or DLC film instead of SiO ₂ Thin film, for example when it is necessary to improve thermal conductivity.

It is also possible to select the passivation/planarization material in the device to be connected, thereby optimizing the dielectric constant, thermal conductivity, and impedance adjacent to the active device. In particular, DLC is very effective due to its relatively high thermal conductivity and low dielectric constant compared to other materials.

As shown in FIG. 5, the HBT device 14 is basically formed on the substrate 20. After connecting the device to the substrate 10, the substrate 20 can be processed such as grinding, or milling and grinding, allowing close access to the back contacts.

In the second embodiment of the present invention, N 2D array devices are connected together by repeating the method described in the first embodiment N times. Starting from the connecting device shown in FIG. 7 (the HBT device shows no component details, such as 30), the substrate 20 will be removed as necessary, and the exposed surface of the device 30 will be polished to become suitable for wafer bonding Flatness. Grinding and milling can be used during the removal of the substrate 20. Another silicon dioxide layer 31 is deposited on the surface of the exposed device 30 and ground to the desired surface roughness in the manner previously described on the laminate 12 or 27 (Figure 8).

In FIG. 9, the next wafer of the substrate 34 without device details such as 32 is shown, which has a thin silicon dioxide layer 33 formed on the surface opposite to the substrate 34. The film 33 is formed and polished in the same way as the films 11, 27 and 31. The film 33 is then attached to the exposed surface of the laminate 31. The resulting device is shown in FIG. 10 after the substrate 34 is removed. The upper surface of the second connecting device is polished again, and another silicon dioxide layer 35 is deposited to prepare for connecting a third device. This can be done N times to produce an N-time integrated device. The device thus connected can be vertically internally connected.

example

Examples of connections between multiple devices can be seen in Figures 11A, 11B and Figures 12-15. Figures 11A, 11B and Figures 12 to 15 show how the connection is used to integrate two 2D device arrays according to the present invention, how it is interconnected to form a vertically integrated multiple wafer module, and how to combine different technology.

Figures 11A and 11B show two devices to be connected. In this example, the devices of FIGS. 11A and 11B are different integrated circuit wafers with internal connections. In FIG. 11A, an intrinsically symmetric HBT (SIHBT) wafer includes a SIHBT substitute substrate 40, a planarizing material 41 formed on the substrate 40, the SIHBT device 43 and internal connections 42 and 44, which are preferably made of a metal form. Figure 11B shows a VCSEL device with a VCSEL substrate 45, planarizing material 46, VCSEL device 48 and interconnections 47 and 49, which are again preferably made of metal. As shown in Figure 12, the devices of Figures 11A and 11B are connected in the aforementioned way _， That is, a material like silicon dioxide is deposited on the upper surface of each device, and then ground to a surface roughness of about 5-10. It also requires a high degree of flatness. The connected device is shown in Figure 12.

Next, as shown in FIG. 13, the substrate 40 is removed to expose the internal connection 44. A via 50 is etched through the planarizing material 41 and into the planarizing material 46 to expose a portion of the interconnect 47. When a via 50 is shown, it can be understood that any number of vias can be formed to form an appropriate device connected to the two connected substrates.

The internal connection 51 is formed in the via 50 to internally connect the devices 43 and 48. At this time, the process can be stopped when only two wafers are needed to join. If one or more devices need to be further integrated ^， The process can be continued by forming a connecting layer 52, for example made of silicon dioxide ^， Then it is ground to a surface roughness of 5-10, which is carried out by the aforementioned method. In this example _， The process may include the step of filling any cavities formed in the interconnection 50 _， This makes it easier to manufacture a flat surface of the laminate 52. The device is shown in Figure 14, which is ready to be connected to other wafers when needed.

For wafers of different technologies, the planarization materials can be the same. The two different technologies are separated by a stack of planarizing materials that do not affect each other. Each of them only interacts with the planarizing material. Because the characteristics of the planarization materials are known and are often used in current manufacturing processes, no new materials are needed to combine the technology. The present invention provides a way to combine different technologies to produce and manufacture.

Furthermore, all customization is carried out at the end of the process. The two types of wafers are manufactured separately and then joined together. The internal connection is executed after the connection. Customers of combined technology do it at the end of the process. Regardless of which technology needs to be obtained, these technologies are currently available and commercially available. There is no need to design a new manufacturing process. It is possible to have a well-defined control in the final combined product. A device manufactured with a stable process can be selected to be combined with an unproven process instead of being considered new. It can provide a small number of manufacturing, reliability or Long-term information.

The structure of connecting a third wafer to FIG. 14 is shown in FIG. 15. It can be noted that FIG. 15 shows an additional metallization 53 formed by etching planarization materials 41 and 46, thereby exposing a part of the internal connection 60 of another device with elements 60-62. The inner connection 53 has an extension on the surface of the planarizing material 41 to form an inner connection on another level. In this example, the device in the third wafer may be a CMOS device 56 with internal connections 55 and 57. Another via is etched through the planarization material 58 and through the joining material 52, exposing a portion of the interconnect 51 to allow connection to the interconnect 59. The internal connection 59 is also connected to the internal connection 55 of the CMOS device 56. The other interconnection is formed by etching a via through the materials 58 and 52, thereby exposing a portion of the interconnection 53. An internal connection 54 is formed to contact the internal connection 53. It should be noted that FIG. 15 does not explicitly show the connecting layer formed between the devices, but it can be understood that these are used in the first embodiment as described above. The device formed by the manufacturing process.

It can also be understood from FIG. 15 that the present invention uses both sides of a contact at the same time. For example, if the pad above the contact 51 is a contact pad or a metal wire, the bottom surface of the pad (or wire) is connected to the inner connection 47 located below the pad (or wire), when The upper part of the pad (or wire) is connected to a contact 59 that overlaps with the inner connection 55. This can reduce the demand for drivers.

FIG. 15 also shows that the advantage of the present invention is that it is not limited to one stack (or two stacks) for the circuit topology. It has the ability to design in three dimensions. The circuit layout can be optimized if it has the ability to distinguish the form type of the device, where the functions or processes interfere with or are incompatible with each other. The circuit layout uses three dimensions instead of only two dimensions, so the area can be minimized. change. For example, three conventional wafers with basically the same area, with different technologies as required, can be implemented by stacking vertically and using only one-third of the area. The area reduction can be even greater when considering reducing the packaging requirements of individual wafers for the stacked wafers. Vertical stacking can also conduct ground, bias, or other planes between the wafers, or in the wafers during routing to improve signal isolation.

Basically, in a system, the signal is amplified and then transmitted on the bus between integrated circuits. This requires considerable level shifts, buses, and compensation for different differences in signal levels among the components that make up the system. As in the same example, a pixel in a light detection device receives a very small charge packet, which is then shifted out of the device and into a memory device. In this example, the light detection device and the memory are both independent integrated circuits, which need to amplify the charge packet through the buffer and the system bus between the pixel and the memory device. Then the signal level is lowered to store the information in a memory unit in the memory device. When the information in the memory needs to be processed, the information uses more buffers and system buses to shift its level again, so as to transmit the data to a processor, which can also use a Independent integrated circuit to form. The power level for different signals is determined by the internal connection and the bus.

The present invention allows to obtain communication and addressability between components. At present, the power of the signal can be determined by the component, not by the internal connection, that is, the system bus and driver. As an example, as shown in FIGS. 16A-16D, a first integrated circuit includes a pixel array for sensing a light signal, etc., which is fabricated on a first substrate (FIG. 16A). In a simplified manner, a pixel 72 is formed in a semiconductor stack 71, which is formed on a substrate 70. On a second substrate, the memory device needed to store the information that is removed from the pixel array is fabricated, as shown in FIG. 16B. A semiconductor layer 74 is formed on a substrate 73. The memory cell 75 is formed in the stack 74. Finally, a processor device for processing the information is fabricated on a third substrate shown in FIG. 16C. The various elements 78 shown (in simplified form) in the stack 77 are formed on the substrate 76. Then each substrate is joined together (with a pixel array on it to expose it to light).

The three substrates can be joined together. The first-generation substrate (not shown) can be attached to an upper surface of the stack 71 using the aforementioned technique, and the substrate 70 can be removed. Then the u-shaped surface of the stack 74 of the memory device can be connected to the surface exposed by the removal of the substrate 70. The substrate 73 can then be removed, and the upper surface of the stack 77 is connected to the surface exposed by the removal of the substrate 73. The substitute substrate can be removed to expose the pixel 72. The internal connection can be made directly between the three substrates by the above-mentioned method, which can eliminate the need for many buffers _， And when the system is designed to use an independent integrated device, it needs to be internally connected to the system bus of the system. The connected circuit is shown in Fig. 16D. It can be noted that FIG. 16D does not show the different stacks used to connect different devices, and the portions of the stacks 71, 74, and 77 can be removed during the removal of the corresponding substrate as needed.

Another example is a typical microprocessor, where the microprocessor contains a certain amount of on-board ROM, when a large amount is stored in a separate RAM and accessed through the system bus. In this example, the processor and the on-board ROM can be fabricated on a first substrate, and the memory can be fabricated on a second substrate. The two substrates can be connected together, and the processor is directly connected to the memory device, which again eliminates the need for system buses, level shifters and other buffers.

The present invention not only allows the system to be manufactured in a smaller way and direct access way _， But a smaller footprint is also allowed. Each of the aforementioned independent devices is at least three times the amount of space required when stacked on top of each other in the present invention, assuming that the wafers occupy almost the same size.

A fourth embodiment of the present invention uses the aforementioned technology to fabricate the internal connection from the integrated circuit under it. Basically, the circuit needs some levels of internal connections to provide all the required complex functions. It requires 6 or more inner connection levels. This requires a considerable amount of heat treatment, exposing the underlying active device to a higher thermal burden, and complicating the manufacturing process. The present invention can be used to separately manufacture active devices, and then the connection is formed according to the present invention to form a hierarchy of internal connections. In particular, each internal connection level can be formed on a separate substrate _， Then connect them together as needed and make internal connections. Several or all interconnect layers can be manufactured at one time. The bonded together or single interconnected substrate can then be bonded to the substrate with the active device. It can use techniques similar to those shown in FIG. 15 for interconnecting different wafers as described above. When completed, the stack of interconnected layers can be connected to the active device.

This is illustrated in FIGS. 17A and 17B, in which interconnect stacks with stacks 80-83 are connected according to the principles of the present invention, and then connected to the integrated circuit shown in FIG. 16B or 16C as shown in FIG. 17A. Figure 17B shows the complete device of the stack used for the joining process, which is omitted for clarity. In this example, the substrate of the integrated circuit can be removed and connected to a better thermal material, such as diamond-like carbon. With this specific embodiment, it can obtain tighter process control, which does not require compensation or compromises for the different effects of the increased thermal load, which is due to the multiple overlaps in the integrated circuit on the active device. Due to the basic treatment of the layer.

Another application of the present invention is the selection of the internal connection layer. By being able to handle the internal connection independently, more design flexibility can be obtained. For example, some stacks that process high-speed signals can be more critical than others. The critical levels can be separated from each other by other non-critical stacks, thereby minimizing overlap. Conversely, non-critical laminates can be placed in adjacent laminates when overlap is not a problem for the high-speed operation of the device.

In addition to the above specific embodiments, the substrate of the integrated circuit can be completely removed in the above specific embodiments. The result is a 2D array of device elements trapped in the insulating planarization material. An example of this is shown in Figure 18. Each element can be completely isolated between each element, and relative to a circuit layer 2-D device array. A second wafer to be joined can be processed in the same way, which constitutes another array of 2-D device elements. Then the device array can be internally connected in the required way to generate circuits and sub-circuits. This can be extended to connect different technologies, such as CMOS and bipolar, to produce a BiCMOS wafer. In this example, the most advanced CMOS and bipolar technologies can be combined by processing two wafers separately. Then, when it is necessary to produce a combined technical device or circuit, the existing advanced and proven technology can be used instead of having to design a new combined process or build an existing combined technology, which does not use And cannot take advantage of the most advanced technology or technological development.

The third wafer and subsequent wafers can also be processed when the substrate has been removed and is ready to be interconnected to the first and second arrays. The third device can also be another technology. Figure 19 is an example.

The wafer bonding may include connecting an integrated circuit or device to another substrate for thermal diffusion, impedance matching, or RF isolation, an antenna or a matching network containing passive components. Combinations of these elements can also be integrated. Partial or complete substrate removal can be included in this embodiment. The circuit or device can be connected to the antenna, expander or other components.

An integrated T/R module can also be integrated with an output transmission power amplifier or other wafers in a MEMS on a substrate. An input receiving wafer can be integrated on the second wafer or a third wafer. Appropriate shielding or isolation can also be integrated in the module and an antenna formed on a wafer.

Optical devices, such as lasers and detectors, can be integrated on one wafer with optical interconnect circuits on another wafer. The device can be integrated into a sufficient part of a wavelength to operate as a superimposed device, so there will be impedance mismatches between devices, which will not cause significant reflection or power loss. The resulting optical architecture allows the present invention to operate at high speed due to low parasitics, and can operate at low power due to avoiding the problem of impedance mismatch that restricts the conventional optical I/O architecture.

The wafer connection can also follow FIGS. 3 and 4, where wafer 10 is a device or circuit wafer, and wafer 16 is a supporting and packaging material as described below. This particular description is of special interest to a packaging technology that can provide improved thermal performance _， Improved noise performance, power, grounding, clock and/or signal line isolation, improved radiation performance, reduced resistance, capacitance and inductance, increased power to ground coupling, etc. After linking ^， The substrate from the device or circuit is sufficiently thinned or completely removed. The remaining part of the substrate may not exceed 10 to 20 μm. Additional processing can be carried out to the remaining silicon substrate or backside, in addition, if the substrate is completely removed on the backside of the stack containing the active device.

For example, the via can be made on the bottom side of the "pad" located on the "front side" of the wafer. These "pads" can be optimized for this purpose, and therefore have a significantly different structure from a typical mat. For example ^， The pad is basically a via window, which starts on the front side of the wafer and is internally connected from the back side. In the example shown in FIG. 20A, the base contact 90 has a via structure that extends to the back of the device ^， It is now exposed by removing the substrate. Figure 20B shows an extended metal contact 90A, which can be accessed through a suitably placed via.

It can form different forms of vias. For example, the via window can be formed in the "top" inner connection level, a "lower" or a "first" inner connection level is next to the device, or the active device can be formed directly from the backside. After making these different forms of vias, an internal connection can be formed in the vias _， Therefore, interconnects are made on the front side of the wafer or directly at any level of interconnects on the active device. Additional levels of metallization can also be formed on the "back side", which is similar to the multiple interconnection levels formed on the "front side". After completing this "backside" process, the wafer can be molded and packaged according to typical methods such as wire bonding and ball grid arrays.

This architecture allows power, ground, clock, and signal routing to be on one or both sides of the active device layer. For example, power and ground can be routed on one side, and ground, clocks and signals can be routed on the other side. There may also be other architectures _， And can use the combination of architectures as needed. This architecture allows the reduction of resistance, inductance and capacitance, and allows the interaction between different forms of internal connections to be minimized, such as power and signals, or maximized, such as power and ground, as needed.

An example is shown in Fig. 20C. It should be noted that the dimensions (and other drawings) shown in Figure 20C are not drawn to scale, but are drawn for illustrative purposes. The dimensions shown are not meant to limit the invention. A pair of devices 105 and 106 can be internally connected with other circuit elements (not shown) through some internal connection layers 93-95. The device is connected to a material that can be used as a mold attachment. The via 102 is filled with interconnects 101 connected to the "top" interconnect layer 93. The via 100 is filled with interconnects 99 connected to an intermediate interconnect layer 94. The via 96 is formed by connecting the device area 104 and the internal connection 97 through the stack 103. The stack 103 can be the remainder of a substantially thinned original substrate, or if the original substrate is completely removed, a stack between the original substrate and the devices 105 and 106, or the substrate shift After removing a stack formed on the devices 105 and 106. When marking the material to separate the different interconnection stacks, it can be regarded as an insulating material.

Another example is shown in FIG. 20D, in which two devices 180 and 181 are connected to the device to be connected through substrates 185 and 187 from both sides. The internal connections 182, 188, and 189 are formed through the substrate 185, and the internal connections 183 and 184 are formed through the substrate 186. The substrates 185 and 186 and the device may include flat layers for bonding as described above.

It must be noted _， The vias made at different levels can pass through semiconductor materials. In this example, measurement needs to be performed before filling, such as oxidizing the exposed semiconductor material in the via. at the same time ^， The device can be formed on an insulating substrate, and the region through which it passes will completely insulate the formed via. This can be achieved, for example, by completely oxidizing the semiconductor material in the area through which the vias pass, and completely etching away the semiconductor material, and refilling with insulating material, or both.

Please note that a thermal diffusion material can also be used as the mold attachment material 92. It can further be a composite material. The composite can be optimized, for example, it can be mostly copper and can be connected to the mold, and it can contain another material to be conducted to the mold compartment, where it can be connected to the channel between the molds.

This architecture further provides improved thermal resistance compared to conventional packages. For example _， A typical package has a silicon substrate between the active device layers, which generates heat, and the mold is attached to the package. This silicon is basically ~600 microns, but can basically be thinned to ~300 microns. The limitation on thinner production is determined by destruction. The heat generated in the active layer is basically conducted through the 300 micron substrate to a copper heat spreader, or a similar thermally conductive material _， And thus constitute a radiator to the surroundings. The specific heat spreader is basically ~24 milS thick or ~600 microns. Because the thermal conductivity of copper is about three times that of silicon, there will be more than half of the temperature rise in the silicon substrate in this part. In another wafer bonding structure, when the material 92 is a copper-like material with a thickness similar to the conventional plug, the temperature rise is reduced by more than half, because the temperature drop through the planarization material is for proper In terms of flattening material and thickness _， Because the temperature drop across the planarization material is negligible compared to the temperature drop across the silicon substrate, the temperature rise will be reduced by at least half. Examples of suitable planarization materials and thicknesses are 0.5 microns of silicon dioxide, and 5 microns of silicon nitride.

Please note that if the efficiency of the radiator can make the heat spreader negligible without causing a significant increase in the temperature of the radiator, a very large reduction in temperature rise can be achieved. In this example, the temperature drop of the silicon nitride passing through about 2 microns is about one tenth of the temperature drop of 300 microns of silicon passing through the same heat flux, which can cause the temperature of the part to rise by about ten. one.

A further improvement in thermal resistance can be achieved by a second packaging material attached to the backside of the device or circuit wafer by the wafer, which is after the substrate is significantly thinned or completely removed, as shown in FIG. 20E . In this example, the substrate 103 is completely removed, and a second packaging material 107 is attached to the surface exposed by removing the substrate. The substrates 92 and 107 can be selected to have high thermal conductivity, and can more effectively diffuse and remove heat from the device. Access to stack 93-95 or to the active device itself ^， Both can be formed by one or two substrates 92 and 107, which are based on the form of interconnection or package structure.

The joining of the substrate 107 can also be completed after further backside processing, as in the example provided previously. Substituting another material for the silicon substrate can reduce the thermal resistance. When used to remove heat from the front side as described above, the thermal resistance can be further improved. The heat sink can be applied to the front surface and the back surface, or the front packaging material and the back packaging material can be thermally insulated with a suitable material.

The sandwich structure of the device or circuit wafer and appropriate materials is used when it is used to match a ball grid array packaging technology, or another packaging technology does not use a ball grid array _， But when using another real contact method in subsequent assembly ^， Is the best. FIG. 20F shows the use of a ball grid array and balls or bumps, and under-bump metallization 108 to interconnect the structure of FIG. 20E to the interconnection level. The ball grid array method can be directly applied to this description by forming a connection through the packaging material to the desired connection point, and then proceed to appropriate under-bump metallization and ball grid formation.

An example of a packaging technique that does not use a ball grid array is shown in FIG. 20G. This example uses a peg grid array 201. This array is formed in the substrate 92, which includes the peg grid array 201 and the interconnect 202 between the stacks 93-95. The bolt can be pressed into a board, card, base plate or other sub-components later. This assembly method can eliminate the need for solder bumps, underfill, etc., and can basically be used for advanced packaging. In addition, the exposed surface of 92 may be formed with an exposed contact area 203 _， It can be internally connected to laminates 93-95, which can subsequently be pressed into a peg grid array formed on a board, card, substrate or other sub-component.

The packaging method and device can also withstand thermal stress. Basically removing all silicon except in the active device area allows the remaining silicon to be significantly more compatible with the packaging material. Further compatibility of the silicon can be achieved by etching or removing all silicon between the molds after the substrate is thinned or completely removed. Maximum compatibility can be achieved after thinning or completely removing the substrate _， This is achieved by removing all silicon except where each active device is located. In this example, the silicon device is not connected to silicon, but is connected to planarization material and interconnect metallization. It is also possible to remove moderate amounts of silicon.

Compared with typical methods, this architecture can reduce stress and improve reliability. Appropriate selection of the packaging material and/or the mold attached to obtain an acceptable strain material _， It can further reduce the stress and improve the reliability of damage caused by strain in typical methods such as ball grid arrays.

The wafer bonding can combine this component with other components to manufacture a system or a system's functional components. Figure 21 shows an exploded view of the integrated system according to the present invention. In this system, a high-density low-speed device 151 is integrated into a high-speed low-density device 153. Other passive components such as heat spreaders, isolation layers and antennas can also be included.

On a substrate 150, the remaining part of the wafer 151 of a high-density low-speed silicon integrated circuit with components 155 and internal connections 156 is connected. The substrate of the wafer 151 has been removed. In the above method, the wafer 150 may be a heat spreader. A low-density high-speed device 153, such as an HBT device (shown after removing the substrate) _， It can be connected to an insulating substrate that has been linked to the wafer 151. The substrate 152 can have electrical and thermal insulation properties, and it can also be a heat spreader _， Made of carbon like diamond or diamond-like. A via is formed in the substrate 152 (not shown), which allows the connection between the silicon device in the wafer 151 and the HBT in the wafer 153. On the wafer 153, a package substrate 154 having contact pads 159 is connected. In addition, the substrate 154 may be an antenna having a chip antenna 159 to receive the signal input to the HBT. Internal connections (also not shown) can be formed between the substrate 154 and the devices on the HBT wafer _， And if necessary, between the substrate 159 and the wafer 151.

Another system can be formed on a microprocessor with a high-density embedded memory. A microprocessor on a wafer (such as 10) can be connected and internally connected to a second wafer (such as 16). This architecture increases the communication speed by reducing the parasitic capacitance between the processor and the memory device, resulting in a significant increase in bit width. Power consumption can also be reduced by eliminating the level shift between the I/O driver and the processor and memory. This architecture further allows memory to be increased compared to the conventional method of embedding memory on the chip. _' Memory body. Furthermore, the processor and memory design and manufacturing processes can also be optimized separately to produce a combination of optimized design and manufacturing devices _， There is no need to compromise the design and process because they need to be manufactured on the same wafer, or the two devices must be connected internally at the circuit board level.

The wafer bonding also includes bonding a substrate, which is mainly used as a mechanical support to a device or circuit wafer. This can be seen in FIGS. 3 and 4, where the wafer 10 is a device or circuit wafer, and the component 16 is a supporting substrate. The substrate of the device or circuit wafer 10 can then be partially or completely removed ^， The wafer can be packaged by being connected to the "backside" of the wafer where the substrate has been removed. For example, FIG. 14 shows the wafer 41 where the substrate 40 has been removed and the interconnection 51 has been formed. As shown in FIG. 22A, the wafer 41 is mounted in a package 113 (shown in a simplified manner to illustrate the present invention). The thin film 52 of the wafer 41 is removed to expose the interconnection 51. A connecting pad 110 is formed on the inner connection 51 _， It is connected to the packaging pad 112 by a cable 113. It does not show terminals connected to other devices. Other package configurations, such as flip chip mounting are also possible. It is also possible to integrate three or more components or wafers, which include a multilayer interconnection. These methods and devices may also include omission of elements 46 and/or 45.

In another case _， A device or circuit wafer is connected to a first substrate, and the substrate of the device or circuit wafer has been removed. A second substrate with better thermal, isolation and/or mechanical properties is then attached to the side of the device, or the circuit wafer exposed after the substrate is removed. The first substrate is then removed to expose the top side of the device or circuit wafer. Starting with the device shown in FIG. 6, the substrate 20 is removed, and a second substrate 115 is attached to the back side of the HBT device. The substrate 10 is then removed, and the top side of the HBT device is exposed. The integrated device can then be installed in a package 116, as shown in Figure 22B. A connecting pad 117 is formed on the contact 26. The pad 117 is connected to the package pad 119 through a cable 117. It does not show terminals connected to other devices. Other package configurations are also possible, such as using a device with multiple layers of interconnects to connect to and flip chip mounting.

Stacked solar cells can also be integrated according to the invention. In Fig. 23, a cross section of a first solar cell is shown. The solar cell 120 includes a back contact 121, a substrate 122, an active area 123 and an upper contact 124. The battery 120 is then flattened with a bonding material 125 and ground to have a high degree of flatness and smoothness (FIG. 24 ), which is in accordance with the method of the first embodiment. The back contact 121 may also be omitted in subsequent forming after the substrate is substantially thinned or removed.

It prepares a second battery 126, which has a substrate 127, an active area 128 and contacts 129 (Figure 25). In FIG. 26, the bonding material 130 is deposited on the battery 126 and planarized in the manner discussed in the first embodiment. The batteries 120 and 126 are connected together, and the substrate of the battery 126 is removed, for example, by overlapping and grinding as shown in FIG. 27. Vias 131-133 are formed to expose part of the contacts 124 and 129 (Figure 28), internal connections 134 are formed in the vias (Figure 29), and contacts 135 are formed to the second battery (Figure 30).

The solar cell integrated according to the present invention can have increased efficiency while maintaining a high degree of optical transparency between cells. It can also achieve low internal connection resistance and high mechanical strength. The stack shown in this example can reduce the contact area by about half, which can be used by a typical contact (<10 ^-5 ohm-cm ² ) And internal connection resistance (<10 ^-6 ohm ^- cm ² ) Accepted. Both single-junction reverse-series junction batteries can be stacked using the present invention. The mechanical stacking of the present invention may avoid the integration with epitaxial technology, which may cause limitations on the lattice growth of series or series-connected batteries. It further provides improved mechanical strength compared to other mechanically stacked solar cells, and can be mechanically compatible with temperature changes by substantially or completely removing the substrate. Optimized compatibility is achieved by removing the active layer between cells on a substrate, and/or by designing the via and interconnection pattern to over-reducing the continuous active layer on the entire substrate area. The laminated area is similar to the previously described packaging.

More batteries can be stacked using the present invention. As shown in FIG. 31, the connecting material 136 is formed by stacking on the battery in FIG. 30, and is flattened in the above-mentioned manner. A third cell with a planarized connection material 137, contacts 138 and a substrate 139 are connected on the material 136 (Figure 32), and a via 140 is formed (Figure 33). Then the contacts 141 and 142 are formed (Figure 34). 35 and 36 show another aspect of the present invention, in which a cavity is formed in a substrate 143 before or after the surface is flattened. Subsequent bonding to a second wafer 145 can create an intentional void near the bonding interface 146. The cavity can be a via window for subsequent connection to the device located on the wafer 143.

The integration method according to the present invention may further include the connection of wafers, molds and surfaces in different regions. Examples of how to accomplish this include first, attaching a small area to a larger area, and then connecting that larger area to another larger area, or second, connecting a small area to a larger area as follows area.

For example, in the first method, it needs to integrate an optical device and an electronic circuit to realize an electronic circuit with optical input/output (I/O). In this example, the area required by the optical device (such as vertical recess emission lasers (VCSELs), pin light diodes, etc.) is basically or much smaller than the area required by the electronic circuit. Furthermore, the size of the wafer required for the manufacture of the optical device is basically smaller than the size of the wafer where the electronic circuit is manufactured. Therefore, it is not suitable for connecting the smaller, wafer and a higher area density of devices/circuits to a smaller area density of devices/circuits, because the electronic circuits will be integrated in more than necessary Optical device, or optical device is not required.

In a preferred method, the molds that need to be connected are divided into smaller wafers with conventional dice, and the separate molds are combined on a carrier wafer, the size of which is similar to that of the wafer containing electronic devices. , And the larger wafer and the connected carrier wafer. This is shown in FIG. 37A, where a smaller mold or device 162 is attached to a substrate 160 with a bonding material 161. Then the substrate removal will occur if necessary, and the internal connections between the connected devices can be made using the methods described above. The mold separation may preferably be performed before the planarization of the wafer containing the mold required for wafer bonding. The mold can also preferably be tested before this flattening ^， And to assist in the differentiation before assembling to a larger wafer.

The mold assembly on a larger wafer can be completed in different ways, including forming a recess in a specific position, and it can be adapted to other wafers containing the required electronic devices, as shown in Figure 37B , Where in the recess 167 or the substrate 163 is a connecting device 165 using connecting materials 164 and 166. It may also be other methods, including mold attachment. For example, the connecting materials 164 and 166 can be omitted when the size of the mold and the recess are suitable for press-fitting anastomosis.

After the mold is assembled on the carrier wafer, the resulting wafer can be planarized to be joined to a larger wafer with electronic devices. This flattening can be performed in a manner suitable for the assembly of the mold. For example, if the mold is assembled in a recess, the recess can be formed to conform to the thickness of the mold so that the surface of the mold can correspond to a larger wafer surface. 37C and 37D show the planarization of the structure shown in FIGS. 37A and 37B, respectively, and the connection to the corresponding substrate. In FIG. 37C, a wafer 160 with a device or mold 162 is bonded to a substrate 170 using bonding materials 168 and 169. The wafer 170 preferably contains an electronic device, which is internally connected to a mold or device 162. At the same time, the wafer 170 may be a heat spreader, and another substrate may be connected to the device or mold 162 by the other side of the substrate 160 to be removed next. FIG. 37D is similar to the connection of the substrate 163 to the substrate 173 when the connecting materials 171 and 172 are used.

In addition, the wafers assembled by the mold can be joined without the need to planarize the entire wafer. For example, the mold may be assembled such that the mold is higher than the wafer on which it is assembled, and it may be substantially the same height. In this example, the subsequent connection mainly occurs at the assembled mold, and it does not exceed the entire surface of the wafer including the assembled mold. Removing the substrate of the wafer after the wafer is joined can thus effectively achieve mold separation before the mold substrate is completely removed. After completion of the mold substrate removal (or subsequent entire substrate), the mold can be internally connected to the electronic circuit as described above.

Furthermore, according to the above-mentioned second method, a method similar to the first method can be performed without the need to assemble a smaller mold on the carrier wafer. In this example, the smaller mold can be independently attached to the larger wafer. After the smaller mold is independently connected, and its substrate is completely removed for the substrate removal in this example, a template of similar material to the mold or roughly removed, it can be internally connected as described above To the device or circuit. Substrate removal can be attached to the mold surrounding the connection to make a better surface to remove the substrate, which includes grinding, overlapping, etc.

The carrier wafer to which the smaller mold is connected may have other functions besides containing the aforementioned electronic circuits. For example, the larger wafer can also be used for rerouting and interconnecting smaller molds with each other. It also has other uses. In this example, referring to FIG. 37C as an example, different devices 162 can be connected through both sides of the wafer 160 and made through the substrate 170. The thinning of the substrates 160 and 170 can preferably reduce the thickness of the via.

Figures 38A and 38B show another method of internally connecting a device and a circuit board, computer card, motherboard, etc. The device can be a device connected as described above ^， That is, a device connected to a packaging material. The connected packaging material may have a topography before the connection, or form a topography after the subsequent vias and internal connections can be contacted after the connection. This terrain uses general processing to allow a press fit, cold welding, sonic welding, or low temperature thermal sonic connection, etc., so as to be formed between the terrain and a motherboard, integrated circuit board, computer card, etc. , This system is designed to fit this terrain. The topography can be made by etching the packaging material or depositing an additional material. Depending on the quality and form of the materials used, the terrain can have an aspect ratio ranging from flat to sudden peaks. This topography may be present on the packaging material and/or on the board to which the packaged device or circuit will be subsequently attached to the board. This attachment mechanism does not rely on increasing the temperature to re-flow the material to form a connection, as is made of solder bumps, ball grid arrays, etc. Therefore, it can significantly reduce stress and increase reliability. This method can also be manufactured at a very low cost, because the packaging of the device or circuit can be completed with the size of the wafer, and the solder bumps do not need to be applied or reflowed to form the packaged device/circuit component to the board, card Wait.

A more specific example is shown in FIG. 38A. On the upper surface of a device 200, it forms a peg grid array 201 with "pitches" 202. The tether is formed using conventional processing techniques, such as metallization, lithography, and etching. The bolt 202 is a metal structure with a narrow tip. The bolt 202 is designed to conform to the corresponding conductive structure, such as a metal pad on the circuit board, computer card, motherboard, etc. This narrow tip provides a secure electronic contact, and the conductive structure is counteracted by pressing down the plug. The peg is shown as having a pyramid shape, but there are other possible shapes. The plug 202 can be formed as small as possible, in a width range of 10 μm, and has an aspect ratio of 1:1 to 1:3. It should be noted that when the device 200 shows only a few pins 202, basically the device will have a large number of pins formed in an array, for example, a square or rectangular matrix of pins in some parts of the array or matrix may be omitted. .

FIG. 38B shows a board 203 with conductive pads 204, which are preferably metal pads formed in a pattern corresponding to the array of pins 202. FIG. As indicated by the arrow 205, the pin 202 is aligned and the corresponding one corresponding to the pad 204 is pressed down. It can be understood that very small contacts can be formed in an array to allow a large number of internal connections to be made between the connected device and the board or card to which the device is connected.

When special devices and materials have been described in conjunction with the first and second specific embodiments, the present invention is not limited thereto. The present invention can be applied to any type of device formed on any type of substrate. Furthermore, it can use any form of technology to manufacture the device to be connected. For example, a GaAS device on a GaAS substrate can be connected to an HBT device. At the same time, a silicon-based device formed on a silicon substrate can also be connected to the GaAS-based device or the HBT type device. It can also use CMOS, BiCMOS, npn and pnp HBT, VCSEL, PIN, HFET, MESFET ^， MOSFET,HEMTS,MEMls andJFET.

The method according to the present invention provides a three-dimensional laminated integrated circuit structure. The device is a multi-chip module with a high integration density, and has reduced internal connection parasitic capacitance compared with other multi-chip modules. The module provides a large shrapnel that allows it to be combined with different devices and different technologies.

Obviously, many modifications and changes of the present invention may also be suggested by the principles of the above disclosure. Therefore, it can be understood that in the scope of the attached patent application, the present invention can be realized without the need to specifically indicate here