Semiconductor device and manufacturing method thereof

Semiconductor device and its manufacturing method

Background of the invention

1. Field of Invention

The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device has a circuit structured as a thin film transistor (hereinafter referred to as TFT), and the thin film transistor is formed on a substrate with an insulating surface. In particular, the present invention provides a technology suitable for use in an optoelectronic device and electronic equipment including optoelectronic devices. The optoelectronic device has always been a liquid crystal display device with a pixel portion and a pixel portion on the same substrate. Provided drive circuit. Note that in this specification, semiconductor devices are represented as general devices that can take advantage of semiconductor characteristics, and above optoelectronic devices, and electronic devices including optoelectronic devices are classified as semiconductor devices.

2. Relevant technical description

In the optoelectronic device that has always been an active matrix liquid crystal display device, a technology using TFT has been developed to form a switching element and an active circuit. TFT uses a semiconductor film formed on a substrate such as a glass substrate with vapor phase growth as an active layer. In the semiconductor film, silicon or silicon germanium with silicon as its main component is appropriately used as a material. According to the manufacturing method of the semiconductor film, this semiconductor film can be classified as an amorphous silicon film or a crystalline silicon film, and has always been a polycrystalline silicon film.

A TFT that uses an amorphous semiconductor (it has always been an amorphous silicon) film as an active layer cannot achieve a few cm due to its origin from an amorphous structure or the electronic physical properties of the like.²/Vsec or greater electric field effect movement rate. For this reason, in an active matrix liquid crystal display device, no matter it can be used as a switchable element (hereinafter referred to as a pixel TFT) to drive the pixel portion of the liquid crystal, the TFT using an amorphous semiconductor as the active layer is no longer available. The driver circuit for image display is formed. Therefore, a technology has been used, using the TAB (automatic tape) method or the COG (chip on glass) method to mount as a driver IC for a driver circuit.

On the other hand, TFTs that use spar structure-containing semiconductor films (hereinafter referred to as crystalline semiconductor films) (which have always been crystalline silicon or polycrystalline silicon) as the active layer can achieve high electrical field efficiency mobility, making it possible to use the same glass Various functional circuits are formed on the structure. In the driving circuit, in addition to forming pixel TFTs of other circuits such as a shift register circuit, a level shifter circuit, and a buffer circuit on the same substrate, a sampling circuit has also been implemented. This circuit is formed by using a CMOS circuit as the basic circuit, which is composed of an n-channel TFT and a p-channel TFT. Due to the technology of mounting this drive circuit, it has become clear that the use of a crystalline semiconductor layer as an active layer of TFT is suitable to promote the reduction of the weight and thickness of the liquid crystal display device, and the crystalline semiconductor layer can form the drive circuit. And the pixel portion on the same substrate.

When compared from the characteristics of the TFT, the TFT using the crystalline semiconductor layer as the active layer is superior. However, in order to manufacture TFTs equivalent to various circuits other than pixel TFTs, there is a problem that the manufacturing process becomes complicated, so the number of steps is increased. The increase in the number of steps is not only a factor in increasing the production cost, but also obviously a reason for lowering the yield.

The operating conditions of the pixel TFT and the driving circuit TFT are not always the same. The consideration is that the required characteristics of TFTs are quite different. The pixel TFT is formed by an n-channel TFT, and a voltage is applied to the liquid crystal to drive the liquid crystal as a switching element. Liquid crystals are driven by alternating current, so a method called frame reverse driving is widely used. In this method, in order to suppress low power consumption, the required characteristic of the pixel TFT is to sufficiently reduce a non-conducting current value (the drain current flowing during the non-conducting operation of the TFT). On the other hand, because a high driving voltage is applied to the buffer circuit of the driving circuit and this circuit, the resistance voltage of the TFT must be increased so that it does not break when a high voltage is applied. Moreover, in order to make the current drive capability higher, an on current (the drain current flowing during the TFT on operation) must be adequately maintained.

As a TFT structure for reducing the non-conduction current value, a low-concentration drain (LDD: Lightly Doped Drain) structure is known. In this structure, a region doped with low-concentration impurity elements is provided. This region is formed between a channel formation region and a source region or drain region doped with high-concentration impurity elements, and this region is called LDD region . Furthermore, as a means to prevent the on-current value from degrading caused by hot carriers, a so-called GOLD (Gate-Drain Overlap LDD) structure is known in which the LDD region is arranged so that it can be overlapped via a gate insulating film. A gate electrode. With this structure, the high electric field near the drain electrode is reduced, thereby preventing hot carriers from being emitted, which is known to be an effective prevention against erosion.

However, in addition to the above off current value and on current value, there is another argument that must be paid attention to. For example, the bias state of the pixel TFT and the driving circuit TFT such as a shift register circuit or a buffer circuit need not be the same. For example, in the pixel TFT, a large reverse bias (a negative voltage in the n-channel TFT) is applied to the gate, but the driving circuit TFT basically cannot operate in the reverse bias state. Also, in terms of operating speed, the pixel TFT may be 1/100 or smaller than the driving circuit TFT.

The GOLD structure is highly effective in preventing the deterioration of the conduction current value, but on the other hand, there is a problem that the non-conduction current value becomes higher compared with a normal LDD structure. Therefore, the GOLD structure is not a preferred structure for pixel TFTs. On the contrary, although the ordinary LDD structure is highly effective in suppressing the non-conduction current value, it is inefficient in reducing the electric field near the bleeder electrode and preventing the degradation caused by the ejection of hot carriers. Therefore, it is in mutual operating conditions. In semiconductor devices with many different integrated circuits, such as active matrix liquid crystal display devices, it is best not to always form all TFTs with the same structure. This problem becomes especially obvious when the characteristics of crystalline silicon TFTs are enhanced, which is more required for the performance of active matrix liquid crystal display devices.

Moreover, in order to stabilize the operation of these circuits manufactured using n-channel TFTs and p-channel TFTs, it is necessary to set values such as TFT threshold voltage and sub-critical coefficient (S value) within a predetermined range. In order to be able to do this, TFTs must be inspected from the structural point of view and the structural material point of view.

Summary of Invention

The technology of the present invention is to solve the above problems, and an object of the present invention is to improve the operating characteristics and reliability of semiconductor devices based on the functions of individual circuits. This utilizes the TFT structure arranged in various circuits of semiconductor devices and optoelectronic devices to achieve Optimized and completed, these devices are formed using TFTs, and have always been an active matrix liquid crystal display device. Moreover, another aspect of the present invention is to achieve low power consumption and reduce the number of steps, thereby reducing production costs and improving yield.

Reducing the number of manufacturing steps is one of the ways to reduce production costs and improve yield. Specifically, the number of masks required to manufacture TFTs must be reduced. In the photolithography technology, a photomask is used to form a resist pattern on the substrate as a mask for the etching process. Therefore, the use of a photomask means that other processes such as resist removal and cleaning and drying processes are added to the film deposition and etching processes in the steps before and after the use of the photomask. This also means that complex procedures such as resist coating, pre-bake, exposure, development and post-bake are implemented in the photolithography technology.

Therefore, when reducing the number of photomasks, an appropriate TFT structure arranged in various circuits is formed according to individual circuits. Specifically, it is expected that in the TFT structure used as a switching element, it is important to reduce the non-conduction current value rather than the operating speed. A multiple gate structure is adopted as this structure. On the other hand, to provide a TFT structure in a driving circuit that requires high-speed operation, it is expected that it is important to increase the operating speed, and at the same time, to suppress the erosion caused by hot carrier injection. This becomes a serious problem when the operating speed increases. problem. Various ideas have been added to the LDD area of the TFT to form this structure. In other words, the LDD region provided in the channel formation region and the drain region is characterized by a concentration gradient, in which the concentration of conductivity control impurity elements gradually rises as it approaches the drain region. This structure is significantly effective in soothing the electric field concentrated in the depleted layer near the drain region.

In order to form an LDD region with such an impurity element concentration gradient, the present invention uses a method of doping an ionized conductivity control impurity element accelerated in an electric field, so that it is infiltrated through a gate electrode and a gate insulating film ( The present invention defines a gate insulating film as the gate insulating film provided between the gate electrode and the semiconductor layer and contacts therewith, and includes an insulating film extending from the gate insulating film to an area in the periphery of the gate insulating film) and adding Doped into a semiconductor layer. It should be noted that throughout this specification, for convenience, this doping method of impurity elements is called "through doping method". Moreover, the shape of the gate electrode in the through-doping method of the present invention is a so-called tapered shape, which means that the thickness of the gate electrode gradually increases from the edge portion inward. The through-doping method for the tapered gate electrode can adjust the thickness of the gate electrode to control the concentration of impurity elements doped in the semiconductor layer. Therefore, an LDD region in which the concentration of impurity elements gradually changes along the length of the TFT channel can be formed.

The material used to form the gate electrode is a heat-resistant material, which is selected from tungsten (W). Tantalum (Ta), and a mixture or alloy of one or more elements of the titanium (Ti) group are formed. The heat-resistant material is etched quickly and accurately, and then the edge part is formed into a cone shape, and the dry etching method using high-density plasma is applied. As a device for achieving high-density plasma, an etching device using microwave or ICP (Inductively Coupled Plasma) is suitable. In particular, the ICP etching device can easily control the plasma and the processing operations of processing large-area surface substrates.

Japanese Patent Application Publication No. Heisei 9-293600 published a reference plasma processing method and plasma processing device using ICP. In this application, as a device for implementing high-precision plasma processing, a plasma forming method of applying high-frequency power to a multiple spiral coil is used. Spiral coil parts are formed. The length of each spiral coil part is set to be 1/4 times longer than the high-frequency wavelength. Moreover, the structure of the plasma processing device is to also apply a different high-frequency power supply to a lower electrode for holding the part to be processed, so a bias voltage is added.

FIG. 20A schematically shows the structure of such a plasma processing apparatus (for example, an etching apparatus) using ICP. An antenna coil 903 is arranged on the quartz substrate 905 in the upper part of the reaction space, and the antenna coil 903 is connected to a first high frequency power source 901 via a matching box 907. The first high frequency power supply 901 is set between 6 and 60 MHz, which is typically 13.56 MHz. Furthermore, a second high-frequency power source 902 is connected to a lower electrode 904 holding a substrate 906 through a matching box 912, wherein the substrate 906 is a part to be processed. The second high frequency power source 902 is set between 100 KHz and 60 MHz (for example, between 6 and 29 MHz). If a high-frequency power is applied to the antenna coil 903, a high-frequency current J flows in the θ direction and develops a magnetic field B in the Z direction (Equation 1). According to Faraday's law of electromagnetic induction (Equation 2), an induced electric field E is developed in the θ direction.

μ₀J=rotB

(Equation 1)

<img file="TW480554B_D0001.tif" />

The electrons accelerate in the θ direction in the induced electric field E and collide with gas molecules, generating plasma. The direction of the induced electric field is the θ direction, and therefore the probability of the energy of the charged particles colliding with the reaction chamber wall and the substrate is reduced. Moreover, the antenna coil 903 has almost no downstream of the magnetic field B, and as a result, a high-density plasma region that spreads out in a thin sheet shape is formed. By adjusting the high frequency power applied to the lower electrode 904, the plasma density and the bias voltage applied to the substrate 906 can be independently controlled. Moreover, the frequency of the applied high-frequency power can also be changed according to the material of the processed part.

In order to obtain an ICP high-density plasma etching device, the flow of the high-frequency current J must be almost lossless. Therefore, the inductive reactance of the antenna coil 903 must be reduced. For this purpose, a method of cutting the antenna coil is effective. No. 20B is a diagram showing this type of structure. On a quartz substrate 911, four spiral coils 910 (multiple spiral coils) are arranged and connected to a high-frequency power supply 908 via a matching box 909. At this time, setting the length of each coil to a positive multiple of the high frequency 1/4 wavelength can make the voltage peak value generated higher, so that a standing wave can be generated in the coil.

If an etching device is used, the etching of heat-resistant materials will perform well. The etching device uses ICP with multiple spiral coils. Here, a dry etching device using Panasonic's multiple spiral ICP (model E645-ICP) is used. Figures 21A and 21B show the results of inspecting the edge portion of the tapered pattern of a W film, which has formed a specified pattern on the glass substrate. Here, the angle of the cone-shaped part is defined as the angle between the cone-shaped part and the inclined part of the base surface (level surface) (theta shown in Figure 4)₁Horn). As normal conditions, set the electrical discharge power (high frequency power applied to the coil, 13, 56MHz) to 3.2W/cm², Set the pressure to 1.OPa, and use CF₄With Cl₂For etching gas. Figure 21A shows the dependence of the angle of the cone on the bias power (13.56MHz) applied to the substrate. Etching gas CF₄With Cl₂The flow rate is both set to 30SCCM. It has become obvious that when the bias power supply range is 128 to 384mW/cm2, the angle of the cone can be varied between 70 degrees and 20 degrees.

Figures 25A to 25C are photographs showing the shape of the W film that has been etched through an electron microscope. Figures 25A, 25B and 25C show that the bias power applied to the substrate is 128mW/cm respectively², 192mW/cm²And 256mW/cm²Photos of the situation. It is obvious from Fig. 26 that when the bias power applied to the substrate becomes higher, the angle of the tapered portion becomes smaller.

Moreover, FIG. 21B shows the inspection result of the dependence of the angle of the tapered portion on the etching gas flow rate ratio. CF4 flow rate varies with CF₄With Cl₂The total flow rate is set to the condition of 60SCCM and varies from 20 to 40SCCM. The bias power at this time is set to 128mW/cm². As a result, the angle of the tapered portion can be changed from 60° to 80°.

As shown here, the angle of the cone is greatly changed by the amount of bias power applied to the substrate. Therefore, the bias power is further increased, and the angle of the cone-shaped part can be changed between 5° and 45° by changing the pressure.

Table 1 shows the processing characteristics of the heat-resistant material for forming the gate electrode in the ICP etching device. In addition to the W film and Ta film, here is the platinum-tungsten (Mo-W) alloy (composition ratio M is often used as the gate electrode material)_O: W=48; 50wt%) Examples. Table 1 shows the typical representative values of the etching rate, applicable etching gas, and the selection ratio of the gate insulating film material. The gate insulating film is the basis of the gate electrode. The gate insulating film is a silicon oxide film or a silicon oxynitride film formed by plasma CVD. The selection ratio here is defined as the ratio of the gate insulating film etching rate to the etching rate of each material.

<img file="TW480554B_D0002.tif" />

The etching rate of the Ta film is between 140 and 160 nm/min, and the selection ratio is selected between 6 and 8. This value is better than the selected ratio value between 2 and 4 for the W film with an etching rate between 70 and 90 nm/min. Therefore, from the viewpoint of workability characteristics, the Ta film is suitable. Although not shown in the table, compared with the resistivity of the W film between 10 and 16 μΩcm, the resistivity of the Ta film is between 20 and 30 μΩcm. Therefore, the resistivity of the Ta film is quite high, causing a defect. On the other hand, the etching rate of Mo-W alloy is low, which is between 40 and 60 nm/min, and the selection ratio is between 0.1 and 2. From the point of view of workability characteristics, it can be seen that this material is not always suitable. As can be seen from Table 1, the Ta film showed the best results. However, as mentioned above, when considering the resistivity, after considering all factors, it is then decided that the W film is appropriate.

Although the example of the W film has been shown here, the ICP etching device of the above heat-resistant material can easily process a patterned edge part into a cone shape. Moreover, by applying this method to provide a gate electrode and then implement a through-doping method, the concentration of impurity elements doped in the semiconductor layer can be controlled by adjusting the thickness of the gate electrode. Therefore, an LDD region in which the concentration of impurity elements gradually changes along the length of the TFT channel can be formed.

According to one aspect of the present invention, using this device, a semiconductor device in which the pixel TFT is formed in a pixel portion and a semiconductor device in which the p-channel TFT and the n-channel TFT are formed on the same substrate on the periphery of the pixel portion are provided. The driving circuit is characterized by:

The n-channel TFT of the driving circuit has a tapered partial gate electrode, a channel formation region, and a first impurity region for forming the LDD region. The LDD region is provided so as to overlap the gate electrode and contact the channel formation region , And having a second impurity region for forming a source region or a drain region provided outside the first impurity region;

The p-channel TFT of the driving circuit has a tapered part of the gate electrode, a channel forming region, and a third impurity region for forming the LDD region. The LDD region is provided so as to overlap the gate electrode and contact the channel forming region. And having a fourth impurity region for forming a source region or a drain region provided outside the third impurity region;

The pixel TFT has a tapered partial gate electrode, a channel formation region, a first impurity region for forming the LDD region, and the LDD region is provided for overlapping the gate electrode and contacting the channel formation region, and has a channel formation region. Forming a second impurity region that provides a source region or a drain region outside the first impurity region;

When the distance from the channel formation region to the adjacent individual impurity regions increases, the concentration of a conductive impurity element in the first impurity region and the concentration of a reverse conductive impurity element in the third impurity region become higher; and

The pixel electrode provided in the pixel portion has a lightly reflective surface, formed on the second interposer insulating film made of an organic insulating material, and passes through at least one first interposer made of inorganic insulating material The insulating film and an opening provided in the second interposer insulating film contacting the upper surface of the first interposer insulating film are formed to connect to the pixel TFT, wherein the inorganic insulating material is formed above the gate electrode of the pixel TFT, or

The pixel electrode provided in the pixel portion has light transmittance, is formed on a second interposer insulating film made of organic insulating material, and is connected to a conductive metal connection, and then connected to the pixel TFT, the conductive metal connection It is formed through an opening provided in at least one first interposer insulating film made of inorganic insulating material and a second interposer insulating film formed in contact with the upper surface of the first interposer insulating film.

Moreover, as another aspect of the present invention, there is provided a semiconductor device in which liquid crystal is held between a pair of substrates, which is characterized by;

The pixel portion and the driving circuit formed on the periphery of the pixel portion are formed on a substrate;

The n-channel TFT of the driving circuit has a tapered partial gate electrode, a channel formation region, and a first impurity region for forming the LDD region. The LDD region is provided so as to overlap the gate electrode and contact the channel formation region , And having a second impurity region for forming a source region or a drain region provided outside the first impurity region;

The p-channel TFT of the driving circuit has a tapered partial gate electrode, a channel formation region, and a third impurity region for forming the LDD region. The LDD region is provided so as to overlap the gate electrode and contact the channel formation region. , And a fourth impurity region for forming a source region or a drain region provided outside the third impurity region;

The pixel TFT has a tapered partial gate electrode, a channel formation region, and a first impurity region for forming the LDD region. The LDD region is provided to allow the gate electrode to overlap and contact with the channel formation region, and has a function Forming a second impurity region that provides a source region or a drain region outside the first impurity region;

When the distance from the channel formation region to the adjacent individual impurity regions increases, the concentration of a conductive impurity element in the first impurity region and the concentration of a reverse conductivity impurity element in the third impurity region become higher;

The pixel electrode provided in the pixel portion has a lightly reflective surface, formed on the second interposer insulating film made of an organic insulating material, and passes through at least one first interposer made of inorganic insulating material The insulating film and an opening provided in the second interposer insulating film contacting the upper surface of the first interposer insulating film are formed to connect to the pixel TFT, wherein the inorganic insulating material is formed above the gate electrode of the pixel TFT, as well as

One substrate is overlapped with another substrate, and a transparent conductive film is formed on the other substrate via at least one columnar spacer formed with the first interlayer insulating film and the second interlayer insulating film. The openings overlap, or the pixel electrode provided in the pixel portion has light transmittance, is formed on a second interposer insulating film made of organic insulating material, and is connected to a conductive metal wire, and then connected to the pixel In TFT, the conductive metal wiring is formed through at least one opening provided in a first interlayer insulating film made of inorganic insulating material and a second interlayer insulating film formed in contact with the upper surface of the first interlayer insulating film ;as well as

One substrate is overlapped to another substrate, and a transparent conductive film is formed on the other substrate via at least one column spacer. The spacer is formed with the first interlayer insulating film and the second interposer insulating film. The openings provided overlap. The angle of the tapered part of the gate electrode is set between 5° and 35°.

As another aspect of the present invention, there is provided a semiconductor device in which the pixel TFT is formed in a pixel portion, and a manufacturing method of a driving circuit in which the p-channel TFT and the n-channel TFT are formed on the same substrate in the periphery of the pixel portion, The method features include:

A first step of forming a semiconducting layer containing a spar structure on the substrate;

The second step of selectively etching the semiconductor layer containing a spar structure to form many island-like semiconductor layers;

A third step of forming a gate insulating film in contact with the island-like semiconductor layer;

A fourth step of forming a conductive layer made of heat-resistant material on the gate insulating film;

The fifth step of selectively etching the conductive layer to form a gate electrode with a tapered portion;

The sixth step of forming a first impurity region of an impurity element with a concentration gradient, the impurity element imparts n-type conductivity in a direction parallel to the substrate by doping the impurity element, and the impurity element imparts n-type conductivity at least to the island-like semiconductor In the layer, the island-like semiconductor layer forms the n-channel TFT and pixel TFT of the driving circuit through the tapered part of the gate electrode and the gate insulating film;

Using the gate electrode as a mask, the seventh step of doping an impurity element to form the second impurity region, the impurity element imparts n-type conductivity to the island-like semiconductor film forming the driver circuit n-channel TFT and p-channel TFT Inside;

The eighth step of forming a third impurity region of an impurity element with a concentration gradient, the impurity element imparts p-type conductivity in a direction parallel to the substrate by doping the impurity element, and the impurity element imparts p-type conductivity to the island-like semiconductor layer Inside, the island-like semiconductor layer forms the p-channel TFT of the driving circuit through the tapered part of the gate electrode and the gate insulating film, and this step is doped with an impurity element imparting p-type conductivity, but not through The tapered part of the gate electrode simultaneously forms a fourth impurity region;

The ninth step of forming a first interlayer insulating film, the first interlayer insulating film is made of an inorganic insulating material above the n-channel TFT of the driving circuit, the pixel TFT and the p-channel TFT;

The tenth step of forming a second interlayer insulating film, the second interlayer insulating film made of an organic insulating material in contact with the first interlayer insulating film; and

An eleventh step of forming a light reflecting surface connected to the pixel electrode of the pixel TFT on the second interposer insulating film. Or a step of forming a pixel electrode with a transparent conductive film and connecting it to a conductive metal contact, wherein the conductive metal wiring is connected to an applicable pixel TFT.

According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device in which a liquid crystal is held between a pair of substrates. The method features include:

The first step of forming a semiconductor device with a spar structure on a substrate having a pixel TFT formed in the pixel portion and an n-channel TFT and p-channel formed in the periphery of the pixel portion TFT drive circuit;

A second step of selectively etching the semiconductor layer containing a spar structure to form many island-like semiconductor layers;

A third step of forming a gate insulating film in contact with the island-like semiconductor layer;

A fourth step of forming a conductive layer made of heat-resistant material on the gate insulating film;

The fifth step of selectively etching the conductive layer to form a gate electrode with a tapered portion;

The sixth step of forming a first impurity region of an impurity element with a concentration gradient, the impurity element imparts n-type conductivity in a direction parallel to the substrate by doping the impurity element, and the impurity element imparts n-type conductivity at least to the island-like semiconductor In the layer, the island-like semiconductor layer forms the n-channel TFT and pixel TFT of the driving circuit through the tapered part of the gate electrode and the gate insulating film;

Using the gate electrode as a mask, the seventh step of doping an impurity element to form a second impurity region, the impurity element imparts n-type conductivity to the island-like semiconductor layer forming the n-channel TFT and the pixel TFT of the driving circuit,

The eighth step of forming a third impurity region of an impurity element with a concentration gradient, the impurity element imparts p-type conductivity in a direction parallel to the substrate by doping the impurity element, and the impurity element imparts p-type conductivity to the island-like semiconductor layer Inside, the island-like semiconductor layer forms the p-channel TFT of the driving circuit through the tapered part of the gate electrode and the gate insulating film, and this step is doped with an impurity element imparting p-type conductivity, but not through The tapered part of the gate electrode simultaneously forms a fourth impurity region;

The ninth step of forming a first interlayer insulating film, the first interlayer insulating film is made of an inorganic insulating material above the n-channel TFT of the driving circuit, the pixel TFT and the p-channel TFT;

The tenth step of forming a second interposer insulating film, which is made of an organic insulating material in contact with the first interposer insulating film;

The eleventh step of forming a pixel electrode on the second interlayer insulating film. The pixel electrode has a light reflecting surface and is connected to the first interlayer insulating film through openings provided in the second interlayer insulating film. Pixel TFT;

The twelfth step of forming at least one transparent conductive film on another substrate; and

The thirteenth step of overlapping one substrate to another substrate through at least one cylindrical spacer forming overlapping openings. Alternatively, through an opening provided in the first interposer insulating film and the second interposer insulating film, a step of forming a conductive metal wire connected to the pixel TFT, and forming a transparent conductive wire on the second interposer insulating film In the step of forming a pixel electrode, the second interposer insulating film is connected to applicable metal wiring.

Description of preferred embodiments

The embodiment mode of the present invention will be described in detail as shown in the following embodiments.

Example 1

Embodiment 1 will be described with reference to FIGS. 1A to 3C. In the first embodiment, a pixel TFT and a storage capacitor of a pixel portion and at the same time, the manufacturing method of the driving circuit TFT provided in the periphery of the pixel portion will be described in detail according to the processing steps.

In Figure 1A, in addition to glass substrates such as barium borosilicate glass or aluminum borosilicate glass, the substrate 101 can use the typical Corning glass 7069 or 1737, which is not as good as polyethylene terephthalic acid (PET), polyvinyl aldehyde ( PEN), and polyether (PES) and other optically anisotropic plastic substrates. In the case of using a glass substrate, the heat treatment can be appropriately carried out in advance at a low temperature between about 10 and 20 degrees C lower than the glass distortion point. In order to prevent the diffusion of impurities in the substrate 101, a base film 102 made of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film is formed on the surface of the substrate 101 where a TFT will be formed.

For example, the thickness of SiH is formed between 10 and 200nm (preferably between 50 and 100nm) by plasma CVD in a layered manner.₄, NH₃And N₂A silicon oxynitride film 102a made of O and similarly a silicon oxynitride film 102b made of SiH4 with a thickness between 50 and 200 nm (preferably between 100 and 150 nm) and N:0 treated with hydrogen . Although the underlying film 102 here is shown as a double-layer structure, it can also be formed as a single-layer insulating film or a double-layer or multilayer build-up layer.

The silicon oxynitride film is formed using a conventional parallel plate type plasma CVD. To prepare the silicon oxynitride film 102a, SiH₄Introduce into the reaction chamber, import NH with 100SCCM₃And import N with 20SCCM₂0, the substrate temperature is set to 325°C, the reaction pressure is set to 40Pa, and the discharge power density is set to 0.41W/cm², And set the discharge frequency to 60MHz. On the other hand, in order to prepare the silicon oxynitride film 102b treated with hydrogen, the SiH₄Introduce into the reaction chamber, import N with 120SCCM₄O and import H with 125SCCM₂, The substrate temperature is set to 400°C, the reaction pressure is set to 20Pa, and the discharge power density is set to 0.41W/cm²And suppose the discharge frequency is 60MHz. These films can be formed continuously only by changing the substrate temperature and the reaction gas.

The density of the silicon oxynitride film formed here is 9.28×10²²/cm³, It is a hard film with a concentration of less than 63mm/min in the mixed solution at 20°C. The mixed solution contains 7.13% ammonium bifluoride (NH₄HF₂) And 15.4% ammonium fluoride (NH₄F) (STELLA CHEMIFA company; product name LAL500). If this type of film is used as the base film, it will effectively prevent the diffusion of alkali metal elements from the glass substrate to the semiconductor layer formed on the base film.

Next, a known method such as plasma CVD or sputtering is used to form the amorphous semiconductor layer 103a with a thickness of 25 to 80 nm (preferably between 30 and 60 nm). For example, a 55nm thick amorphous silicon film is formed by plasma CVD. The amorphous semiconductor layer and the microcrystalline semiconductor film exist as semiconductor films with an amorphous structure, and are also suitable for compound semiconductor films with an amorphous structure such as an amorphous silicon germanium film. Furthermore, the base film 102 and the amorphous semiconductor layer 103a can be continuously formed. For example, after the silicon oxynitride film 102a and the silicon oxynitride film 102b treated with hydrogen are successively deposited by the above-mentioned plasma CVD, the reaction gas is changed from SiH₄, N₂O and H₂Become SiH⁴With H₂Or just SiH₄When it is not once exposed to the atmosphere, the film can be continuously formed. As a result, the surface contamination of the silicon oxynitride film 102b treated with hydrogen can be prevented, and the fluctuation in the characteristics of the manufactured TFT and the change in the threshold voltage can be reduced.

Then, a crystallization step of forming a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a is performed. Methods such as laser annealing and thermal annealing (solid phase growth method), or rapid thermal annealing (RTA) are applicable. Especially, in the case of using a substrate such as the above, that is, a glass substrate and a thermally resistant plastic substrate, it is best to apply the laser annealing method. In the RTA method, for example, an infrared light bulb is used. Halogen bulbs, metal rock salt bulbs, or xenon bulbs are the light sources. On the other hand, according to the technique published in Japanese Patent Application Publication No. Heisei 7-130652, the crystalline semiconductor layer 163b can be formed by a crystallization method using a catalytic element. First, in the crystallization step, it is better to expel the hydrogen contained in the amorphous semiconductor layer, and therefore, it is expected to perform a heat treatment between 400°C and 500°C for about 1 hour to reduce the amount of hydrogen contained in the amorphous semiconductor layer. The amount of hydrogen gas is 5 atomic% or less, and then crystallization is performed.

Moreover, during the film deposition in the process of forming an amorphous silicon film by plasma CVD, SiH is used at a substrate temperature of 400°C to 450°C.₄With argon (Ar) as a reaction gas, the amount of hydrogen contained in the amorphous silicon film can be reduced to 5 atomic% or less. In this case, there is no need to perform heat treatment to drive out the hydrogen contained in the amorphous silicon film.

When performing crystallization by laser annealing, pulse oscillation type or continuous emission type excimer laser or hydrogen laser is used as the light source. If a pulse oscillation type excimer laser is used, laser annealing is performed after the laser light is formed into a linear shape. The operator can appropriately select the laser annealing conditions, but for example, set the laser pulse oscillation frequency to 30 Hz, and the laser energy density to 100 and 500 mJ/cm²Between (typically 300 to 400mJ/cm²). Then the linear beam is irradiated on the entire surface of the substrate, and the irradiation is performed so that the overlap ratio of the linear beam is between 80 and 98%. Therefore, the crystalline semiconductor layer 103b shown in FIG. 1B can be formed.

Using a first photomask (PM1), a photolithography technique is used, and then a resist pattern is formed on the crystalline semiconductor layer 103b. Then, the crystalline semiconductor layer is cut into island shapes by dry etching, and island-like semiconductor layers 104 to 108 are formed as shown in FIG. 1C. Use CF in dry etching of crystalline silicon film₄With O₂The mixed gas.

Regarding this type of island-like semiconductor layer, in order to control the threshold voltage (Vth) of the TFT, the concentration can be about 1×10¹⁶To 5×10¹⁷Atom/cm³Next, impurity elements imparting p-type are doped into the entire surface of the island-like semiconductor layer. It is known that elements of the 13th group of the periodic table, such as boron (B), aluminum (Al) and gallium (Ga), are used as impurity elements that impart p-type to semiconductors. The ion injection method and ion doping method (or ion pouring doping method) can be used as the doping method. The ion doping method is suitable for forming a large area of the substrate as the source gas. Here to use diborane (B₂H₆The ion doping of) incorporates boron (B). Doping with impurity elements like this is not always necessary and it is not harmful to omit it, but it is a method of proper use, especially when the threshold voltage of n-channel TFT is placed in a predetermined range.

Using plasma CVD or sputtering, a gate insulating film 109 having a thickness of 40 to 150 nm is formed from an insulating film containing silicon. In this embodiment, a gate insulating film 109 with a thickness of 120 nm is formed from a silicon oxynitride film. Next, use doped O₂SiH₄With N₂The silicon oxynitride film formed by O becomes the preferred material used here because the specified charge density in the film has been reduced. Of course, the gate insulating film is not limited to this type of silicon oxynitride film. A single layer can be formed from another insulating film containing silicon, or a gate insulating film with a laminated structure of one or more layers can be formed. For example, in the case of using a silicon monoxide film, tetraethylorthosilicate (TEOS) can be mixed with O₂Plasma CVD to form silicon oxide film, the reaction pressure is set to 40Pa, the substrate temperature is set between 300 and 4000C, and the discharge is 0.5 to 0.8W/cm²The high frequency (13.56MHz) power density is conducted. Then, thermal annealing is performed between 400°C and 500°C on the silicon oxide film made in this way, so that a good-quality gate insulating film is obtained.

Next, as shown in FIG. 10, in order to form a gate electrode, an anti-heat conduction layer is formed on the gate insulating film 109. The anti-heat conduction layer can be formed as a single layer, but if necessary, it can also be formed as a multilayer structure composed of multiple layers such as two or three layers. For example, using this heat-resistant material, the gate electrode can be a laminated structure of a conductive layer (A) made of a conductive metal nitride film and a conductive layer (B) made of a metal film. The conductive layer (B) 111 may be formed of an element selected from the group containing Ta, Ti, and W, or an alloy containing one of these elements as its main component, or an alloy film of a combination of these elements. The conductive layer (A) 110 is formed of tantalum nitride (TaN), tungsten nitride (WN), and titanium nitride (TiN). Moreover, tungsten silicate and titanium silicate can be applied to the conductive layer (A) 110. In order to lower the impedance of the conductive layer (B) 111, it is better to reduce the concentration of impurities contained, in particular, to appropriately reduce the oxygen concentration to 30 ppm or less. For example, by reducing the oxygen concentration of W to 30 ppm or less, the resistivity value of W can be realized to be 20 μmΩcm or less.

The thickness of the conductive layer (A) 110 can be from 10 to 50 nm (preferably 20 to 30 nm), and the thickness of the conductive layer (B) 111 can be from 200 to 400 nm (preferably 250 to 350 nm). In the case of using W to form the gate electrode, the conductive layer (A) 110 forms a WN film with a thickness of 50 nm and the conductive layer (B) 111 forms a W film with a thickness of 250 nm. The two films are formed by sputtering, with W as the target and introducing Ar gas and nitrogen as the sputtering gas. As another method, the W film can also be formed by thermal CVD using tungsten hexafluoride (WF6). In any case, it is necessary to reduce the impedance of the W film for use as a gate electrode. The expected resistivity of the W film is 20μΩcm or less. Growing larger grains in the W film can reduce the resistivity. However, when many impurity elements such as oxygen are present in W, crystallization is hindered, and then the W film becomes high impedance. For this reason, the case of sputtering uses a W target with a purity of 99.9999%, and during the deposition of the W film, full consideration must be given to preventing impurities from the vapor from being mixed into the film. Therefore, the achievable resistivity is between 9 and 20μΩcm.

On the other hand, when a TaN film is used as the conductive layer (A) 110 and the Ta film is the conductive layer (B) 111, the two films can be formed by sputtering similarly. The TaN film is formed using Ta as the target and a mixture of Ar and nitrogen as the sputtering gas. The Ta film is formed using Ar as the sputtering gas. Moreover, if an appropriate amount of Xe or Kr is added to these sputtering gases, the internal pressure in the film formation can be reduced and peeling can be prevented. The resistivity of the α-phase Ta film is about 20 μmΩcm and it can be suitably used in the gate electrode, but the resistivity of the β-phase Ta film is about 180 nΩcm, and it is not suitable for the gate electrode. The TaN film has a spar structure close to the alpha phase, and if a Ta film is formed on the TaN film, the alpha phase Ta film can be easily obtained. Note that although not shown in the figure, a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 mm may be formed under the conductive layer (A) 110. By doing so, as well as improving the adhesion of the conductive film formed on the silicon film and preventing oxidation, it can prevent the extremely small amount of alkali metal elements contained in the conductive layer (A) 110 or the conductive layer (B) 111 from diffusing into the gate insulationmembrane109in. The film 109. Regardless of the completion, it is preferable that the resistivity of the conductive layer (B) 111 can be in the range of 10 to 50 μΩcm.

In this embodiment, in order to form the gate electrode, the conductive layer (A) 110 is formed from the WN film and the conductive layer (B) 111 is formed from the W film. Then, a second photomask (PM2) is used to form resist masks 112 to 117 by photolithography technology. Then, the conductive layer (A) 110 and the conductive layer (B) 111 are etched together to form the gate electrodes 118 to 122 and the capacitor wiring 123. The gate electrodes 118 to 122 and the capacitor wiring 123 are integrally formed of the conductive layers 118a to 122a made of the conductive layer (A) and the conductive layers 118b to 122b made of the conductive layer (B) (see Fig. 2A).

At this time, the etching is performed to form a tapered portion at least on the edge portions of the gate electrodes 118 to 122. In this etching process, an ICP etching device is used and the details of this technique are explained above. Perform etching with the following specific etching conditions: use CF₄With Cl₂The mixed gas is etching gas, the flow rate is set to 30SCCM, and the discharge power is set to 3.2W/cm²(13.56MHz), the bias power is set to 224mW/cm²(13.56MHz), and the reaction pressure is set to 1.0Pa. At the edge portions of the gate electrodes 118 to 122, a tapered portion whose thickness gradually increases from the edge portion inward is formed under this etching condition. The angle of these tapered parts is 5° to 35°, preferably 10° to 25°. The angle θ1 of the cone-shaped part is the angle illustrated in Figure 4. The angle θ1 greatly affects the concentration gradient of the first impurity region used to form the LDD region in a later step. It should be noted that the cone-shaped part angle θ1 is represented by Tan(θ1)=HG/WG, where (WG) is the length of the cone-shaped part and (HG) is the thickness of the cone-shaped part.

Moreover, no residue is left in order to perform etching. Appropriately increase the etching time by about 10% to 20% to implement over-etching. However, at this time, attention must be paid to the etching selectivity of the base film. For example, the selection rate of the silicon oxynitride film (gate insulating film 109) to the W film shown in Table 1 is between 2 and 4 (typically represented as 3). Due to this over-etching process, the exposed surface of the silicon oxynitride film is etched between 20 and 50 nm, and it becomes substantially thinner, thereby forming a new-shaped gate insulating film 130.

In order to form an LDD region of a pixel TFT and an n-channel TFT of a driving circuit, an impurity element doping process that imparts n-type conductivity (n-doping process) is implemented. The resist masks 112 to 117 used to form the gate electrodes are left intact, and the gate electrodes 118 to 122 with tapered portions at the edges are used as masks, and ion doping is used to impart n by self-calibration doping. -Type conductivity impurity element. In this step, in order to dope impurity elements imparting n-type conductivity through the tapered part in the edge portion of the gate electrode and pass through the gate insulating film to touch the semiconductor layer located below, the amount is set to 1 ×10¹³With 5×10¹⁴Atom/cm³And set the acceleration voltage between 80 and 160keV to form an LDD zone. The 15th group elements of the periodic table are used, typically represented by phosphorus (P) and arsenic (As) as impurity elements that impart n-type conductivity to a semiconductor. Phosphorus (P) is used in this step here. Using this ion doping method, the phosphorus concentration of the semiconductor is in the range of 1×10¹⁶With 1×10¹⁹Between atoms/cm3. In this way, as shown in FIG. 2B, the first impurity regions 124 to 129 are thus formed in the island-like semiconductor layer.

In this step, the concentration gradient of phosphorus contained in at least the portions of the first impurity regions 124 to 128 overlapping the gate electrodes 118 to 122 reflects the change in the film thickness of the tapered portions of the gate electrodes 118 to 122. In other words, the concentration of phosphorus doped into the first impurity regions 124 to 128 becomes higher in the overlapping gate electrode region toward the edge of the gate electrode. This is because the phosphorus concentration that has touched the semiconductor layer changes due to the difference in the film thickness of the tapered portion. Note that FIG. 2B shows a perspective view of the first impurity regions 124 to 128. However, this figure does not really show the phosphorous doped area figure, but a figure showing the above change in phosphorous concentration according to the shape of the tapered part of the gate electrodes 118 to 122.

Next, a second impurity region is formed as a source region or a drain region in the n-channel TFT (n+ doping process). The resist masks 112-117 remain in place, and under the condition of a low acceleration voltage between 10 and 30 keV, phosphorus is doped by ion doping, so that the gate electrodes 118 to 122 are used as masks to shield the phosphorus (P). Therefore, second impurity regions 131 to 136 are formed. Since the gate insulating film 130 in these regions has been processed by over-etching in the step of forming the gate electrode, the gate insulating film becomes thinner, which is between 70 and 100 nm compared with the initial thickness of 120 nm. Therefore, even under such low accelerating voltage conditions, phosphorus must be appropriately doped. Set the phosphorus concentration in these areas so that the concentration range is 1×10²⁰With 1×10²¹Atom/cm³Between (see Figure 2C).

Next, fourth impurity regions 140 and 141 are formed as source regions and drain regions in island-like semiconductor layers 104 and 106 forming p-channel TFTs. Here, p-type impurity elements and gate electrodes 118 and 120 are doped as a mask, and a fourth impurity region is formed in a self-alignment manner. At this time, the entire surface of the island-like semiconductor layers 105, 107, and 108 forming the n-channel TFT is covered by the resist masks 137 to 139 formed by the third photomask (PM3). Then use diborane (B₂H₆The ion doping of) forms the impurity regions 140 and 141 to be formed here. Then the concentration of boron (B) in the fourth impurity regions 140a and 141a that do not overlap with the gate electrode is 3×10²⁰To 3×10²¹Atom/cm³. Moreover, since impurity elements are doped into the impurity regions 140b and 141b of the overlapped gate electrode through the gate insulating film and the tapered portion of the gate electrode, these regions are substantially formed at a concentration of at least 1.5×10¹⁹Atom/cm³Or more third impurity regions. Since phosphorus (P) has been doped into the fourth impurity regions 140a and 141a, and the third impurity regions 140b and 141b in the previous step, the concentration of the fourth impurity regions 140a and 141a ranges from 1×10²⁰To 1×10²¹Atom/cm³And the concentration of the third impurity regions 140b and 141b is from 1×10¹⁶To 1X10²⁹Atom/cm³. The concentration of boron (B) to be doped in this step is set to 1.5 to 1.3 times the concentration of phosphorus (P). Therefore, when the p-type impurity region is used as the source region and the drain region of the p-channel TFT, any kind of interference will not occur.

Then, a first interlayer insulating film 142, as shown in FIG. 3A, is formed on the gate electrode and the gate insulating film. From a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a laminated film of a combination of these films, the first interposer insulating film is appropriately formed. Regardless of which one, the first interposer insulating film 142 is formed of an inorganic insulating material. The thickness of the first interposer insulating film 142 is between 100 and 200 nm. In the case of using silicon oxide film here, TEOS and O can be mixed₂Plasma CVD to form silicon oxide film, the reaction pressure is set to 40 Pa, and the substrate temperature is set between 300°C and 400°C, and 0.5 to 0.8W/cm²The high frequency (13.56MHz) power density is discharged. Moreover, when a silicon oxynitride film is used, it can be formed from a silicon oxynitride film, which is formed from SiH by plasma CVD.₄, N₂O and NH₃Or from SiH₄With M₂O made. In this case, the manufacturing conditions are as follows: the reaction pressure is set between 20 and 200 Pa, the substrate temperature is set between 300°C and 400°C, and the high frequency (60MHz) power density is 0.1 to 1.0 W/cm². Moreover, it is also suitable for SiH₄, N₂O and H₂The produced silicon oxynitride film treated with hydrogen. Similarly, silicon nitride film can also be made of SiH by plasma CVD₄, And NH₃To be manufactured.

Next, a step of triggering an impurity element is performed by thermal annealing, and the impurity element imparts n-type or p-type and is added at respective concentrations. In this step, an annealing furnace is used to perform thermal annealing. Moreover, laser annealing or rapid thermal annealing (RTA) can also be used. Thermal annealing is performed at 400°C to 700°C, typically 500°C to 600°C, in a nitrogen atmosphere. The oxygen concentration in the nitrogen atmosphere is 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, the heat treatment is performed at 550°C for 4 hours. Moreover, if a plastic substrate with a low heat resistance temperature is used as the substrate 101, the laser annealing method is expected to be used (see Fig. 3B).

After the triggering procedure, the gas in the atmosphere is changed, and the heat treatment is performed at 300°C to 450°C for 1 to 12 hours in an atmosphere containing between 3 and 100% hydrogen. Then, a step of treating the island-like semiconductor layer with hydrogen is performed. This step uses thermally excited hydrogen to terminate the island-like semiconductor layer 10¹⁶To 10¹⁸/cm³The suspension line. Moreover, plasma hydrogen treatment (using hydrogen excited by plasma) can be implemented as another hydrogen treatment method. Regardless of which one is used, it is expected to reduce the defect density in the island-like semiconductor layers 104 to 108 to 10¹⁶/cm³Or smaller. In order to do so, about 0.01 to 0.1 atomic% of hydrogen can be added.

After the triggering and hydrogen treatment procedures are completed, a second interposer insulating film 143 with an average thickness of 1.0 to 2.0 nm is formed from an organic insulating material. Materials such as polyimide, acrylic, polyimide, polyimide, and BCB (BENZOCYCLOBUTENE) can be used as organic insulating materials. For example, when a thermally polymerized polyimide is used, it is burned at 300°C in a clean furnace after it is coated on the substrate. In the case of acrylic, use a double box type and mix it with a main material and a hardener. After coating the entire substrate surface with a spinner, a hot plate is used to perform preheating at 80°C for 60 seconds. Then, it is further burned at 250° C. for 60 minutes in a clean furnace to form a second interposer insulating film.

In this way, an organic insulating material is used to form the second interlayer insulating film, and a good plane can be formed. Moreover, the dielectric of the organic insulating material is generally low, and therefore, the parasitic capacitive reactance can be reduced. However, since the second interposer insulating film is absorptive, it is not suitable as a protective film. Therefore, as in this embodiment, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a combination of these films may be used to form the first interposer insulating film 142.

Next, a fourth photomask (PM4) is used to form a predetermined patterned resist mask, and a contact hole is formed, which touches the source region and the drain region formed by each island-like semiconductor layer. These contact holes are formed by dry etching. In this case, use CF₄, O₂The mixed gas with He is an etching gas. The second interposer insulating film 143 made of an organic resin material is first etched, and then CF₄With O₂The first interposer insulating film 142 is etched for the etching gas. Moreover, in order to increase the selectivity of island-like semiconductor layers, switch the etching gas to CHF₃The gate insulating film 30 is etched, and therefore, a contact hole can be formed well.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method. A fifth photomask (PM5) is then used to form a resist mask pattern and etched, thereby forming source wirings 144 to 148 and drain wirings 149 to 153. The drain wiring 153 serves as a pixel electrode here. The drain wiring 154 represents a pixel electrode belonging to a neighboring pixel. In this embodiment, although not shown in the figure, these wirings form a Ti film with a thickness between 50 and 100 nm, and a contact hole is formed in the semiconductor film forming the source or drain region of the island-like semiconductor layer, and An aluminum (Al) film (indicated by reference numbers 144a to 154a in Figure 3C) with a thickness between 300 and 400 nm is formed on the Ti film overlapped thereon. Furthermore, a transparent conductive film with a thickness between 80 and 120 nm (indicated by reference numbers 144b to 154b in Figure 3C) is formed on the upper end of the aluminum film. Indium oxide/zinc oxide alloy (In₂O₃ZnO) and zinc oxide (ZnO) are suitable as transparent conductive film materials. In order to further improve the transmittance and conductivity of visible light, it is best to use gallium-doped zinc oxide (ZnO: G).

Therefore, the fifth photomask can thus be used to form a substrate with a driver circuit TFT and a pixel TFT formed on the same single substrate. The driving circuit consists of a first p-channel TFT (A) 200a, a first n-channel TFT (A) 201a, a second p-channel TFT (A) 202a, and a second n-channel TFT (A) 203a composition. The pixel part is composed of a pixel TFT 204 and a storage capacitor 205. For convenience, this type of substrate is called an active matrix substrate in this specification.

The structure of the first p-channel TFT (A) 200a of the driving circuit has a channel formation region 206, an LDD region 207 overlapping the gate electrode, a source region 208, and a fourth impurity from the island-like semiconductor layer 104 The area formed by the drain pole area 209. The first n-channel TFT (A) 201a has a channel formation region 210, an LDD region 211 formed from a first impurity region overlapping the gate electrode 119, and a source formed from an island-like second impurity region in the semiconductor layer 105 Polar region 212 and drain region 213. With reference to the overlapping gate electrode 119 as an LDD region of a Lov region, the length of the Lov region in the channel length direction is set between 0.1 and 1.5 μm, and for those with a channel length of 3 to 7 μm, it is preferably 0.3 to 0.8 μm. The length of the Lov will be controlled from the thickness of the gate electrode 119 and the angle of the tapered portion θ1.

This LDD area will be illustrated using Figure 4. Fig. 4 shows a partial enlarged view of the first n-channel TFT (A) 201a in Fig. 3C. The LDD region 211 is formed under a tapered portion 261. At this time, as represented by a curve 232, when phosphorus (P) further away from the channel formation region 211, the phosphorus (P) concentration distribution in the LDD region increases. The increase ratio depends on conditions such as the acceleration voltage and ion doping dose, the angle θ1 of the tapered portion 261, and the thickness of the gate electrode 119. To form the edge portion of the tapered gate electrode, impurity elements can be doped through the tapered portion. Therefore, an impurity region in which the concentration of impurity elements gradually changes can be formed in the semiconductor layer existing under the tapered portion. The present invention actively utilizes such impurity regions. Using this type of LDD region in the formation of n-channel TFTs can relieve the high electric field generated near the drain region, and therefore, can prevent the generation of hot carriers and the degradation of the TFT.

Similarly, the structure of the second p-channel TFT (A) 2029 of the driving circuit has a channel formation region 214, an LDD region 215 overlapping the gate electrode 120, a source region 216, and an island-like semiconductor layer 106 The fourth impurity region has formed a drain region 217. The first n-channel TFT (A) 203a has a channel formation region 218, an LDD region 219 overlapping the gate electrode 121, a source region 220 and a drain region formed from the second impurity region in the island-like semiconductor layer 107 221. The structure of the LDD region 219 is the same as that of the LDD region 211. The island-like semiconductor layer 108 of the pixel TFT 204 has channel formation regions 222a and 222b, LDD regions 223a and 223b formed from the first impurity region, and source or drain regions 225 to 227 formed from the second impurity region. The structure of the LDD regions 223a and 223b is the same as that of the LDD region 211. Furthermore, a storage capacitor 205 is formed from the capacitor wiring 123, the gate insulating film, and the semiconductor layers 228 and 229 connected to the drain region 227 of the pixel TFT 204. In Figure 3C, the n-channel TFT and the p-channel TFT of the driving circuit have a single gate structure. In this structure, a gate electrode is provided between a pair of source/drain regions and the pixel TFT is A double gate structure. However, these TFTs may have a single-gate structure or a multi-gate structure in which many gate electrodes are provided between a pair of source/drain regions without causing any problems.

Figure 10 is a top view showing almost a complete pixel portion. As shown in Figure 10, the cross-sectional view taken along the line AA' is equal to the cross-sectional view of the pixel portion shown in Figure 3C. In the pixel TFT 204, the gate electrode 122 crosses the underlying semiconductor layer 108 via a gate insulating film not shown in the figure, and extends over many island-like semiconductor layers, and also serves as a gate wiring. The source region, drain region, and LDD region illustrated in Figure 3C, although not shown in the figure, form island-like semiconductor layers. Moreover, the reference number 230 represents the contact area between the source wiring 148 and the source region 225, and the reference number 231 represents the contact area between the drain wiring 153 and the drain region 227. The storage capacitor 205 is formed in a region where the semiconductor layers 228 and 229 extending from the drain region 227 of the pixel TFT 204 overlap the capacitor wiring 123 via the gate insulating film. In this structure, the impurity element intended to control the valence selection is not doped into the semiconductor layer 228. To optimize the TFT structure, the above structure may improve the operating performance and reliability of the semiconductor device. The TFT responds to the specifications required by the pixel TFT and the driving circuit, and includes various semiconductor device circuits. Moreover, since the gate electrode is formed from a heat-resistant conductive material, the LDD region, the source region, and the drain region can be easily triggered.

Furthermore, during the formation of the LDD region overlapping the gate electrode via the gate insulating film, the LDD region is formed, and an impurity element with a concentration gradient is doped in order to control the conductivity type. Therefore, it is expected that such a region with a concentration gradient will enhance the effect of reducing the electric field, especially in the vicinity of the leakage region.

In the case of an active matrix type liquid crystal display device, the first p-channel TFT (A) 200a and the first n-channel TFT (A) 201a are used to form such as a shift register circuit, a buffer circuit, and a The driving circuit of the level shifter circuit, among which the level shifter circuit occupies an important role in high-speed operation. These circuits are represented by the logic circuit components in Figure 3C. The structure of the LDD region 211 of the first n-channel TFT (A) 201a plays an important role in the countermeasures against hot carriers. Moreover, in order to increase the voltage resistance and stabilize the operation, the TFT of the logic circuit part as shown in Fig. 8A may be formed by a first p-channel TFT (B) 200b and a first n-channel TFT (B) 210b. This TFT has a double gate structure in which two gate electrodes are formed between a pair of source/drain regions. Similarly, this type of TFT can be manufactured using the procedure of this embodiment. The structure of the first p-channel TFT (B) 200b has channel forming regions 236a and 236b, the LDD regions 237a and 237b made of the third impurity region and overlapping the gate electrode 118, and the fourth impurity in the semiconductor layer is similar to islands The source region 238 and the drain regions 239 and 240 are formed by the region. The first n-channel TFT (B) 201b has channel formation regions 241a and 241B, is formed from the first impurity region and overlaps the LDD regions 242a and 242b of the gate electrode 119, and is formed by the second impurity region in the island-like semiconductor layer The source region 243 and the drain regions 244 and 245. When the Lov region, that is, the LDD region overlapping the gate electrode, has a channel length between 0.1 and 1.5 μm, preferably 0.3 to 0.8 μm, the channel length is set to 3 to 7 μm.

Moreover, the second p-channel TFT (A) 202a and the second n-channel TFT (A) 203a with similar structures can be applied to a sampling circuit composed of an analog gate. The sampling circuit plays an important role in dealing with anti-hot carrier and low non-conducting current operations. Therefore, as shown in Figure 8B, the TFT of this circuit can be formed from a second p-channel TFT (B) 202b and a second n-channel TFT (B) 203b. This second p-channel TFT (B) 202b is a triple-gate structure. In this structure, the triple-gate electrode is formed between a pair of source/drain regions. This type of TFT can be similarly manufactured using the procedure of this embodiment. The structure of the second p-channel TFT (B) 202b has channel formation regions 246a, 246b, and 246c, which are made of a third impurity region and overlap the LDD regions 247a, 247b, and 247c of the gate electrode 120, and are similar to islands The source region 249 and the drain regions 250 to 252 are made of the fourth impurity region in the semiconductor layer. The second n-channel TFT (B) 203b has channel formation regions 253 and 253b, is formed from the first impurity region and overlaps the LDD regions 254a and 254b of the gate electrode 121, and is formed by the second impurity region in the island-like semiconductor layer The source region 255 and the drain regions 256 and 257.

The operator can respond to the characteristics of the circuit and appropriately choose to make the gate electrode structure of the TFT into a single structure or a multiple gate structure in which a plurality of gate electrodes are provided between a pair of source/drain regions. Moreover, the active matrix substrate completed in this embodiment can be used to manufacture a reflective liquid crystal display device.

Example 2

Embodiment 1 shows an example of using heat-resistant materials such as W and Ta as the gate electrode. The reason for using this type of material is that in order to control the conductivity of the gate electrode after forming the gate electrode by thermal annealing between 400°C and 700°C, it is necessary to trigger the doping of impurity elements into the semiconductor layer. By performing this step, the gate electrode must have a thermal resistance coefficient. However, this type of heat-resistant material has an area impedance of about 10Ωm, and therefore may not be suitable for liquid crystal display devices with a screen size of 4 inches or larger. This is because if the gate wiring to be connected to the gate electrode is formed of the same material, inevitably, the perimeter in the substrate becomes larger. Therefore, the wiring delay caused by the influence of wiring impedance cannot be ignored.

For example, when the pixel density is VGA and the 768 gate wiring and 102 source wiring form XGA, then 480 gate wiring and 640 source wiring are formed. The screen size of the display area becomes 340mm diagonal for the 13-inch class and 460mm for the 18-inch class. In this embodiment, as a device for realizing such a liquid crystal display device, Figures 5A to 5C will be used to illustrate the method of forming gate wiring from low-resistance conductive materials such as Al and copper (Cu).

First, similar to Embodiment 1, the steps shown in Figures 1A to 2D will be implemented. In order to control this conductivity type, a step is implemented to trigger the doping of impurity elements in each island-like semiconductor layer. In this step, thermal annealing is performed using an annealing furnace. Moreover, laser annealing or rapid thermal annealing (RTA) can also be used. The thermal annealing process is carried out under a nitrogen atmosphere at 400°C to 700°C, typically 500°C to 600°C. The oxygen concentration in the nitrogen atmosphere is 1 ppm or less, preferably 0.1 ppm or less. For example, a heat treatment of 4 hours at 500°C was performed.

Through this heat treatment, the conductive layers (B) 118b to 123b of the gate electrodes 118 to 122 are formed, and the capacitor wiring 123 becomes a conductive layer (C) 118c to 123c with a thickness of 5 to 80 nm formed from the surface. For example, when the conductive layers (B) 118b to 123b are tungsten (W), tungsten nitride (WN) is formed, and when the conductive layer is tantalum (Ta), barium nitride (TaN) may be formed. Furthermore, when the gate electrodes 118 to 123 are exposed to the plasma atmosphere containing nitrogen using nitrogen, ammonia water, etc., the conductive layers (C) 118c to 123c can be formed similarly. Furthermore, in an atmosphere containing between 3 and 100% hydrogen, the hydrogenation step of the island-like semiconductor layer is performed at 300 to 450° C. for 1 and 12 hours of heat treatment. This step is to use heat to excite hydrogen gas to interrupt the suspension wires in the semiconductor layer. Plasma hydroprocessing (using hydrogen excited by plasma) can be implemented as another hydrogenation method (see Figure 5A).

After completing the triggering and hydrogenation steps, a gate connection is formed from a low-impedance conductive material. The low-impedance conductive layer is formed by a conductive layer (D) made of a low-impedance conductive material whose main component is aluminum (Al) or copper (Cu). For example, an aluminum film containing between 0.1 and 2% by weight of titanium (Ti) is formed on the entire surface (not shown) as the conductive layer (D). The conductive layer (D) can be formed in a thickness of 200 to 400 nm (preferably 250 to 350 nm). A photomask is then used to form a predetermined resist pattern, and the conductive layer is etched to form the gate wiring 233 and 234 and the capacitor wiring 235. Then, a phosphoric acid etching solution is used to remove the conductive layer (D) by wet etching to form the gate wiring, while maintaining the basic selection operability. The first interposer insulating film 260 is formed in the same manner as in Embodiment 1 (see FIG. 5B).

Then, similar to Embodiment 1, by forming a second interposer insulating film 147 made of an organic insulating material, the source wirings 148 to 151 and 167, and the drain wirings 153 to 156 and 168, the active matrix can be completed accordinglyformulabase.

Figures 6A and 6B show the top view of this state, and the cross-sections taken from the line BB' in Figure 6A and the line CC' in Figure 6B are respectively equal to the cross-sections along AA' and CC' in Figure 5C. Although the gate insulating film, the first interposer insulating film, and the second interposer insulating film are omitted from Figures 6A and 6B, the source and drain of the island-like semiconductor layers 104, 105, and 108 are not shown in the figure. The regions are connected to source wirings 144, 145, and 148 and drain wirings 149, 150, and 153 through contact holes. Moreover, the cross-sections taken along the line DD' in Figure 6A and the line EE' in Figure 6B are shown in Figures 7A and 7B, respectively. The gate wiring 233 is overlapped and formed on the gate electrodes 118 and 119 and the gate wiring 234 is overlapped and formed on the outside of the gate electrode 122 and the island-like semiconductor layers 104, 105, and 108. Therefore, the conductive layer (C) and the conductive layer (D) are in close contact to be electrically connected. In this way, the gate wiring is formed from a low-impedance conductive material, which can sufficiently reduce the wiring impedance. Therefore, the pixel portion (screen size) can be applied to a 4-inch or larger display device.

Example 3

The active matrix substrate manufactured in Example 1 is still suitable for reflective liquid crystal display devices. On the other hand, when it is applied to a transmission type liquid crystal display device, the pixel electrode provided in each pixel of the pixel portion with a transparent electrode can be appropriately formed. With reference to FIGS. 9A to 9D, Embodiment 3 illustrates the manufacturing method of an active matrix substrate equivalent to a transmission type liquid crystal display device.

This active matrix substrate is manufactured in the same manner as in Example 1. In Figure 9A, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, resulting in the formation of a source wiring and a drain wiring. With reference to Fig. 9B, this structure will be explained in detail using the drain wiring 256 as an example. A Ti film 256a is formed with a thickness between 50 and 150 nm, and then a contact hole and then a semiconductor film is formed, which forms an island-like source or drain region of the semiconductor layer. Next, an aluminum (Al) film 256b with a thickness of between 300 and 400 nm is formed on the Ti film 256a. Furthermore, a Ti film 256C or a titanium nitride (TiN) film with a thickness between 100 and 200 nm is formed, thereby forming a three-layer structure. Then a transparent conductive film is formed on the entire surface. Using a photomask and etching process, the pixel electrode 257 is formed in a patterning process. The pixel electrode 257 is formed on a second interposer insulating film made of organic resin material, and a part is set aside to form an electrical connection, overlapping with the drain wiring 256 of the pixel TFT 204.

FIG. 9c is an example of forming a drain connection by forming a transparent conductive film on the second interposer insulating film 143 first. Then, after the patterning process and the etching process are performed to form the pixel electrode 258, a portion overlapping with the pixel electrode 258 is provided to form a drain connection 259. As shown in Figure 9D, by forming a Ti film 259a with a thickness between 50 and 150 nm, forming a contact hole and forming an island-like semiconductor film in the source or drain region of the semiconductor layer, and then overlaying the Ti film An aluminum film 259b with a thickness between 300 and 400 nm is formed on 259a. With this structure, the pixel electrode 258 is only in contact with the Ti film 259a forming the drain wiring 259. As a result, it is undoubtedly prevented that the transparent conductive film material and Al reacted from direct contact.

Can be used such as indium oxide (In₂O₃), or indium oxide/tin oxide alloy formed by sputtering and vacuum evaporation (In₂O₃-SnO₂: ITO) is used as a transparent conductive film material. The etching treatment of this type of material is implemented with a hydrochloric acid solution. However, especially the etching of ITO easily produces residues. Therefore, in order to improve the handleability of etching, indium oxide/zinc oxide alloy (In₂O₃ZnO). Indium oxide/zinc oxide alloy has excellent smooth surface properties and excellent thermal stability to ITO. Therefore, in the structures in FIGS. 9A and 9B, the edge surface of the drain wiring 256 where the Al film 256 is in contact with the pixel electrode 257 can prevent corrosion caused by the reaction with Al. Similarly, zinc oxide (ZnO) is also a suitable material. In order to further improve the visible light transmittance and conductivity, zinc oxide (Zn; Ga) doped with (Ga) can be used.

In Example 1, an active matrix substrate was fabricated using 5 photomasks, and this substrate was used to fabricate a reflective liquid crystal display device. Adding a mask (total of 6 masks) can thus complete an active matrix substrate equivalent to a transmission liquid crystal display device. Although the steps described in this embodiment are similar to those in the first embodiment, this structure can be applied to the active matrix substrate shown in the second embodiment.

Example 4

Another method for forming the crystalline semiconductor layer of the TFT active layer of one of the active matrix substrates shown in Examples 1 to 3 is shown in Example 4 herein. The crystalline semiconductor layer is formed of an amorphous semiconductor layer that is crystallized by thermal annealing, laser annealing, or rapid thermal annealing (RTA). It is also possible to apply another crystallization method published in Japanese Patent Application Publication No. Heisei 7-130652 in which catalytic elements are used. An example of this situation is explained with reference to Figs. 11A to 11c.

As shown in FIG. 11A, similar to the first embodiment, the base films 1102a and 1102b and the semiconductor layer 1103 having an amorphous structure with a thickness of 25 to 80 nm are formed on a glass substrate 1101. Amorphous silicon (a-Si) film, amorphous silicon chromium (a-SiGe) film, amorphous silicon carbide (a-SiC) film, amorphous silicon tin (a-SiSn) film, etc. are suitable for Amorphous semiconductor layer. These amorphous semiconductor layers are appropriately formed to contain about 0.1 to 40 atomic% of hydrogen. For example, an amorphous silicon film with a thickness of 55 nm is formed. Then, an aqueous solution containing 10 ppm of the weight conversion catalytic element is applied by spin coating. In the spin coating, a spinner is used to rotate the substrate to form a layer film 1104 containing the catalytic element. Catalytic elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (CO), platinum (pt), copper (Cu), gold ( Au) and the like. In addition to spin coating, printing, spraying, grit coating, sputtering, or vacuum vaporization can also be used to form a -1 to 5nm thick layer of catalytic elements to make a layered film 1104. element.

In the crystallization step shown in Figure 11B, heat treatment is first performed at 400°C and 500°C for about 1 hour, so that the amount of hydrogen contained in the amorphous silicon film is 5 atomic% or less. If the initial amount of hydrogen contained in the amorphous silicon film after thin film deposition is this value, heat treatment is not necessary in this case. Then use an annealing furnace to perform thermal annealing for 1 to 8 hours in a nitrogen atmosphere at 550°C to 600°C. A crystalline semiconductor layer 1105 made of a crystalline silicon film can thus be obtained through the above steps (see FIG. 11C). However, if the crystalline semiconductor layer 1105 manufactured by this thermal annealing is observed carefully with an optical microscope, it is possible to identify the partially left amorphous region. In this case, using the spectral observation of Raman spectroscopy, at 480cm^-1The amorphous composition observed below has a broad wave. Therefore, under thermal annealing, the laser annealing method described in Embodiment 1 to treat the crystalline semiconductor layer 1105 is an effective method suitable for enhancing the crystallinity of the crystalline semiconductor film.

Similarly, Figures 12A to 12C also show an example of using a catalyst element as a crystallization method, in which a layer film containing a catalyst element is formed by sputtering. First, similar to Embodiment 1, the base films 1202a and 1202b and the semiconductor layer 1203 having an amorphous structure with a thickness of 25 to 80 nm are formed on the glass substrate 1201. Then, an oxide film with a thickness of about 0.5 to 5 nm is formed on the surface of the semiconductor layer 1203 having an amorphous structure layer (also shown in the figure). As an oxide film with this thickness, a suitable coating film can be actively formed by plasma CVD or sputtering. However, the oxide film can also be formed by exposing the surface of the semiconductor layer 1203 with an amorphous structure to a substrate. Heat and process the plasma inside the oxygen atmosphere at 100°C to 300°C, or expose the surface of the semiconductor layer 1203 with an amorphous structure to hydrogen peroxide (H₂O₂) In the solution. It is also possible to inject infrared rays into an oxygen-containing atmosphere to form an oxide film to generate ozone, and then expose the semiconductor layer 1203 with an amorphous structure to the ozone atmosphere.

In this way, a sputtering method is used to form a layer film 1204 containing the above catalytic element on the semiconductor layer 1203. The semiconductor layer 1203 has an amorphous structure and a thin oxide film on its surface. The thickness of the film is not limited, but it is appropriate to form the film to be about 10 to 100 nm. For example, an effective method is to form a Ni film with Ni as the target. In the sputtering method, the high-energy particles made of the above catalytic elements accelerated in the electric field also fly to the edge of the substrate and are driven into the vicinity of the surface of the semiconductor layer 1203 with an amorphous structure or into the semiconductor layer 1203. In the oxide film on the surface of layer 1203. This part differs depending on the conditions under which the plasma is generated or the state of the substrate bias. However, ideally, the amount of the catalytic element is appropriately set so that it is driven into the vicinity of the surface of the semiconductor layer 1203 with an amorphous structure and is within 1×10¹¹With 1×10¹⁴Atom/cm2 between the oxide film.

Then, the layer film 1204 containing a catalytic element is selectively removed. For example, if the film is formed of a Ni film, it can be removed as a solution of nitric acid, or if an aqueous solution containing a fluorinated acid is used, not only the Ni film, but also the semiconductor layer with an amorphous structure is formed The oxide film on 1203 is also removed at the same time. No matter which one is used, the amount of catalytic elements in the vicinity of the surface of the semiconductor 1203 with an amorphous structure should be 1×10¹¹To 1×10¹⁴Atom/cm²between. As shown in Fig. 12B, similar to Fig. 11B, the crystallization step is performed by thermal annealing, and a crystalline semiconductor layer 1205 can be obtained accordingly (see Fig. 11c).

The crystalline semiconductor layers 1105 and 1205 manufactured in FIGS. 11A to 11c or FIGS. 12A to 12C form island-like semiconductor layers 104 to 108. Similar to Embodiment 1, an active matrix substrate can be completed. However, in the crystallization process, if a catalytic element that promotes the crystallization of silicon is used, a small amount (about 1×10¹⁷To 1×10¹⁹Atom/cm³The catalytic element of) remains in the island-like semiconductor layer. Of course, it is possible to complete the TFT in this state, but it is better to at least remove the remaining catalytic elements from the channel forming region. One of the methods to remove this catalytic element is a method using phosphorus (P) absorption.

The phosphorus absorption treatment used in this purpose can be implemented together with the triggering step described in Figure 3B. This state is explained with reference to Figure 13. The phosphorus (P) concentration required for absorption can be similar to the impurity concentration of the second impurity region, and in the triggering step, thermal annealing can be used to remove the catalytic element from the channel formation region of the n-channel TFT and the p-channel TFT at this concentration. Separated into the phosphorus (p) impurity zone. As a result, the catalytic element was separated into a concentration of about 1×10¹⁷To 1×10¹⁹Atom/cm³The impurity zone. Since the on-current value of a TFT manufactured in this way is reduced, a TFT with good characteristics can be obtained, and a high electric field mobility can be obtained due to good crystallinity.

Example 5

In this embodiment, the manufacturing method of an active matrix liquid crystal display device from the active matrix substrate manufactured in the first embodiment will be described. As shown in Figure 14A, first, a spacer made of a columnar spacer is formed on the active matrix substrate in the state of Figure 3C. The spacer can be provided by spraying several μm crystal grains. In this embodiment, a method of forming spacers by patterning after forming a resin film on the entire surface of the substrate is adopted. The material used for this spacer is unlimited. For example, using JSR product NN700, after applying a rotator to the substrate, a predetermined pattern is formed by exposure and development processing. Moreover, it is fumigated by heating at 150°C to 200°C in a clean furnace. According to the conditions of exposure and development, the shape of the spacer formed in this way can be different. Forming spacers as shown in Figure 15 to make the shape of a columnar with a flat top can ensure its mechanical strength as a liquid crystal display panel. Among them, when an opposing substrate is overlapped to this substrate, it is flat. The top column shape is a preferred shape. The shape of the spacer such as cone or pyramid is not particularly limited to this. For example, when the spacer is a conical shape, its specific size is as follows: the height H is set between 1.2 and 5nm, the average radius L1 is set between 5 and 7μm, and the ratio of the average radius L1 to the bottom radius L2 is set to 1. To 1.5. The surface taper angle at this point is ±15° or less.

The arrangement of the columnar spacers can be arbitrarily determined, but it is better to appropriately form a spacer 406 with the contact area 231 of the drain wiring 153 (pixel electrode) in the overlapping pixel portion so as to cover the overlapping portion as shown in Figure 14A share. The liquid crystal cannot be smoothly determined in the direction of the damaged part of the contact area 231 surface. Therefore, the columnar spacer 406 is formed in the form of filling the contact area 231 with the resin used for the spacer, so that distinction or the like can be prevented. Furthermore, spacers 405a to 405e are formed on the TFT of the driving circuit. These spacers can be extended and formed on the entire surface of the driving circuit part, and can be formed to cover the source wiring and the drain wiring as shown in Figures 14A and 14B.

Then, an azimuth film 407 is formed. Polyimide resin is often used as the orientation film of liquid crystal display devices. After the azimuth film is formed, a rubbing procedure is implemented to make the azimuth of the liquid crystal molecules have a fixed forward tilt angle. The rubbing procedure is implemented so that it does not rub to an area 2 μm or less from the edge portion of the columnar spacer 406, which is provided in the pixel portion along the rubbing direction. Moreover, since the generation of static electricity from the rubbing process is often a problem, forming spacers 405a to 405e on the TFT of the driving circuit can achieve the effect of preventing static electricity of the TFT. Although not illustrated in the figure, the substrate may have a structure in which the azimuth film 407 is formed before the spacers 406 and 405a to 405e are formed.

A light-shielding film 402, a transparent conductive film 403, and an orientation film 404 are formed on an opposite substrate 401, and the opposite substrate 401 is opposite to the active matrix substrate. The light-shielding film 402 is formed of a Ti film, a Cr film, and an Al film having a thickness between 150 and 300 μm. Then, the active matrix substrate and the opposite substrate are joined with the sealing agent 408, wherein the pixel portion and the driving circuit are formed on the active matrix substrate. The filler (not shown in the figure) is mixed into the sealing agent 408, and the two substrates are joined together with the filler and spacers 406 and 405a to 405e separated by a nearly uniform interval. Then, a liquid crystal material 409 is injected between the two substrates. A known liquid crystal material can be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a non-critical anti-electric iron mixed liquid crystal can also be used. The anti-electric iron mixed liquid crystal represents the photoelectric response characteristic of the continuous change of the transmittance to an electric field. There is a type of V-shaped photoelectric response characteristic in this non-critical value anti-electric iron mixed liquid crystal. Therefore, the active matrix type liquid crystal display device shown in Figure 14B is completed.

Figure 16 is a top view showing the positional relationship between this type of active matrix substrate and pixel portion, drive circuit portion, spacer, and sealing agent. A scanning signal driving circuit 605 and an image signal driving circuit 606 as one of the driving circuits are provided in the periphery of the pixel portion 604 on the glass substrate 101 described in the first embodiment. Moreover, a signal processing circuit 607 such as a CPU or a memory circuit can also be added. Then, a connecting wire 603 connects these driving circuits to an external input/output terminal 602. In the pixel portion 604, a set of gate wirings 608 extending from the scanning signal driving circuit 605 and a set of source wirings extending from the image signal driving circuit 606 intersect in a matrix to form pixels. Each pixel is provided with a pixel TFT 204 and a storage capacitor 205.

In FIG. 14A, the column spacer 406 provided in the pixel portion can be provided not only for each pixel, but also for every few pixels or a few pixels arranged in the matrix shown in FIG. 16. In other words, it is possible to set the ratio of the total number of pixels constituting the pixel portion to the number of spacers at zero between 20% and 100%. Furthermore, the spacers 405a to 405e provided in the driver circuit part can be formed to cover the entire surface of the circuit, or can be provided according to the positions of the source wiring and drain wiring of each TFT. In Figure 16, reference numerals 610 to 612 indicate the arrangement of spacers provided in the driver circuit section. On the substrate 101 shown in Figure 16, the sealing agent 619 is formed on the pixel portion 604, the scanning signal driving circuit 605, the image signal driving circuit 606, and the outside of the signal processing circuit 607 of other circuits, and an external input/ Inside the output terminal 602.

Next, the structure of such an active matrix liquid crystal display device will be explained using the perspective view of FIG. 17. In FIG. 17, the active matrix substrate is composed of a pixel portion 604, a scanning signal driving circuit 605, an image signal driving circuit 606, and a signal processing circuit 607 of other circuits formed on the glass substrate 101. The channel TFT 204 and the storage capacitor 205 are provided in the pixel portion 204, and the driving circuit formed in the periphery thereof is composed of a CMOS circuit. The scanning signal driving circuit 605 and the image signal driving circuit 606 are connected to the pixel TFT 204 via the gate wiring 122 and the source wiring 148 respectively, and extend to the pixel portion 604. Furthermore, an FPC (flexible printed circuit) 613 is connected to the external input/output terminal 602 for inputting such image signals. The reinforced resin 614 is used to firmly adhere the FPC613 in this area. The connection line 603 is connected to each drive circuit. Moreover, although not shown in the figure, a light-shielding film and a transparent conductive film are provided in the opposite substrate 401.

The active matrix substrate shown in Examples 1 to 3 can be used to form a liquid crystal display device having such a structure. The active matrix substrate shown in Example 1 is used to obtain a reflective liquid crystal display device, but the active matrix substrate shown in Example 3 is used to obtain a transmission type liquid crystal display device.

Example 6

FIG. 18 illustrates an example of the circuit structure of the active matrix substrate shown in Embodiments 1 to 3, and shows the circuit structure of a direct view display device. The active matrix substrate is composed of an image signal driving circuit 606, scanning signal driving circuits (A) and (B) 605, and a pixel portion 604. Note that the driving circuit described in this specification is a generic name including the image signal driving circuit 606 and the scanning signal driving circuit 605.

The image signal driving circuit 606 is composed of a shift register circuit 501a, a level shifter circuit 502a, a buffer circuit 503a, and a sampling circuit 504. Moreover, the scanning signal driving circuits 185(A) and 185(B) are composed of a shift register circuit 501b, a level shifter circuit 502b, and a buffer circuit 503b.

The driving voltage of the shift register circuits 501a and 501b is between 5 and 16V (typically 10V). The CMOS circuit TFT that forms one of the circuits is formed by the first p-channel TFT (A) 200a and the first n-channel TFT (A) 201a in Figure 3C, or this TFT can be the first shown in Figure 8A The p-channel TFT (B) 200b is formed with the first n-channel TFT (B) 201b. However, since the driving voltages of the level shifter circuits 502a and 502b and the buffer circuits 503a and 503b become as high as 14 to 16V, the TFT structure is expected to form a multiple gate structure as shown in FIG. 8A. Forming a TFT into a multiple gate structure is effective in increasing the voltage resistance and improving circuit reliability.

The sampling circuit 504 is formed by an analog switch and its driving voltage is between 14V and 16V. Because the polarities are reversed to drive and the current value during non-conduction must be reduced, the sampling circuit 504 is expected to be formed by the second β-channel TFT (A) 202a and the second n-channel TFT (A) 203a as shown in FIG. 3C. Or, in order to effectively reduce the current value when it is not conducting, the sampling circuit can be formed by the second β-channel TFT (B) 200b and the second n-channel TFT (B) 201b.

Moreover, the driving voltage of the pixel part is between 14 and 16V. From the viewpoint of reducing power consumption, it is necessary to further reduce the non-conduction current value of the pixel part rather than the sampling circuit part. Therefore, as a basic structure, the pixel portion forms a multiple-gate structure of the pixel TFT 204 shown in FIG. 3C.

Note that fabricating TFTs according to the steps shown in Embodiments 1 to 3 can easily realize the structure of this embodiment. The structure of the pixel portion and the driving circuit is only shown in this embodiment. Other circuits such as signal distribution circuits, a frequency dividing circuit, a D/A converter, a gamma correction circuit, an op-amp circuit, and a further signal processing circuit 187 such as a memory circuit and an arithmetic operation circuit, and It is still a logic circuit, all of which can be formed on the same structure according to the processing procedures of the first to third embodiments. Therefore, according to the present invention, a semiconductor device with a pixel portion and a driving circuit formed on the same substrate can be realized, for example, a liquid crystal display device with a signal control circuit and a pixel portion.

Example 7

Due to the precise control of the etching process of the gate electrode using ICP, the gate electrode can be etched and a gate insulating film with a thickness of 20 to 50 nm can be formed from its surface. In this point of view, proper selection of etching conditions can form a tapered portion in the gate insulating film area that is in contact with the edge portion of the gate electrode.

In this type of etching, for example, in the gate electrode formation step shown in Figure 2A, resist masks 112 to 117 are provided, and then a bias power is not applied to the substrate end first, and the W film Etch with WN film. In this case, the anti-corrosion mask remains uncorroded. Then, the bias power is applied to the place where the gate insulating film is almost exposed. Therefore, the resist mask is etched to reprocess the edge portion, and thus the cone-shaped etching of the W film is completed. The selection ratio of anti-etching to W film (resist etching rate/W film etching rate) becomes smaller as the bias power increases, which means that the resist mask is quickly etched.

Using this etching method, the TFT manufactured according to the steps of the first embodiment will be described using FIGS. 19A and 19B. Figure 16 is a cross-sectional view of a completed TFT, and similar to Embodiment 1, the substrate 601 is made up of a base film 602 (a silicon oxynitride film 602a and a hydrogenated silicon oxynitride film 602b) and islands. The semiconductor layers 603 and 604 are composed. The gate insulating film 605 forms a tapered portion in the vicinity of the edge portions of the gate electrodes 606 and 607 having tapered portions, and the thickness of the film gradually changes in this tapered portion. Similar to Embodiment 1, a first interposer insulating film 608, a second interposer insulating film 609, source wirings 610 and 613, and drain wirings 611 and 612 are formed. Under this etching condition, in the edge portions of the gate electrodes 606 and 607, the tapered portion whose thickness gradually increases from the edge portion inward forms an angle between 25° and 35°, preferably 30° . These angles greatly affect the concentration gradient of the first impurity region forming the LDD region. As shown in Figure 19B, notice that the cone angle θl is represented as Tan(θl)=HGI/WGI, where (WG1) is the length of the gate electrode cone and (HG1) is the cone The tapered angle θ2 is expressed as Tan(θ2)=HG2/WG2, where (WG2) is the length of the tapered portion of the gate insulating film and (HG2) is the thickness of the tapered portion.

In an n-channel TFT, a first impurity region for forming an LDD region is formed by ion doping. An impurity element controlling a conductivity type is doped through the gate electrodes 606 and 607 having a tapered portion and infiltrated through the gate insulating film having a tapered portion, and touches the lower semiconductor layer. Dosage is set to 1×10¹³With 5×10¹⁴Atom/cm³The acceleration voltage is set between 80 and 160 keV to form an impurity region. Also, set the amount to be 1×10¹⁵With 5×10¹⁵Atom/cm³And the acceleration voltage is between 10 and 30 keV to form a second impurity region for forming a source region or a drain region. Therefore, what is formed in a third n-channel TFT 615 is a channel formation region 621, an LDD region 622 with an overlapped gate electrode and a non-overlapped gate electrode, an LDD region 623 formed from the first impurity region, and a source The pole region 624 and the drain region 625 formed from the second impurity region.

These LDD areas will be illustrated using Figure 19B. FIG. 19B is a partially enlarged view showing the third n-channel TFT 615 in FIG. 19A. The LDD region 622 is formed under a gate electrode tapered portion 628, and the LDD region 623 is formed under a gate insulating film tapered portion 627. Under this point of view, the concentration distribution of phosphorus (P) in the two LDD regions increases when they are far from the channel formation region 621 as shown by the curve 625. The increase ratio depends on conditions such as the acceleration angle and ion doping amount, the angles θ1 and θ2 of the tapered portion 627 and 628, and the thickness of the gate electrode 607. The edge part of the gate electrode and the gate insulating film forming the cone-shaped neighbor can be doped with dopant elements through the cone-shaped part. Therefore, an impurity region whose concentration of impurity elements gradually changes can be formed in the semiconductor layer below the tapered portion. For the impurity concentration of LDD region 622, the lowest concentration range is set at 1×10¹⁶With 1×10¹⁷Atom/cm³, And the highest concentration range is set at 1×10¹⁷With 1×10¹⁸Atom/cm³between. Moreover, for the impurity concentration of the LDD region 623, the lowest concentration range is set at 1×10¹⁷With 1×10¹⁸Atom/cm³, And the highest concentration range is set at 1×10¹⁹With 1×10²⁰Atom/cm³between. By providing these types of impurity regions, in the n-channel TFT, the high electric field generated near the drain region can be relieved, and therefore the generation of hot carriers and degradation of the TFT can be prevented and at the same time, the non-conduction current value can be reduced.

On the other hand, in the p-channel TFT, the amount is set to 2×10¹⁵With 1×10¹⁶Atom/cm³An impurity region is formed between the speed and the acceleration voltage between 80 and 160 keV. Next, a channel formation region 616 is formed in a third p-channel TFT 614, an LDD region 617 with an overlapping gate electrode and a non-overlapping gate electrode, an LDD region 618 formed from the third impurity region, and a source region 619, and a drain region 620 formed from the fourth impurity region. Then, for the impurity concentration of the LDD region 617, the lowest concentration range is set to 2×10¹⁶With 3×10¹⁷Atom/cm³, And the highest concentration range is set at 2×10¹⁷With 3×10¹⁸Atom/cm³between. Moreover, for the impurity concentration of the LDD region 618, the lowest concentration range is set to 2×10¹⁷With 3×10¹⁸Atom/cm³, And the highest concentration range is set at 2×10¹⁹With 5×10²⁰Atom/cm³Of. Therefore, the provision of such impurity regions can reduce the current value when the p-channel TFT is not conducting.

Example 8

An active matrix substrate, a liquid crystal display device and an EL type display device manufactured by the implementation of the present invention can be used in various optoelectronic devices. Then, the present invention is applied to all electronic devices that include such optoelectronic devices as display media. The following are this type of electronic equipment: personal computers; digital cameras; video cameras; portable information terminals (such as mobile computers; portable phones, and e-books); and navigation systems.

FIG. 22A shows a portable information terminal, which is composed of a main body 2201, an image input unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

This type of portable information terminal is often used outdoors, let alone indoors. When the portable information terminal is used outdoors for several hours, the reflective liquid crystal display device that uses external light instead of the backlight is suitable for a low power consumption type, but when the environment is dark or not bright enough, it is suitable for the emissive liquid crystal display with backlight. Display device. Therefore, based on this background factor, a hybrid liquid crystal display device has been developed, which has two characteristics: reflective and emissive. The present invention is also applicable to this type of hybrid liquid crystal display device. The display device 2205 is composed of a touch panel 3002, a liquid crystal display device 3003, and an LED backlight 3004. In order to make the operation of the portable information terminal simpler and easier, a touch panel 3002 is provided. The structure of the touch panel 3002 is composed of a light emitting element 3100 such as an LED provided on one end, and a light receiving element 3200 such as a photodiode is provided on the other end, and a light path is formed between the two elements. If the touch panel 3002 is pressed and the light path is blocked, the output from the light receiving element 3200 changes. Therefore, based on this principle, the light-emitting elements and the light-receiving elements are arranged in a matrix on the liquid crystal display device, and therefore, serve as an input medium.

FIG. 22B shows the structure of the pixel portion of the hybrid liquid crystal display device, in which the drain wiring 263 and the pixel electrode 262 are provided on the second interposer insulating film on the pixel TFT 204 and the storage capacitor 205. Application Example 3 can form such a structure. The drain wiring has a laminated structure of Ti film and Al film and functions as a pixel electrode. The pixel electrode 262 is formed using the transparent conductive material described in the embodiment. The liquid crystal display device 3003 manufactured from this active matrix substrate can be suitably applied to portable information terminals.

No. 23A shows a personal computer including a main body 2001. The main body is equipped with a microprocessor, a memory, etc., an image input unit 2002, a display device 2003, and a keyboard 2004. The present invention can form the display device 2003 and other signal control circuits.

FIG. 23B shows a video camera, which is composed of a main body 2101, a display device 2102, an audio input device 2103, operation switches 2104, a battery 2105, and an image receiving unit 2106. The present invention can be applied to the display device 2102 and other signal control circuits.

Figure 23 shows an electronic amusement device such as a video game or a video game. It includes: a main body 2301 carrying an electronic circuit 2308 such as a CPU and a recording medium 2304; a controller 2305; a display device 2303; The display device 2302 built in the main body 2301. The display device 2303 and the display device 2302 incorporated in the main body 2301 can display the same information, or the former can be used as a primary display and the latter is a secondary display to display the display information or equipment operation status from the recording medium 2304, or can add touch The sensor is used as an operation panel. Moreover, in order for the main body 2301, the controller 2305, and the display device 2303 to transmit signals to each other, wired communication may be used, or the sensor units 2306 and 2307 may be provided for wireless communication or optical communication. The present invention can be applied to the display devices 2302 and 2303. A conventional CRT can also be used as the display device 2303.

FIG. 23D shows a playback device using a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and it includes a main body 2401, a display device 2402, a speaker unit 2403, a recording medium 2404, and an operation switch 2405. Note that a DVD (audio-visual disc player) or laser disc player is used as the recording medium of this device, and the device can copy music programs, display images, and display via video games (or TV games) and via the Internet News. The present invention can be suitably used in the display device 2402 and other signal control circuits.

FIG. 23E shows a digital camera, which includes a main body 2501, a display device 2502, a peephole portion 2503, an operation switch 2504, and an image receiving unit (not shown in the figure). The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 24A shows a front-facing projector, which includes a light source system and display device 2601, and a screen 2602. The present invention can be applied to display devices and other signal control circuits. FIG. 24B shows a rear-facing projector, which includes a main body 2701, a light source system and display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.

24C shows an example of the structure of the light source system and the display devices 2601 and 2702 in FIGS. 24A and 24B. The light source system and the display devices 2601 and 2702 each include a light source system 2801, mirrors 2802 and 2804 to 2806, a bidirectional color mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and an optical projection system 2810. The optical projection system 2810 includes many optical lenses. Fig. 24C shows an example of a three-board system using three liquid crystal display devices 2808, but for example, there is no particular limitation and an optical system of a single-board system is acceptable. Moreover, the operator can appropriately set the optical lens, polarization film, phase stabilizer film, IR film, etc. in the optical path indicated by the arrow in Figure 24C. Furthermore, Fig. 24D shows an example of the structure of the light source system 2801 in Fig. 24C. In this embodiment, the light source system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source system shown in Figure 24D is an example, not limited to the structure shown in the figure.

Moreover, although it is not shown in the figure, it is also possible to apply the present invention to, for example, a navigation system or a reading circuit of an image sensor. Therefore, the scope of application of the present invention is quite wide, and it can be applied to electronic devices in all fields. Moreover, the electronic device of this embodiment can be realized by the techniques published in Embodiments 1 to 5.

According to the present invention, in a semiconductor device with many functional circuits formed on the same single substrate (in this specification, specifically an optoelectronic device), TFTs with appropriate capabilities can be arranged according to the specifications required by each circuit, which greatly improves the semiconductor device The operating characteristics and reliability.

According to the manufacturing method of the semiconductor device of the present invention, five photomasks can be used to manufacture an active matrix substrate structure. In the substrate structure, the driving circuit of the overlapping gate electrode is formed between the LDD area of the p-channel TFT and the n-channel TFT and the pixel TFT. LDD area. A reflective liquid crystal display device can be manufactured from this active matrix substrate. Moreover, according to the manufacturing method of the present invention, an emissive liquid crystal display device can be manufactured using six photomasks.

In a TFT with a gate electrode formed of a heat-resistant material and a gate wiring formed of a low-resistance conductive material, according to the method of manufacturing a semiconductor device of the present invention, 6 photomasks can be used to manufacture an active matrix substrate structure In this base structure, the LDD area of the p-channel TFT and the n-channel TFT of the driving circuit overlapping the gate electrode and the LDD area of the pixel TFT are formed. A reflective liquid crystal display device can be manufactured from this active matrix substrate. Moreover, according to the manufacturing method of the present invention, an emissive liquid crystal display device can be manufactured by using 7 photomasks.

<p>903 Antenna coil</p><p>905 Quartz substrate</p><p>901, 902, 908 power supply</p><p>907, 912, 909 matching box</p><p>904 electrode</p><p>906, 911, 101, 401, 1103, 1201, 601 base</p><p>910 Spiral coil</p><p>102, 1102, 1202 base film</p><p>103-108, 228, 229 semiconductor layer</p><p>109, 130, 605 Gate insulating film</p><p>111, 110, 118a-122a, 118b-122b conductive layer</p><p>112-117, 137-139 Anti-corrosion cover</p><p>118-123, 606, 607 Gate electrode</p><p>123, 235 capacitor wiring</p><p>124-129, 131-136, 140, 141 impurity region</p><p>144-151, 167, 609, 610, 613 source wiring</p><p>149-156, 168, 263, 259, 611, 612 drain wiring</p><p>200a, 202a, 614, 200b, 202bp channel TFT</p><p>201a, 203a, 615, 201b, 203b n channel TFT</p><p>205 capacitance</p><p>206, 210, 214, 218, 246, 621, 222, 236, 241, 253, 616 Channel formation area</p><p>207, 211, 215, 219, 247, 622, 617, 223, 237, 242, 254, 623, 618 LDD area</p><p>208, 212, 216, 220, 225, 619, 238, 243, 249, 255, 624 source region</p><p>209, 213, 217, 221, 226, 227, 239, 240, 244, 245, 250-252, 256, 257, 625, 620 Drain area</p><p>261, 628, 627 Conical part</p><p>232 curve</p><p>204 Pixel TFT</p><p>233,234,608,202 Gate wiring</p><p>260, 147, 143, 142, 608, 609 interposer insulating film</p><p>104, 105, 108, 1203, 603, 604, 1103, 1105, 1205 semiconductor layer</p><p>257, 258, 262 pixel electrode</p><p>1104, 1204 layers of film</p><p>406, 405 spacer</p><p>231 Contact area</p><p>407,404 azimuth film</p><p>402 Light shielding film</p><p>403 Transparent conductive film</p><p>408,619 Sealing agent</p><p>409 LCD material</p><p>605, 606 drive circuit</p><p>604, 204 pixel portion</p><p>607, 187 signal processing circuit</p><p>602 Input/output</p><p>603 Connection line</p><p>613 Flexible printed circuit</p><p>614 Reinforced resin</p><p>501a, 501b displacement register circuit</p><p>502a, 502b level shifter circuit</p><p>503a, 503b buffer circuit</p><p>504 Sampling circuit</p><p>185(A), 185(B) scanning signal drive circuit</p><p>112-117 Anti-corrosion cover</p><p>2201, 2101, 2501, 2301, 2401, 2701 main body</p><p>2202, 2002 Image input unit</p><p>2203, 2106 image receiving unit</p><p>2204, 2104, 2405, 2504 operation switch</p><p>2205, 3003, 2303, 2402, 2601, 2808, 2003, 2102, 2302, 2502, 2702 display device</p><p>3002 Touch panel</p><p>3004LED backlight</p><p>3100 Light-emitting element</p><p>3200 Light receiving element</p><p>2004 keyboard</p><p>2103 Audio input unit</p><p>2105 Battery</p><p>2308 electronic circuit</p><p>2304, 2404 recording media</p><p>2305 Controller</p><p>2306, 2307 sensor unit</p><p>2403 Speaker unit</p><p>2503 Peephole part</p><p>2602, 2704 screen</p><p>2703, 2802, 2804-2806 mirror</p><p>2801 Light source system</p><p>2803 Two-way color mirror</p><p>2807 Spectroscope</p><p>2809 Phase difference plate</p><p>2810 Optical projection system</p><p>2811 reflector</p><p>2812 light source</p><p>2813, 2814 lens array</p><p>2815 Polarization conversion element</p><p>2816 Condenser lens.</p>

Figures 1A to 1D show a cross-sectional view of the manufacturing process of a pixel TFT and a driving circuit TFT;

Figures 2A to 2D show a cross-sectional view of the manufacturing process of a pixel TFT and a driving circuit TFT;

Figures 3A to 3C show a cross-sectional view of the manufacturing process of a pixel TFT and a driving circuit TFT;

Figure 4 is an explanatory diagram of the structure of the LDD region of an n-channel TFT

Figures 5A to 5C show a cross-sectional view of the manufacturing process of a pixel TFT and a driving circuit TFT;

Figures 6A and 6B are top views showing the structure of a driving circuit TFT and a pixel TFT;

7A and 7B show a cross-sectional view of the TFT manufacturing process of a driving circuit;

Figures 8A and 8B show cross-sectional views of the TFT structure of the driving circuit;

Figures 9A to 9D show cross-sectional views of a pixel TFT structure;

Figure 10 is a top view showing a pixel portion of a pixel;

Figures 11A to 11C are cross-sectional views showing the manufacturing process of a spar semiconductor layer;

Figures 12A to 12C are cross-sectional views showing the manufacturing process of a spar semiconductor layer;

Figure 13 shows a cross-sectional view of the manufacturing process of a pixel TFT and a driving circuit TFT;

14A and 14B show a cross-sectional view of the manufacturing process of an active matrix liquid crystal display device;

Figure 15 is an explanatory diagram of a cylindrical spacer;

Figure 16 is a top view illustrating an input/output terminal layout, a wiring, a circuit layout, a spacer, and a liquid crystal display device sealing agent;

Figure 17 shows a perspective view of the structure of a liquid crystal display device;

Figure 18 is a block diagram illustrating the circuit structure of a liquid crystal display device;

Figures 19A and 19B are respectively a cross-sectional view of a TFT and an explanatory view of the structure of an LDD region;

Figures 20A and 20B are explanatory diagrams of the principle of ICP;

Figures 21A and 21B are explanatory diagrams of the relationship between the angles of a tapered portion of the edge portion of the W film formed by pattern and etching conditions;

Figures 22A and 22B show an example diagram of a portable information terminal;

Figures 23A to 23E show example diagrams of a semiconductor device;

Nos. 24A to 24D show the structural diagrams of a projection type liquid crystal display device; and

Figures 25A to 25C are electron micrographs showing the shape of an edge portion of the W film that has been formed by the pattern table .