DDR DRAM data coherence scheme
Abstract
The invention provides a double-data-speed dynamic random access memory that is read and written with data coherence, wherein the data is a continuous or inserted data burst type of any length, and the data is double-data-speed Dynamic random access memory readout depends on whether the starting address is odd or even and considers the row address strobe signal delay. Around the edges of the clock are used to transfer data to and from the double data speed. Dynamic random access memory. For writing data, only the starting address of the data burst is used to maintain data homology. The data homology system Guaranteed by reading the same data from the same memory cell after writing.
Term
No projected expiry on record.
- Priority
- Filed
- Granted
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17 claims: 17 independent, 0 dependent
- 1申請專利範圍 1 種資料讀取電料允許雙倍轉速度_隨機存取 5己憶體之資料同調，其包括： a. 以一時脈的兩緣讀取之儲存資料； b. 在供電m〇s(絲輪入細线)权之行位 址選通信號延遲； · C·該行位址麵信艇紗定該時脈之—緣被用來讀 取該儲存資料的第一資料； g d. 存資料藉由行位址選通信號週觸取至偶數與 可數位元線感測放大器； e. 藉由該位元線感測放大器讀取之資料組織成時脈正 緣貧料與時脈負緣資料； ί _脈正緣資_時脈正緣對應—選通器之輸出； 以及 §·該時脈負緣資料以時脈負緣對應該選通器之輪出。 !^翻顧第1撕狀資·取電路，其中當 貝料組触她為縣且該雜址選通 時脈週期的整數，或者該資料組起始位址為奇數2 仃位址廷通信號延遲非為時脈週期的整數時，來自偶 數位址的資料被組織成時脈正緣資料，來自奇數位址 的貧料被組織成時脈負緣資料。 如申請專利範圍第1項所述之資料讀取電路，其中當 請 閱 讀 背' ιέ 之 注， 事 項 再 頁 訂 φί 經濟部智恙財—負工消費合作社印繁 3 、.—、::1尺度適用中國國家標孽 (css ) A規格（ Μ〇X 297公釐 4 申請專利範圍 二資料組域恤騎數，贿位 =_r:或者當該資料組起 X仃位址k通k遽延遲非為時脈週期的整， 數位址的資料独織成貞時脈猶倾，奇數位址 的貧料被组織成正時脈端緣資料。 •請專利範圍第【項所述之資料讀取電路，其中當 Γ資料組位址為偶數，且該選通器之輸出的第二位I 係來自-偶數儲存位址時，資料同調存在 •如欠申請專利範圍第4項所述之資料讀取電路，其令該 貧料同調_於任何資料組長度的連續或者插 料爆衝。 .1資料寫人電路以允許雙倍倾速度_隨機存取 °己~•思體之資料同調，其包括： a·於時脈正緣使用一正緣資料選通信號以及於一時 脈負緣使用一負緣資料選通信號選通之資料； b.寫入偶數位址及奇數位址位元線感測放大器之資 料；以及 ' c•資料爆衝之起始位址決定哪些選通的資料連接至 该偶數位址位元線感測放大器，哪些選通的資料連 接至奇數位址位元線感測放大器。 卜申請專利範圍第6項所述之資料寫入電路，其中當 4賓料爆衝起始位址為偶數時，該正緣資料選通传號 ^¾1T------ (請先閱讀背面之注意事項再填寫本f) 7 · 六'申請專利範圍 選通之資料被連接至該偶數位址位元線感測放大器， quot;亥負緣資料選通信號選通之資料被連接至該奇數位址 位元線感測放大器。 8如申晴專利範圍第6項所述之資料寫入電路，其中當 邊資料爆衝起始位址為奇數時，該正緣資料選通信號 選通之資料被連接至該奇數位址位元線感測放大器， 该負緣資料選通信號選通之資料被連接至該偶數位址 位元線感測放大器。 9如申請專利範圍第Θ項所述之資料寫入電路，其中同 凋適用於任何資料組長度的連續或者插入型的資料爆 衝。 1〇 ·如申請專利範圍第6項所述之資料寫入電路，其中 係藉由在寫入後讀取相同記憶胞的相同資料以保證 資料同調。 11.一種雙倍資料速度動態隨機存取記憶體之讀取方 法，包括下列步驟： 經濟部智总財.4¾¾工消费合作社印製 a·連接儲存在記憶體的資料，其中偶數儲存位址的 • 資料連接至一偶數位元線感測放大器，奇數儲存 位址的資料連接至一奇數位元線感測放大器； b·當一資料組起始位址為偶數而行位址選通信號延 遲為時脈週期的整數時，或者當該資料組起始位 址為可數而行位址選通信號延遲為時脈週期的非 公董)---- Α8 Β8 — C8 quot;~ -~ — D8 ~、申請專利範圍 ~一~~- 正放日可’連接來自偶數位元線感測放大器的資料 至一正緣資料暫存器，以及連接來自奇數位元線 感測放大器的資料至一負緣資料暫存器； ^ 4為料組起始位址為奇數而行位址選通信號延 遲為時脈週期的整數，或者當該資料組起始位址 為偶數而行位址選通信號延遲為時脈週期的非整 數日可’連接偶數位元線感測放大器的資料至一負 緣資料暫存器，以及連接奇數位元線感測放大器 的資料至一正緣資料暫存器； d·使ΰ亥正％資料暫存器進入一選通器之資料對應時 脈正緣，使該負緣資料暫存器進入該選通器之資 料對應時脈負緣；以及 e，在該選通器之輸出產生一資料輸出。 12如申請專利範圍第11項所述之方法，其中連接來 自該偶數與奇數位元線感測放大器係與該資料組起 始位址與該行位址選通信號延遲有關，以維持資料同 調。 13 ·如申請專利範圍第i丄項所述之方法，其中該方法 適用於任何資料組長度的連續或者插入型資料爆衝。 14 ·如申請專利範圍第11項所述之方法，其中該行位 址選通信號延遲係在供電期間由基本輸入輪出系統 °又疋’邊延遲決定在讀取命令被設定之後讀取第一資 (請先閱讀背面之注意事項-^填寫本頁) 裝 、17 經濟部智忽財4局3(工闭費合作社印货 ~----~ 絰濟部智慧財凌^:只工消費合作社印災 479260 as Β8 C8 quot;quot;_____________ 六、申請專利範圍 ^ ^— 料的時脈週期數目。 15.-種寫人雙倍資料速度動態隨機存取記憶體之方 法，包括下列步驟： a.連接欲寫入記憶體的資料組資料至一解除選通 ES · OU ^ b·以資料魏選通信號正緣選通雜位元以連接該 資料位元至一資料要求選通信號正緣暫存器； c. 以資料要⑽通信號負緣選通資料位元以連接該 資料位元至一資料要求選通信號負緣暫存器； d. 當該資料組資料起始位址為偶數，連接該資料要 求選通信號正緣暫钟的簡至—偶數位元線感 測放大器以及連接來自該雜縣·信號負緣 暫存器的資料至-奇數位元線感測放大器； e. 當該資料組資料起始位址鱗數，連接來自該資 料要求選通信號正緣暫存器的資料至一奇數位元 線感測放大|§，以及連接來自該資料要求選通信 就貞緣暫存器的資料至—偶數位元線感測放大 器；以及 f·儲存該資料組資料至記憶體。 1 6 ·如申請專利麵第1 5項所述之方法，其中該方法 適用於任何H喊度喊觀麵人娜料爆衝。 1 7 · ”請專利範卿1 5項所述之方法，其中該偶數 479260 A8 B8 C8 D8 申請專利範圍 與奇數位元線感測放大器係以位元開關選擇 (請先閱讀背面之注意事項再填寫本頁) -裝· 、1T 經濟部智慧財是^ρ、工消費合作社印製 夂紙張尺度適用中國國家標準（CNS ) Α4規格（210xi$7公釐）
73 paragraphs in 2 sections, as filed
Data coherence method of double data speed dynamic random access memory
<p>10. . .Even BLSA</p><p>11. . .Odd BLSA</p><p>12. . .Condition A</p><p>13. . .Condition B</p><p>30. . .Data entry</p><p>32. . .Register reg_dqs_p</p><p> 33. . .Register reg_dqs <sub>＿</sub> n </p><p>38. . .BLSA</p><p>39. . .BLSA</p><p>34. . .Register</p><p>35. . .Register</p><p>14. . .Register</p><p>15. . .Register</p><p>16. . .Clockwise</p><p>17. . .Negative clock edge</p><p>18. . .Data output strobe</p><p>19. . .Output</p><p>50. . .Odd BLSA</p><p>51. . .Clock cycle</p><p>52. . .even</p><p>54. . .odd number</p><p>56. . .Clock cycle</p><p>57. . .odd number</p><p>58. . .Negative clock edge</p><p>59. . .even</p><p>60. . .Clockwise</p><p>70. . .Deselector</p><p>71. .Data request strobe signal positive edge strobe signal and data request strobe signal negative edge strobe signal</p><p>72. . .even</p><p>73. . .Odd BLSA</p><p>74. . .odd number</p><p>75. . .Even BLSA</p><p>76. . .Data coherence</p>
The present invention will be described with the following drawings, in which:
Figure 1a is a block diagram showing the connection of a dynamic random access memory that reads double the data speed.
Figure 1b shows the connection of the bit line sense amplifier data to a data output strobe.
Figure 2a is a block diagram showing the connection of a dynamic random access memory with a double data write speed.
Figure 2b shows the connection data into the bit line sense amplifier data.
Figure 3 shows the timing diagram of reading the double data speed of the dynamic random access memory.
Figure 4 shows the timing diagram of writing double data rate dynamic random access memory.
FIG. 5 is a flowchart of a method for reading data from a double-data-rate dynamic random access memory and maintaining the same data.
FIG. 6 is a flowchart of a method for writing data to double data speed dynamic random access memory and maintaining data homogeneity.
Background of the Invention: Technical Field of the Invention:
The invention relates to a semiconductor memory, and more particularly to a data coherence method for a double data speed dynamic random access memory.
Related prior technical notes:
The data in the double data rate dynamic random access memory (DDRDRAM) is read and written to the double data rate dynamic random access memory at both ends of the clock. In order to maintain data coherence, it must be determined Writing and reading a memory cell is actually performed in the same storage memory cell. Double data speed. The burst read operation of dynamic random access memory requires a start address and a data group length after the output data appears at the non-row address strobe delay. To read coherence, you must know whether the delay of the NOT row address strobe signal is an integer or a non-integer in order to understand that if the first part of the data is read at the positive or negative edge of the clock. When writing data, there is no NOT row address strobe signal delay. The starting address is odd or even, which is important to find the memory cell that stores the data.
U.S. Patent No. 5,901,109 discloses a synchronous dynamic random access memory (SDRAM) circuit capable of providing read and write control asynchronously and without clock restrictions. In U.S. Patent No. 5,892,730, Sato et al. Disclose that a synchronous dynamic random access memory can operate in pipeline mode or prefetch mode, which allows multiple data write modes to be executed on a chip. . In US Patent No. 5,402,388, Wojcicki et al. Disclose a method for adjusting the delay of a synchronous dynamic random access memory by adjusting the timing of the row address strobe signal corresponding to the system clock.
Brief description of the invention:
The invention uses the positive edge and the negative edge of the system clock to provide double data speed under burst mode. The read and write data of the dynamic random access memory are coherent. The data set can be of any length, and its starting data is written or read from even or odd addresses. If the starting address is even, the subsequent data of the data group is written or read from an odd address. If the starting address is odd, the subsequent data of the data group is written or read from an even address. Out. In order to read data, the computer basic input and output system is established during power supply. <img file="TW479260B_D0001.tif" /> The address strobe signal is delayed to determine the number of clock cycles for reading the first data after the read command is set. A bit switch is used to select the BLSA. When reading out stored data, the row address strobe signal delay is an integer or non-integer of the clock period. The row address strobe signal delay and the start address must be considered to maintain homology.
When the start address of the data group is even and the delay of the row address strobe signal is an integer of the clock period, or when the start address of the data group is odd and the delay of the row address strobe signal is a non-integer of the clock period During the read operation, the data of the odd BLSA and the even BLSA directly correspond to the clock of an output strobe. The positive edge of the clock is used to correspond to the even address data of the output strobe, and the negative edge of the clock is used to correspond to the odd address data of the output strobe. When the start address of the data group is even and the delay of the row address strobe signal is a non-integer of the clock period, or when the start address of the data group is odd and the delay of the row address strobe signal is an integer of the clock period, The data in the even BLSA are connected to the output strobe by a circuit means based on the negative edge of the clock, and the data in the odd BLSA are connected to the output strobe by the circuit means based on the positive edge of the clock.
In a write operation, the delay of the row address strobe signal is not a factor. The only criterion is to connect the data group data to the appropriate address location. For a write operation, the data bit of the data group is gated into the register by the data query strobe (DQS), and the data is requested to enter the register reg_dqs_p. A negative data requires the strobe signal to enter the register reg_dqs_n. If the starting address of the data group is even, the data gated into the register reg_dqs_p is connected to an even BLSA (BLSA_E), and the data gated into the register reg_dqs_n is connected to an odd BLSA (BLSA_O). If the starting address of the data group is odd, the data gated into the register reg_dqs_p is connected to an odd BLSA_O, and the data gated into the register reg_dqs_n is connected to an even BLSA_E.
Data homology is guaranteed by reading the same data in the same memory cell after the write operation. When the starting address of the data group is even and when the first bit of the output comes from an even storage address, Homology exists. Either continuous or inserted data sets can be read or written using the method of the present invention.
Schematic illustration
The present invention will be described with the following drawings, in which:
Figure 1a is a block diagram showing the connection of a dynamic random access memory that reads double the data speed.
Figure 1b shows the connection of the bit line sense amplifier data to a data output strobe.
Figure 2a is a block diagram showing the connection of a dynamic random access memory with a double data write speed.
Figure 2b shows the connection data into the bit line sense amplifier data.
Figure 3 shows the timing diagram of reading the double data speed of the dynamic random access memory.
Figure 4 shows the timing diagram of writing double data rate dynamic random access memory.
FIG. 5 is a flowchart of a method for reading data from a double-data-rate dynamic random access memory and maintaining the same data.
FIG. 6 is a flowchart of a method for writing data to double data speed dynamic random access memory and maintaining data homogeneity.
Explanation of main component symbols
10. . .Even BLSA
11. . .Odd BLSA
12. . .Condition A
13. . .Condition B
30. . .Data entry
32. . .Register reg_dqs_p
33. . .Register reg_dqs <sub>＿</sub> n
38. . .BLSA
39. . .BLSA
34. . .Register
35. . .Register
14. . .Register
15. . .Register
16. . .Clockwise
17. . .Negative clock edge
18. . .Data output strobe
19. . .Output
50. . .Odd BLSA
51. . .Clock cycle
52. . .even
54. . .odd number
56. . .Clock cycle
57. . .odd number
58. . .Negative clock edge
59. . .even
60. . .Clockwise
70. . .Deselector
71. .Data request strobe signal positive edge strobe signal and data request strobe signal negative edge strobe signal
72. . .even
73. . .Odd BLSA
74. . .odd number
75. . .Even BLSA
76. . .Data coherence
Detailed description of the preferred embodiment:
Figure 1a shows a block diagram of a double-data-rate dynamic random access memory. The data in the even BLSA10 and the odd BLSA11 are connected to the registers 14 and 15, which correspond to the positive clock edge 16 and the negative clock edge 17. In condition A12 and condition B13 shown in Figure 1b, the data is connected to the data registers 14 and 15. The data in the positive data register 14 corresponds to the clock of the data output multiplexer 18.Positive fate 16. Positive edge 16. The data in the negative edge data register 15 corresponds to the clock negative edge 17 of the data output strobe 18. The data is output 19 at the positive and negative edges of the clock, until the data at the data burst length is transferred. The length of the data group can be unlimited, and its starting address can be even or odd.
Reading data from a double-data-speed dynamic random access memory is based on the line address strobe signal delay determined by the BIOS (Basic Input Output System) during computer power up. Figure 1b shows the situation when the row address strobe signal is delayed by integer and non-integer clock cycles, and the data is read by the double-data-rate dynamic random access memory. When the starting address of the data group is even and the delay of the row address strobe signal is an integer, the condition A12 is used to connect the data of the even address BLSA10 and the odd address BLSA11 to the output strobe through the registers 14 and 15 Device 18, wherein the data of the even address uses the positive clock edge 16 and the data of the odd address uses the negative clock edge 17. When the start address of the data group is odd and the delay of the row address strobe signal is non-integer, the condition A12 is used to connect the data of the odd address BLSA11 and the even address BLSA10 to the output selection through the registers 14 and 15 The pass device 18 uses clock positive edge 16 for data at even addresses, and clock negative edge 17 for data at odd addresses.
Continue to refer to Figures 1a and 1b. When the starting address of the data group is odd, the delay of the row address strobe signal is an integer, and the condition b13 uses the negative clock edge 17 to connect the data of the even address BLSA10 to the negative clock edge The register 15 to the output strobe 18, and the data connected to the odd-numbered address BLSA11 using the clock positive edge 16 pass the clock negative edge register 14 to the output strobe 18. When the starting address of the data group is even and the delay of the row address strobe signal is non-integer, case b uses the negative clock edge 17 to connect the data of the even address BLSA10 via the negative clock edge register 15 to the output gate. And the clock positive edge 16 is used to connect the data of the odd address BLSA11 to the clock positive edge register 14 to the output strobe 18.
Referring to Fig. 2a, a block diagram showing the writing of data to double data speed dynamic random access memory is shown. Among them, the row address strobe signal delay is not included in the writing of the data set. Only the start address is required to connect the input data to the appropriate BLSA 38 or 39. Data enters 30. A positive edge data strobe signal (DQS_P) is gated into the integer reg_dqs_p32, and a negative edge data strobe signal (DQS_N) is gated into the integer reg_dqs_n33. As shown in Figure 2b, when the starting address of the data group is an even address, in case C, the data requires that the even data of the strobe register 34 be connected to the even address BLSA38, and the data comes from the data. The odd data of the strobe negative register 35 is required to be connected to the odd address BLSA39. When the data group start signal address is odd, use case D, the data requires the data of the strobe positive edge register 34 to be connected to the odd address BLSA39, and the data requires the data of the strobe negative register 35. Connected to the even address BLSA38.
Referring to Figure 3, a timing diagram of the read operation of the dynamic data access memory with double data speed is shown. It executes a read command at the rising edge of the clock. If the row address strobe signal delay is a clock cycle, Non-integer, for example, the third figure shows 1.5 clock cycles. The first data D00 of the starting address of the data group appears on the negative edge of the second clock cycle. The subsequent data of the data group is at each clock. The positive edge and the negative edge of the clock appear alternately until the length of the data set ends. If the delay of the row address strobe signal is an integer of the clock period, such as the two clock periods shown in the figure, the first data D00 of the starting address of the data group appears at the positive edge of the third clock period. Subsequent data from the data set appear alternately at each negative clock edge and positive clock edge until the end of the data group length. Among them, a larger integer and non-integer row address strobe signal delay than the embodiment shown in the third figure may be required.
Please refer to Figure 4, which shows the timing diagram of writing data group data to double data speed dynamic random access memory. The write command is performed at the rising edge of the clock cycle. The first data D10 of the data group is in the data request. The rising edge of the strobe signal is written into the next data of the data group. D12 is written on the negative edge of the data request strobe signal, and the data of the data group continues to be sequentially on the positive and negative edges of the data request strobe signal. Write double data speed to dynamic random access memory until the end of the data group length.
In the fifth figure, a coherence method of data continuation from the double data speed dynamic random access memory is shown. The data of the even address is connected to the even BLSA, and the data of the odd address is connected to the odd BLSA50. If the delay of the row address strobe signal is an integer of the clock period 51, and the start address of the data group is an even number 52, then the even BLSA is connected to the temporary register corresponding to the positive edge of the clock, and the odd BLSA is connected to the temporary register corresponding to the negative edge of the clock. Memory. If the row address strobe signal delay is an integer of the clock period 51 and the data group start bit is an odd number 54, then the even BLSA corresponds to the negative edge of the clock and is connected to the register, and the odd BLSA corresponds to the positive edge of the clock to the register. Device. If the row address strobe signal delay is a non-integer of the clock period 56 and the data group start address is an odd 57, the even BLSA corresponds to the positive edge of the clock connected to the register, and the odd BLSA corresponds to the negative edge 58 of the clock. Connect to the scratchpad. If the row address strobe signal delay is a non-integer of the clock period 56 and the data group start address is an even number 59, then the even BLSA is connected to the register for the negative clock edge and the odd BLSA is connected for the positive clock edge 60 connection. To the register. The data of the clock register enters the gate to generate one of the data sets. The output is the same as the writing of the data set.
In the sixth figure, a coherent method for writing data to a double data speed dynamic random access memory is shown, in which the data group data is connected to a de-gating device 70, and the data bits are selected by a data request communication. The positive edge strobe signal and a data request strobe signal the negative edge strobe signal 71 is strobe. If the starting address of the data group is even 72, the register data gated by the positive edge of the data request strobe signal is connected to the even BLSA and the register data gated by the negative edge of the data request strobe signal is connected to Odd BLSA73. If the starting address of the data group is an odd number 74, the register data gated by the positive edge of the data request strobe signal is connected to the odd BLSA, and the register data gated by the negative edge of the data request strobe signal is connected To the even number BLSA75, the data set data is stored at the data homology 76 to double the data speed of the dynamic random access memory.
However, the above is only a preferred embodiment of the present invention. Those skilled in the art can understand that many changes in types and details are possible, but they do not depart from the spirit and scope of the present invention.
Contents2
8 sheets
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| Document | Relation | Office | Cited during |
|---|---|---|---|
| US7522440B2 | Cited by | United States of America | Applicant |
2 members in 2 offices
Priority claims4
| Document | Office | Kind | Date |
|---|---|---|---|
| 09453045 | United States of America | – | |
| 45304599 | United States of America | A | |
| 19990453045 | – | – | – |
| US19990453045 | – | – | – |
Members2
| Document | Office | Kind | |
|---|---|---|---|
| TW479260BThis record | Taiwan Province of China | B | |
| US6453381B1 | United States of America | B1 |
2 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Annulment or lapse of patent due to non-payment of feesLapsedMM4A | MM4A | |
| Issue of patent certificate for granted invention patentGrantedGD4A | GD4A |
Numbers
- Publication
- 479260
- Publication, DOCDB
- 479260
- Publication, EPODOC
- TW479260B
- Application
- 89119193
- Application, DOCDB
- 89119193
- Application, EPODOC
- TW20000119193
Titles4
- English
- DDR DRAM data coherence scheme
- Chinese
- 雙倍資料速度動態隨機存取記憶體之資料同調方法
- Unlabeled
- 雙倍資料速度動態隨機存取記憶體之資料同調方法
- Unlabeled
- Data coherence method of double data speed dynamic random access memory
Classification
- CPC, 3
- G11C7/1066
- G11C7/1018
- G11C7/1072
- IPC, 1
- G11C7 10