Switching down conversion mixer for use in multi-stage receiver architectures

Switching down-conversion mixer used in multi-stage receiver architecture

Scope of invention

The present invention relates generally to mixers, and more particularly to a switched down-conversion mixer circuit for a multi-stage receiver architecture, such as a 90° quadrature receiver.

Background of the invention

A trend in the wireless communications industry today is to integrate all radio frequency (RF) transceiver functions into a single module. The term "single chip transceiver" is often used by industry insiders when discussing this topic. Although this work is accompanied by technical challenges, a few academic supporters still believe that direct conversion technology can provide a solution with sales potential. Those who are familiar with the art can appreciate that direct conversion refers to the technique of receiving an input radio frequency signal and converting it directly to a set of fundamental frequency (audio) components without converting to a set of intermediate frequency (IF) components.

In the receiver architecture considered above, the downmixer circuit plays a key role. It must be fast and support high-frequency operation. It must exhibit strong local oscillation (LO) isolation characteristics, since the RF signal and the local oscillation reference operate at the same frequency. It should have a low noise figure to improve the sensitivity of the receiver. In addition, it must be energy efficient to help the competition of current draw. Based on the foregoing, it is very advantageous to provide an improved downmixer circuit and method that is best used in a multi-stage direct conversion receiver.

Description of preferred embodiments

Although the features of the present invention are summarized in the scope of the patent application, it is believed that the present invention will be better understood from the following description and accompanying drawings, in which the same reference values are used for the drawings.

Referring now to FIG. 1, it shows a block diagram of a prior art receiver architecture 10 employing a downmixer circuit. The receiver 10 includes an antenna 100 for receiving radio frequency (RF) signals. By way of example, but not limitation, the received radio frequency signal may have a frequency of 450 MHz. The signal is filtered by the passive filter 102 and amplified by the pre-amplifier 104. The amplified signal is mixed with a first local oscillator (LO) signal in the mixer 106. By way of example, but not limitation, the first local oscillation reference can be a 495 MHz signal, which is mixed with the received signal of 450 MHz to form a first intermediate frequency signal of approximately 45 MHz. The first intermediate frequency signal is filtered by the passive filter 108. A second mixing stage 110 mixes the first intermediate frequency signal with a 45.45 MHz second local oscillation, and mixes it with the 45 MHz first intermediate frequency signal to form a second intermediate frequency of approximately 450 kHz Signal. The down-converted second intermediate frequency signal is filtered by a second filtering stage 112 and demodulated by the detection circuit 114. The detected signal is then sent to the speaker 116.

Next, refer to FIG. 2, which depicts a block diagram of a direct conversion receiver. The front end of the receiver 20 is similar to the front end of the receiver 10 in FIG. 1. In comparison, it includes: an antenna 100, a passive filter 102 and a pre-amplifier 104. The amplified signal is mixed with a first local oscillation signal in the mixer 206. By way of example, but not limitation, the first local oscillation reference is a 450 MHz signal, which is mixed with the received signal of 450 MHz to form the fundamental frequency I and Q components, which are respectively generated by the I and Q components of the fundamental frequency filter 208 Q is filtered, demodulated by the demodulation circuit 210, and sent to the speaker 116. Those familiar with the art will notice that the direct conversion receiver in Figure 2 does not use the two-stage IF down-conversion circuit in Figure I.

FIG. 3 depicts a detailed circuit block diagram of the mixer circuit 206 according to the prior art. Upon examination in detail, those familiar with the art will understand that the mixer circuit in Figure 3 is a well-known Gilber mixer, often referred to as a Gilber cell mixer. This type of mixer has often been used in the direct conversion receiver 20 of FIG. 2. However, when it is to be integrated into a single silicon module, this receiver has a set of serious limitations. First, the local oscillation isolation becomes the separation that limits the distance to be measured in microns. Second, the number of transistors required to generate 90-degree phase difference signals with two fundamental frequencies increases the current draw requirements of current devices.

FIG. 4 depicts a detailed circuit block diagram of a switching down-conversion mixer circuit according to the present invention. After inspection, those familiar with the art will understand that the mixer 400 in FIG. 4 is different from the mixer 300 in FIG. 3 in that it is a non-differential circuit that passes through a single input path 401. According to the present invention, the mixer 400 includes a single voltage-to-current converter 402. By comparison, the Gilber cell mixer 300 in FIG. 3 is a differential circuit with two parallel input paths, and each path applies two voltage-to-current converter pairs 301, 303 and 305, 309.

Returning to FIG. 4, the voltage-to-current converter 402 establishes a single current node 404. By comparison, each of the voltage-to-current converter pairs 301, 303 and 305, 309 of the Gilber cell mixer 300 in FIG. 3 provides a current node within its respective parallel input path.

Returning to FIG. 4, the mixer 400 employs a switching network 408 including multiple stages. According to the present invention, the switching network 408 has four levels, each denoted as 406. Those who are familiar with this technique will understand that configurations other than level four can also be achieved. The number of stages is only the number of stages that determine the attainable output. In the example of the present invention, the mixer 400 is applied to a ninety degree phase difference receiver. In this regard, four output stages are required, so the switching network 408 applies four stages. If 3, 6, or 8 output stages are considered advantageous, the number of stages of the switching network will need to be changed to suit the receiver design. However, it is important to note that each stage 406 of the switching network 408 is connected to a single current node 404.

By comparison, the Gilber cell mixer 300 in FIG. 3 uses a decentralized switching network type, which uses four current nodes 302, 304, 306, and 308, two each in its own parallel input path. The mixer 400 in FIG. 4 produces a<img file="TW443045B_D0001.tif" />The four states of output, so it has better cost and current benefits than the previous technology. The cost-effectiveness is achieved by the reduced part count between the mixer 400 of FIG. 4 and the mixer 300 of FIG. 3. The current benefit is partly improved by the reduction of some counts, and partly by the non-distributed switching network type of the switching network 408. This can be immediately understood by referring to Figures 6 and 7.

Figures 6 and 7 show timing diagrams of the operation of the mixer circuits of Figures 3 and 4 and 5, respectively. Those familiar with the art will understand that the mixer circuit 300 of FIG. 3 requires at least two mixer circuit stages to be active at any moment to generate an output state.<img file="TW443045B_D0001.tif" />. By comparison, the mixer 400 only needs one mixer circuit stage 406 to be active to generate an output state<img file="TW443045B_D0003.tif" />. The duty cycle of the operation of the control switching network 408 in FIG. 7 is derived from a clock signal generator circuit (not shown). The clock in FIG. 7 is delivered to the control lines labeled A, B, C, and D and connected to the individual stages 406 of the switching network 408. During the existence of the clock signal on a control line A, B, C, or D, only the receiving stage 406 is active (ie, activated).

This type of configuration results in the mixer circuit greatly reducing the cost and current draw requirements of the device. In battery-operated, handheld, consumer electronics, and communication devices, such as two-way radios, cellular phones, personal mobile phones, pagers, etc., it is equivalent to two different competitions: longer battery life and reduced device costs. Sexual benefits.

FIG. 5 depicts a detailed circuit block diagram of the second embodiment of the switching mixer circuit of FIG. 4. FIG. Those familiar with the art will understand that the mixer circuit 500 of FIG. 5 is a differential embodiment of the circuit 400 disclosed in FIG. 4. It uses parallel input paths. It is worth noting that each individual input path has a voltage-to-current converter 501 and 505. Each input path has a current node 502 and 506. Each input path has a switching network 510 and 515. Each switching network is connected to a single individual current node. It is worth noting that during operation, only one switching network level in each individual switching network 510 and 515 is active at each instant.

The mixer circuits 400 and 500 of the present invention can be characterized as having a single RF transistor operating in a linear mode to generate a current proportional to the intensity of the received RF input signal. The output current of this transistor is then fed into a direct conversion switching network. According to the present invention, the switching network is a four-level network that supports the operation of a ninety degree phase difference receiver.

Each of the four levels in the network has its own transistor, such as an NPN transistor, which switches the current to four to generate two differential baseband signals<img file="TW443045B_D0001.tif" />The load resistance. The four switching network levels are controlled by clock signals labeled A, B, C, and D. The relationship between the clock signals is shown in Figure 7, and the frequency is equal to the carrier frequency of the received RF input signal. The four-level switching action that generates two fundamental frequency T and Q signals is governed by the following equation:

<img file="TW443045B_D0005.tif" />

This mixer circuit, which is fully integrated into an integrated circuit (IC), has several advantages and exhibits better performance than current integrated mixers, such as Gilber cell mixers. By way of example rather than being limited to examples, a single RF transistor determines the noise index of the mixer to allow the design of a low-cost, high-robust receiver. Comparing the current draw exhibited by the Gilber cell mixer, a single transistor generates the I and Q fundamental frequency signals, which greatly reduces the current draw in the combined device. Reducing current draw is equivalent to longer battery life in communication devices that use batteries.

<p>10 Receiver architecture 401 input</p><p>20 Receiver 402 current converter</p><p>100 Antenna 404 Single current node</p><p>102 Passive filter 406 receiving stage</p><p>104 Pre-amplifier 408 switch network</p><p>106 Mixer 500 mixer</p><p>108 Passive filter 501, 505 current converter</p><p>110 Mixing stage 502, 506 current node</p><p>112 Filter stage 510, 515 switch network</p><p>114 Detection circuit 520 input</p><p>116 speaker</p><p>200 Multistage receiver</p><p>206 Mixer</p><p>208 I and Q fundamental frequency filters</p><p>210 Demodulation circuit</p><p>300 Mixer</p><p>301, 303 Current converter pair</p><p>302, 304, 306, 308 current node</p><p>305, 309 Current Converter Pair</p><p>400 Mixer circuit</p>

Figure 1 depicts the receiver architecture of a downmixer circuit based on the prior art;

Figure 2 depicts a direct conversion receiver according to the present invention;

Figure 3 depicts a detailed circuit block diagram of a Gilbert (Gilbert) cell mixer circuit according to the prior art;

Figure 4 depicts a detailed circuit block diagram of a switching down-conversion mixer circuit according to the present invention; and

FIG. 5 depicts a detailed circuit block diagram of the second embodiment of the switching mixer circuit of FIG. 4; and

6 and 7 respectively show the timing diagrams of the operation of the mixer circuit in the third, fourth and fifth diagrams.