Integrated multiport switch having shared media access control circuitry

Integrated multi-port switch with shared medium access control circuit

Description of related patent applications

This patent application claims priority based on the provisional patent application with application number 60/038,025 dated February 14, 1997, and the patent application is hereby incorporated for reference.

The present invention relates to network switching, especially to the shared multi-port media access control on the logic chip of data network switching.

The data network switch allows data communication in most media sites on the local network. Through the data network switch media access control (MAC), the function of the network interface card or circuit can be achieved in each switch port, and data frames or packets can be transmitted between stations. MAC monitors the transmission of traffic from the port to the network, receives the traffic from the network at the port, and coordinates the data volume at the port to avoid collisions. The network switch sends the data frame received from the sending station to the destination station according to the header information in the received data frame. The transmit and receive buffers of each port are connected to the MAC. Depending on the operating mode, incoming packets are temporarily maintained in the port receiving buffer, and can be moved to the memory outside the switch for later transmission, or placed in the transmission buffer of the appropriate port for immediate transmission from the network.

Generally, the packet transmission events are tracked to provide a statistical analysis basis for each data network switching port during network operation. For example, the number of transmitted packets, received packets, transmission collisions, etc. can be calculated and polled periodically. By using statistical counters, you can determine incorrect device operations such as missing packets. Generally, each MAC unit may include a receiving state machine and a transmitting state machine. The transmitting state machine has an internal counter with a limited capacity to count the few transmission event parameters of each frame, which passes through a separate switch port. Whenever the items in the box are identified, the flip-flops belonging to the special parameters are added respectively. As for each entry frame, temporarily store it in the receiving FIFO buffer, read the individual flip-flops in the receiving state machine, and add the final result data to the back of the frame. As for the leave box, similar processing occurs, so the leave box temporarily stored in the transmit FIFO buffer includes additional data related to the receive operation and the transmit operation. When the frame is transmitted from the transmission FIFO buffer, the transmission operation data is added.

When the data network becomes more efficient and the amount of explanation increases, the additional operating parameters become more significant. Tracking more parameters requires increasing the complexity of the MAC, such as providing more registers and supporting logic components, and a larger buffer capacity. Integrating these additional components of each MAC on the switch logic chip will become a burden on the chip architecture. As the development of switches requires larger flow capabilities and the number of switch ports increases, the effective use of the chip architecture becomes more important.

The present invention overcomes the above-mentioned needs and shortcomings. Part of the method is to realize that certain MAC functions of each port can be executed by a circuit, and the circuit does not need to be individually set in each port in a conventional manner. The advantage of the present invention is to set the combinational logic and register configuration to perform similar functions of most switch ports. This advantage is partly based on the realization that if the function of the shared circuit can be correctly related to each port at any known time, the different settings of similar circuits in each port will become redundant and unnecessary.

Another advantage of the present invention is to maintain the current access state of each of the multiple switch ports in a single state storage location, thereby simplifying the access to the MAC state and update of the storage port. Another advantage of the present invention is that the access state is stored in combination with a single shared combinational logic and register configuration, so that the MAC function of each of the multiple ports can be executed in a time-sharing manner. Therefore, compared with conventional devices, the present invention provides more efficient use of chip resources and architecture space.

From the following detailed description, those skilled in the art will better understand the additional advantages of the present invention. Among them, only the preferred embodiments of the present invention are shown and described, and only the best mode for implementing the present invention will be described. It will be understood that the present invention is capable of other and different embodiments, and its details can be modified in many ways without departing from the present invention. Therefore, the drawings and descriptions should be regarded as illustrative rather than restrictive.

Referring now to the drawings, all the elements with the same reference numbers denote the same elements, in which: Figure 1 is a block diagram of the packet switching system environment of the present invention.

Figure 2 is a block diagram of a multi-port switch related to the present invention, which can be used in the packet switching system of Figure 1.

Figure 3 is a block diagram illustrating media access control according to the present invention.

FIG. 4 is a detailed block diagram of a preferred configuration of the media access control logic unit 80 and the state memory control unit 82 of the present invention.

Figure 5 is a waveform diagram illustrating the operation of the hierarchical pipeline according to the present invention.

The present invention herein can be best represented by a packet-switched network environment such as Ethernet (IEEE802.3). It should be clear from the following detailed description that the present invention is also applicable to other packet switching systems. Figure 1 is a block diagram of a packet switching system 10, which provides the environment of the present invention. The packet switching network includes an integrated multi-port switch (IMS) 12 to facilitate data packet communication between network stations. The network stations have different configurations. In this example, 24 10 million bits per second (Mb/s) network stations 14 transmit and receive data at a network data rate of 10Mb/s, and 2 100Mb/s network stations 16 use 100Mb/s. s network speed to send and receive data packets. The multi-port switch 12 selectively transmits the data packet received by the network station 14 or 16 to an appropriate destination in accordance with the Ethernet protocol.

The 10Mb/s network station 14 transmits data packets to the multi-port switch 12 and receives data packets from the multi-port switch 12 via the medium 18 and in accordance with the half-duplex Ethernet protocol. The Ethernet protocol ISO/IEC8802-3 (ANSI/IEEE Std.802.3, 1993 Ed.) defines a half-duplex media access mechanism, which allows all stations 14 to access the network channel equally. The traffic in the half-duplex environment is not distinguishable or prioritized on the media 18. On the contrary, each station 14 includes an Ethernet interface card, which uses Carrier Sense Multiple Access (CSMA/CD) with collision detection to monitor the traffic on the media. The disappearance of network traffic is detected by sensing the unassigned of the receiving carrier on the media. Any station 14 that has data to transmit will try to access the channel by waiting for a preset time after the receiving carrier on the media is not designated. This preset time is called the Inter-Packet Gap (IPG). If most stations 14 have data to be transmitted on the network, each station will try to transmit in response to the unspecified sense of the receiving carrier on the media, and cause collision after the IPG gap. Therefore, the transmitting station will monitor the media to determine whether a collision has occurred due to the simultaneous transmission of data by another station. If a collision is detected, both stations will stop and try to transmit after waiting for an indefinite period of time.

The 100Mb/s network station 16 preferably operates in the full-duplex mode according to the proposed Ethernet standard IEEE802.3x full-duplex with traffic control-working draft (0.3). The full-duplex environment provides a two-way point-to-point communication link between each 100Mb/s network station 16 and the multi-port switch 12, so the IMS and each station 16 can transmit and receive data packets at the same time without collision. The 100Mb/s network stations 16 are each connected to the network media 18 via 100-based Tx, 100-based T4, or 100-based FX-type 100Mb/s physical (PHY) devices 26. The multi-port switch 12 includes a media independent interface (MII) 28 to provide a connection with a physical device 26. The embodiment of the 100Mb/s network station 16 is a server or a router to connect to other networks. If necessary, the 100Mb/s network station 16 can also be operated in half-duplex mode. Similarly, the 10Mb/s network station 14 can be modified to operate according to a full-duplex protocol with throughput control.

As shown in FIG. 1, the network 10 includes a serial switching transceiver 20 called QuEST to perform time-sharing demultiplexing of data packets transmitted between the multi-port switch 12 and the 10 Mb/s station 14. The magnetic converter module 19 maintains the signal waveform on the medium 18. The multi-port switch 12 includes a transceiver interface 22. The transceiver interface 22 uses a time-sharing multiplexing protocol to receive data packets from each switch transceiver 20 in a single serial non-return-to-zero (NRZ) interface 24 and transfer data The packet is sent to each switching transceiver 20. The switching transceiver 20 receives the packet from the serial NRZ interface 24, demultiplexes the received packet, and outputs the packet to the appropriate end station 14 via the network medium 18. In the exemplary embodiment herein, each switching transceiver 20 has 4 independent 10Mb/s twisted pairs, and uses 4:1 multiplexing in the serial NRZ interface to make the pins required by the multi-port switch 12 ( The number of PINs is reduced by only a quarter.

Multi-port switch 12 includes: decision engine, switching engine, buffer memory interface, configuration/control/status register, management counter, and MAC (Media Access Control) protocol interface to support data in the Ethernet port Packets are sent to service network stations 14, 16. The multi-port switch 12 also includes enhanced functions to make intelligent switching decisions and provide statistical network information to external management entities in the form of management information base (MIB) targets, as described below. An additional interface is provided to achieve external storage of packet data and switching logic so that the chip size of the multi-port switch 12 is extremely small. For example, the multi-port switch 12 includes a synchronous dynamic RAM (SDRAM) interface 32 to provide access to an external memory 34 to store received frame data, memory structure, and MIB counter information. The memory 34 is 80, 100, or 120 MHz synchronous DRAM, which has a memory size of 2 or 4 Mb.

The management port 36 enables an external management entity to control all operations of the multi-port switch 12 via the management MAC interface 38, and the PCI interface 39 allows the management entity to access via the PCI host and bridge 40. Or the PCI host and the bridge 40 can be used as an expansion bus for most IMS devices.

The internal decision engine in the switch 12 selectively transmits data packets received from a source to at least one destination station. If the logic does not use an internal decision engine, it can be replaced by an external specification detector. The external specification detector interface (ERCI) 42 allows the use of an external specification detector 44 to make transmission frame decisions instead of the internal decision engine. Therefore, the transmission frame determination can be performed by the internal switching engine or the external specification detector 44.

The LED interface 46 sends the condition status of each port at the end of the clock and drives the LED external logic 48. The LED external logic 48 sequentially drives the LED display element 50 for human reading. The oscillator 30 provides a 40 MHz clock input for the system function of the multi-port switch 12.

Figure 2 is a detailed block diagram of the multi-port switch related to the present invention, which can be used in the packet switching system of Figure 1. The multi-port switch 12 includes 24 10Mb/s media access control (MAC) ports 60 to facilitate half-duplex transmission and reception of data packets between each 10Mb/s network station 14 (ports 1-24) , And two 100Mb/sMAC ports 62 for each 100Mb/s network station 16 (ports 25, 26) to send and receive data packets in full duplex mode. As mentioned above, the management interface 36 also operates according to the MAC layer protocol (port 0).

Each MAC port 60, 62, and 36 includes conventional logic and register access control circuits to control data transmission, data reception, and collision coordination in the port. Each port is also provided with a receiving first-in first-out (FIFO) buffer 64 and a transmitting FIFO buffer 66. The external memory interface 32 is connected to each MAC receive FIFO buffer by a common bus, and the external memory interface 32 is connected to each MAC transmit FIFO buffer by another common bus.

The data packet from the network station is received by the corresponding MAC port and stored in the corresponding receiving FIFO buffer 64. The received data packet is output from the corresponding receiving FIFO buffer 64 to the external memory interface 32 to be stored in the external memory 34.

The header of the received packet is also sent to the decision engine, which includes an internal specification detector 68 and an external specification detector interface 42 to determine which MAC ports will output data packets. The transmission of the packet header to the internal specification detector 68 or the external specification detector interface 42 depends on the operating configuration of the multiport switch 12. The use of the external specification detector 44 provides the following advantages such as increased capacity, random arrangement in the decision queue so that the frame is completely buffered in the external memory before making the decision of the transmission frame, and the order in which the decision is made is the same as that of the multi-port switch 12. The order in which the boxes are received is irrelevant.

The internal specification detector 68 and the external specification detector 44 provide decision logic to determine the destination MAC port of the known data packet. The decision engine instructs the known data packet to be output to a single port, multiple ports, or all ports (ie, broadcast). Each data packet includes a header with source and destination addresses, and the decision engine can identify the appropriate output MAC port accordingly. The destination address corresponds to a virtual address. In this case, the decision engine recognizes the output ports of most network stations. Alternatively, the received data packet includes a VLAN (virtual LAN) tag frame according to the IEEE802.1d protocol to designate another network (via one of the routers located at 100Mb/s site 16) or a group of designated sites. Therefore, the internal specification detector 68 or the external specification detector 44 can determine through the interface 42 that the frame temporarily stored in the buffer memory 34 should be output to a single MAC port or multiple MAC ports.

The decision engine outputs a transmission decision in the form of a port vector to the switch subsystem 70 to identify each MAC port, which should receive the data packet. The port vector from the detector of appropriate specification includes the address location of the data packet stored in the external memory 34, and the identification code of the MAC port to receive the data packet for transmission (for example, MAC ports 0-26). The switch subsystem 70 retrieves the data packet identified in the port vector from the external memory 34 via the external memory interface 32, and provides the retrieved data packet to an appropriate transmission FIFO 66 of the identified port.

The additional interface provides management and control information as shown in the following components. The management data interface 72 enables the multi-port switch 12 to exchange control and status information with the switch transceiver 20 and the 100Mb/s physical device 26 according to the MII management standard (IEEE802.3u). The management data interface 72 also outputs a management data clock (MDC) for timing reference on the bidirectional management data IO (MDIO) signal path. The PCI interface 39 is a 32-bit PCI version 2.1 compliant servo interface for the PCI host processor 40 to access the internal IMS status and configuration register 74, and to access the external memory SDRAM 34. The PCI interface 39 can also be used as an expansion bus for multiple IMS devices. The management port 36 interfaces with an external MAC engine through a standard seven-wire inverted serial GPSI interface, so that the main controller can access the multi-port switch 12 through a standard MAC layer protocol.

Figure 3 is a block diagram illustrating the system of Figure 1 for media access control according to the present invention. In contrast with the configuration in Figure 2, a single media access control logic unit 80 is set up for the common use of 24 10Mb/s switch ports 60 and MII management control ports. The unit 80 is connected to the transceiver interface 22 through a transmission connection and a reception connection. The unit 80 is also connected to the transmit FIFO 64 and the receive FIFO 66 at each port 60. It should be understood that although only a single port FIFO pair is shown for the convenience of description, the corresponding FIFOs of all ports 60 can be represented. FIFO64 and FIFO66 are connected to the bus 84. Although only a single line, bus 84 indicates that all ports 60 receive FIFOs are connected to the shared receive bus in the external memory interface 32, and all ports 60 transmit FIFOs are connected to the shared transmit bus in the external memory interface 32.

The state memory control unit 82 stores the media access state of each port 80. The unit 82 is connected to the unit media access control logic unit 80 to facilitate the transfer of status data. Data communication also exists between the state memory control unit 82 and the transceiver interface 22. The state memory control unit 82 has a clock input to receive an 80 MHz signal. As described in detail below, the clock signal provides synchronization timing for the time-sharing media access control function, which is executed by the logic unit 80 for each of the 24 switch ports 60.

FIG. 4 is a detailed block diagram of a preferred configuration of the media access control logic unit 80 and the state memory control unit 82 in FIG. 3. FIG. The state memory control unit 82 includes a state memory 90, an output register 92, an input register 94, a counter 96 and a delay circuit 98. The state memory 90, which stores the access state in each port 60, can be, for example, a random access memory (RAM) or one or more registers to which each port 60 belongs. The output register 92 and the input register 94 are connected to the state memory 90 to receive data from the state memory or input data to the state memory respectively. The counter 96, which has an input from an 80 MHz clock source, outputs a data signal with enough bits to uniquely identify each port 60. For the 25-port embodiment in Figure 1, the counter output signal is preferably 5 bits in length. The value of this signal is increased by one when it receives each pulse of the clock signal.

The counter output signal is sent to the output register 92 to identify the out port, and the state memory data is accessed from the state memory 90. The counter output signal is also sent to the delay circuit 98, which holds and delays the signal for most clock stages. The output of the delay circuit 98 is sent to the input register 94 to identify the port to store data in the state memory 90. Therefore, the time period between the acquisition of the stored data of a known port and the new data written into the port is determined by the number of clock stages delayed by the delay circuit 98. The determination of this number is determined by the number of clock pipeline stages required by the MAC logic unit 80. Registers, counters, and delay circuits are all conventional components.

The processing of the media access control function and the indication of the access status occur in the combinational logic unit 100, and the combinational logic 100 includes a majority logic gate. The register 102 connects the input data to the logic unit, such as the status output register 92 and the transceiver interface 22. After processing the data received from the register 102, the logic unit outputs the processed data to the register 104. The processed data includes commands to be sent to the FIFO at the relevant port, any communication data to be transmitted, and changes to the port access status (if any), and the latter is sent to the status input register 94. The input data of the register 102, the transmission of data from the register 102 to the logic unit 100 for processing, the transmission of processed data from the register 104 to the status input register 94, and the update of the status memory 90 all occur In the sequential clock pipeline stage.

The waveforms in Figure 5 illustrate hierarchical pipeline operation. In a preferred embodiment, the delay circuit 104 includes two delay stages. The waveform (a) represents the 80Mhz clock signal, and the waveform (b) represents the output of the counter 96 in each cycle of the clock signal of the waveform (a). This signal identifies the MAC port and increases with each clock signal, thereby establishing a sequential time-sharing operation. Each clock cycle therefore defines a MAC slot to correspond to the port pointed to by the counter. For the convenience of description, the MAC slot pointed to by the counter output in the first clock cycle is slot 16. Waveforms (c) and (d) represent the MAC slot identification of two delay stages in each clock signal cycle. Therefore, the MAC slot 16 is represented by the waveform (c) in the second clock cycle and the waveform (d) in the third clock cycle.

Each of the waveforms (b) to (c) is related to one of the three-level media access control actions (as shown in bold type launch, capture and update), so it can be identified that the action is related to which MAC port . The three actions are operated at the same time for different MAC ports in each clock cycle. The figure illustrates the three operating levels of MAC port 16. The emission stage of this port occurs in the first clock cycle. In this cycle, the counter recognizes the port 16 to access data from the state memory 90 and store it in the register 92. In the next clock cycle, the capture stage of MAC port 16 occurs. The data from the register 92 and the interface of the transceiver are then input to the register 80 and processed by the combinational logic unit 100, and the final data is stored in the register 104. Also in this cycle, the counter will identify the next MAC port when the transmitter is operating. In the next clock cycle, the update level of MAC port 16 occurs. The status update data of the register 104 is transferred to the input register 94 and stored in the status memory 90. The operation data is transmitted to the appropriate FIFO, and the media access control of each MAC port is continued in this order.

The present invention therefore advantageously provides effective media access control while maintaining the chip architecture. This text only shows and explains the preferred embodiments of the present invention and a few examples of its changes. It should be understood that the invention and the environment can be modified and changed within the scope of the concept of the invention described herein.