Method and apparatus for automatically reducing cross-talk between wires coupled to a common network device

Method and device for automatically reducing crosstalk between lines coupled to a common network device

The present invention generally relates to the scope of network communication, and more specifically, relates to the reduction of crosstalk between individual network wires coupled to opposite ports of a multi-port network device.

In a typical network environment, switches can be used in a smart and efficient manner to facilitate communication between various sections of a single network, or between individual and separate networks. Specifically, the switch can learn the URLs of various network devices on the network segment or individual networks in time, and the individual networks are coupled to the opposite ports of the switch through opposite wires. Such wires include copper wires of twisted pairs or coaxial cables. In addition, these wires can be divided into categories 1-5 wiring according to EIA/TIA 568 specifications. By checking each received packet on the switch, the switch can determine whether the received packet should be sent out a special port, and based on the destination address information of the received packet, it can be sent on a special section or network.

FIG. 1 depicts a packet switching environment 1010 in which packet communication between three individual networks, namely networks 1014, 1016, and 1018, is assisted by a switch 1012. Of course, the switch 1012 includes any number of ports and is coupled to any number of networks. The net 1014 is coupled to the port 1020 of the switch 1012 by a wire 1022, the net 1016 is coupled to the port 1024 by a wire 1026, and the net 1018 is coupled to the port 1028 by a wire 1030. Each of these ports 1020, 1024, and 1028 is coupled to the switch core 1032 (also known as "switch organization") through packet transmission or routing between ports. The switch core 1032 shown is coupled to the memory resource by a dynamic random access memory (DRAM) 1034, and the DRAM provides the buffer resource to the switch core 1032. All valid packets received on the switch core 1032 will be transmitted to the DRAM 1034 on the bus 1035 and the switch core 1032 coupled to the DRAM 1034. The displayed address query device 1036 will detect the bus 1035 in order to learn the address information and form an address query table that maps the address of the network device to the switch 1012 port.

In the packet switching environment 1010 shown in FIG. 1, the wires 1026 and 1030 shown are actually separated from each other. Therefore, packet transmission 1038 between the networks 1014 and 1016 will occur without any crosstalk on the wire 1030. On the other hand, FIG. 2 depicts another packet switching environment 1040, in which wires 1026 and 1030 are bundled in a common cable 1342. In such a situation, so-called "near-end" crosstalk (or signal leakage) will occur between wires 1026 and 1030. When a packet is to be transmitted from one of these ports and the other port is listening on its opposite wire, crosstalk is most likely to occur close to ports 1024 and 1028. For example, consider packet transmission from network 1014 to network 1016, as shown at 1044. When the packet is transmitted from port 1024, the signal strength is the maximum. When the wire 1026 is close to the wire 1030 to transmit high power transmission signals, the generation of crosstalk is possible, as shown by 1046 on the wire 1030. The receiver of the port 1028 is in the state of maximum receiving sensitivity, so the crosstalk signal can be received at the port 1028 and routed to the switch core 1032. The address query device 1036 has previously learned the packet source address represented by the crosstalk signal, and when combined with the device on the network 1014, an incorrect modification of the address query table may occur. Specifically, the address query device 1036 will indicate the source address of the crosstalk signal belonging to the network 1018 device. This will then generate packet exchange errors.

When the wires 1026 and 1030 are not properly insulated, the verification issues discussed above in relation to Figure 2 can worsen. For example, if the wires 1026 and 1030 include category 1 unshielded twisted pair (UTP) wires, it is possible to increase the generation of crosstalk signals. In addition, in certain network environments, the frequency and power level of the transmitted signal will increase the vulnerability of the network to crosstalk.

According to the present invention, it provides a method for adjusting the sensitivity of the receiver. On receiving the detection URL, confirm the remote network device on the port of the multi-port network device, and determine whether the URL is combined with the URL of the further port of the multi-port network device. If so, the receiver sensitivity of the combined port will be automatically adjusted from the first level of sensitivity to the second level of sensitivity.

Other features of the present invention will become more apparent from the drawings and detailed description.

The present invention is described by examples, and is not limited to the drawings, in which the same numbers indicate similar elements.

Figures 1 and 2 are block diagrams showing examples of packet switching environments.

Fig. 3 shows the multi-configuration unit (MDU) scheme used in the present invention.

Fig. 4 is a diagram showing an access concentrator according to a specific embodiment of the present invention.

FIG. 5 is a block diagram showing the detailed structure of the wiring interface card according to a specific embodiment of the present invention.

Fig. 6 is a block diagram illustrating a switch according to a specific embodiment of the present invention.

FIG. 7 is a detailed structural block diagram of the receiver structure included in the physical layer device according to a specific embodiment of the present invention.

FIG. 8 is a flowchart of a method for creating and implementing an interrupt servo routine (ISR) according to a specific embodiment of the present invention, and the interrupt servo routine is a port for confirming that a crosstalk has been detected.

FIG. 9 is a flow chart describing a method for implementing a polling loop according to a specific embodiment of the present invention, and the detection loop adjusts the level of the receiver's sensitivity.

Detailed description of the schema

What is disclosed is a method and device for adjusting the sensitivity of a receiver for data transmission and reception in a communication network. In the following description, for the purpose of illustration, many specific details are provided based on the understanding of the present invention. However, the present invention can be realized without using these special details, which is obvious in the art.

FIG. 3 is a diagram showing the multiple configuration unit (MDU) 10 used in the present invention. The MDU 10 shown includes two buildings 12 and 14, and each of the buildings 12 and 14 includes a number of units 16, which can be apartments, hotel rooms, offices, or small rooms. The units 16 may be located in each of the multi-storey buildings 12 and 14. The MDU 10 may be a multi-story apartment complex, a garden-style apartment complex, a hotel, or any other structure that includes discontinuous residential equipment. The present invention can also be used in office complexes, factories, exhibition halls, or any other environment where two or more devices require a network.

Each unit 16 shown is a network connection that includes an example of an RJ-11 socket 18, which is coupled to the transmission medium by pure old telephone service (POTS) wiring 20, which includes a bundle of wire pairs. The wiring 20 includes an unshielded twisted pair (UTP) used to establish a telephone connection network throughout the building 12 or 14. In this case, the wiring 20 can be type 1 or type 2 wiring, such as EIA/TIA As defined by the 568 specification. The wiring 20 further includes many wire pairs, each pair is used for a special unit 16, and these wire pairs are bundled together to form a single cable with a sheath. In each unit 16, the general telephone unit 22 and computer 24 shown (via a network interface chip (NIC), modem, or other adapter) are coupled to the wiring via the opposite RJ-11 socket 18 20. The wiring 20 shown in each of the buildings 12 and 14 is coupled to the main distribution frame (MDF) panel 26 in the wiring room 28 of the building 14. The MDF panel 26 couples the wiring 20 to the public switched telephone network (PSTN) 30. The MDF panel 26 shown is also coupled to the access concentrator 32, which is constructed in accordance with the description of the present invention to provide a device that can access the wiring 20 via the Internet 34, such as the described computer 24 . The present invention described in the following text implements a network using POTS wiring 20 as a medium, which can be implemented in any network environment where exchange occurs through the description of the present invention, for example, a portable device that uses a higher transmission rate to transmit. Media networks, such as type 5 four-wire pairs capable of transmitting data at 100 Mbps, to support technologies such as Ethernet or Asynchronous Transfer Mode (ATM).

Figure 4 is a diagram depicting the access concentrator 32 in further details about this unit. The first computer 24 shown in the building 12 is coupled to the opposite RJ-11 socket via an external adapter 38, including a physical layer device (PHY) adapter 38, which can be connected to the POTS wiring 20 Produce faithful network communication. In a specific embodiment, the adapter 38 is made by Tut Systems, located in Pleasant Hill, California, USA. HomeRun adapter developed by Inc. The second computer 24 shown includes a Network Interface Card (NIC) 40, which also includes a physical layer device (PHY) to facilitate communication on the POTS wiring 20. Now explicitly transferred to the access concentrator 32, the chassis or rack 42 is suitable for a series of wiring interface cards 44, and these interface cards are coupled to a multiplexer (MUX) interface card 46. The chassis 42 includes 17 slots on the wiring interface card 44. In a basic structure, eight connection interface cards 44 are coupled to a single MUX interface card 46 through 10BaseT connections. The MUX interface card 46 can gather up to 64 1 Mbps local area networks (LANs), and these networks are coupled to the opposite ports of the line interface card 44 at 10 Mbps or 100 Mbps LAN. The collective local area network can be connected to a local router 48, a local server 50, or a wide area network (WAN) via a T1 WAN interface card 52.

FIG. 5 is a block diagram illustrating a further structure of the wiring interface card 44 according to a specific embodiment of the present invention. The wiring interface card 44 includes a switch 60, and the switch may be an Ethernet switch based on the Texas Instruments TNETX3100 switch. The switch 60 can provide eight 10 Mbps ports and two 10/100 Mbps ports. The switch 60 may further have a direct interface 66 between each port 62 and the physical layer device (PHY) 66. In a specific embodiment of the present invention, PHYs 66 may be manufactured by Tut Systems, HomeRun PHYs developed by Inc. are used to help the communication server POTS wiring. The PHYs 66 can also be traditional Ethernet PHYs, which are determined by the network transmission media supported by the various ports of the switch 60. Eight of the ports 62 shown are coupled to the opposing local area network 68 via a physical layer device 66. In a specific embodiment, the local area network 68 can be implemented with each of the units 16 described in FIG. 3 using the POTS wiring 20. In this case, the twisted pair from each of the units 16 is coupled to the opposite PHY. Two of the ports 64 and 65 shown are coupled to opposing 10BaseT PHYs 70. For convenience, the ports 62 and 64 are labeled as "downstream" ports, and the port 65 is labeled as "upstream" ports. The connection port 64 allows the connection interface card 44 to be connected to a further connection interface card 44, and the connection port 65 is regarded as an "output" port. As described in 72, the ports 64 and 65 can be selectively coupled to further wiring interface cards, MUX interface cards, or external 10BaseT ports. The wiring interface card 44 shown also includes a power supply 74 and a microprocessor 76.

In the MDU 10 as depicted in FIG. 3, the users on the local area network 68 (each of the ports 62 coupled to the switch 60) are typically individual users who have not joined other local networks 68 users. This creates a security issue. Users on the local area network can imagine that they can detect the back and forth network routing transmissions of users on another local area network 68, and the local area network 68 is coupled to the switch 60. In addition, it is conceivable that users on the first local area network 68 can create a network server, which can be accessed by users of other local networks without using the services of an Internet service provider (ISP). This is not intended in some situations. For the purpose of data security, it is intended that users who are coupled to any of these local networks 68 cannot see and communicate with users connected to other local networks 68. Moreover, the data transmission should be safe in both directions (that is, the upstream and downstream directions indicated by the arrow 78).

FIG. 6 is a block diagram illustrating an example of making the switch 60 shown in FIG. 5. The switch core 80 (also referred to as the switch structure) shown includes ports 62, 64, and 65 relative to the arrangement of the Media Access Control (MAC) port 82 and the External Address Match (EAM) interface 84. An external physical layer device (PHY) 66 is coupled to each port. Each of the PHYs 66 can be a 10BaseT PHY or a special PHY to facilitate communication on the POTS wiring 20. In a specific embodiment, such a special PHY includes the HomeRun PHY developed by Tut Systems, Inc., located in Pleasant Hill, California, USA. The switch core 80 also includes data path, transition logic, internal single-site comparison, and network statistics logic (all not shown in the figure).

The switch core 80 can support two-way routing, which can transmit on the destination port before the packet is completely received and stored and forwarded, and it needs to receive the entire packet before the packet is sent to the destination port. Pass-through routing will reduce the overall switching latency, and store-and-forward routing provides the ability to filter out frames containing erroneous data.

Three packet forwarding modes are also implemented by the switch core 80, namely, the internal single address comparison mode, the external address matching (EAM) mode, and the data frame receiving mode. The EAM interface 84 facilitates the multi-address support of each port. Compared with the single-address mode, it only supports the single-bit address of the port. Therefore, to support multiple users on the local area network 68 coupled to each port 62/64/65, the switching logic in the form of the address query device 86 provides an input in the form of a port indication (EAM) signal 90 For the EAM interface 84 of the switch core 80. The EAM signal 90 is a multi-bit signal (for example, the 16-bit signal EAM [0.15]), which is the switch core 80 indicating that the packet should be forwarded within the switch. The EAM signal 90 also indicates whether the switch core 80 implements single-address comparison. For example, EAM [15] can be set or reset to choose between single address comparison or external address matching mode. In the event of EAM reset (ie, low level), the external address matching mode will be realized, and EAM [0. . 14] indicates the port mask for packet forwarding. For example, if the packet is to be forwarded to ports 00, 07, and 14, the EAM signal 90 will be "100000010000001".

The memory resources in the form of dynamic random access memory (DRAM) 92 are coupled to the switch core 80 through the DRAM bus 94. The DRAM 92 implements a packet buffer and enables the switch core 80 to support single access operations and page burst access operations. Specifically, all valid packets are transmitted to the DRAM 92 by the DRAM bus 94. The address query device 86 shown is coupled to the DRAM bus 94 and actively detects the DRAM bus 94 to realize the external address matching function of the switch 60. The address query device 86 uses the switch core 80 to capture the packet address placed on the DRAM bus 94 to generate the EAM signal 90. In the specific embodiment of the present invention, the device 86 includes TNETX15AE address query device manufactured by Instruments. The address query device 86 implements many state machines 98 (for example, query, delete, add, discover, and stage state machines) to manage and maintain the bits in the combined external static random access memory (SRAM) 102 Address lookup table 100. The address lookup table 100 maps the original address (for example, MAC address) of the packet received on the switch 60 to the corresponding switch 60 port 62/64/65 determined by the address lookup device 86 to receive the packet. The process of forming the address look-up table 100 is called "learning" by the address of the switch 60. Once the address/port record has been created in the address look-up table 100, the switch 60 can determine which port has a "learned" destination address for the packet to be routed. In a specific embodiment, the address query device 86 may be coupled to an EEPROM (not shown in the figure) storing a series of initial codes, and the codes allow the address query device 86 to be automatically configured. In another embodiment, the initial data can be downloaded from the microprocessor 120 coupled to the address query device 86.

As mentioned above, all valid packets received on the switch 60 will be transmitted through the DRAM bus 94. The switch core 80 can write data to DRAM in a special format 92, and this special format can be confirmed by the address query device 86 to determine the correct destination and source address of the packet. The address query device 86 can detect the start of a new packet from the flag byte information included in the packet transmission. For example, the row address repeat signal (DRAS) and the column address repeat signal (DCAS) can be used to confirm the position of the forward indicator, the highest level of the flag byte, and whether the nibble contains the beginning of the data frame code . The data bit 35 may be non-deterministic (that is, set to 0) to indicate the beginning of the packet. In the first word transmitted on the DRAM bus 94, the data bytes 27-24 of a line indicate the active port number, and the field address repeat signal can also be used to confirm the destination on the DRAM bus 94 and The appearance of source address data. Therefore, in a specific embodiment, to determine the start of the data frame, the address query device 86 will test the data bit 35 of the forward indicator and decode the first half bit of the flag placed on the DRAM bus 94 Tuple. In this case, the data bit 35 should be zero, which indicates that the valid packet starts to be transmitted relative to the link buffer. Using field address repetition, the destination address and source address of the packet are extracted by the external processing of the address query device 86. The address query device 86 then executes the query cycle by accessing the address query table 100, selects the appropriate EAM code to be output to the EAM interface 84 of the switch core 80, and then outputs the EAM code. Further details about the detection procedure can be provided in the information book about the TNETX3100 Ethernet switch and the TNETX15AE address query device published by Texas Instruments.

The address query device 86 implements an interrupt to indicate the change of the address query table 100. Specifically, the interrupt is generated by the address query device 86 to indicate when a new address is added to the table 100 (that is, a new interrupt), when the address changes the port (that is, the interrupt is changed), the address changes When the port is safe, and when the address is deleted by stage processing. To instruct an external device such as the microprocessor 120 to interrupt, the address query device 86 will determine the interrupt signal 122 (for example, the EINT signal). The address query device 86 further includes an interrupt register 124, an interrupt mask register 126, and a new port register 128. The interrupt register 124 can always be accessed and read by an external device, and contains information about all current interrupts. The interrupt mask register 126 is a mask process that facilitates interruption. If the interruption occurs in accordance with the mask value stored here, it only allows the interrupt signal 122 to be determined. For example, if there is a one-to-one correspondence between the bits stored in the interrupt register 124 and the interrupt mask register 126, the interrupt signal 122 will be determined. In the event of a new or change interruption, the addressed new port confirmation is provided in the new port register 128. The contents of the registers 124, 126, and 128 can be accessed by an external device such as the microprocessor 120 via a data input/output (DIO) bus 130.

The microprocessor 120 shown is coupled to a combined memory, such as a random access memory (RAM) 132, which stores an interrupt service routine (ISR) 134, a detection loop 136, a set of global variables 138, and a Group area variable 140. The microprocessor 120 can access and execute the instruction sequence including the ISR 134 and the detection circuit 136. As mentioned above, the whole or at least part of the local memory (for example, cache memory) of the microprocessor 120 is stored. The global variable 138 and the regional variable 140 also show that the register can be stored in the microprocessor unit 120. However, the logic and functions of the present invention can exist in software, hardware, or any combination. For the proposed specifications, the term "machine-readable medium" includes any memory resource (e.g., RAM 132), internal and external of the machine, which can be stored by the machine (e.g., microprocessor 120) The sequence of instructions executed and the substance that causes the machine to execute any of these functions specified in the current specifications. Therefore, the term "machine-readable medium" includes, but is not limited to, full crystal memory, magnetic memory, optical memory, chemical memory, or carrier signal.

The shown microprocessor unit 120 also includes a general purpose serial interface (GPSI) 142, which can send data to one of the PHYs 66 via the microprocessor 120, and the data can be sent from the PHYs 66 to the connection 144 On the microprocessor 120. In a specific embodiment of the present invention, each of the PHYs 66 operates in a slave mode, and the microprocessor unit 120 can therefore control the operation of the PHYs 66 via the GPSI 142. Each of these PHYs 66 can support a variety of control and status registers. Specifically, each PHY 66 includes a noise critical register 146, which is implemented by the noise tracker 148 in the receiver of the PHY 66.

FIG. 7 is a block diagram depicting further details of the structure of an example of the receiver 150 in each of the PHYs 66. The receiver 150 shown includes a socket 160 that receives a jack, and the jack couples the receiver 150 to the POTS distribution network 152. The multi-cycle waveform containing the received signal is transmitted from the socket 160 to the Butterworth filter 162, which limits the bandwidth of the received signal to 5.5 and 9.5 The spectrum mask between MHz. The filtered signal is then transmitted from the Butterworth filter 162 to the differential amplifier 164, and then to the envelope detector 166, which outputs the envelope signal obtained by amplifying and filtering the received signal. This envelope signal is then provided to the pulse detector logic 170 via a unipolar operational amplifier (opamp) 168, which transmits and receives the signal from the critical logic 172. Specifically, the threshold logic 172 transmits the analog signal to the pulse detector logic 170, which indicates the noise threshold level of the comparator included in the pulse detector logic 170. For this purpose, the threshold logic 172 includes a noise tracker 148, which implements a noise threshold level state machine, and includes a noise threshold register 146. The noise threshold register 146 stores an 8-bit sequence, which can be increased or decreased particularly by the noise threshold level state machine. The 8-bit sequence is sent to the digital-to-analog converter, which converts the 8-bit sequence into an analog signal, and the analog signal indicates the noise threshold level of the pulse detector logic 170 comparator. The output of the pulse detector logic 170 is then sent to the decoder in the PHY 66. Please refer to FIG. 6, the microprocessor 120 shown can increase the 8-bit sequence stored in the noise threshold register 146 via the connection 144.

The example operation of the switch 60 shown in FIG. 6 will now be described with reference to the flowcharts shown in FIGS. 8 and 9. Specifically, FIG. 8 is a flowchart describing a method 200 according to a specific embodiment of the present invention for authoring and implementing ISR 134. The method 200 starts at step 202, where the address query device 86 interrupts the microprocessor 120 by determining the interrupt signal 122. In a specific embodiment, the interrupt mask register 126 is configured so that only new or changed interrupts will cause the interrupt signal 122 to be determined. It is due to the fact that the change interrupt will be generated in the situation described above with reference to Figure 2, where the crosstalk signal is received on port 1028, and the packet source address described in this crosstalk signal has been combined with other ports, such as Port 1020. In response to the determination of the interrupt signal in step 202, the microprocessor 120 will start the ISR 134 in step 204. The ISR 134 will inquire the address query device 86 of the relevant MAC address, and the relevant MAC address will generate an interrupt and the cause of the interrupt (that is, whether the new address has been detected or the address change has been detected). This information is provided in the interrupt register 124 accessed by the microprocessor 120. In step 206, the ISR 134 accesses the new port register 128 of the address query device 86. ISR 134 is therefore able to confirm the new port 62/64/65, and the media access control (MAC) address it has will be confirmed (for example, port 1028). In step 207, the ISR 134 stores the related MAC address and the determined interruption reason information.

At decision block 208, the ISR 134 determines whether the generated interrupt result will be that the known MAC address will appear on the new port (and therefore on the new network) or whether the generated interrupt result will be unknown The MAC address will appear on the port. In the case that the generated interrupt result is that the known MAC address appears on the new port (that is, the change interrupt is generated), the method 200 will process step 210, in which the ISR 134 will be deleted from the address look-up table 100 The relevant MAC address. Specifically, when the MAC address changes the port, the communication path will become inactive, and the step of deleting the MAC address will obtain the MAC address deleted by the stage processing. Before the upper layer communication protocol can end the related connection, the communication path can be rebuilt. At step 212, the ISR 134 will determine that the seen MAC address is coupled to the new port of the predetermined network type. Specifically, the ISR 134 can confirm a new port using the contents of the new port register 128. The ISR 134 can further access the port/network type mapping based on that the ISR 34 can confirm the network type combined with the new port. In a specific embodiment, the ISR 134 can determine whether the new port is coupled to the HomeRun local area network (LAN), which is based on the above mentioned by Tut Systems, Inc. and other companies developed communication protocols. In step 214, the ISR 134 updates the global variable 138 of the PHY 66 combined with the new port to indicate that the occurrence of the crosstalk event is related to the new port. For example, the relative global variable can be set to logic 1 to indicate a crosstalk event. The method 200 will then end at step 216. Therefore, it is due to the method 200 being interrupt driven.

Please refer to FIG. 9, which is a flowchart of a method 240 for implementing the detection loop 136 according to a specific embodiment of the present invention. The method 240 works in a continuous loop without being driven by interruption. The method 240 starts at step 242, where a variable equal to the maximum number of ports (based on PHYs) in the switch 60 is reset to zero (0). In step 244, the global variable under consideration is copied to the regional variable, and the related global variable is cleared in step 246. In step 248, it is determined whether the regional variable under consideration is set to logic 1, thereby instructing the combined port to receive the crosstalk signal and the network or wiring that is coupled to the port experiencing the crosstalk situation. If not, the variable value will be increased by 1 in step 250, so the next continuous global variable and regional variable combined with further ports and PHYs will be processed and considered during subsequent repeats of steps 244-248. Alternatively, the relevant area variable should be set to logic 1, and the detection loop 136 will query the combined PHY 66 in step 252 to determine the noise threshold level indicated by the content of the noise threshold register 146 of the PHY 66. In step 254, the noise threshold level of PHY 66 is determined by a predetermined increment (for example, 10 mV), thereby reducing the combined PHY 66 receiver sensitivity. Specifically, the microprocessor 120 outputs a serial signal on the connection 144, and the signal is received by the noise tracker 148, resulting in an 8-bit sequence stored in the noise threshold register 146, which It is incremented by a predetermined amount. Therefore, the threshold level of noise sent to the comparator of the pulse detection logic 70 will increase. By increasing the noise threshold level, the sensitivity of the PHY 66 will be reduced. The detection loop 136 will seek to provide a PHY 66 that is less affected by the detected crosstalk signal, which typically has a lower voltage amplitude than the effective signal . In the decision block 256, it is determined whether the corrected noise threshold level of the PHY 66 is greater than a predetermined maximum noise threshold level. If so, the relevant PHY 66 will not be reconfigured to achieve the corrected noise threshold level, and the method will directly process the decision block 262. Alternatively, the PHY 66 under consideration will be reconfigured to use the corrected noise threshold level in step 260. Then, in the decision block 262, it is determined whether the variable indicating any of the PHYs in the switch 60 has reached a predetermined maximum value (that is, the total number of PHYs included in the switch 60). If so, the variable value will then be reset at step 242, and the method 240 will perform another iteration. If not, the variable value will be incremented by 1, and the next iteration will start in step 244.

In a nutshell, when a URL appears on a port of a multi-port network device, the present invention proposes to detect a crosstalk situation, which is to receive packets with the relevant URL under abnormal operation conditions. The present invention searches for the address of the crosstalk situation by dynamically reducing the receiver sensitivity of the network or the connection port where the crosstalk situation occurs.

Therefore, methods and devices for dynamically adjusting receiver sensitivity to reduce crosstalk have been described. Although the present invention has described specific specific embodiments, it is obvious that various modifications and changes can be made in these specific embodiments without departing from the scope and spirit of the present invention. Therefore, the specifications and drawings are for illustration rather than limitation.