Line receiver circuit with line termination impedance

The invention relates to a transmission line receiver circuit, which includes a buffer section for connecting the input end of the transmission line, and an output stage that provides a data signal according to the signal received by the transmission line, and further includes a terminal impedance device connected to The input end of the buffer section is used to terminate the characteristic impedance of the transmission line.

To transmit information signals on a transmission line at a high rate, a terminal impedance in accordance with the characteristic impedance of the transmission line must be provided at the receiving end of the transmission line. The more important the transmission line is, the higher the bandwidth of the transmission signal. In order to keep the design of the transmission line receiver circuit as simple as possible, the termination impedance can be an integrated part of the circuit, for example, the remaining sections in the same semiconductor chip circuit can be integrated.

It can be known from the transmission line receiver circuit of WO 95/24089 that it is necessary to provide an electronic impedance conforming to the receiving end of the transmission line. The circuit can work with various transmission lines with different characteristic impedances. The terminal impedance device known from this document includes: a controllable impedance element having an impedance control input terminal for receiving an impedance control signal. Furthermore, an impedance control signal generating device is provided, which includes a pair of impedance elements having a pair of impedance control input terminals and electronic characteristics corresponding to the electronic characteristics of the terminal impedance element in a set relationship. The control signal to the impedance element makes the paired impedance approximate the target device. The target value can be set in advance by connecting an external reference resistor. Further, a control signal is provided to the terminal impedance element to control the impedance of the paired impedance element to form the electronic characteristics corresponding to the terminal impedance element and the paired impedance element, and the terminal impedance will correspond to the paired impedance.

In this document, the controllable impedance element is a metal oxide semiconductor field effect crystal (MOSFET), and its gate functions as an impedance control input. With this type of semiconductor impedance element, the following disadvantages occur when the circuit has to overcome a wide range of different operating voltages.

In order for the circuit to operate properly in the lower supply voltage range, the impedance element must have the necessary minimum adjustable impedance to determine a certain minimum channel width. If the supply voltage of this circuit increases, the control circuit will generate an impedance control signal, so that the impedance element instinctively maintains the impedance. The large width of the impedance element will then result in the impedance control voltage not being able to increase to the same extension as the supply voltage, while still being low. This immediately means that the paired impedance element and the terminating impedance element no longer behave like an impedance function, but rather like a power supply function, and will not terminate the transmission line in an optimal way. Furthermore, in this power mode, the paired impedance elements and terminal impedance elements will be more sensitive to changes or noise in the control signal. This change or noise is a serious problem, especially for the larger circuits in the digital signal environment. .

Therefore, the subject matter of the present invention is to provide an improved transmission line receiver circuit that can operate in a large operating voltage range, has a terminal impedance device and a paired impedance device, and functions basically like the impedance across the entire operating voltage range.

According to the invention, the subject matter is as defined in item 1 of the scope of patent application.

A transmission line receiver circuit according to the present invention includes a plurality of paired impedance elements connected together to provide a paired impedance. Each pair of impedance elements receives an individual impedance control signal from the impedance control signal generating device. At the same time, the terminal impedance device includes a plurality of terminal impedance elements, and each element has a different impedance control input terminal. The impedance control signal generating device includes a device for providing a control signal of a terminal impedance element corresponding to a control signal of a pair of impedance elements in a set relationship.

By providing individual control signals for each impedance element in the paired impedance device, and obtaining control signals for the terminal impedance element from these paired impedance control signals, the transmission line receiver circuit according to the present invention can provide a power supply voltage exceeding a wide range. Terminal impedance.

The term "paired impedance element" means that the electronic characteristics of this element are proportional to the electronic characteristics of the corresponding connected terminal impedance element. As an example, integrated semiconductor technology allows different components to be created in the same manufacturing process, such as two transistors, which have essentially the same electronic characteristics, as is well known in the art.

Specific embodiments useful in the present invention are stated in the scope of additional patent applications.

Preferably, for a high supply voltage, at least one impedance control signal will cause the connected controllable impedance element to be in a high impedance state, such as being switched off, and whether other impedance elements are activated depends on the set target impedance value. As the supply voltage decreases, an impedance control signal will be generated, so that the lower the supply voltage, the larger the number of impedance elements that leave the high impedance state and turn into activation.

Preferably, the impedance element is a semiconductor device, and preferably a metal oxide semiconductor field effect crystal (MOSFET) or a bipolar transistor. A control signal device is used to generate each pair of impedance elements, so that the impedance of the pair of impedances approximates the target value. It is better to avoid as many impedance elements as possible in operation to meet the target impedance value. The control of each impedance element can be implemented by providing individual control loops of each pair of impedance elements.

It is better that there is one more control loop, as long as the control loop has been started before and reaches a state where the difference between the entire paired impedance and the target impedance value becomes too large, for example, it is larger than a preset threshold , Suddenly or gradually do not activate its connected impedance element. The impedance elements that are still starting are driven to maintain a low impedance or saturated startup state, where the impedance difference is quite close to the absolute impedance. In this respect, it is satisfactory that a linear function of the impedance device has been achieved.

Preferably, the paired impedance elements are connected in parallel to form a paired impedance device.

The individual control signal device used to generate each pair of impedance elements may include multiple operational amplifiers, each connected to detect the difference between the pair impedance of the pair of impedance devices relative to the target value, and control the paired impedance of the connection One component. Operational amplifiers have different compensation voltages. As the supply voltage increases, individual impedance components can be turned off in series.

According to another specific embodiment, the device for generating individual control signals for each pair of impedance elements includes a multi-output stage operational amplifier with different offsets, which can be added or replaced to provide different offsets for the output stages of the operational amplifier. Whether the provided compensation generating circuit generates compensation between different impedance control signals depends on the supply voltage and the target impedance value.

According to the impedance control signal generating device of the present invention, it is preferable to include a fixed power source to transmit a fixed current to the paired impedance device, so that the voltage potential drop through the paired impedance device represents the actual impedance value of the paired impedance device. Whether this fixed power supply is controlled to provide a fixed current depends on the target impedance of the paired impedance device. Preferably, a controllable fixed power source is additionally provided to deliver a fixed current to the reference resistor. The external fixed power supply is controlled so that the voltage potential drop through the reference resistor is set to a reference value, and the supporting current of the external power supply is transmitted to the fixed power supply of the paired impedance device for mirroring. The voltage potential drop through the reference resistor and the difference between the voltage potential drop through the paired impedance device can be used as an error signal, indicating the paired impedance relative to the reference impedance R_refThe gap. It is very convenient to detect the paired impedance circuit, and it can provide a large error signal between the given paired impedance and the target impedance value.

According to a preferred embodiment, the transmission line receiver circuit includes a plurality of input buffer sections as interfaces with a plurality of transmission lines, each having its terminal impedance device. Each impedance control device provides the same or corresponding control signal to each terminal impedance device.

In the following, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 1: Schematic diagram of the first specific embodiment of the transmission line receiver circuit according to the present invention; Figures 2a to 2e: Schematic diagrams of the second specific embodiment and the modification of the transmission line receiver circuit according to the present invention; Figure 3: Terminal impedance Modification of the device; Figure 4: Another modification of the terminal impedance device; and Figure 5: A characteristic diagram for explaining the operation of the specific embodiment of Figures 1 and 2.

FIG. 1 is a schematic diagram of a first embodiment of a transmission line receiver circuit according to the present invention. In the figure, TR denotes a transmission line connected to an input terminal IN of an input buffer amplifier 1. OUT represents an output terminal of the buffer 1 for outputting a data signal according to a signal received by a transmission line terminal impedance (TR).

Reference numeral 2 denotes a connected transmission line terminal impedance device, which is used to terminate the transmission line terminal impedance (TR) through the input terminal of the buffer amplifier 1. In this specific embodiment, the transmission line termination impedance device 2 includes three metal oxide semiconductor field effect crystal (MOSFET) transistors TZ1 to TZ3, and the drain source paths thereof are connected in parallel. Each transistor TZ1 to TZ3 receives an impedance control signal generated by the impedance and control signal generating device 3 in the gate. The impedance control signal generating device 3 of the present invention includes operational amplifiers A1 to A3, and provides individual impedance control signals at each output stage. The output compensation voltages of the three amplifiers A1 to A3 are different from each other. The reason will be explained further below. The internal structure of each operational amplifier A1 to A3 may be a conventional type. How to compensate the input offset voltage of the op amp is a well-known technique. The same mechanism can be applied to achieve different input offset voltages. One of the many possibilities is to provide a transistor to make the differential inputs of the operational amplifiers asymmetric, for example, the physical sizes are different from each other.

Reference numeral 4 denotes a controllable paired impedance device. In this specific embodiment, the controllable paired impedance device includes three metal oxide semiconductor field effect crystal (MOSFET) transistors NZ1 to NZ3, and their drain source paths are connected in parallel. Each transistor NZ1 to NZ3 receives an individual control signal in the gate to control the impedance of the pair of impedance devices 4. In the specific embodiment shown in FIG. 1, the transistors TZ1 to TZ3 of the terminal impedance device 2 respectively provide the paired transistors NZ1, NZ2 and NZ3 connected to each other. Each pair of transistors receives an impedance control signal in the gate from one of the connected amplifiers A1 to A3. The term "paired transistor" means that for two pairs of transistors, the dependency of the drain source voltage on the drain source path impedance at the gate control voltage is essentially the same. In the well-known technique, a pair of transistors can be produced by the same procedures and essentially the same geometric principles. In general, the electronic characteristics of a pair of transistors do not need to be consistent, but it is sufficient that the corresponding electronic characteristics of the two transistors are known and predetermined. For example, the channel size of one of the paired transistors is predetermined to be a multiple of the corresponding channel size of the other of the paired transistors. And the word "pair" in this and similar situations should apply.

R_refDenotes a reference resistor used to set a hypothetical impedance value of the transmission line termination impedance device 2. Provide reference resistance R_refAs internal components, or more ideally for external connection, transmission lines with different characteristic impedances can be adjusted by R_refThe device is simply terminated.

CI1 and CI2 represent controllable power supplies that provide fixed currents I1 and I2, respectively, depending on the current control signals provided by the output stage of the operational amplifier AR. In the specific embodiment of FIG. 1, the two fixed power sources CI1 and CI2 receive the same control signal from the amplifier AR. Power sources CI1 and CI2 form a mirror of current. That is, in an ideal situation, the current amount I1 and the current amount I2 have a fixed setting relationship. For example, the current I1 is equal to the current I2. Among these types of current mirror circuits, this technique is most famous. For example, in a specific implementation of CI1, a metal oxide semiconductor field effect crystal (MOSFET) having a gate connection drain and an amplifier AR output stage may be used. CI2 can be a P-type metal-oxide-semiconductor field-effect crystal (MOSFET) with a gate-connected amplifier AR output stage.

Connect the fixed power source CI1 to make the fixed current I1 pass through the reference resistor R_ref. By connecting the fixed power source CI2, the fixed current I2 can pass through the paired impedance device 4. Connect the inverting inputs of operational amplifiers A1 to A3 and AR so that their reception passes R_refThe voltage potential drops. The non-inverting input terminals of the three amplifiers A1 to A3 are connected to receive the voltage potential drop generated by the current I2 through the paired impedance device 4. V_refRefers to the reference voltage applied to the non-inverting input of the operational amplifier AR. Such a reference voltage can be provided by a simple resistance voltage divider circuit (not shown), or preferably a fixed reference voltage is output by a fixed power source, such as one fifth of the minimum allowable power supply voltage To a third. Better but not necessary, V_refApproximately equal to the signal voltage through the transmission line termination impedance device 2. Vcc represents a positive power supply potential, and GND represents a ground potential.

Reference resistor R during operation_refThe fixed power supply CI1 and the operational amplifier AR constitute a fixed current I1, which depends on the reference resistor R_refControl loop. Because the power sources CI1 and CI2 form a current mirror, the current I2 also depends on the reference resistor R._ref. In particular, the operational amplifier AR adjusts the fixed current I1, which is provided by the power source CI1, through the reference resistor R_ref, So that R through the negative input terminal of the operational amplifier AR_refThe voltage potential drop is equal to the reference voltage V at the non-inverting input of the operational amplifier AR_ref。

Due to the setting relationship between I2 and I1, the voltage potential drop through the paired impedance device 4 and through the reference resistor R_refThe difference between the voltage potential drop is marked with ERR, which indicates the difference between the paired impedance and the target impedance value. This target impedance value is equal to R_refThe ratio between them is the setting relationship between I1 and I2.

The impedance control device 3 is used to provide individual control signals to each pair of impedance elements NZ1 to NZ3, so that the difference between the impedance of the paired impedance device and the target impedance value is close to zero. And the impedance of the terminal impedance device 2 will adopt the desired value, because the terminal impedance elements TZ1 to TZ3 respectively receive the same impedance control signals as the pair of impedance elements NZ1 to NZ3 to which they are connected.

The design of the impedance control device 3, wherein a compensation exists between the impedance control signals VZ1 to VZ3. The effect of this compensation is to ensure as many pairs of impedance elements NZ1 to NZ3 as possible. Therefore, when a small number of terminal impedance elements TZ1 to TZ3 are activated, and as many as possible, all elements are in the lowest possible impedance state, such as in The saturation state, because the linearity of the impedance element in this state, such as a metal oxide semiconductor field effect crystal (MOSFET) or a bipolar transistor, is the most ideal.

To explain the operation of the specific embodiment shown in FIG. 1, it is assumed that the supply voltage Vcc is increased. For simplicity, suppose I1 is equal to I2. For the supply voltage at the lower end of the supply voltage operating range of the circuit shown in Figure 1, the impedance of the paired impedance device 4 will be higher than R_ref, Even if the three control voltages VZ1 to VZ3 use the maximum possible value (Vcc or lower, depending on the special design of the amplifier A1 to A3 output stage). Therefore, the voltage potential drop through the paired impedance device 4 will be greater than through R_refThe voltage potential drops, so that all impedance elements NZ1 to NZ3 are in the lowest possible impedance state.

As the supply voltage Vcc increases, the potential at the gates of the transistors NZ1 to NZ3 will rise. Subsequently, the impedance of the paired impedance device 4 will gradually decrease. Then, as Vcc increases, the error signal, that is, the voltage difference between the non-inverting input terminal and the inverting input terminal of the amplifiers A1 to A3 will decrease, and as Vcc decreases again, the sign will be reversed.

Since the three input amplifiers A1 to A3 are provided with different input offset voltages, the amplifier A3 with the largest negative input offset voltage will first reduce its voltage VZ3 at the output stage. Therefore, the impedance element NZ3 will be gradually or suddenly turned off, and the terminal impedance element TZ3 will also be turned off. The same, while the other amplifiers A1 and A2 will keep their connected impedance components all activated, that is, in a lower possible impedance state.

As the supply voltage Vcc increases again, the second amplifier A2 with an input offset voltage has a more positive input offset voltage than A3, but is lower than the input offset of A1. Finally, its connected impedance elements NZ2 and TZ2 will be closed. The impedance component connected to amplifier A1 will still be in the linear region.

It can be known from this that the impedance control signal generating device 3 can be modified, and the impedance of the pair of impedance devices 4 is controlled by controlling the number of impedance elements in the linear operation area so as to correspond to the impedance of the terminal impedance device 2. In this way, the linear function of the terminal impedance device can be achieved over a wide range of operating voltages and a wide range of terminal impedance values.

Fig. 2a shows a second embodiment of a linear receiver circuit according to the invention. Components that are similar or identical to corresponding elements in the specific embodiment of FIG. 1 are denoted by the same reference numerals. Regarding the connections and functions of these components, the previous specific embodiments can be used as a reference to avoid repetition.

In the specific embodiment of FIG. 2a, the terminal impedance device 2 and the paired impedance device 4 respectively include two impedance elements TZ1, TZ2 and NZ1, NZ2. Generally speaking, the number of impedance elements is basically unimportant and can be arbitrarily selected depending on the desired operating range and the desired terminal accuracy. The larger the number of impedance components, the better the termination accuracy.

In this embodiment, the impedance control device 3 includes an inverting input terminal connected to receive the reference resistor R._refThe voltage potential drops, and the non-inverting input terminal is connected to receive the operational amplifier A4 having the voltage potential drop through the paired impedance device 4. The operational amplifier A4 further includes a first output stage Q1 and a second output stage Q2. The first output stage Q1 is connected to provide an impedance control signal VZ1 to the paired impedance element NZ1 and the connected terminal impedance element TZ1. The output stage connected to the amplifier A4 provides an impedance control signal VZ2 to the paired impedance element NZ2 and the connected terminal impedance element TZ2. Similar to the first specific embodiment, the terminal impedance device 2 and the paired impedance device 4 include impedance elements, which are specifically implemented by metal oxide semiconductor field effect crystal (MOSFET) transistors, and the gates thereof receive individual impedance control signals.

In this specific embodiment, the operational amplifier A4 adjusts the paired impedance elements NZ1 and NZ2 respectively, so that the impedances of all the paired impedance devices 4 approximate the target value. Similar to the previous specific embodiment, this target value is the reference impedance R_refMultiply by I1 / I2. Amplifier A4 contains individual output stages for Q1 and Q2. The design of the output stage, where there is a compensation between the output stage Q1 and the output stage Q2, depends on the difference between the paired impedance and the target impedance value. To further explain the specific embodiment, it is assumed in the following that the power supply voltage Vcc is increased. For simplicity, suppose I2 is equal to I1, so that the target impedance value of the paired impedance device 4 is the reference impedance R_ref. At the lower end of the supply voltage operating range, all impedances of the paired impedance device 4 are slightly higher than the target impedance R_refEven if the two output stages Q1 and Q2 of the amplifier A4 provide the highest possible output potential, which is equal to or less than Vcc, it depends on the special design of each output stage. Therefore, in these cases, the two output stages Q1 and Q2 will cause the paired impedance elements and terminal impedance elements NZ1, TZ1 and NZ2, TZ2 to be driven to the lowest possible impedance state of the given supply voltage Vcc.

As the supply voltage Vcc increases, the output voltages of the A4 output stages Q1 and Q2 will increase, causing all paired impedances to decrease. Therefore, the paired impedance and the target impedance R_refThe gap will eventually be close to zero, and the sign will be reversed, that is, as Vcc increases, all impedance elements of the paired impedance device 4 will be driven to start all, and all paired impedances will eventually fall below the target impedance. At the inverting input of amplifier A4, the potential will be below the potential of the non-inverting input of A4. Due to the compensation function of output stages Q1 and Q2, the condition of the first output stage, such as Q1, will be lower than its output potential, while other output stages, such as Q2, are still at high potential. As the supply voltage Vcc increases again, the gap between all paired impedances and their target impedance values will grow even more, and finally the second output stage Q2 will begin to fall below its output potential. Obviously, there will be an output stage that will close its connected impedance element after the others, so that the impedance element that is still activated can stay in the linear operation area.

FIG. 2b is a specific embodiment of the operational amplifier A4 of FIG. 2a. According to this specific embodiment, the operational amplifier A4 includes a current difference terminal T6, T7 driven by an inverting input terminal INN and a non-inverting input terminal INP. And it includes multiple output stages, for example, the two output stages are T1, T3 and T2, T4. It further includes a current mirror circuit that mirrors the current passing through one branch of the current differential terminal to the higher branch of the output stage, and a current mirror circuit that passes the other branch of the current differential terminal. The current mirror is on the lower branch of the output stage. The geometric principles of the transistors provided to the output stages are different, so that the output compensation function of the two output stages can be achieved.

In particular, the terminals INN and INP represent the inverting and non-inverting input terminals of the amplifier A4, respectively. Transistors T1, T2, T5, T6, and T7 are P-type metal-oxide-semiconductor field-effect crystals (MOSFETs), while the remaining transistors T3, T4, T8, T9, and T10 are N-type metal-oxide-semiconductor field-effect crystals (MOSFETs) . CI3 stands for fixed power. The connected transistors T6 and T7 are used to form different input terminals. The sources of transistors T6 and T7 are connected to a fixed power source CI3. The gate of transistor T6 constitutes the inverting input terminal INN of amplifier A4, and the gate of transistor T7 constitutes the non-inverting input terminal INP. The drain of transistor T6 is connected to the first current mirror circuit, which is composed of transistors T8 and T9. In particular, the drain of transistor T6 is connected to the drain of transistor T9, and then the gates of transistors T9 and T8 are connected. Transistors T5 and T1 form a second current mirror circuit. Furthermore, the transistor T5 and the transistor T2 constitute a third current mirror circuit. The second and third current mirror circuits mirror the current passing through transistor T8 to the output stage of amplifier A4, that is, the first output stage composed of transistors T1 and T3, and mirror to transistor T2. And T4 constitutes the second output stage. The drain of transistor T8 is connected to the drain and gate of transistor T5, and then to the gates of transistors T1 and T2. The transistor T10 and T3 are connected to form a fourth current mirror circuit. In addition, the transistor T10 and the transistor T4 constitute a fifth current mirror circuit, and the current passing through the transistor T7 is mirrored at two output stages, which are T1, T3 and T2, T4. In particular, the drain of transistor T7 is connected to the drain of transistor T10 and the gates of transistor T10, T3 and T4. The drain of the transistor T1 is connected to the drain of the transistor T3 to form the output stage Q1 of the amplifier A4. The drain of the transistor T2 is connected to the drain of the transistor T4 to form the output stage Q2 of the amplifier A4. The sources of the transistors T1, T2 and T5 are connected to a positive power supply potential Vcc. The sources of the transistors T3, T4, T8, T9 and T10 are connected to the ground point GND. The terminal of the fixed power source CI3 is not connected to the transistors T6 and T7, but is connected to Vcc.

In order for the output stages Q1 and Q2 to display the compensation function, the physical sizes of T1 and T2 are different from each other, or the physical sizes of T3 and T4 are different from each other, or both. Preferably, the difference in physical size is the bandwidth of each component. During operation, the potential difference between the inverting input terminal INN and the non-inverting input terminal INP of the amplifier A4 will cause the difference between the drain currents of the transistors T6 and T7. The drain current of the transistor T6 is mirrored by the transistors T8 and T9 to present a drain current like the transistor T5. The drain current of transistor T7 is the drain current of transistor T10. The drain voltages of the transistors T5 and T10 are input signals to the output stages T1, T3 and T2, T4 of the operational amplifier A4.

The following assumes that the compensation function between output stages Q1 and Q2 is achieved by providing the bandwidth of transistor T1 to be larger than the bandwidth of transistor T2 and the channel of providing transistor T3 to be smaller than the bandwidth of transistor T4. Then, for a given current through T5, transistors T1 and T2 can provide different drain currents, that is, the mirror current through T1 is greater than the mirror current through T2. Similarly, for a given current through T7 and T10, the mirror current through T3 is greater than the mirror current through T4. The output potential at each output stage Q1 and Q2 now depends on the higher transistor of each output stage, namely T1 and T2, respectively, whether it is driven to provide a lower transistor than each output stage, that is, respectively T3 and T4, larger currents, which will lead to the high output potential of Q1 and Q2 respectively, or the higher branches of each transistor will drive to provide a lower current than the lower branches of each transistor, which will Resulting in low output potentials respectively at Q1 and Q2. Because the two higher branch transistors T1 and T2 receive the same gate signal from T5, and because the two lower branch transistors T3 and T4 receive the same gate signal from T10, because of the high branch and Different band widths of low-branch transistors require smaller potential differences to pass through INP and INN of output stage Q1 and become higher potentials than output stage Q2, which can achieve output compensation for different output stages Q1 and Q2.

The amplifier A4 shown in FIG. 2b includes two separate output stages, which can provide more than two output stages to correspond to the number of impedance elements in the paired impedance device 4 and the terminal impedance device 2.

In the specific embodiment of FIG. 2a, reference numeral OC denotes a compensation circuit. This compensation circuit is purely for operational use, and can additionally provide or replace the device in the amplifier A4 to trigger compensation of different amplifier A4 output stages. Fig. 2c shows a schematic representation and a specific embodiment of the compensation circuit OC of Fig. 2a. It can be known from the schematic representation of the circuit OC that the circuit includes a common input terminal, which is labeled "+", and a reference input terminal, which is labeled "-". The circuit is designed to compare the input voltage at the non-inverting input terminal with the reference voltage at the other input terminal. If the input voltage at "+" is higher than the reference voltage at "-", the output stage of the circuit OC is in a high impedance state. Otherwise, the output stage is pulled down to the ground point GND. In Figure 2c, CI4 represents a fixed power supply. T11 to T14 represent N-type metal oxide semiconductor field effect crystals (MOSFETs). T15 and T16 represent P-type metal oxide semiconductor field effect crystals (MOSFETs). The sources of the transistors T11 and T12 are connected, and the fixed power source CI4 is connected. The drain of transistor T12 is connected to the drain and gate of transistor T16, and is connected to the gate of transistor T15. The drain connections of transistors T14 and T15 are connected to the gates of transistors T14 and T13. The drain of transistor T13 is connected to output stage Q2 of amplifier A4, and the gate of transistor T11 is connected to output stage Q1 of amplifier A4. The gate of transistor T12 receives a reference voltage Vref2. The drain of transistor T11 and the sources of transistors T15 and T16 are connected to Vcc. The sources of the transistors T13 and T14, and the terminal of the fixed power source CI4 are not connected to the transistor T11, and T12 is connected to the ground point GND.

The compensation circuit OC of FIG. 2c is suitable for forcibly performing different compensations of the output stage of the amplifier A4. As long as the potential of the output stage Q1 is lower than the reference potential Vref2, the main part of the current from CI4 will flow through the transistor T12 and be mirrored, and the current will mirror T15 and T16 to the transistor T14. This will start transistor T13, forcing output stage Q2 to remain low.

Only after the potential of the output stage Q1 of the amplifier A4 exceeds the reference potential Vref2, the transistor T13 is turned off, so that the potential of the output stage Q2 rises. Because in fact, if Q1 is above Vref2, then all current from CI4 will be replaced by transistor T11, and no subsequent current will flow through transistor T15. Finally, transistors T14 and T13 will be effectively turned off.

Generally, the selective compensation circuit OC in FIG. 2a can be used to support different compensations of the output stages of the amplifier A4, or as a single device to achieve different compensations of the output stages of the amplifier A4. That is, the compensation circuit OC can be applied to each of the impedance elements NZ1, NZ2,. . .The impedance control input of the connected terminal impedance element provides a compensation function, even if the output stage of the amplifier A4 itself cannot display such a compensation function. For example, the situation is: if the transistors T1 and T2 in Figure 2b are basically different from each other, The transistors T3 and T4 of FIG. 2b are basically different from each other.

The reference voltage Vref2 defines that the voltage is forced to be lower than VZ2 to maintain the potential VZ1 to be high. Obviously, if more than two impedance elements are individually controlled, this can be achieved by connecting several compensation circuits as shown in the example of FIG. 2d. In the figure, OC1 and OC2 represent compensation circuits that can be implemented in the example shown in FIG. 2c. R1, R2, and R3 represent resistors, which are connected to form a voltage distributor network, and provide reference voltages for the compensation circuits OC1 and OC2. In particular, one end of the resistor R1 is connected to a positive power supply potential Vcc. The other end of R1 is connected to one end of the resistor R2 and the reference voltage input end of the compensation circuit OC1. The other end of the resistor R3 is connected to a ground point GND.

The first output stage Q1 provides an impedance control signal VZ1 and is connected to the positive input terminals of each of the compensation circuits OC1 and OC2.

The output stage of the second compensation circuit OC2 is connected to the second output stage of the amplifier A4, and the output stage of the first compensation circuit OC1 is connected to the third output stage of the amplifier A4.

The size of the resistors R1 to R3 can make the reference voltage applied to the first compensation circuit OC1 slightly lower than the maximum output voltage provided by the output stage of the amplifier A4, and make the reference voltage applied to the second compensation circuit OC2 slightly lower. For the reference voltage applied to OC1.

When working, consider the situation: the power supply voltage moves from the lower limit of the operating range to the higher limit of the operating range. At the lower limit, all impedance components will be fully activated, making VZ1 higher than that used in the two compensation circuits OC1 and Reference voltage of OC2. As the power supply voltage increases, the amplifier A4 will try lower impedance control voltages VZ1 to VZ3, bringing VZ1 below the voltage reference applied to OC1. As a result, the impedance control signal VZ3 is pulled down, so that VZ1 and VZ2 can be maintained close to Vcc.

If the power supply voltage increases again, the voltages VZ1 and VZ2 will increase and finally reach the reference voltage applied to the second compensation circuit OC2. This compensation circuit will then pull down the second impedance control signal VZ2, so that the only impedance element remains activated, which is the impedance element controlled by VZ1.

Fig. 2e Correction of compensation circuits for two or more individual impedance control signals VZ1 to VZ3. According to this modification, the first impedance control signal VZ1 is applied to the positive input terminal of the first compensation circuit OC1. The output stage of the first compensation circuit is connected to the positive input terminal of the second compensation circuit OC2 and the second output stage of the amplifier A4 to provide a second impedance control signal VZ2. The output stage of the second compensation control circuit OC2 is connected to the third output stage of the amplifier A4 to provide a third impedance control signal VZ3. The two negative input terminals of the first compensation circuit OC1 and the second compensation circuit OC2 are connected to a reference voltage obtained through a resistor-voltage divider and resistors R4 and R5. Similar to the circuits of FIGS. 2d and 2e, the compensation circuits OC1 and OC2 can be implemented as shown in FIG. 2c.

As a matter of fact, the output stage of the first compensation circuit OC1 is also sent to the positive input of the second compensation circuit OC2. The series connection of this compensation circuit will be the first one. Pull down its connected impedance control signal. With the increase of the supply voltage, the latter impedance control signal will also be pulled down until the only impedance element, which remains activated, is the impedance element controlled by VZ1. Because the amplification of the series connection increases the amplification of the control amplifier A4, in this specific embodiment, it is very convenient to provide a low potential between the series terminals through a decoupling device (not shown in FIG. 2e).

FIG. 3 is a modification of a termination impedance device for terminating a symmetric transmission line TR, such as a twisted pair type transmission line. The symmetrical transmission line is connected to a common input terminal and an inverting input terminal of an input buffer circuit 1. For each input terminal of the input buffer 1, a separate terminal impedance device 2 and 2 'are provided, each of which includes a plurality of terminal impedance elements, which are TZ1 to TZ3 and TZ1' to TZ3 ', respectively. Individual terminal impedance elements of each terminal impedance device 2 and 2 'receive individual impedance control signals VZ1 to VZ3, as shown in the figure. The connected transistors of the transistors TZ1 to TZ3 are paired devices of NZ1 to NZ3, respectively, so that the functions of the terminal impedance devices 2 and 2 'can be achieved, which are basically the same as the functions of the paired impedance device 4.

The modification of the paired impedance device 4 in FIG. 4 or FIG. 1 or 2a is similar to the termination impedance device. According to the modification of FIG. 4, each pair of impedance elements is formed by connecting four or any number of metal oxide semiconductor field effect crystal (MOSFET) transistors in series, and their gates receive the same impedance control signal. This modification is suitable for: when it is desired that the electrical characteristics of the paired impedance element and the connected terminal impedance element are different, a set and known ratio is adopted in order to save power in the paired impedance element. In the specific embodiment illustrated in FIG. 4, the paired impedance element is composed of four metal-oxide-semiconductor field-effect crystal (MOSFET) transistors connected in series, each receiving the same gate voltage, assuming approximately four times the impedance of its connected terminal impedance element. Impedance, assuming that the transistors of the paired impedance elements have the same geometric size as the corresponding terminal impedance elements.

FIG. 5 is a diagram illustrating the functions of the impedance control signals VZ1 to VZ3 in the specific embodiments of FIGS. 1 and 2 described above. It can be known from the legend that for the low operating voltage Vcc, all the impedance control signals VZ1 to VZ3 remain close to the supply voltage Vcc. As the supply voltage increases, a pair of impedance elements and their connected terminal impedance elements will be closed after other elements, while the remaining impedance elements are driven to stay as long as possible in the linear operating area.

Legend R of Figure 5_ref= Constant function. The distance between the position of each curve VZ1 to VZ3 and the asymptote Vcc depends on the set target impedance, that is, depends on R_ref. R_refThe smaller the position, the higher these positions are in the legend of FIG.

It will be apparent to those skilled in the art that the present invention may be embodied in many different aspects. Therefore, the scope of the present invention is not limited to the specific embodiments described above.

Transmission line receiver circuit with transmission line terminal impedance