Ferroelectric memory cell and method of making the same

Ferroelectric memory unit and manufacturing method thereof

Background of the invention

This case relates to ferroelectric thin films for non-volatile memory, in particular to metal-ferroelectric-metal-oxide-germanium semiconductors.

This case relates to ferroelectric thin films for non-volatile memory, and in particular to metal-ferroelectric-metal-tellurium semiconductors (or shallow junction metal-ferroelectric-metal-antimony semiconductors). Ferroelectric random access memory (FRAM) is known to be composed of a transistor (1T) and a capacitor (1C). Capacitors are typically fabricated between two conductive electrodes via interposed ferroelectric thin films, which are typically made of platinum. The circuit configuration and read/write sequence of this type of memory are similar to conventional dynamic random access memory (DRAM), but FRAM does not require data update. FRAM is known to have fatigue problems and fatigue problems observed in ferroelectric capacitors, which is a major obstacle to the commercial use of such memories. Fatigue is due to an increase in the exchangeable polarization as the number of exchange cycles increases (the stored non-volatile charge decreases). For this example, the "switching cycle" represents the sum of the read and write pulses of the memory.

Another known use of ferroelectric thin films for memory applications is the formation of ferroelectric gated field effect transistors (FETs) on FET gates via direct deposition of ferroelectric thin films. Such ferroelectric brake devices have been known for some time and include devices known as metal-ferroelectric-methane (MFS) FETs. The FRAMs incorporating the MFS FET structure have two advantages over the transistor-capacitor configuration: (1) the MFS FET occupies less surface area, and (2) provides non-destructive readout (NDR). The characteristics described later allow the MFS FET device to read thousands of times without exchanging ferroelectric polarization. Therefore, fatigue is not a problem when using an MFS FET device. Various types of MFS FET structures can be constructed, such as metal ferroelectric insulator MF (MFIS) FETs, metal ferroelectric metal germanium (MFMS) FETs, and metal ferroelectric metal oxide germanium (MFMOS) FETs.

To solve an effective MFS FET device, various problems must be overcome. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on the crucible. Such a structure is suitable for U.S. Patent No. 3,832,700. In addition, it is extremely difficult to have a clean interface between the ferroelectric material and the crucible. Another problem is the appropriate charge for ferroelectric materials. The FEM structure on the gate is shown in U.S. Patent No. 5,303,182, which emphasizes that the transfer of metal ions to the gate is undesirable. A similar structure is shown in U.S. Patent No. 5,416,735.

The object of the present invention is to overcome the aforementioned problems.

It is an object of the present invention to provide an MFS FET device that provides non-destructive readout.

Another object of the present invention is to provide an MFS FET device that occupies a relatively small surface area.

Another object of the present invention is to provide an MFS FET device that requires a relatively low programming voltage.

Another object of the present invention is to provide an FEM memory cell having a very low leakage current.

Another object of the present invention is to provide an MFS FET device including a FEM unit over a MOS transistor.

Another object of the present invention is to provide a paving p^-FEM gate unit on the layer, the p^-The layer extends beyond the edge of the FEM gate unit.

Another object of the present invention is to provide an FEM unit having a diffusion barrier layer which is easily formed therein.

Another object of the present invention is to provide a contact including a drain electrode⁺And p^-FEM unit for the conductive surface.

Another object of the present invention is to provide an FEM device that occupies a relatively small surface area and requires a relatively low program planning voltage.

Another object of the present invention is to provide an FEM gate unit having asymmetric ferroelectric polarization.

The method of forming a semiconductor structure of an FEM cell of the present invention includes forming a device region for a ferroelectric memory FEM gate cell on a germanium substrate. A suitable impurity implanting device region forms a conductive path for use as a source junction region, a gate junction region, and a drain junction region. The FEM unit includes an FEM gate unit formed on a substrate. The gate junction region is formed in the source junction region and the drain junction region of the FEM gate unit region, and the FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer and an upper metal layer. A Schotty barrier layer or a very shallow junction layer is formed in the FEM gate unit and the gate junction region as another conductive path. The FEM gate unit is separated from the source region and the gate region. Depending on other devices built on the substrate, and depending on the efficiency of the various construction sequences, the formation of multiple conductive paths can be performed at multiple stages of fabrication.

The FEM unit semiconductor structure includes a substrate which may be a body substrate or an SOI type substrate, first and second types of conductive paths are formed on the substrate, and an FEM gate unit is formed on the gate region, wherein the FEM gate unit includes a layer under The metal layer, one layer of FE layer and one layer of upper metal layer, and one of the third type of conductive paths are formed in the FEM gate unit and the gate region. The FEM unit can be constructed in series with a conventional MOS transistor.

The method of the present invention for forming two types of transistor semiconductor structures includes forming a device region of a MOS transistor and a ferroelectric memory (FEM) gate unit on a germanium substrate. A suitable impurity implanting device region forms a conductive path for use as a source junction region, a gate junction region, and a drain junction region. Conventional MOS transistors are formed on a substrate. The FEM unit includes an FEM gate unit formed on the substrate, which may be located above or alongside the MOS transistor. The gate junction region is formed in a source junction region and a drain junction region of the FEM gate unit, and the FEM gate unit includes a lower metal layer, a ferroelectric (FE) layer and an upper metal layer. The FEM gate unit is separated from the source and drain regions, as is the conductive path between the FEM gate unit and the gate junction. Depending on the other devices built on the substrate and depending on the efficiency of the various construction sequences, the formation of multiple conductive paths can be performed at multiple stages of fabrication.

The dimorphic semiconductor structure comprises a germanium substrate, which may be a bulk germanium substrate or an SOI type substrate. Three types of conductive paths are located above the substrate. The FEM gate unit is located above the gate region and can be above or alongside the conventional MOS transistor, wherein the FEM gate unit includes a lower metal layer, an FE layer and an upper metal layer.

The method of forming a semiconductor structure of a FEM cell of the present invention includes forming a device region of a ferroelectric memory FEM gate cell on a germanium substrate. A suitable impurity implanting device region forms a conductive path for use as a source junction region, a gate junction region, and a drain junction region. The FEM unit includes an FEM gate unit formed on the substrate. Forming a gate junction region of the FEM gate unit on the FEM gate unit region between the source junction region and the drain junction region, the FEM gate unit including a lower metal layer, a ferroelectric (FE) layer and an upper metal layer . The shallow junction region is formed in the FEM gate unit and the gate junction region as another conductive path. Like the conductive path between the FEM gate unit and the gate junction, the FEM gate unit is separated from the source and drain regions. Depending on the other devices built on the substrate and depending on the efficiency of the various construction sequences, the formation of a plurality of conductive vias can be performed at various stages of fabrication.

The FEM cell semiconductor structure includes a substrate which may be a body germanium substrate or an SOI type substrate. The first and second types of conductive paths are located above the substrate. The FEM gate unit is located above the via region, wherein the FEM gate unit includes a lower metal layer, an FE layer and an upper metal layer. The third type of conductive path is located in the FEM gate unit and the path section. The FEM unit can be constructed in series with a conventional MOS transistor.

The method of forming a semiconductor structure of a FEM cell of the present invention includes forming a device region of a ferroelectric memory FEM gate cell on a germanium substrate. Suitable impurities are implanted into the device to form a conductive path for use as a source junction region, a gate junction region and a drain junction region. The FEM unit includes an FEM gate unit formed on the substrate. Forming a gate junction region of the FEM gate unit on the FEM gate unit region between the source junction region and the drain junction region, the FEM gate unit including a lower metal layer, a ferroelectric (FE) layer and an upper metal Floor. The shallow junction layer is formed in the FEM gate unit and the gate junction region as another conductive path that extends into the drain junction region. Like the conductive path between the FEM gate unit and the gate junction, the FEM gate unit is separated from the source and drain regions. Depending on the other devices on the substrate and the efficiency of the various configuration sequences, the formation of multiple conductive paths can be performed at multiple stages of fabrication.

The FEM cell semiconductor structure includes a germanium substrate, which may be a body germanium substrate or an SOI type substrate. Two types of conductive paths are located above the substrate. The FEM gate unit is located above the gate region, wherein the FEM gate unit includes a lower metal layer, an FE layer and an upper metal layer. Another type III conductive path is located in the FEM gate unit and the via section and extends into the drain region. The FEM unit can be constructed in series with a conventional MOS transistor.

A method of forming a semiconductor memory device on a germanium substrate includes implanting a first type of impurity impurity to a germanium substrate to form a first type conductive path for use as a gate region; forming a MOS capacitor on the first type of conductive path; depositing a FEM capacitor The MOS capacitor includes a deposited metal layer, an FE layer and an upper metal layer, thereby forming a stacked gate unit; and implanting a second type of impurity impurity on the germanium substrate on either side of the gate region to form a second type conductive path for use as a a source junction region and a drain junction region; and a deposition insulating structure surrounding the FEM gate unit.

A ferroelectric memory (FEM) unit constructed in accordance with the present invention includes a germanium substrate; a gate region is located on the substrate and is doped to form a first type of conductive path; a source junction region and a drain junction region are located a pair of second-type conductive paths are formed by doping on either side of the gate region of the substrate; a MOS capacitor includes an oxide layer and a third-type conductive layer is located on the gate junction region, wherein the MOS capacitor has a predetermined Surface area; a FEM capacitor includes a lower metal layer, an FE layer and an upper metal layer; wherein the FEM capacitor is stacked on and laid on at least a portion of the MOS capacitor, thereby forming a stacked gate unit with the MOS capacitor; and an insulating layer having an upper surface Laying on the junction area, the stacking gate unit and the substrate; and a source electrode and a drain electrode are respectively located on the upper surface of the insulating layer and extending through the insulating layer to make electrical contact with the individual junction regions; and a gate The pole electrode is located on the upper surface of the insulating layer and extends through the insulating layer to make electrical contact with the metal layer above the stacked gate unit.

These and other objects and advantages of the present invention will become more fully apparent from the description of the appended claims.

1 and 2 illustrate an example of a sequential step of forming a substrate for use in the FEM unit of the present invention.

Figure 3 illustrates an FEM gate unit constructed on a substrate.

Fig. 4 illustrates a specific example of the FEM unit of the present invention, which comprises a layer of germanium formed under the FEM gate unit.

Figure 5 illustrates the preparation of a substrate for use in another embodiment of the present invention.

Figure 6 illustrates the formation in p^-Another specific example of the FEM gate unit of the present invention on the conductive layer.

Figure 7 illustrates the current flow of the FEM unit of the present invention.

8(a) to (b) illustrate the basic operation principle of the MFS FET device of the present invention.

9(a) to (b) are the I of the FEM gate unit of the present invention_DRelative to V_GLine diagram.

Figures 10-13 illustrate the sequential stages of preparing a substrate and forming an active region for use with the FEM unit of the present invention.

Figure 14 illustrates a complete two transistor memory cell constructed as a body on a substrate.

Figure 15 illustrates a complete two transistor memory cell constructed on an SOI substrate.

Figure 16 illustrates another specific example of a complete two transistor memory cell constructed on an SOI substrate.

Figure 17 illustrates a 4 x 4 array of memory cells of the present invention.

18(a) to (b) illustrate the basic operation principle of the MFS FET device of the present invention.

19(a) to (b) are the I of the FEM gate unit of the present invention_DRelative to V_GLine diagram.

Figure 20 illustrates the substrate and active region of the FEM unit used in the present invention.

Figure 21 illustrates a substrate on which an FEM gate unit is formed.

Figure 22 illustrates an FEM gate unit constructed on a substrate and surrounded by an insulating region.

Figure 23 illustrates that the FEM gate unit of the present invention has a source, gate and drain regions attached to the substrate.

Figure 24 illustrates that the FEM unit of the present invention has a shallow junction layer formed below the FEM gate unit.

Figure 25 illustrates the complete FEM unit of the present invention and also illustrates the current flowing therethrough.

26(a) to (b) illustrate the basic operation principle of the MFS FET device of the present invention.

27(a) to (b) are the I of the FEM gate unit of the present invention_DRelative to V_GLine diagram.

Figures 28-30 illustrate the sequential stages of preparing a substrate and forming an active region for use with the FEM unit of the present invention.

Figure 31 illustrates an FEM gate unit constructed on a substrate and surrounded by an insulating region.

Figure 32 illustrates that the FEM gate unit of the present invention has a source, gate and drain regions attached to the substrate.

Figure 33 illustrates that the FEM unit of the present invention has a shallow junction layer formed beneath the FEM gate unit.

Figure 34 illustrates the complete FEM unit of the present invention and also illustrates the current flowing therethrough.

Figure 35 illustrates an alternative embodiment of the FEM unit formed on the body raft substrate.

Fig. 36 illustrates an alternative example of the FEM unit formed on the SOI substrate.

37(a) to (b) illustrate the basic operation principle of the MFS FET device of the present invention.

38(a) to (b) are the I of the FEM gate unit of the present invention_DRelative to V_GLine diagram.

Figure 39 illustrates a sheet of tantalum substrate that has been fabricated to aid in forming the FEM unit of the present invention.

Figure 40 illustrates a single transistor offset stacked gate unit constructed in accordance with the present invention.

41(a) and 41(b)-45(a) and 45(b) illustrate the sequential steps of the stacked transistor gate structure constructed in accordance with the present invention.

Figures 46-49 illustrate the sequential steps of a variation of a single transistor stacked gate unit constructed in accordance with the present invention.

Figure 50 is a diagram showing a PE hysteresis loop for the FE of the present invention.

51a and 51b are diagrams showing the charge distribution of the device of the present invention in the "0" state and the "1" state, respectively.

52(a) to (b) are the I of the FEM gate unit of the present invention_DRelative to V_GLine diagram.

Figure 53 illustrates a FEM unit constructed in accordance with the present invention.

Figure 54 (a) ~ (b) is the I of the FEM gate unit of the present invention_DRelative to V_GLine diagram.

Figures 55(a)-(b) illustrate PE hysteresis loops for various FEM gate units.

Figures 56(a) to (b) illustrate the basic operation principle of the MFS FET device of the present invention.

Figure 57 illustrates a memory array constructed in accordance with the present invention.

(Example 1)

The ferroelectric memory (FEM) unit of the present example may be formed on a SOI (SIMOX) substrate, or may be formed on the body substrate to form a p^-trap. The preliminary description focuses on the formation of FEM gate units on the SIMOX substrate. In a few specific examples of the FEM gate unit, the MOS electro-crystal system is manufactured simultaneously with the ferroelectric memory unit by conventional means well known to those skilled in the art. Thus, for the sake of clarity, the drawings do not illustrate the formation of MOS transistors.

Referring now to Figure 1, the SIMOX substrate is illustrated at 30. In a preferred embodiment, the substrate 30 is formed of hafnium oxide and is a single crystal substrate. As illustrated in Figure 1, substrate 30 can already be partially etched into a clarified configuration, and a portion of the substrate has been slightly noisy to form an active region or device region 32 that provides the desired background polarity, in this example n^-The background polarity of the area. As is well known in the art, a plurality of such zones are formed on a wafer surface. For the FEM gate unit of the present invention, the cells are arranged in a vertical grid to form a memory array.

A preliminary description of the substrate formation and preparation method, the FEM gate unit will be laid on the substrate, and the final result will form a FEM memory unit. The edge of the active region 32 encloses an inactive region or insulating region 30a, 30b which is an upward extension of the substrate 30. A trench is formed in a region of the substrate, which is schematically illustrated at 34, 36. The trench region is ultimately filled with an insulating material, typically cerium oxide.

Referring now to Figure 2, it can be seen that the active region 32 has been modified into a source region 38, a gate region 40 and a drain region 42. These regions are shielded across the active region 32 by application of a photoresist, which will eventually become the region of the gate region 40 and the appropriate ion implantation into the remainder of the active region 32 to form two layers.⁺The layer, also referred to herein as the first type of conductive path, will be formed as source region 38 and drain region 42. The appropriate ion implantation of this example can implant arsenic ions at a preferred energy of about 50 keV, but is acceptable in the range of 40 keV to 70 keV, and the dose is 2×10.¹⁵/cm 2 to 5×10¹⁵/ square centimeter range. In addition, phosphorus ions can be implanted in the same dose range from 30 keV to 60 keV. The wafer is then heat treated to excite and diffuse the implanted ions. The temperature of the heat treatment ranges from 500 ° C to 1100 ° C.

At this point, the formation of the FEM gate unit can begin. Referring now to Figure 3, the FEM gate unit is generally indicated at 44 and includes a lower electrode 46, a ferroelectric (FE) material 48 and an upper electrode 50. The FEM gate unit 44 is constructed by depositing a lower electrode on the gate region 40, also referred to herein as a second type of conductive path. The lower electrode 46 can be made of platinum or rhodium, platinum/rhodium alloy or other suitable electrically conductive material. The metal thickness is from 20 nanometers to 100 nanometers.

Second, the FE material is deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb(Zr, Ti)O₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁,BaTiO₃, or LiNbO₃. The preferred order of preferred compounds is Pb₅Ge₃O₁₁, SBT and PZT. Most of the experimental work in the field of FEM gate units is performed on PZT compounds. The FE material 48 is deposited to a thickness of from 100 nanometers to 400 nanometers.

The upper electrode 50 is then formed on the FE material. The upper electrode may be formed of the same material of the lower electrode to a thickness of 20 nm to 200 nm. The conductive path precursor is indicated at 52. This precursor eventually diffuses into the gate region 40 by the metal ions from the lower electrode 46 to become a metal halide layer.

The photoresist is applied to the FEM gate unit and the unit is then etched into the appropriate configuration and dimensions. It is to be understood that the three-layer FEM gate unit does not need to be accurately aligned as shown, since its shape can be formed by applying photoresist and masking with different geometries. However, for the sake of clarity, the FEM gate unit is illustrated as having a structure that abuts the aligned sidewalls.

Referring now to FIG. 4, FEM gate unit 44 is illustrated as a component of FEM memory unit 53, which includes FEM gate unit 44 and a lower source region, via region, and drain region, the specific example including a layer formed below FEM gate unit 44. A thin layer 54 of telluride, where the conductive path precursor 52 is located. As described in the second embodiment of the method of the present invention, the telluride layer 54 may be formed prior to deposition of the components of the FEM gate unit 44; or it is assumed that the lower electrode 46 is made of platinum (Pt) or an alloy thereof to allow diffusion of platinum into In the upper part of the gate region 40, a shallow telluride layer is formed as a shoal barrier layer, which is referred to herein as a third type of conductive path.

The titanium oxide 56 or other suitable barrier insulating material layer is formed by CVD to form a FEM gate unit. The titanium oxide is etched to form a sidewall insulating layer of the gate electrode. Photoresist is applied and appropriate⁺And p⁺The area is formed by ion implantation. The oxide layer is formed by CVD or other suitable passivation insulation is applied. The structure is heat treated at 500 ° C to 1000 ° C to passivate and diffuse the implanted ions. To fully illustrate the FEM cell 53, the oxide layer 58 and the source electrode 60, the gate electrode 62, and the drain electrode 64 are formed with pupils and bonded to their individual components.

The specific example illustrated in Fig. 4 shows the simplest example of the structure of the present invention. The structure is a ferroelectric gate depletion type MIS transistor. At 0 gate voltage, below the FEM gate unit^-The charge in the path is completely depleted. Therefore, the leakage current is extremely small. To maintain a small leakage current, the lower electrode 46 contacts n^-Any point on the edge of the point and n⁺Source area or n⁺The edge spacing of the drain region is indicated by "D" and must be at least 50 nm to maintain a small leakage current. However, as D increases, the series resistance of the memory cell also increases. Therefore, it is preferred that D is not more than 300 nm. Gate leakage current from platinum to n^-Type Xiao di barrier contact and platinum to ferroelectric material contact decision. Leakage current is the gate current from very small to medium field strength. Platinum and n^-The potential barrier between the turns is 0.9 eV. a potential barrier of this size makes n^-The enthalpy path is completely depleted when the ferroelectric material is not polarized, or the ferroelectric material is polarized with a negative charge at the lower electrode. When the ferroelectric material is polarized with a positive charge at the lower electrode, the threshold voltage of the memory transistor is small. The nature of these memory charges and the technique for changing the amount of voltage required to program the unit are detailed later.

In another specific example of the MFS FET of the present invention, referring to FIG. 5, p^-Layer 70 can be formed as a conductive path precursor in gate via region 40. The substrate 30 and the active region 32 are formed as described in FIGS. 1 and 2. p^-Layer can be implanted with B or BF₂Ions are formed or formed by diffusion of metal ions by the FEM gate unit. Boron ions can be implanted at 3 keV to 10 keV, while BF₂The ions can be implanted at an energy of 15 keV to 50 keV. The ion concentration of the two cases is 1 × 10¹¹/cm 2 to 1×10¹⁵/ square centimeter range.

Using the bulk CMOS substrate as an example to illustrate the manufacturing process, the first step is to manufacture n^-Well and p^-The well structure separates the structures and implants appropriate ions to provide threshold voltage adjustment of the transistor. The photoresist is used to shield the CMOS segments of the wafer. Secondly, the phosphorus ion has an energy of 30 keV to 120 keV and a dose of 1.0×10.¹²/cm 2 to 5.0×10¹⁵/cm2 implant p^-The well, here will constitute the FEM gate unit. Multiple implantation steps and/or thermal diffusion are required to obtain n^-The best supplier distribution of the layers. The photoresist is stripped and removed. Implanted n^-The ruthenium layer can also be replaced by a selective epitaxial film growth of 100 nm to 1000 nm. Boron (3 keV to 5 keV) or BF₂(30 keV to 50 keV) ion implantation with a dose of 5.0×10¹²/cm 2 to 1.0×10¹³/ square centimeter. The ions are excited by heat.

Referring now to Figure 6, the lower electrode 46 is now formed by depositing platinum or other suitable material as previously described to form the FEM gate unit. Such metals have a thickness of from 20 nanometers to 100 nanometers. Implantable swell or BF₂ion. The FE material 48 is deposited to a thickness of from 100 nanometers to 400 nanometers, and the upper electrode 50 is formed by depositing a thickness of 20 nanometers to 200 nanometers of platinum or other suitable electrode material. The photoresist is applied, and the upper and lower electrodes and FE are etched to provide an appropriate spacing "D" from the source and drain regions as previously described. The photoresist is then removed by structural stripping. As illustrated in Figure 4, the titanium oxide (56) or another suitable barrier insulating layer protects the ferroelectric material by CVD deposition. The titanium oxide is etched to form a sidewall insulating layer on the gate electrode. Other oxides can be used in this step. Reapply photoresist and implant n⁺ion. Photoresist FEM stripping removal and oxide or another suitable passivation insulating layer is applied by CVD. The structure is heat treated to densify the passivation insulating layer and activate the implanted ions. The photoresist is applied again, and the contact holes are etched to form a method which is well known in the art.

As for the method for forming the shoal barrier layer 54 or the shallow junction layer 70, the barrier layer structure is used to provide an efficient exchange mechanism for the FEM unit of the present invention.

In addition, if the ferroelectric material cannot be subjected to high-temperature heat treatment, the source/drain ion implantation and annealing can be completed before the deposition of the lower gate electrode.

operation:

The structure constructed in accordance with the present invention is particularly effective because the FEM gate unit located above the conductive path of the gate region can move the polarity of the gate region, and an effective current can flow from the source through the gate to the drain. The structure provides almost complete charge depletion in the "off" state and provides effective low heat transfer in the "on" state. Figure 7 is an enlarged view of the FEM unit of the present invention illustrating a typical prior art current flow indicated by dashed line 72, wherein the current flowing through the gate region 40 is located just below the FEM gate unit. The reason is that the known FEM cell configuration does not fully allow current to flow through the gate region. This configuration can be considered as a semi-"open" switch. The solid line 74 illustrates the full "off" switch of the present invention where current can flow through the entire gate region below the barrier structure 70.

A memory unit constructed in accordance with the present invention can be placed in an array of memory cells such that the gate lines are perpendicular to the drain lines. To write to the FEM gate unit 44, +V_P1Applied to all gate electrodes, the source and drain electrodes of the memory cell are at ground potential. The FE 48 is thus polarized, so that the positive charge is located at the lower electrode 46 and the negative charge is located at the upper electrode 50 (see Fig. 8b). The FEM gate unit 44 is thus in a highly conductive state.

When negative voltage -V_P0Applied to the gate electrode (programming line) and positive voltage +V_P0Applied to the drain, and the source is grounded and here |V_P1|>|V_P0At the time of FE, FE is polarized by the negative charge of the lower electrode 46. The FEM gate unit 44 is thus placed in a low conduction state (see Figure 8a). The writing process allows individual memory transistors in the memory array to be written independently of other memory cells in the array without causing or interference from threshold voltages from other memory cells of the array.

The threshold voltage of the FEM gate unit 44 is determined as follows: For large arrays, the threshold voltage in the "1" state must be a positive value of 0.4 V to 0.8 V. The threshold voltage of the "0" state must be greater than the supply voltage, which is 3.3 V. n^-Path layer is p^-Type substrate junction and the bottom electrode barrier layer, or very shallow p^-The surface layer and gate bias are depleted. The memory window can be displayed equal to:<maths><img file="TW409366B_D0001.tif" /></maths>Here Q_FEFor residual charge and C_FEThe ferroelectric capacitor for the gate unit.

During the reading operation, the voltage V is not greater than the coercive voltage (that is, the voltage at which the memory contents can be changed)_aApplied to the gate electrode and the drain electrode. Because when any electrode is in V_aWhen the bias voltage is applied, the contents of the memory unit are not disturbed, so the reading operation will not interfere with the memory contents of any memory unit. Therefore, long-term charge retention can be obtained.

Single transistor memory unit:

General I of MFMOS FET_DRelative to V_GThe diagram is illustrated in Figure 9. Figure 9a illustrates the attachment of a high-pass doped N_DI of the FEM unit_DRelative to V_Gcharacteristic. When the FEM gate unit is not energized, the center line is I_DRelative to V_Ocurve. When the FEM unit is programmed to the "1" state, the threshold voltage of the FEM unit is negative. Such a large bungee current flows through the passage area even if V_G=0 V. This type of device is not suitable for large array applications.

Figure 9b illustrates the accompanying low path noisy N_DI of the FEM unit_DRelative to V_Gcharacteristic. The threshold voltage of the FEM unit is positive when the program is programmed to the "1" state. When the gate is at ground potential, no current flows through the device. The large memory array of such a device will have minimal standby leakage current, so no frequent updates are required.

Ferroelectric Pb for MFMOS applications₅Ge₃O₁₁film:

Displaying lower ferroelectric capacitance results in higher memory windows and lower programming voltages. Thicker film and lower<img file="TW409366B_D0002.tif" />The material can obtain lower ferroelectric capacitance; however, if the ferroelectric exchange field is clearly defined, the former option can increase the program planning voltage. Common oxide ferroelectric materials have higher<img file="TW409366B_D0003.tif" />And T_c, not oxide ferroelectric materials have lower<img file="TW409366B_D0004.tif" />And T_c. Oxide Pb₅Ge₃O₁₁The film has extremely low εr and medium T_c(178 ° C). Table 1 compares the memory window and Pb of the MFMOS device₅Ge₃O₁₁, PZT and SrBi₂Ta₂O₉The ferroelectric gate of the film. Even Pb₅Ge₃O₁₁The steady-state polarization of the film is much better than PZT and SrBi₂Ta₂O₉Lower film due to low<img file="TW409366B_D0005.tif" />Therefore, via Pb₅Ge₃O₁₁The memory window of the gate controlled MFMOS device is larger than its opposite window.

<tables><img file="TW409366B_D0006.tif" /></tables>

Gate oxide (cerium oxide) thickness: 100 angstroms

Steady state V_DepAssumed to be 0.5V

The FEM memory unit and its constituent methods are thus disclosed. The FEM gate unit can be constructed as a single transistor device or can be constructed with associated MOS transistors. Although the preferred embodiment of the invention has been disclosed, it is understood that the scope of the invention, which is defined by the scope of the appended claims,

(Example 2)

The ferroelectric memory (FEM) unit of this example may be formed on a SOI (SIMOX) substrate or may be formed on a bulk germanium substrate. Here, the description focuses on forming the FEM gate unit on the body substrate, but as used herein, the "base substrate" means the SOI substrate or the body substrate. It is to be understood that the MOS transistor and the FEM gate unit can be fabricated sequentially or simultaneously to form the dual transistor structure of the present invention. The completed structure provides a cost-effective, extremely small memory unit with a simple circuit configuration, non-volatile memory and very low leakage current.

Referring now to Figure 10, the germanium substrate is illustrated at 210. In this specific example, the substrate 210 is a single crystal substrate and is made of a body. As illustrated in Figure 10, the substrate 210 has been modified to the illustrated configuration, and a portion of the substrate is slightly noisy to form an active region or device region 212 that provides the desired background polarity, in this case n^-The background polarity of the zone is referred to as the first type of conductive path. Phosphorus ions are also referred to herein as first-type impurity impurities, with an energy of 30 keV to 120 keV, 1.0 × 10¹²/cm 2 to 5.0×10¹³/ square centimeter dose implanted into the FEM gate unit^-The well forms a first type of conductive path. Multiple implantation steps and/or thermal diffusion are required for n^-The layer gets the best donor distribution. Implanted n^-The ruthenium layer can also be replaced by a selective epitaxial film growth of 100 nm to 1000 nm. The active region 212 is surrounded by an insulating region 214 which is made of cerium oxide by thermal oxidation or by chemical vapor deposition (CVD) to form LOCOS or mesa isolation between devices. As is well known in the art, a plurality of active regions are formed on the surface of the germanium wafer. As for the dual transistor memory cell of the present invention, the active regions are arranged in a vertical grid to form a memory array (described in detail later).

Referring now to Figure 11, it will be appreciated that the construction of the semiconductor device of the present invention progresses to that point where MOS transistor 215 has formed on the substrate. Active area 212 has been modified to include p^-The well 216 is completed by masking the active region 212 and ion implantation. p^-Layer can be implanted via B or BF₂Ions (herein referred to as second type dopant impurities) are formed in the active layer 212. Boron ions can be implanted at 3 keV to 10 keV, BF₂The ion system is implanted at an energy of 15 keV to 50 keV. The ion concentration of the two cases is at 5×10¹¹/cm 2 to 1×10¹⁵/ square centimeter range. The ions are excited by annealing heat. Implanted ions diffuse into n^-Active region to form p^-The n layer, referred to herein as the second type of conductive path. Annealing is carried out at a temperature of from 500 ° C to 1100 ° C. The via region 218 of the first type of conductive path remains in the p^-On either side of the well 216.

The outer side of the active region 212 is shielded, and a layer of ruthenium dioxide layer 220 is CVD.^-The well 216 and a portion of the via region 218 are formed. One layer n⁺The polysilicon is again deposited by CVD. A layer of germanide layer 224 can be formed by CVD on n^-Polycrystalline germanium and as a component of a MOS transistor, although illustrated in the drawings, are an optional part of the method and structure of the present invention. Another layer of ruthenium dioxide layer 226, also referred to herein as a dielectric insulating layer, is deposited by CVD.

In addition, a layer of ruthenium dioxide can be deposited on p^-The non-shielding region of the well 216 and the via region 218, the ruthenium dioxide layer is etched to form a sidewall, n⁺Polycrystalline germanium layer 222 and layer 224 are deposited therein. A top layer of ruthenium dioxide is deposited on the sidewalls and layer 224.

The MOS transistor is covered by a photoresist 228 that covers the MOS transistor 215 of the FEM gate unit and the via region 218. Then the remaining device area 212 is implanted by arsenic ions to form n⁺ source area 230 and n⁺The bungee region 232, referred to herein as the third type of conductive path. The appropriate ion implantation in this example can be used for arsenic ion implantation at a preferred energy of about 50 keV, but implants of 40 keV to 70 keV are acceptable, and the dose is 1 x 10¹⁵/cm 2 to 5×10¹⁵/ square centimeter range. In addition, phosphorus ions can be implanted in the same dose range from 30 keV to 60 keV. In either case, the material implanted in this constituent step is referred to herein as a third type dopant impurity.

The photoresist is stripped and removed. Referring now to Figure 12, a FEM gate unit 234 is fabricated. The gate unit 234 includes a lower electrode 236, an FE layer 238, and an upper electrode 240. The construction of the FEM gate unit 234 begins with depositing a lower electrode on the ceria layer 226 and a portion of the ceria layer extending over the via region 218. The lower electrode 236 can be made of platinum or tantalum, ruthenium dioxide or a platinum/ruthenium alloy or other suitable electrically conductive material. Other suitable conductive barrier layers can also be used. The preferred embodiment of the electrode 236 has a thickness of from 20 nanometers to 100 nanometers.

Next, FE material 238 is deposited by CVD. The FE material can be any of the following: Pb(Zr, Ti)O₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁,BaTiO₃, or LiNbO₃. Arranged in a preferred order, the preferred compound is Pb₅Ge₃O₁₁, SBT and PZT. Most of the experimental work in the field of FEM gate units is carried out on PZT compounds. The FE material 238 is deposited to a thickness of 50 nanometers to 400 nanometers.

The upper electrode 240 is then formed on the FE material. The upper electrode may be made of the same material of the lower electrode to a thickness of from 2.0 nm to 100 nm.

The photoresist is applied to the FEM gate unit and the unit is then etched to the appropriate configuration and size. It is to be understood that the three layers of the FEM gate unit do not need to be accurately aligned as shown, since the shape is formed by applying photoresist and masking with different geometries. However, for the sake of clarity, the FEM gate unit is illustrated as having a structure that abuts the aligned sidewalls.

Referring now to Figure 13, the photoresist is stripped and removed by the FEM gate unit, a layer of TiO_x242,Si₃N₄Or other suitable dielectric material is used to isolate the ferroelectric material from the cerium oxide by CVD deposition.

As shown in FIG. 14, the structure is formed by depositing a ruthenium dioxide layer 244, covering the insulating layer on the extension of the structure, and grinding and interposing the drain electrode 246, and the gate electrode 248 and the source electrode 250 are completed.

Referring now to Figure 15, the structure of the present invention is illustrated as being formed on an SOI substrate, which includes substantially all of the same components labeled with the same reference numerals in the specific example of Figure 14, but the substrate is made of cerium oxide 252 instead of Figure 14 The body used in the example.

Referring now to Figure 16, an alternative embodiment of a memory unit is schematically illustrated at 260. In this embodiment, the body is used as the substrate 262 to form the active region 264 and subsequently modified into p^-Well 266,n^-The regions 268, 270 serve as gate regions for the MOS transistor 272 and the FEM unit 274, respectively. Like n⁺Source region 278, forming n⁺Bungee area 276. The oxide region 279 is adjacent to the active region 264 and is formed by thermal oxidation or CVD. The materials of both the MOS transistor 272 and the FEM gate unit 274 are sequentially laid. As for the layers of the MOS transistor 272, the cerium oxide layer 280, n⁺Polycrystalline germanium layer 282 and selective germanide layer 284. The FEM gate unit 274 is formed via a deposition bottom electrode 286, an FE material 288, and a top electrode 290. Second, depositing TiO by CVD_x,Si₃N₄Or other suitable insulating layer 292, and a layer of cerium oxide 294 is also deposited by CVD. The manufacturing process is completed by mounting the gate electrode 296, the gate electrode 298, and the source electrode 2100. MOS transistor and FEM with TiO_xOr Si₃N₄Layer isolation. In this embodiment, layer 292 is used as a dielectric insulating layer, and layer 294 is used as a cover insulating layer.

Several specific examples of forming MFS transistor combinations adjacent to MOS transistors have thus been shown. As used herein, "adjacent" means that a double crystal is formed along both sides, or one transistor is stacked on top of another.

The specific examples illustrated in Figs. 14, 15, and 16 show a ferroelectric gate depletion type MIS transistor combined with a conventional MOS transistor. When the FE is polarized with a positive charge at the bottom electrode interface 238a, the threshold voltage of the MFS transistor can be a negative value. When the FE is polarized with a negative charge of the bottom electrode interface 238a, the threshold voltage of the MFS transistor is extremely large. At zero gate voltage, the MOS transistor is not conducting. Therefore, even if the threshold voltage of the MFS transistor is negative, no current flows through the device.

When the gate voltage is equal to the operating voltage, the MOS transistor is extremely conductive. The device current is controlled by the current flow of the MFS transistor. When the MFS transistor is in the "0" state, that is, when the threshold voltage is greater than the operating voltage, no current flows through the device. To maintain a small leakage current in the "0" state, any of the lower electrodes 236 and 286 and n⁺Source area and n⁺The spacing between any edge of the bungee zone is indicated by "D" and must be at least 50 nm. However, as D increases, the series resistance of the memory cell also increases. Therefore, it is preferred that D is not more than 300 nm. When the MFS transistor is in the "1" state, that is, when the threshold voltage is extremely low or has a negative value, both the MOS transistor and the MFS transistor are electrically conductive. Therefore, a large current flows through the device. Thus, even if the "1" threshold voltage of the MFS transistor is negative, the device can be used for a large memory array.

operation:

A memory unit constructed in accordance with the present invention can be placed in a memory cell array with gate lines perpendicular to the drain lines, as shown in FIG. Referring now to Figures 14, 17 and 18, to write to the FEM gate unit 234, +V_P1Applied to all of the gate electrodes 248 (Y1, Y2, Y3, and Y4), the source electrode 250 and the drain electrode 246 (X1, X2, X3, and X4) of the memory cell are at ground potential. The FE 238 is thus polarized such that a positive charge is located at the lower electrode interface 238a and a negative charge is located at the upper electrode interface 238b (see Figure 18b). This causes the FEM gate unit 234 to become in a highly conductive state.

When negative voltage -V_P0When applied to the gate electrode 248 (programming line), for example, Y2, positive voltage +V_P0Applied to the drain 232, such as X3, and the source 230 is grounded and here |V_P1|&gt;|V_P0|FE, for example, 2102, X3, Y2, for negative charge polarization of the lower electrode interface 238a. The FEM gate unit 234 is thus placed in a low conduction state (see Figure 18a). The writing process allows individual memory transistors of the memory array to be written out of phase with other memory cells in the array without interfering with other memory cells of the array.

The threshold voltages of the FEM gate units 215, 274 shown in Figures 14 and 16 are determined as follows: for large arrays, the threshold voltage in the "1" state can be a negative or a small positive voltage. The threshold voltage of the "0" state must be greater than the supply voltage, which is 3.3 V.

If n^-The doping density of the area is about 1.0×10¹⁶/ cubic centimeter, then Pt-n barrier layer n^-The spacing of the zones is about 0.3 microns. Threshold voltage can be changed by n^-The doped density and thickness of the via region, and the permittivity and residual charge adjustment of the ferroelectric capacitor gas.

In the reading operation, the voltage V is not greater than the coercive voltage (ie, the voltage of the memory content can be changed)_aApplied to the gate electrode and the drain electrode. Because when any electrode is in V_aWhen the bias voltage is applied, the contents of the memory unit are not disturbed, so the reading operation will not interfere with the memory contents of any memory unit. Therefore, long-term charge retention is obtained.

MFMOS FET I_DRelative to V_GThe sketch is illustrated in Figure 19. Figure 19a illustrates a high path noisy N_DI of the FEM unit_DRelative to V_Gcharacteristic. When the FEM gate unit is not powered, the center line 2104 is I_DRelative to V_Ocurve. When the FEM unit program is programmed to the "1" state (line 2106), the threshold voltage of the FEM unit is negative. When the FEM unit program is programmed to the "0" state (line 2108), the threshold voltage of the FEM unit is positive. So in the "1" state, even V_G=0 V, large buckling current can flow through the access zone. This type of device alone is not suitable for large array applications.

Figure 19b illustrates the I of the device of the present invention_DRelative to V_Gcharacteristic. Line 2112 illustrates I when the FEM gate unit is not powered_DRelative to V_Ocurve. When the FEM unit program is programmed to the "1" state (line 2110), the threshold voltage of the FEM unit is negative. When the FEM unit program is programmed to the "0" state (line 2114), the threshold voltage of the FEM unit is positive. When the threshold voltage of the MOS transistor (dashed line 2116) is programmed to the "1" state, the device threshold voltage is limited to a small positive value. When the gate is at ground potential, no current flows through the device. A large memory array of such devices will have minimal standby leakage current.

Thus, a dual transistor memory cell including a MOS transistor and an FEM gate unit and a method of constructing the same have been disclosed. Although the preferred embodiment of the invention and its variations are disclosed, it is to be understood that modifications may be made in the construction and method without departing from the scope of the invention as defined by the appended claims.

(Example 3)

The ferroelectric memory (FEM) unit of the present example may be formed on a SOI (SIMOX) substrate or may be formed on a bulk germanium substrate. The description herein focuses on forming an FEM gate unit on a body substrate. In a few specific examples of the FEM gate unit, the MOS electro-crystal system is manufactured simultaneously with the ferroelectric memory unit by conventional means well known to those skilled in the art. Thus, for the sake of clarity, the drawings do not illustrate the formation of MOS transistors.

Referring now to Figure 20, the germanium substrate is illustrated at 310. In a preferred embodiment, the substrate 310 is a single crystal substrate which is made of a body. Other specific examples can be formed on the SOI substrate. The term "tantalum substrate" is used herein to mean a body substrate or SOI substrate or any other suitable ruthenium-based substrate. As illustrated in Figure 20, the substrate 310 has been partially etched to the illustrated configuration, and a portion of the substrate has been slightly noisy to form an active region or device region 312 that provides the desired background polarity, in this case n^-The polarity of the region is referred to herein as the first type of conductive path. The active region 312 is surrounded by an insulating region 314 made of cerium oxide. As is well known in the industry, a plurality of such zones are formed on the surface of the germanium wafer. For the FEM gate unit of the present invention, the cells are arranged in a vertical grid to form a memory array.

Using the bulk CMOS substrate as an example to explain the process, the initial steps are to manufacture n^-Well and p^-The well structure isolates these structures and implants appropriate ions to provide threshold voltage adjustment of the transistor. The photoresist is used to shield the wafer segments. Secondly, phosphorus ions (also referred to herein as first-type impurity impurities) are at an energy of 30 keV to 120 keV at 1.0×10.¹²/cm 2 to 5.0×10¹³/ square centimeter dose implant, will constitute the FEM gate unit p^-trap. Multiple implantation steps and/or thermal diffusion are required for n^-The layer gets the best donor distribution. The photoresist is stripped and removed. Implanted n^-The ruthenium layer can also be replaced by a selective epitaxial film growth of 100 nm to 1000 nm thick.

At this point, the formation of the FEM gate unit begins. Referring now to Figure 21, the FEM gate unit is generally indicated at 316 and includes a lower metal layer or electrode 318, a ferroelectric (FE) material 320 and an upper metal layer or electrode 322. The FEM gate unit 316 is constructed by depositing a lower electrode on the active region 312. Lower electrode 318 can be made of Pt, Ir, or Pt/Ir alloy or other suitable electrically conductive material. In a preferred embodiment, the metal has a thickness of from 20 nm to 100 nm.

Finally, p can be formed in the FEM gate unit 316 and the gate junction interval.^-Floor. p^-Layers can be via B or BF₂The ion implanted first type conductive path surface or lower electrode 318 is formed. Boron ions can be implanted at 3 keV to 10 keV, while BF₂The ion system is implanted at 15 keV to 50 keV. The ion concentration in both cases is 1 × 10¹¹/cm 2 to 1×10¹⁵/ square centimeter range. During the annealing step (detailed later), the implanted ions diffuse into the n^-Gate junction area forms p^-The layer, referred to herein as the third type of conductive path.

Second, after proper masking, the FE material is deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb(Zr, Ti)O₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁,BaTiO₃, or LiNbO₃. Preferred compounds are arranged in a preferred order as Pb₅Ge₃O₁₁, SBT and PZT. The experimental work in the field of most half FEM gate units is performed on PZT compounds. The FE material 320 is deposited to a thickness of 50 nanometers to 400 nanometers.

An upper electrode 322 is then formed on the FE material. The upper electrode can be made of the same material of the lower electrode to a thickness of 20 nm to 200 nm. The photoresist is applied to the FEM gate unit and the unit is then etched to the appropriate configuration and size. It should be understood that the three-layer FEM gate unit as shown does not need to be accurately aligned, as its shape may be formed by applying photoresist and masking with different geometries. However, for the sake of clarity, the FEM gate unit is illustrated as having a structure that abuts the aligned sidewalls.

TiO_x,Si₃N₄Or other suitable barrier insulating material layer 324, as shown in Figure 22, protects the FEM gate unit by CVD formation. The barrier insulating material is etched to form a sidewall insulating layer of the gate electrode.

Referring now to Figure 23, it can be seen that active region 312 has been modified to source region 326, gate region 328 and drain region 330. Each zone forms two layers by implanting appropriate ions (also referred to herein as second type impurity impurities) into the remainder of the active zone 312.⁺A layer (also referred to herein as a second type of conductive path) will be formed as source region 326 and drain region 330. The appropriate ion implantation of this example can be performed by implanting arsenic ions at a preferred energy of about 50 keV, but it can be implanted in a range of 40 keV to 70 keV and using 1×10.¹⁵/cm 2 to 5×10¹⁵/ square centimeter dose. In addition, phosphorus ions can be implanted in the same dose range from 30 keV to 60 keV.

Referring now to Figure 24, the wafer is heat treated to excite and diffuse implanted ions, including ions in the source and drain regions and ions in the lower electrode. The diffusion of ions implanted by the lower electrode 318 results in the formation of a shallow junction 332 below the FEM gate unit 316, which is a third type of conductive path. The heat treatment is carried out at a temperature ranging from 500 ° C to 1100 ° C to passivate and diffuse the implanted ions. A cerium oxide layer 334 is then formed over the structure by CVD, or other suitable passivation insulation can be applied.

Referring now to Figure 25, FEM gate unit 316 is illustrated as part of FEM memory unit 336, which includes FEM gate unit 316 and lower source, via and drain regions, including a shallow shallow junction region 332 which is p^-A layer is formed below the FEM gate unit 316.

To complete the description of FEM unit 336, a via is formed in oxide layer 334 to accommodate source electrode 338, which is coupled to its individual components.

The specific example illustrated in Fig. 25 represents a ferroelectric gate depletion type MIS transistor. At zero gate voltage, below the FEM gate unit^-The charge in the path is completely depleted. This leakage current is extremely small. To maintain a small leakage current, either edge of the lower electrode 318 and n^-Source area or n^-The edge spacing of the drain region is indicated by "D" to maintain a small leakage current of at least 50 nm. However, as D increases, the series resistance of the memory cell also increases. Therefore, it is preferred that D is not more than 300 nm. Gate leakage current borrowed p^-The type of shallow joint 332 and the contact of platinum to ferroelectric material are determined. Platinum and n^-The potential barrier between the turns is 0.9 eV. Third type p^-Conductive layer 332 and first type n^-The potential barrier between conductive layers 328 is also about 0.9 eV. When the potential barrier of this size causes the ferroelectric material to be unpolarized, n^-The type channel is completely depleted. When the ferroelectric material is polarized with a positive charge at the lower electrode interface 348, the threshold voltage is small. When the ferroelectric material is polarized with a negative charge at the lower electrode interface 348, the threshold voltage of the memory transistor is extremely large. The nature of such memory charge and the technical requirements for changing the voltage requirements of the programming unit are detailed later.

Implanted B or BF₂The diffusion of ions into the gate junction region is controlled by maintaining any edge of the shallow junction layer 332 and the source region and the drain region spacing "C". In a preferred embodiment, "C" is from about 0 nm to about 300 nm. The shallow junction structure is used to provide a low leakage current reliable potential barrier between the gate region 328 and the conductive vias and to provide an efficient switching mechanism for the FEM unit of the present invention.

In addition, if the ferroelectric material cannot maintain the high temperature heat treatment, the source/drain ion implantation and annealing can be completed before the deposition of the lower gate electrode.

operation:

The structure constructed in accordance with the present invention is particularly effective because the FEM gate unit above the conductive path of the gate region can shift the polarity of the gate region, thereby permitting the effective current to flow from the source to the drain. The structure provides full charge depletion when in the "off" state. Figure 25 also illustrates a typical prior art current flow, indicated by dashed line 344, wherein the current flowing through the gate region 328 flows only directly below the FEM gate unit. The reason is that the known FEM unit configuration is a surface-dump type structure, and the device disclosed herein is of a depletion type. The operational theory of a depletion device is similar to the operational theory of a junction FET. Solid line 346 illustrates the current flowing through the device of the present invention, which can flow through the entire gate region below junction 332.

The memory unit constructed in accordance with the present invention can be disposed in the memory cell array such that the gate line is perpendicular to the drain line. At negative voltage, -V_P0Applied to gate electrode 340 (programming line), and +V at positive voltage_P0Applied to drain 330, and source 326 grounded and here |V_P1|&gt;|V_P0At the time, FE is polarized by the negative charge of the lower electrode interface 348. The FEM gate unit 316 is thus placed in a low conduction state (see Fig. 26a). The writing process allows individual memory transistors in the memory array to be written independently of other memory cells in the array without interfering with other memory cells in the array.

To write to the FEM gate unit 316, +V_P1Applied to all of the gate electrodes 340, the source electrode 338 and the drain electrode 342 of the memory cell are all at ground potential. Thus polarized FE 320, a positive charge is located at the lower electrode interface 348 and a negative charge is located at the upper electrode interface 350 (see Figure 26b). This allows the FEM gate unit 316 to be in a highly conductive state.

The threshold voltage of the FEM gate unit 316 is determined as follows: For large arrays, the threshold voltage in the "1" state must be a small positive value, that is, 0.4 V to 0.8 V. The threshold voltage of the "0" state must be greater than the supply voltage, which is 3.3 V. n^-Path layer borrowing p^-Type substrate junction depletion and borrowing extremely shallow p^-The surface layer and gate bias are depleted. Can be displayed as a memory window equal to:<maths><img file="TW409366B_D0007.tif" /></maths>Here Q_FEFor residual charge and C_FEThe ferroelectric capacitor for the gate unit.

The voltage V in the reading operation that is not greater than the coercive voltage (that is, the voltage at which the memory contents can be changed)_aApplied to the gate electrode and the drain electrode. Because when any electrode is in V_aWhen the bias voltage is applied, the contents of the memory unit are not disturbed, so the reading operation does not interfere with the memory contents of the memory unit. Therefore, the charge can be held for a long time.

Single transistor memory unit:

General I of MFMS FET_DRelative to V_GThe plot is illustrated in Figure 27. Figure 27a illustrates a high-pass doped N_DI of the FEM unit_DRelative to V_Gcharacteristic. When the FEM gate unit is not energized, the center line is I_DRelative to V_Ocurve. When the FEM unit is programmed to the "1" state, the threshold voltage of the FEM unit is negative. So even V_G=0 V large current can flow through the access area. This type of device is not suitable for large array applications.

Figure 27b illustrates a low-pass doped N_DI of the FEM unit_DRelative to V_Gcharacteristic. When the FEM unit is programmed to the "1" state, the threshold voltage is positive. When the gate is at ground potential, no current flows through the device. The large memory array of such devices has minimal standby leakage current.

Ferroelectric Pb for MFMS applications₅Ge₃O₁₁film:

It is clear that lower ferroelectric capacitors result in higher memory windows and lower programming voltages. Thicker film and lower<img file="TW409366B_D0008.tif" />The material can result in lower ferroelectric capacitance; however, the former option can increase the programming voltage. Oxide Pb₅Ge₃O₁₁The film has a very low<img file="TW409366B_D0009.tif" />And medium T_c(178 ° C). Even Pb₅Ge₃O₁₁The steady-state polarization of the film is much lower than that of PZT and SrBi.₂Ta₂O₉Polarization of the membrane, but because of the former<img file="TW409366B_D0010.tif" />Low, so Pb₅Ge₃O₁₁The memory window of the MFMS device of the gate control is larger than the memory window of the latter two.

Thus, the FEM memory unit and its constituent methods have been disclosed. The FEM gate unit may be constructed as a single transistor device or may be configured to incorporate a MOS transistor. Although the preferred embodiment of the invention has been disclosed, it is to be understood that the scope of the invention may be modified without departing from the scope of the invention as defined by the appended claims.

(Example 4)

The ferroelectric memory (FEM) unit of the present example may be formed on a SOI (SIMOX) substrate or may be formed in a bulk germanium substrate. Here, the description will focus on the body substrate forming the FEM gate unit, but as used herein, the " substrate" means an SOI substrate or a body substrate. In a few specific examples of the FEM gate unit, the MOS electro-crystal system is manufactured simultaneously with the ferroelectric memory unit by conventional means well known to those skilled in the art. For the sake of clarity, the figures do not clarify the MOS transistor.

Referring now to Figure 28, the germanium substrate is illustrated at 410. The substrate 410 of this specific example is a single crystal substrate and is made of a body crucible. As illustrated in Figure 28, the substrate 410 has been partially etched into the illustrated configuration, with portions of the substrate being slightly noisy to form an active region or device region 412 that provides the desired background polarity, in this case n^-The background polarity of the zone is referred to herein as the first type of conductive path. An insulating region 414 formed of cerium oxide is surrounded by the active region 412. As is well known in the industry, multiple regions are formed on the surface of the wafer. As for the FEM gate unit of the present invention, the cells are arranged in a vertical grid to form a memory array.

Using the bulk CMOS substrate as an example to explain the manufacturing process, the initial step is to manufacture n^-Well and p^-The well structure, separating the structures, and implanting appropriate ions provides threshold voltage adjustment to the transistor. The substrate 410 of this specific example has been fabricated into p^- or p^-trap. The photoresist is used to shield the wafer segments. Secondly, the phosphorus ion is also referred to herein as the first type impurity impurity at 30 keV to 120 keV energy at 1.0×10.¹²/cm 2 to 5.0×10¹³/cm square dose implant p^-The well, here will constitute the FEM gate unit. Multiple implantation steps and/or thermal diffusion are required to obtain n^-The best donor distribution of the layers. The photoresist is stripped and removed. Implanted n^-The ruthenium layer can also be selectively epitaxially grown to a thickness of 100 nm to 1000 nm instead.

Referring now to Figure 29, followed by formation of p on active region 412^--Layer 16. p^--Layer can be implanted with B or BF₂Ions (herein referred to as second type dopant impurities) are formed into the active region 412. Boron ions can be implanted at 3 keV to 10 keV, while BF₂Ions can be implanted at 15 keV to 50 keV. The ion concentration of the two cases is at 5×10¹¹/cm 2 to 1×10¹⁵/ square centimeter range. The ions are thermally excited by annealing. Implanted ions will diffuse into n^-Active region to form p^-The n layer, referred to herein as the second type of conductive path. Annealing is carried out at a temperature of from 500 ° C to 1100 ° C.

At this point, the formation of the FEM gate unit can begin. Referring now to Figure 30, the FEM gate unit is generally indicated at 418 and includes a lower metal layer or electrode 420, a ferroelectric (FE) material 422 and an upper metal layer or electrode 424. The construction of the FEM gate unit 418 begins with the deposition of the lower electrode at p^-Layer 416. The lower electrode 420 can be Pt or Ir, IrO₂Or made of Pt/Ir alloy or other suitable conductive material. Other suitable conductive barrier materials can also be used. In a preferred embodiment, the electrode 420 has a thickness of from 20 nanometers to 100 nanometers.

Second, the FE material is deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb(Zr, Ti)O₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁,BaTiO₃, or LiNbO₃. Preferred compounds are arranged in a preferred order as Pb₅Ge₃O₁₁, SBT and PZT. Most of the experimental work in the FEM gate unit field is performed on PZT compounds. The FE material 422 is deposited to a thickness of from 100 nanometers to 400 nanometers.

An upper electrode 424 is then formed over the FE material. The upper electrode can be made of the same material of the lower electrode to a thickness of 20 nm to 200 nm.

The photoresist is applied to the FEM gate unit and the unit is then etched to the appropriate configuration and size. It should be understood that the three layers of the FEM gate unit as shown do not need to be accurately aligned, as their shape may be formed by applying photoresist and masking with different geometries. However, for the sake of clarity, the FEM gate unit is illustrated as having a structure that abuts the aligned sidewalls.

As shown in Figure 31, TiO_xLayer 426 or other suitable barrier insulating material protects the FEM gate unit by CVD formation. TiO_xThe sidewall insulating layer of the gate electrode is formed by etching.

Referring now to Figure 32, it can be seen that active region 412 has been modified to source region 428, gate region 430, and drain region 432. Each zone spans the active zone 412 via the application of a photoresist, p^-Layer 416 and FEM gate unit 418 mask the region that will eventually become gate region 430 and will implant the appropriate ions, also referred to herein as third type dopant impurities, into the remainder of active region 412 to form two layers.⁺The layer, referred to herein as the third type of conductive path, will serve as source region 428 and drain region 432. Must pay attention to p^-Layer 416 extends over gate junction region 430 and partially over drain junction region 432. In this case, proper ion implantation can be used at a preferred energy of about 50 keV, but 40 keV to 70 keV is acceptable, and 1 x 10¹⁵/cm 2 to 5×10¹⁵Arsenic ions are implanted at a dose of / square centimeter. In addition, phosphorus ions can be implanted in the same dose range from 30 keV to 60 keV.

Referring now to Figure 33, the wafer is excited and diffused by the heat treatment, including the source region, the drain region, and the lower electrode. Implanted layer 416 B or BF₂Ion diffusion results in the formation of a shallow p under the FEM gate unit 418^-n junction, this is the second type of conductive path. The heat treatment temperature range is in the range of 500 ° C to 1100 ° C to passivate and diffuse the implanted ions. A cerium oxide layer 434 is then formed over the structure by CVD, or other passivation insulation is applied.

Referring now to Figure 34, FEM gate unit 418 is illustrated as part of FEM memory unit 436, which includes FEM gate unit 418 and the underlying source, via, and drain regions, including a thin film formed under FEM gate unit 418. Shallow junction area 416, which is p^-n layer.

To fully illustrate the FEM cell 436, a via is formed in the oxide layer 434 to receive the source electrode 438, which is connected to the individual components. The drain electrode 442 can be connected to the drain region 432 and p^-n junction 416.

The specific example illustrated in Fig. 33 shows a ferroelectric gate depletion type MIS transistor. At zero gate voltage, below the FEM gate unit^-The charge in the path is completely depleted. This leakage current is extremely small. To maintain a small leakage current, any edge of the lower electrode 420 and n⁺Source or n⁺The edge spacing of the bungee region is indicated by "D" and must be at least 50 nm to maintain a small leakage current. However, as D increases, the series resistance of the memory cell also increases. Therefore, it is preferred that D is not more than 300 nm. Gate leakage current is composed of platinum and p^-The contact between the shallow contact surface 432 and the contact of platinum with the ferroelectric material is determined. Leakage current is the gate current for very small to medium field strength. p^-Layer and n^-The potential barrier between the turns is 0.8 eV to 1.0 eV. A potential barrier of this size may cause the ferroelectric material to be unpolarized, or when the positive charge of the electrode below the ferroelectric material is polarized,^-The type channel is completely depleted. When the ferroelectric material is polarized by the negative charge of the lower electrode, the threshold voltage of the memory transistor is small. The nature of such memory charge and the technique for changing the amount of voltage required by the programming unit are detailed later.

In addition, if the ferroelectric material cannot maintain the high temperature heat treatment, the source/drain ion implantation and annealing can be completed before the deposition of the lower gate electrode.

Referring now to Figure 35, an alternative embodiment of the FEM unit is illustrated, which includes two layers of germanide layers 444, 446 formed in the source and drain junction regions. The telluride layer is formed by CVD before depositing the insulating layer 434. This structure and advantage has a lower resistance to the source and drain regions. This increases the drain current of the memory cell.

A specific example of the FEM unit formed on the SOI substrate 448 is illustrated in FIG.

operation:

The structure constructed in accordance with the present invention is particularly effective because the FEM gate unit located above the conductive path of the gate region can change the polarity of the gate region, permitting the effective current to flow from the source to the drain. This structure provides complete depletion of charge when in the "off" state. When in the "on" state, current flows through the entire path region.

A memory unit constructed in accordance with the present invention can be placed in an array of memory cells such that the gate lines are perpendicular to the drain lines. To write to the FEM gate unit 418, +V_P1Applied to all gate electrodes, the source and drain electrodes of the memory cell are at ground potential. Thus, the FE 422 is polarized, so that the negative charge is located at the lower electrode 420 and the positive charge is located at the upper electrode 424 (refer to FIG. 10b). This causes the FEM gate unit 418 to become in a highly conductive state.

When negative voltage -V_P0Applied to the gate electrode (programming line), and positive voltage +V_P0Applied to the bungee, and the source is grounded and here |V_P1|&gt;|V_P0When the FE is polarized by the positive charge of the lower electrode 420. The FEM gate unit 418 is thus brought into a low conduction state (refer to Fig. 37a). The writing process allows individual memory transistors of the memory array to be written independently of other memory cells in the array without interfering with the programming of other memory cells in the array.

The threshold voltage of the FEM gate unit 418 is determined as follows: For large arrays, the threshold voltage in the "1" state must be a positive value of 0.4 V to 0.8 V. The threshold voltage of the "0" state must be greater than the supply voltage, which is 3.3 V. n^-Path layer is p^-Type substrate junction and is extremely shallow p^-The surface layer and gate bias are depleted. The memory window is displayed as equal to:<maths><img file="TW409366B_D0011.tif" /></maths>Here Q_FEFor residual charge and C_FEThe ferroelectric capacitor for the gate unit.

p⁺/n junction n^-The space width of the area is n^-The area density is 1.0×10¹⁶/ cubic centimeter, about 0.3 microns. Obviously if n^-When the thickness of the via layer is small and the noise is small, the threshold voltage of the "1" state can be a positive value. Threshold voltage can be borrowed n^-Path layer and p^-The doped density and thickness of the surface layer, the permittivity and the residual charge adjustment of the ferroelectric capacitor.

In the reading operation, the voltage V is not greater than the coercive voltage (ie, the voltage of the memory content can be changed)_aApplied to the gate electrode and the drain electrode. Because when the electrode is V_aWhen the bias voltage is applied, the contents of the memory unit are not disturbed, so the reading operation does not interfere with the memory contents of the memory unit. Therefore, long-term charge can be maintained.

Single transistor memory unit:

General I of MFMOS FET_DRelative to V_GThe drawing is illustrated in Figure 38. Figure 38a illustrates a high-pass doped N_DI of the FEM unit_DRelative to V_Gcharacteristic. When the FEM gate unit is not energized, the center line is I_DRelative to V_Ocurve. When the FEM unit program is programmed to the "1" state, the threshold voltage of the FEM unit is negative. So even V_G=0, large buckling current flows through the access zone. This type of device is not suitable for large array applications.

Figure 38b illustrates a low-pass doped N_DI of the FEM unit_DRelative to V_Gcharacteristic. When the FEM unit is programmed to the "1" state, the threshold voltage is positive. When the gate is at ground potential, no current flows through the device. The large memory array of such devices has minimal standby leakage current and does not require frequent updates.

Ferroelectric Pb for MFMOS use₅Ge₃O₁₁film:

It is clear that lower ferroelectric capacitors result in higher memory windows and lower programming voltages. Thicker film and lower<img file="TW409366B_D0012.tif" />The material can result in lower ferroelectric capacitance; however, if the ferroelectric switching domain is clearly defined, the former option can increase the programming voltage. Common oxide ferroelectric materials have higher<img file="TW409366B_D0013.tif" />And T_c. Oxide Pb₅Ge₃O₁₁The film has a very low<img file="TW409366B_D0014.tif" />And medium T_c(178 ° C). Table 2 compares the memory window and Pb of the MFMOS device₅Ge₃O₁₁, PZT and SrBi₂Ta₂O₉The ferroelectric gate of the film. Even Pb₅Ge₃O₁₁The steady-state polarization of the film is much lower than that of PZT and SrBi.₂Ta₂O₉Steady-state polarization of the film, borrowed Pb₅Ge₃O₁₁The memory window of the gate-controlled MFMOS device is still larger than the other because<img file="TW409366B_D0015.tif" />Low.

<tables><img file="TW409366B_D0016.tif" /></tables>

Steady state V_DepAssumed to be 0.5V

The FEM memory unit and its constituent methods are thus disclosed. The FEM gate unit can be constructed as a single transistor device or can be constructed with associated MOS transistors. Although the preferred embodiment of the invention has been disclosed, it is understood that the scope of the invention may be further modified without departing from the scope of the invention as defined by the appended claims.

(Example 5)

As described above, the present invention is a method of fabricating a MFMOS memory cell comprising a ferroelectric (FE) capacitor or a FEM gate unit on top of a MOS capacitor, the two devices being collectively referred to herein as a stacked gate unit. In a specific example of the present invention, the area of the MOS capacitor is larger than the area of the ferroelectric capacitor, thereby increasing the coupling efficiency and reducing the programming voltage of the device. Another specific example is described in which a second transistor is formed along the side of the stacked MOS and FE capacitors, and a ferroelectric capacitor is disposed on top of the MOS capacitor, wherein the ferroelectric capacitor and the MOS capacitor have the same cross section. This configuration allows for higher programming levels for small cells and for comparison of different size structures (also known as bias gate ferroelectric memory cells). Yet another specific example includes a MOS capacitor stacked on an FE capacitor, wherein the two capacitors have the same footprint.

The stacked ferroelectric memory cell unit of the present invention can be formed on a SOI (SIMOX) substrate or can form a p therein^-The body of the well is formed by a substrate. As used herein, "tantalum substrate" means an SOI substrate, a bulk substrate or any other type of substrate containing tantalum as a component and suitable for use in the present invention.

When the body substrate is used, the substrate is n^-type. The initial steps were made in n^-Well and p^-The well structure isolates the two structures and implants appropriate ions to make threshold voltage adjustments to the transistor. When using an SOI substrate, there is no need to form n^-Well or p^-trap.

Referring now to Figure 39, the germanium substrate is illustrated at 510. In a preferred embodiment, the substrate 510 is a single crystal substrate and is made of a body. As shown in FIG. 39, the substrate 510 is composed of n^-Made of . p^-Well 512 can borrow B or BF₂Ions are implanted into the surface of the substrate, followed by a thermal diffusion step at 950 ° C to 1200 ° C for 1 to 4 hours. Boron ions can be implanted at 3 keV to 10 keV, while BF₂The ions can be implanted at an energy of 15 keV to 50 keV. The ion concentration of the two cases is 1 × 10¹²/cm 2 to 1×10¹⁴/ square centimeter range.

In order to isolate the device, the insulating region 514 formed by cerium oxide is attached to p^-The well 512 grows before it forms on the substrate. As is well known in the industry, a plurality of such regions are formed on the surface of the germanium wafer. For the structure of the present invention, the unit is gated 2 to the bungee and p^-A vertical grid of wells forms a memory array.

Referring now to Figure 40, a single transistor memory unit of the present invention is illustrated. As shown in Figure 40, the active region 512 is modified to contain two n⁺Regions 516 and 518, which ultimately serve as the source and drain of the memory cell. p^-The well via region 520, referred to herein as the first type of conductive via, remains on the substrate 510. The source region 516 and the drain region 518 form two n by implanting appropriate ions (herein referred to as second type impurity impurities) to the active region 512.⁺The zone, also referred to herein as the second type of conductive path. In this case, proper ion implantation can be a preferred energy of about 50 keV, but an implant of 40 keV to 80 keV is acceptable and 1 x 10¹⁵/cm 2 to 5×10¹⁵The dose range of / square centimeter is implanted with arsenic ions. In addition, phosphorus ions can be implanted in the same dose range from 20 keV to 50 keV.

The MOS capacitor 522 is thinned by a thin layer of thermal oxide 524 after proper shielding.^-A via 520 is formed. In a preferred embodiment, layer 524 has a thickness of from 3 nanometers to 10 nanometers. Selective n⁺The polysilicon layer 524 is formed by CVD to a thickness of 100 nm to 300 nm to complete the MOS capacitor 522. n⁺The polysilicon acts as a buffer layer to relieve stress between the lower electrode of the FEM capacitor and the underlying oxide.

At this point, the formation of the FEM capacitor gate unit begins. The FEM gate unit 528 includes a lower metal layer or electrode 530, a ferroelectric (FE) material 532, and an upper metal layer or electrode 534. The FEM gate unit 528 is constructed by depositing a lower electrode on the MOS capacitor 522.

The lower electrode 530 can be Pt, Ir, IrO₂Or made of Pt/Ir alloy or other suitable conductive material. The metal thickness is preferably from 20 nm to 100 nm in a preferred embodiment. Lower electrode 530 and n⁺The polysilicon layer constitutes the upper electrode of the MOS capacitor 522 when used.

Second, the FE material is deposited by chemical vapor deposition (CVD). The FE material can be any of the following: Pb(Zr, Ti)O₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁,BaTiO₃, LiNbO₃Or other suitable ferroelectric materials. Preferred compounds are arranged in a preferred order as Pb₅Ge₃O₁₁, SBT and PZT. Most of the experimental work in the FEM gate unit field is performed on PZT compounds. The FE material 532 is deposited to a thickness of 50 nanometers to 400 nanometers.

An upper electrode 534 is then formed on the FE material. The upper electrode may be made of the same material of the lower electrode to a thickness of 20 nm to 200 nm, and the stacked gate unit is formed to include the FEM gate unit 528 and the MOS capacitor 522. This particular example shows the characteristics of a biased FEM gate unit in which the FEM gate unit has a smaller footprint than the full surface area of the MOS capacitor.

Figure 40 is a structure based on deposition of a suitable insulating material such as TiO_x,Si₃N₄Or other suitable barrier insulating material is completed on the memory unit. A thick interlaminar dielectric material is formed to obtain proper contact between the source region, the gate region and the drain region.

Referring now to Figures 41a and 41b, the construction and construction of two types of transistor memory cells having stacked gate cells will now be described. In this example, the structure is formed on the germanium substrate 540 on which the oxide layer 542 has been formed. The source, drain and gate regions may be formed at this step of the method or formed later. In summary, it is better to deposit n by CVD.⁺A polysilicon layer 544, which together with the oxide layer 542, forms a MOS capacitor 546. Then as mentioned above in n⁺A lower metal layer or electrode 548 is formed on the polysilicon layer 544. A top plan view of the lower metal layer 548 is illustrated in Figure 41b.

In the next step, as illustrated in the single transistor specific example, a ferroelectric material 550 is deposited on the lower electrode 548 and then an upper metal layer 552 is formed. A top plan view of lower metal layer 548 and upper metal layer 552 is illustrated in Figure 42b. The upper and lower metal layers and the FE material constitute the FEM gate unit 554.

Photoresist applied and lower electrodes 548 and n⁺The polysilicon layer 544 is etched to obtain the configuration shown in FIG. The structure shown in Figure 43 includes a second transistor 556 that includes a portion of the oxide layer 542;⁺The polysilicon layer 544' and the lower metal layer 548' are labeled with "nickname". The previously applied photoresist is stripped and removed, a new photoresist is applied, and the second type of impurity is implanted as described above to form the n illustrated in FIG.⁺Zone 558, 560, 562 is referred to herein as a second type of conductive path.

Referring now to Figure 45, the strip is stripped of the original photoresist, the wafer is passivated with a suitable insulating layer, a new photoresist is applied to the open contact holes and the first interconnect metal is defined, resulting in electrical bonding of the upper metal layer 552 to the metal layer 548'. .

This configuration has the advantage of low leakage current. The device leakage current is limited by the MOS transistor current.

A second specific example of the present invention begins again with the tantalum substrate. Referring to Figure 46, p^-An oxide layer 572 is formed over the well 570. Additional layers are deposited sequentially, including n⁺Polycrystalline germanium layer 574, lower metal layer 576, FE layer 578 and upper metal layer 580.

The photoresist is applied and the structure is etched, resulting in a configuration as shown in FIG. 47 which includes a MOS capacitor 582 and an FEM gate unit or capacitor 584 formed as a stacked gate unit 585. At this point a layer of insulating material such as TiO_xOr other suitable insulating material may be applied to protect the ferroelectric. Then, implant n⁺Ion formation⁺Source area 586 and n⁺Bungee area 588. The rest of p^-The material is illustrated at 590 to provide a gate path.

Referring now to Figure 49, the final structure is illustrated and has an insulating layer 592 disposed therein including a source electrode 594, a gate electrode 596 and a drain electrode 598.

This particular embodiment provides a very small unit. This device is especially suitable for VLSI memory applications.

The program is programmed to a high threshold voltage state:

Figure 50 illustrates the PE hysteresis loop for the ferroelectric material used herein. Pr is the polarization value of the ferroelectric material. Pr₀It is a negative polarity saturation polarization. Pr₀₀The polarization of the ferroelectric material after relaxation of the device has been programmed for the device to a high threshold voltage state. Pr₁It is a positive polarity saturation polarization. Pr₁₀The polarization of the ferroelectric material after the device has been programmed to a low threshold voltage state after relaxation of the device.

The charge distribution of the device constructed in accordance with the present invention is illustrated in Figure 51, wherein Figure 51a illustrates the charge distribution of the device program as a "0" state. And Figure 51b illustrates the charge distribution when the device program is programmed to the "1" state. To program the memory transistor to the "0" state for a large positive threshold voltage program, the device is non-conductive at the normal operating voltage and a negative voltage is applied to the control gate, resulting in a charge distribution as shown in Figure 51a. The Poison equation is:<maths><img file="TW409366B_D0017.tif" /></maths>Points are earned twice:<maths><img file="TW409366B_D0018.tif" /></maths>Here Pr₀Shown in Figure 50. The voltage drop across the ferroelectric capacitor is:<maths><img file="TW409366B_D0019.tif" /></maths>Therefore, the programming voltage is:<maths><img file="TW409366B_D0020.tif" /></maths>The threshold voltage after programming is:<maths><img file="TW409366B_D0021.tif" /></maths>Here Pr₀₀The polarization of the ferroelectric material after the device is programmed to a high threshold voltage relaxation.

Program programming to low threshold voltage state:

The program programming memory is a low threshold voltage, that is, a "1" state, a positive voltage V_P1Applied to the gate and negative voltage V_D1Applied to bungee and p^-trap. When the device is fabricated on an SOI substrate, no p^-trap. The source is extremely ground potential. The charge distribution is plotted in Figure 51b. The Posen equation is:<maths><img file="TW409366B_D0022.tif" /></maths>Integral (9) is obtained twice:<maths><img file="TW409366B_D0023.tif" /></maths>Equation (10) is rewritten as:<maths><img file="TW409366B_D0024.tif" /></maths>The pressure drop from the surface to the top electrode of the ferroelectric capacitor is:<maths><img file="TW409366B_D0025.tif" /></maths>The voltage drop of the ferroelectric capacitor is:<maths><img file="TW409366B_D0026.tif" /></maths>Therefore the supply voltage is:<maths><img file="TW409366B_D0027.tif" /></maths>The threshold voltage is:<maths><img file="TW409366B_D0028.tif" /></maths>Here, after programming to low-threshold voltage state relaxation, Pr₁₀Is a polarized charge. Thus, (1) increasing the channel doping density NA, (2) reducing the ferroelectric capacitance by selecting a lower dielectric constant material and/or increasing the ferroelectric film thickness, and (3) increasing by using a thinner thermal oxide layer. Gate oxide capacitor C_OxThe threshold voltage of the device in the "0" state can be greater than 0.0 V. This is a requirement for a single transistor RAM VLSI array. The result clearly indicates that the program planning voltage becomes smaller as the oxide capacitance increases.

Under various polarization conditions, the programmed voltage and threshold voltage of the device can be calculated from the above formula and shown in Table 3. Here, the programming voltage and path doping density are adjusted to obtain the "1" threshold voltage of V._T1=0.6 V. The polarization charge during program planning is assumed to be 36% higher than steady state polarization. Further assume that the ferroelectric material has a thickness of 300 nm and a capacitance of 2.9 × 10^-7 F/cm². The voltage drop across the ferroelectric material during programming is 3 V. Two gate oxide thicknesses, namely 5 nm and 6 nm, have been evaluated. Memory window ΔV_THShown in the last column of Table 3 and illustrated in Figure 52.

<tables><img file="TW409366B_D0029.tif" /></tables>

Referring now to Figure 52a, the prior art device I is illustrated_DFor V_GDrawing. Line 5100 represents V_T1Less than zero and V_T0It is a positive situation. A structure having such characteristics requires at least two devices (a memory transistor and a common transistor) for the RAM array, and a single transistor RAM array will require a relatively high program planning voltage.

Figure 52b illustrates that the "1" threshold voltage of the device formed by the method of the present invention is represented by line 5104, and the "0" threshold voltage is represented by line 5106.

The FEM memory unit and its constituent methods are thus disclosed. Although the preferred embodiment of the invention has been disclosed, it is understood that the scope of the invention may be further modified without departing from the scope of the invention as defined by the appended claims.

(Example 6)

The ferroelectric memory (FEM) unit of the present example is formed on a SOI (SIMOX) substrate or may be formed on a bulk germanium substrate. Described herein is an FEM gate unit that will focus on the body substrate.

Referring now to Figure 53, the ruthenium substrate is illustrated at 610. In a preferred embodiment, the substrate 610 is a single crystal substrate and is made of a body. Other specific examples can be formed on the SOI substrate. As used herein, "tantalum substrate" means a body substrate or SOI substrate or any other substrate that is suitably -based. As illustrated in Figure 53, p^-The substrate 610 contains a first type impurity impurity, which is a boron or boron compound, and has a concentration of about 1.0×10.¹⁵/cm 3 to 5.0×10¹⁵/ cubic centimeter.

Shallow n^-The type layer 612 (well structure), also referred to herein as a second type of conductive path, contains a second type of dopant impurity which is then implanted under the gate region by implantation of phosphorus or arsenic. Ion energy from 10 keV to 50 keV and dose of 1.0×10¹²/cm 2 to 1.0×10¹³/ square centimeter.

p^-The very shallow layer 14 (sub-well structure) of the type is formed in shallow n^-Type layer 12 and contains a third type of impurity impurity to BF₂Implanted n^-The second conductive layer is on top. BF₂Can be in the range of 10 keV to 40 keV and the dose is 5.0×10¹¹/cm 2 to 5.0×10¹²/ square centimeter range. This layer is referred to herein as the third type of conductive path.

At this point, the formation of the FEM gate unit can begin. The FEM gate unit is generally designated 616 and includes a lower metal layer or electrode 618, a ferroelectric (FE) material 620, and an upper metal layer or electrode 622. The composition of the FEM gate unit 616 begins with deposition of the lower electrode 618 and p.^-On layer 614. The lower electrode 618 can be Ir or Ir/IrO₂Made of alloy or Pt/Ir alloy or other suitable conductive material. In a preferred embodiment, the metal has a thickness of from 20 nanometers to 100 nanometers.

Second, the FE material is deposited by chemical vapor deposition (CVD) after proper shielding. The FE material can be any of the following: Pb(Zr, Ti)O₃ (PZT), SrBi₂Ta₂O₉ (SBT), Pb₅Ge₃O₁₁,BaTiO₃, or LiNbO₃. Expressed in a preferred order, the preferred compound is Pb₅Ge₃O₁₁, SBT and PZT. Most of the experimental work in the FEM gate unit field is performed on PZT compounds. The FE material 620 is deposited to a thickness of 50 nanometers to 400 nanometers.

Then, an upper electrode 622 is formed on the FE material. The upper electrode can be made of Pt, Pt/Ir alloy, Pt/IrO₂The alloy or other suitable material is made to a thickness of from 20 nanometers to 200 nanometers.

The photoresist is applied to the FEM gate unit and the unit is then etched into the appropriate configuration and dimensions. It will be appreciated that the three layers of the FEM gate unit as shown need not be accurately aligned, as their shape can be formed by applying photoresist and masking with different geometries. However, for the sake of clarity, the FEM gate unit is illustrated as having a structure that abuts the aligned sidewalls.

Now p^-The substrate 610 is formed into two layers by implanting appropriate ions, also referred to as fourth type impurity impurities.⁺The layer, also referred to herein as a fourth type of conductive path, serves as source region 624 and drain region 626. In this case, proper ion implantation can be a preferred energy of about 50 keV, but 40 keV to 70 keV is acceptable and 1 x 10¹⁵/cm 2 to 5×10¹⁵Arsenic ions are implanted at a dose per square centimeter. In addition, phosphorus ions can be implanted in the same dose range from 30 keV to 60 keV.

The wafer is heated to excite and diffuse implanted ions in the source and drain regions. The temperature of the heat treatment ranges from 500 ° C to 1100 ° C to cause the implant ions to excite and diffuse.

TiO_x,Si₃N₄Or other suitable barrier insulating material layer 630 protects the FEM gate unit by CVD formation, resulting in the formation of FE memory unit 632.

To complete the description of FEM cell 632, a via is formed in insulating layer 630 to accommodate word line (WL) (gate) electrode 634 and bit line (BL) electrode 636 which are connected to their individual components. Source 624 is grounded 640.

The specific example illustrated in Fig. 53 shows a ferroelectric gate depletion type MFMS transistor. At zero gate voltage, below the FEM gate unit^-The charge in the path is completely depleted. This leakage current is extremely small. To maintain a small leakage current, between any edge of the lower electrode 618 and n⁺Source region 624 and n⁺The edge spacing of the drain region 626 is "D" indicating that it must be at least 50 nanometers to maintain a small leakage current. However, as D increases, the series resistance of the memory cell also increases. Therefore, it is preferred that D is not more than 300 nm. Third type p^-Conductive layer 14 and second type n^-The potential barrier between conductive layers 612 is about 0.9 eV. a potential barrier of this size can make n^-The helium channel is completely depleted when the ferroelectric material is not polarized. When the ferroelectric material 620 is polarized with a positive charge adjacent to the lower electrode 618, the threshold voltage is small. When the ferroelectric material 620 is polarized with a negative charge adjacent the lower electrode 618, the threshold voltage of the memory transistor is extremely large. The nature of this memory charge and the amount of voltage required to change the programming unit are detailed later.

In addition, if the ferroelectric material cannot withstand the high temperature heat treatment, the source/drain ion implantation and annealing can be completed before the deposition of the lower gate electrode.

operation:

The structure constructed in accordance with the present invention is particularly effective because the FEM gate unit located above the conductive path of the gate region can change the polarity of the gate region. The licensed effective current flows from the source to the drain. The structure provides full charge depletion during the "off" condition. The operational theory of a depletion device is similar to a junction FET.

Summary of IMFMS FET I_DFor V_GThe plot is illustrated in Figure 54. Figure 54a illustrates the I of a symmetric FEM unit_DFor V_Gcharacteristic. When the FEM gate unit is not energized, the center line is I_DRelative to V_OCurve, where Pr=0. When the FEM unit program is programmed to the "1" state, the threshold voltage of the FEM unit is negative. So even V_G=0V, a large buckling current can flow through the via area. This type of device is not suitable for large array applications.

Figure 54b illustrates an I of the asymmetric FEM unit of the present invention_DFor V_Gcharacteristic. When the program is programmed to the "1" state, the threshold voltage of the FEM unit is positive. When the gate is at ground potential, no current flows through the device. A large memory array of such devices can have minimal standby leakage current.

The asymmetric polarization ferroelectric memory transistor unit of the present invention can be applied to an MFMS unit and an MFMOS unit to provide a low leakage current, high speed, maximum memory array. The low leakage current can be achieved by obtaining a positive threshold voltage for the "1" state and the "0" state. High-speed read and write can be achieved by increasing the drive current and reducing the path capacitance of the device. Because of the mobility of electrons, the mobility of pores is much higher, so n^-The channel memory device is preferably used for high speed operation.

Referring now to Figure 55, Jiang et al. "High Density Nonvolatile Ferroelectric SrBi₂Ta₂O₉Novel Technology of Memory, 1996 VLSI Technology Symposium, Honolulu, June 11-13, 1996, page 26, describes the use of indium instead of platinum as the electrode under the ferroelectric memory capacitor for improved performance. As illustrated in Figure 55, the description of SrBi with different lower electrodes is described.₂Ta₂O₉ The (SBT) capacitor is a 100 kHz click pulse layer measured PE hysteresis loop. The electrode below Figure 55a is Pt/TiO₂The electrode below Figure 55b is IrO₂And the electrode below Figure 55c is pure Ir. The remaining polarization P is measured 10 seconds after the capacitor is written_NV. As shown in Fig. 55c, the Pt/SBT/Ir capacitor exhibits a large depolarization charge in positive polarization, while the depolarization of the negative polarization capacitor is extremely small.

To obtain a positive "1" (highly conductive) threshold voltage, the device must have a small positive polarization charge at the lower ferroelectric/electrode interface, as shown in Figure 56a. To maintain a large memory window, there is also a large polarized negative charge on the lower ferroelectric/electrode interface, as shown in Figure 56b. This can be achieved with a Pt/SBT/Ir semiconductor structure. Steady state "1" state polarization charge is about 10 μC/cm², and the steady-state "0" polarization charge is about -2 μC/cm.². For a 0.3 micron SBT film with a dielectric constant of 280, the corresponding threshold voltage shifts were 12.1 V and -2.42 V, respectively. V can be obtained by adjusting the doping density of the via and achieving a threshold voltage of about 3 V at 0 ferroelectric polarization._T1And V_T0They are about 0.6 volts and 15 volts, respectively, as shown in Figure 54b.

Such a ferroelectric memory device can be used for low voltage, high density, and high speed applications. Memory unit is placed in p^-The well 610 is as shown in FIG. Figure 57 illustrates a nine-cell memory array in which the word lines are labeled WL1, WL2 and WL3, and the bit lines or drain lines are labeled BL1, BL2 and BL3. The source region of the entire transistor and the substrate are grounded. The source, word line and bit line are independently connected to the peripheral circuit as shown in FIG. Memory array via application of V_PPThe positive voltage is connected to the word line (gate) and the bit line is grounded and the block program is planned to be "1" (highly conductive). It is planned to program the individual memory cells to be "0" (low conduction) state. Negative programming voltage-V_PPApply to the word line and program the voltage V_PPApplied to the bit line. This results in only one unit having a bias voltage on the gate -V_PPAnd Yu Hao is extremely +V_PP. This memory unit is the only unit in the entire array that will be written to the "0" state.

Asymmetric polarization relaxation can be observed with many electrode combinations. In addition, it can be observed in any ferroelectric film and any kind of ferroelectric gate structure. The asymmetric polarization relaxation mechanism is both complex and sensitive to processing conditions. Thus required in a preferred embodiment of the invention, an asymmetric polarization relaxation technique is used to fabricate a single transistor memory cell controlled by a ferroelectric gate.

The threshold voltage of the FEM gate unit 616 is determined as follows: For large arrays, the threshold voltage in the "1" state must be a small positive value, that is, 0.4 V to 0.8 V. The threshold voltage of the "0" state must be greater than the supply voltage, which is 3.3 V. n^-Path layer is p^-Type substrate junction and is extremely shallow p^-The surface layer and gate bias are depleted. The memory window is displayed as equal to:<maths><img file="TW409366B_D0030.tif" /></maths>Here Q_FEFor residual charge and C_FEThe ferroelectric capacitor for the gate unit.

During the reading operation, the voltage V is not greater than the coercive voltage (ie, the voltage of the memory content can be changed)_aApplied to the gate electrode and the drain electrode. Because the electrode is V_aWhen the bias voltage is applied, the contents of the memory unit are not disturbed, so the reading operation does not interfere with the memory contents of any memory unit. Therefore, it is possible to obtain a charge for a long time.