Improved policide

Polysilicon-silicide

The technical field of the present invention generally relates to semiconductor manufacturing, and more particularly relates to transistors with polysilicon silicide gates.

In device manufacturing, insulating, semiconducting and conductive layers are formed on a substrate. The layers are patterned to form features and spaces. The components and spacing are scribed to form devices such as transistors, capacitors, and resistors. Secondly, these devices will be connected to each other to obtain the desired electrical functions, resulting in integrated circuits (ICs).

To reduce sheet resistance, metal oxide semiconductor (MOS) transistor systems use polysilicon silicide gates. The polysilicon silicide gate includes metal silicide such as tungsten silicide (WSix) covering heavily doped polysilicon. The polysilicon system is typically doped with phosphorus (P). The polysilicon should contain a high doping concentration to reduce sheet resistance.

However, metal silicides covering heavily doped polysilicon have stoichiometric control problems, which appear in the form of metal-rich interfaces. The metal-rich interface is undesirable because it cannot resist subsequent thermal processing. As a result, the interface will be oxidized. Oxidation will roughen the surface and in some cases will peel off the silicide film. Conventionally, the adverse effect of the metal-rich interface is avoided by providing an intrinsic layer (undoped layer) of polysilicon at the interface between the heavily doped polysilicon and the metal silicide. The addition of an undoped polysilicon layer will increase the height of the gate stack, thereby increasing the aspect ratio of the gate stack. Reducing the groundrule will increase the aspect ratio even more, thus causing processing problems. In addition, the addition of an undoped polysilicon layer will also increase the gate resistance, which will reduce the device performance. Another technique to avoid the metal-rich interface is to reduce the dopant concentration of polysilicon. The P concentration of the polysilicon layer should typically be maintained at 10²⁰Atom/cubic centimeter or less. This technique also poorly increases the gate resistance.

From the above, it is necessary to provide a reliable polysilicon gate system with reduced sheet resistance.

The present invention relates to the formation of reliable gate conductors with thinner thickness and lower sheet resistance. In one embodiment, the thinner thickness and lower sheet resistance are obtained by depositing a metal silicide layer doped in-situ on the doped polysilicon layer. Doping in the metal silicide layer will reduce the problems related to the metal-rich interface. This will allow the metal silicide layer to be deposited without essentially covering the polysilicon layer or requiring the polysilicon to have a lower dopant concentration.

<p>100Dynamic Random Access Memory Unit</p><p>101Substrate</p><p>110Transistor</p><p>112Polysilicon silicide gate stack</p><p>120Polysilicon layer</p><p>121Intrinsic polysilicon layer</p><p>122Metal silicide layer</p><p>160Trench capacitor</p><p>161Polysilicon</p><p>163node dielectric</p><p>170Buried well</p><p>173well</p><p>201Substrate</p><p>220Thin oxide</p><p>230Polysilicon layer</p><p>240Metal silicide layer</p><p>280Gate Conductor</p><p>285Conductive area</p><p>288Nitride layer</p><p>290Dielectric layer</p><p>291Contact</p><p>293Conductive layer</p><p>113Proliferation Zone</p><p>114Proliferation Zone</p><p>165Embedded electrode plate</p><p>168ring</p><p>189Intermediate dielectric layer</p>

Figure 1 shows an exemplary DRAM cell; Figures 2a-c show an embodiment of the invention for forming a polysilicon gate stack.

Detailed description of the invention

The present invention relates to reliable polysilicon silicide gates with lower sheet resistance. In order to assist the description of the present invention, the description of this text is made with a memory IC. However, the present invention is obviously more extensive and can be applied to general ICs. A description of the DRAM cell is also provided.

Referring to FIG. 1, it shows a trench capacitor type DRAM cell 100. The trench capacitor type DRAM cell is described in, for example, Nesbit et al.<u style="single">A 0.6μm</u>^{<u style="single">2</u>}<u style="single"> 256Mb Trench DRAM Cell With Self-Aligned Buried Strap (BEST)</u>, In IEDM 93-627, it is incorporated into this case for reference. Although a trench capacitor DRAM cell is shown here, the present invention is not limited to this. For example, stacked capacitor DRAM cells can also be used. The array of cells is typically interconnected by word lines and bit lines to form a DRAM IC.

As an example, the DRAM cell 100 includes a trench capacitor 160 formed in the substrate 101. The trench is typically doped and filled with polysilicon 161, which is heavily doped with dopants having a first conductivity, such as n-type. The doped polysilicon is used as the electrode of the capacitor and is called the "storage node". If necessary, a damascene electrode plate 165 doped with dopants of the first conductivity can surround the bottom of the trench. The embedded electrode plate can be used as another electrode of the capacitor. The ring 168 for reducing parasitic leakage current is located at the top of the trench. The one-node dielectric 163 isolates the two electrode plates of the capacitor. A damascene well 170 containing dopants of the first conductivity is provided to connect the damascene electrode plates of the DRAM cells in the array. Above the mosaic well is a well 173 containing a second conductivity dopant such as p-type. The p-well contains a dopant concentration sufficient to form an opposite conductive junction to reduce the vertical leakage current of the transistor 110.

The transistor includes a polysilicon silicide gate stack 112. The gate stack, sometimes called "gate conductor" (GC), is used as the word line in the DRAM array. Because the word line is connected to the capacitor, it is called "active word line". As shown, the gate stack includes a polysilicon layer 120 heavily doped with dopants. In one embodiment, the polysilicon layer 120 is heavily doped with p dopants. Boron (B) or arsenic (As) dopants can also be used. In order to maintain low sheet resistance, the dopant concentration of polysilicon should be high enough. An inherent polysilicon layer 121 and a metal silicide layer 122 are provided on the heavily doped polysilicon 120. The inherent polysilicon layer serves as a buffer layer to prevent a metal-rich interface from being formed between the silicide and the heavily doped polysilicon layer. Although the doping from the heavily doped polysilicon layer will diffuse into the inherent polysilicon during subsequent thermal processing, the polysilicon system is original and unchanged during the initial deposition of the metal silicide layer. Above the metal silicide layer is a nitride layer such as an etch stop layer.

The heavily doped diffusion regions 113 and 114 are arranged beside the gate. The diffusion region contains dopants with the same conductivity as the polysilicon layer and opposite to the well 173. For example, the diffusion region is heavily doped with n-type dopants. The diffusion regions 113 and 114 are respectively called "drain" or "source" according to the direction of the current. The terms "drain" and "source" used here are interchangeable. The connection between the transistor and the capacitor is achieved through the diffusion region 125, which is called "node diffusion".

A shallow trench isolation (STI) 180 is provided to isolate the DRAM cell from other cells or devices. As shown, a character line 120 is formed on the trench and separated by STI. The word line 120 is called a "passing word line" because it is not electrically connected to the DRAM cell. This structure is called a folded bit line structure. Other structures containing windows or folding openings can also be used.

An intermediate dielectric layer 189 is formed on the character line. A conductive layer representing a bit line is formed on the intermediate dielectric layer. The bit line contact window 186 is provided in the intermediate dielectric layer so that the source electrode 113 is in contact with the bit line 190.

As mentioned above, the use of a polysilicon buffer layer between the heavily doped polysilicon layer and the silicide layer will increase the thickness of the gate stack. This increased thickness is undesirable because it will produce higher aspect ratio components and make processing difficult.

Figures 2a-c show the method of forming a polysilicon silicide gate stack according to the present invention. Refer to Figure 2a, which represents a part of the substrate surface of the IC. The IC is a memory such as random access memory (RAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), static random access memory (SRAM) or read-only memory (ROM) IC. In addition, the IC can be a logic device such as a programmable logic array (PLA), a special application IC (ASIC), a combined dynamic random access memory-logic IC (embedded DRAM), or any other logic device.

Typically, a plurality of ICs are manufactured in parallel on a semiconductor substrate such as a silicon wafer. After the processing is completed, the wafer will be diced to divide the IC into a plurality of individual wafers. The chip will then be packaged for use in final products, such as computer systems, office equipment including photocopiers, printers, and fax systems, cellular phones, personal digital assistant systems (PDAs), and other consumer products such as electronic products.

The substrate 201 may be, for example, a silicon wafer. Other substrates such as silicon on insulator (SOI), silicon on sapphire (SOS), germanium, gallium arsenide, and III-V group compounds can also be used. In one embodiment, the substrate is slightly doped with dopants having the first conductivity. Although the substrate shown does not include other device layers and device elements, it should be understood that the term "substrate" as used herein can be a substrate having one or more device layers and device elements thereon. In one embodiment, the substrate is slightly doped with p-type dopants (p-) such as B. The concentration of B is about 1.5×10¹⁶Atom/cubic centimeter.

The substrate includes, for example, a plurality of trench capacitors (not shown in the figure) formed therein. The trench capacitor may be such as that described in FIG. 1. In one embodiment, the trench capacitor is used as a storage capacitor for an n-channel DRAM cell. The embedded n-type well is used to connect the n-type embedded electrode plates of the capacitor together. The p-type well is arranged on the n-channel DRAM access transistor. The concentration of p-type well is about 5×10¹⁷To 8×10¹⁷ cm³. In addition, n-type wells are provided in p-channel transistors, such as those used to support circuits. Other diffusion regions are arranged in the substrate as required.

In this processing stage, the substrate includes a flat surface 210. A sacrificial oxide layer (not shown in the figure) is formed on the surface. The sacrificial oxide layer is used as a mask oxide for ion implantation to adjust the gate valve voltage (Vt) of the subsequently formed transistor. The Vt adjustment implant system uses techniques such as traditional lithography and masking techniques to selectively implant dopants into the gate channel region. The technique includes depositing a photoresist layer on the mask oxide layer and selectively exposing it with an exposure source and the mask. Depending on whether the user is a positive or negative photoresist, the exposed or unexposed part of the photoresist layer is removed during development to selectively expose the underlying substrate area. Second, implant ions in the exposed area to obtain the desired Vt.

After Vt implantation, the photoresist and mask oxide layer are removed by, for example, wet etching. Next, a thin oxide layer 220 is formed on the surface of the substrate. The oxide layer serves as a gate oxide. In one embodiment, the gate oxide is grown by thermal oxidation. The thickness of the gate oxide is, for example, about 6-10 nm.

A polysilicon layer 230 is deposited on the gate oxide. The polysilicon layer is deposited by, for example, chemical vapor deposition (CVD). In addition, an amorphous silicon layer can be used instead of polysilicon. The polysilicon layer typically contains dopants to reduce its resistance. The dopant contains, for example, phosphorus (P), arsenic (As), or boron (B). The polysilicon layer can be doped during or after its formation. The mixing of dopants during the CVD process is known as instant doping.

In one embodiment, the polysilicon layer is doped with P dopants. The polysilicon system is instantly doped. The concentration of P dopant is about 10¹⁹To 5×10²¹Atom/cm3, preferably about 10²⁰To 10²¹Atom/cubic centimeter, and more preferably about 5×10²⁰Atom/cubic centimeter.

The polysilicon system uses SiH₄As the precursor of silicon and use PH₃As a P dopant source, it is deposited in a CVD reactor at a temperature of about 600-650° C. and a pressure of about 100-180 Torr. The thickness of the doped polysilicon is about 10-200 nm, preferably about 40-150 nm, and more preferably about 50-100 nm. Of course, the actual thickness can vary depending on different factors. For example, the minimum thickness is required based on the work function, and it depends on the design requirements. In some cases, the minimum thickness may be about 10 nm.

Referring to FIG. 2b, a metal silicide layer 240 is deposited on the polysilicon layer 230. The metal silicide contains materials such as tungsten silicide (WSi_x), molybdenum silicide (MoSi_x), tantalum silicide (TaSi_x), titanium silicide (TiSi_x), cobalt silicide (CoSi_x) Or its metal silicide. According to an embodiment, the metal silicide contains p- or n-type dopants. The dopant contains, for example, phosphorus (P), arsenic (As), or boron (B). The dopant type is the same as that of the doped polysilicon layer 230. The typical concentration of the metal silicide layer is about 10¹⁹To 5×10²¹Atom/cm3, preferably about 10²⁰To 10²¹Atom/cubic centimeter, and more preferably about 5×10²⁰Atom/cubic centimeter. Instant doping of the metal silicide will virtually increase the tendency to deposit in an amorphous state. Depositing the metal silicide in an amorphous state will increase the grain size of the film, thereby reducing its resistance.

The instant doped metal silicide is deposited by traditional CVD technology used to deposit undoped metal silicide films. The dopant source is included in the CVD process to provide instant doping of the deposited film.

In one embodiment, the doped metal silicide layer includes P-doped WSi_x. The WSi_xThe line is doped instantly. The concentration of P dopant is about 10¹⁹To 5×10²¹Atom/cm3, preferably about 10²⁰To 10²¹Atom/cubic centimeter, and more preferably about 5×10²⁰Atom/cubic centimeter. The thickness of the doped metal silicide is about 50-200nm, preferably about 80nm. Of course, the actual thickness can vary depending on the design and parameters.

Traditional W, Si and doped precursors are used to form doped WSi_xmembrane. Traditional Si precursors include such as silane (SiH₄), disilane (Si₂H₆) Or dichlorosilane (SiH₂Cl2); W precursor contains tungsten hexafluoride (WF₆), tungsten hexachloride (WCl₆) Or tungsten hexacarbonyl (W[CO]₆). Phosphine (PH₃Or POCl₄) Is used to provide a source of P dopants. In one embodiment, the PH₃Department was added to WF₆With SiH₄, To form WSi doped with P_xmembrane. These precursors are introduced into a CVD reactor, such as the Centura CVD reactor manufactured by Applied Materials located in Santa Clara, CA. The typical temperature and pressure used in the CVD process are about 450-600°C and about 1-5 Torr, respectively. The temperature is preferably about 550°C, and the pressure is about 1.5 Torr.

Adding dopants to the metal silicide film during deposition will reduce the formation of metal-rich interfaces. Although the mechanism used to reduce the metal-rich interface is not fully understood, it is generally believed that the dopant will increase the efficiency of the metal reaction. For example, WF₆The efficiency of the reaction is improved. Because dopants are mixed in during the deposition process, WF₆The efficiency of the reaction has been improved. Therefore, W is in the whole WSi_xThe distribution in the film is quite uniform, thus avoiding the formation of metal-rich interfaces.

The ability to deposit a metal silicide film on a large number of doped layers without the formation of a metal-rich interface will make the deposition of a metal silicide film on a large number of doped layers no longer require an inherent polysilicon cover layer. This system is particularly advantageous, especially for smaller base criteria, because it will form a gate stack with a lower aspect ratio. In addition, lower resistance can also be obtained, thereby increasing device performance.

Furthermore, because a doped silicide layer is used, the polysilicon layer can be free of doping. An undoped amorphous silicon can be used instead of polysilicon. The thickness of the undoped polysilicon or amorphous silicon may be, for example, about 20-50 nm.

Exposure to heat during subsequent processing will cause dopants in the metal silicide and polysilicon layer to diffuse. If necessary, annealing can be performed to diffuse the dopants in the layer. The annealing system is designed to improve or optimize the properties of the film. The annealing is performed at a temperature such as about normal pressure and at a temperature of about 1000°C. The annealing atmosphere contains such as oxygen (O₂), argon (Ar) or nitrogen (N₂). In the case where the dopant concentration contained in the polysilicon layer is less than that of the silicide layer, annealing will increase the dopant concentration in the polysilicon layer. By providing a doped silicide material as a dopant source, the polysilicon layer can be formed with a dopant concentration lower than the dopant concentration formed by the metal-rich interface. The polysilicon layer of the gate stack can therefore contain a higher dopant concentration without increasing the thickness, so as to avoid the formation of a metal-rich interface. As a result, a reliable gate stack with low sheet resistance is provided.

An etching stop layer is formed on the metal silicide layer for subsequent processing. The etch stop layer includes, for example, silicon nitride.

Referring to FIG. 2c, the gate stack is scribed to form a gate conductor 280. The scribing of the gate conductor is done using traditional lithography and etching techniques. The technique includes depositing a photoresist layer, and selectively exposing the photoresist layer with an exposure source and a mask. Part of the photoresist is removed after development, leaving an unprotected part of the gate stack. The unprotected portion of the gate stack is removed by, for example, reactive ion etching (RIE).

The spacer (not shown in the figure) can be selectively formed on the edge of the gate conductor. After the spacer is formed, dopants are implanted to form a diffusion region adjacent to the transistor gate. The spacer will limit the upward diffusion of the diffusion zone, which will reduce the overlap capacitance.

A nitride layer 288 is deposited on the surface of the substrate to serve as a barrier for flowing ions and as an etch barrier during the formation of borderless bit line contacts. A dielectric layer 290 is formed on the device structure to provide insulation between the conductive layer 293 and the gate conductor. The dielectric layer also serves as a protective layer to isolate the device structure from impurities, moisture, and scratches. The dielectric layer includes phosphorous silicate such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG).

Contacts 291 are formed in the dielectric layer to provide an interconnection between the conductive layer and the conductive region 285 below. This conductive layer represents a bit line such as a DRAM wafer.

Although the present invention has been specifically disclosed and explained with reference to different embodiments, those skilled in the art will understand that the present invention can be improved and modified without departing from the scope of the present invention. Therefore, the scope of the present invention is not determined by referring to the above description, but by referring to the scope of the attached patent application and the scope of its equivalents.