Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits

Gas immersion laser toughening method suitable for manufacturing small-size integrated circuits

The present invention relates to the manufacture of integrated circuits (IC), and more particularly to the manufacture of ICs including metal oxide semiconductor field-effect transistors (MOSFETs) using shallow junction formation technology.

Incorporated herein by reference is US Patent Application 08/792,107 filed on January 31, 1997 and attributed to the assignee of this application. The present invention and the aforementioned patent application are about alternative solutions to the problems in the manufacture of MOSFETs (such as CMOS field effect transistors) whose gate length is reduced from 0.25 μm to only 0.18 μm. For 0.18μm CMOS technology, according to "The National Technical Roadmap for Semiconductors" (1995) of the Semiconductor Industry Association, these junction depths are highlighted by less than 80 nm.

The first step of each of these alternative solutions is to amorphize the selected surface layer of the crystalline silicon of each MOSFET to the selected depth. However, the remaining steps of each of these alternative solutions are different from each other.

In the example of the solution disclosed in the aforementioned patent application, the selected amount of doping material is deposited as a thin film on the surface of the selected surface layer of amorphous silicon, and then at least a part of the amorphous silicon is selected The surface layer is temporarily heated, using the conventional projected gas immersion laser doping (P-GILD), for a period of time to reach a temperature sufficient to melt amorphous silicon but not enough to melt crystalline silicon (due to the melting temperature of amorphous silicon It is substantially lower than crystalline silicon). P-GILD is a fairly new technology for doping silicon in this art. It eliminates as many as 11 steps in the current process and can cover a wide range of doping concentrations to produce very shallow, well-shaped doped regions. . As a revolutionary solution for merging the precise location of impurities in silicon, P-GILD eliminates the need to build a mask on the wafer to define the doped area before implantation. According to the content of the aforementioned patent application, the doping depth (and thus the depth of the junction formed in the selected surface layer) is completely determined by the depth of the molten amorphous selected surface layer. After a certain period of heating time is completed, the silicon melted by the heated part is allowed to cool, thereby causing the recrystallization of the silicon of the selected surface layer. Eventually, the recrystallized silicon of the selected surface layer will be toughened.

As is known, amorphous implants produce oversaturation of point defects. During toughening, the injection of point defects leads to the accumulation of expanded defects. Usually, a strict toughening temperature is required to continue applying the traditional rapid heat treatment for a selected time (for example, 1050°C for 10 seconds) to make the expanded defect toughening disappear. However, the laser melting of amorphous silicon for P-GILD doping operation inherently provides some toughness. Moreover, due to the few point defects that occur after laser processing, the junction is unlikely to move much due to this thermal cycle. Therefore, as speculated in the aforementioned patent application, the junction after laser toughening does not require any additional toughening. However, as inferred in the aforementioned patent application, the exact degree of diffusion after laser toughening needs to be experimentally determined in order to determine whether additional toughening is required.

The solution provided by the present invention utilizes ion implantation of dopants in at least a part of the selected amorphous surface layer of silicon, and then the surface layer of silicon is treated with laser thermal toughening (LTA ) Temporarily heating for a period of time to reach a temperature sufficient to melt amorphous silicon but not enough to melt crystalline silicon (because the melting temperature of amorphous silicon is substantially lower than that of crystalline silicon). After the heating time is completed, the silicon melted by the heated part is allowed to cool, thereby causing the recrystallization of the silicon on the selected surface layer of this part.

Although the LTA program is similar to the P-GILD program in some aspects, the LTA program is significantly different from the P-GILD program in other aspects. In both procedures, selected areas of the silicon wafer are immersed in gas, and high-power projected laser radiation is used to heat the immersed gas and those specific areas of the wafer surface that are then irradiated by the radiation. However, the immersion gas used in the P-GILD process is an active gas including vaporized dopants, while the immersion gas used in the LTA process is a relatively inert gas, such as nitrogen. Moreover, in the P-GILD process, the resolution of the projection lens must be high enough to correctly map a group of separated mesh patterns on the clearly separated regions of the corresponding group in the doping of the silicon wafer. . However, in the LTA process, the resolution capability of the projection lens (which must only be sufficient to fill the entire selected area of the silicon wafer with irradiation radiation) is significantly lower than the high resolution capability of the projection lens required by the P-GILD process . Therefore, it is obvious that the projection lens suitable for the LTA program is simpler and lower in cost than the projection lens suitable for the P-GILD program. However, in order to use the LTA process when manufacturing MOSFETs using shallow junction formation technology, the process margin must be large enough to account for changes in laser brightness energy. With the correct selection of the laser and the spatial homogenization of the laser brightness, this condition can be met.

Nonetheless, in the manufacture of MOSFETs using shallow junctions, problems arise when the LTA process implants dopants in the amorphous silicon layer and then is directly applied to the surface of the silicon wafer. These problems are due to the fact that the surface of the silicon wafer is not a uniform absorber of incident radiation. This non-uniformity results in a geometric change of the melting threshold and offset of the shallow junction MOSFET being manufactured for the selected area to which the radiation flows. This shift in the melting threshold introduces too much variability for the LTA procedure to be unusable as known.

The present invention focuses on the shortcoming of the offset of the melting threshold, so that the LTA process is manufacturable when manufacturing a large number of shallow junction MOSFETs, which are separated from each other by substantially transparent isolation elements.

An improved method is disclosed to fabricate at least a part of the source and drain junctions of a plurality of separated MOSFETs on a selected area of a surface layer of a substrate. The selected area includes an isolation element arranged between adjacent crystalline silicon materials of a plurality of manufactured MOSFETs, and is composed of a first selected material that is substantially transparent to the selected-wavelength laser radiation. One of the steps in the foregoing method includes amorphizing the surface layer of the crystalline silicon material of a plurality of manufactured MOSFETs to a selected depth. The improvement in the aforementioned method further includes the following steps: before or after the amorphization step, the silicon surface layer of a plurality of n-channel or p-channel MOSFETs to be manufactured is doped with an appropriate form of ion implantation at the selected dose. Impurities; depositing at least one layer of a second selected material of a first selected thickness over the entire selected area of the surface layer of the substrate, the second selected material (1) of this layer is an absorber for the selected wavelength laser radiation incident on it ; (2) Have a higher melting temperature than crystalline silicon; and (3) Have a surface at the exposure position relative to the incident selected wavelength laser; and then use the selected value of the selected wavelength to be substantially uniform The laser radiation of energy fills the entire selected area of the surface of the second selected material of the layer, and the selected value is used to cause the silicon under the selected area to be heated enough to melt amorphous silicon but not enough to melt crystals The temperature of silicon.

During cooling, the molten silicon recrystallizes, thus ensuring that the depth of a certain portion of the source and drain junctions of a plurality of separated MOSFETs is completely determined by the selected depth of the amorphous surface layer.

<p>100Silicone substrate</p><p>102Isolation element</p><p>104a, 104bComplementary MOSFET</p><p>106an type well</p><p>106bp type well</p><p>108ap⁺Source</p><p>108bn⁺Source</p><p>110ap⁺Dip pole</p><p>110bn⁺Dip pole</p><p>112Gate polysilicon</p><p>114SiO₂Thin layer</p><p>116Side wall spacer</p><p>117Silicide electrical contact</p><p>118Extension</p><p>200, 202a, 202b, 204a, 204bAmorphous Silicon</p><p>206High-power laser radiation</p><p>208a, 208b, 208ccontour element</p><p>310SiO₂Thin layer</p><p>312Tantalum nitride thick layer</p>

Figure 1 (which is the same as Figure 1 of the aforementioned patent application) schematically shows the structure of n-channel and p-channel FETs that have been manufactured according to modern silicon CMOS technology; Figure 2 schematically shows the structure that will be based on The structure of the two FETs in Fig. 1 produced by the method steps of the present invention. In the manufacturing stage, this happens exactly when (1) the FET isolation element is manufactured, (2) the doping of the FET well, and (3) the silicon surface layer of the FET. Amorphization and (4) After the doping of the source of the FET has been completed; Figure 2a will be used to describe the melting threshold offset heating problem. If the surface of the structure in Figure 2 is directly irradiated according to the LTA procedure, this will Occurs; Figure 2b illustrates SiO₂The variability of reflectivity is a function of thickness, compared to SiO₂The consistency of reflectivity is a function of thickness; Fig. 3 schematically shows the construction of two FETs manufactured according to the method steps of the present invention in Fig. 1 at a later manufacturing stage shown in Fig. 2; and Fig. 3a The figure will be used to describe the heating effect of the surface of the structure in figure 3 being directly irradiated according to the LTA procedure.

Refer to Figure 1, showing two complementary CMOS structures, including a silicon substrate 100, an isolation element 102 (made of SiO₂Composition) and complementary FETs 104a and 104b. The structure of complementary FET 104a and 104b is different in that FET 104a contains n-type wells 106a, p⁺Source 108a and p⁺Drain 110a, and FET 104b contains p-type well 106b, n⁺Source 108b and n⁺Drain 110b. In all other respects, the construction of the complementary MOSFETs 104a and 104b is similar. In particular, the two complementary MOSFETs 104a and 104b include (1) gate polysilicon 112, which is made of SiO₂The thin layer 114 is isolated from the well of the MOSFET, (2) sidewall spacer 116, the gate polysilicon 112 supporting each MOSFET 104a and 104b, (3) the silicide electrical contact 117, located between each complementary MOSFET 104a and 104b the top of its individual gate polysilicon, source and drain, and (4) lightly doped extension 118, connecting the source and drain of each complementary MOSFET 104a and 104b to the channel area under the gate polysilicon .

It is obvious from Figure 1 that the shallowest junction is the lightly doped extension 118, which connects the deep source and drain to the gate polysilicon channel. To prevent DIBL and penetration caused by the drain electrode, the extension 118 is necessary.

In both the method disclosed in the aforementioned patent application and the method of the present invention, the earliest step for manufacturing the complementary MOSFET 104a and 104b of Figure 1 involves the doping of the silicon substrate 100 to form each well 106a and 106b, followed by In SiO₂Fabrication of the gate polysilicon 112 above the thin layer 114. As shown in Figure 2, the next step of both the manufacturing method disclosed in the aforementioned patent application and the method of the present invention includes amorphization. Figure 1 includes the upper polycrystalline silicon of the gate polycrystalline silicon 112 in the MOSFET being manufactured. Those areas of the crystalline silicon surface layers 202a, 202b, 204a, and 204b above the layer 200 and the well 106 (these surface layers 202a, 202b, 204a, and 204b will be included in the source and drain electrodes 108a, 108b of the MOSFET being manufactured , 110a and 110b) to reach the desired extremely shallow depth of the extension 118 to be manufactured. Amorphization can be achieved by ion implantation of heavy atoms such as argon, silicon or germanium. However, germanium would be preferable because it is a heavy atom that requires a low dose to amorphize silicon, can produce steep amorphous-crystalline junctions, and is isoelectronic in the silicon lattice.

In particular, as shown in FIG. 2, the surface layers 202a, 202b, 204a, and 204b on the side of the gate polysilicon 112 to be amorphous will extend to the isolation element 102 in each direction. For example, if the extremely shallow depth required for these layers to be amorphous is actually 30 nm (which is less than 80 nm), 2×10¹⁴A dose of atom/cm² to achieve the required depth of amorphization of 30 nm. 2×10¹⁴The implantation of germanium with a dose of 20 thousand electron volts at an atom/cm² square achieves the desired depth of amorphization of layers 202 and 204 at 30 nm. This implantation condition can be easily obtained by using an existing high-current implanter. However, depending on the desired amorphous depth, the implant dose range is 1×10¹³Atom/cm2 and 1×10¹⁶Between atoms/cm², and the implant energy range is between 5 thousand electron volts and 400 thousand electron volts.

In the next step of the method of the present invention, the amorphous layers 202a and 204a have p⁺The dose of dopant (for example, boron) ions are distributed therein, and the layers 202b and 204b have n⁺The dose of dopant (such as phosphorus or arsenic) ions is distributed therein. The typical dose for lightly doped extensions is 5×10¹⁴Atom/cm2. The implantation energies of boron, phosphorus, and arsenic are typically 250, 2000, and 5000 eV, respectively. Generally, the ion implantation dose can be in the range of 10¹³To 10¹⁶The range of implant energy can be between 10 and 100,000 electron volts.

Now refer to Figure 2a, which shows the melting threshold offset heating problem. This problem will occur if the surface of the structure in Figure 2 is to be directly heated according to the LTA procedure. In Figure 2a, the structure in Figure 2 is indicated by a broken line. The entire upper surface of this structure is irradiated with substantially uniform high-power laser radiation 206. The applicant has used a pulsed xenon chloride excimer laser operating at a wavelength of 308 nm to deliver radiation 206, although other forms of excimer lasers can be used (such as 193 nm argon fluoride lasers, 248 nm fluorine Krypton laser or 351 nm xenon fluoride laser) instead. When the fluence range of laser irradiation extends from 0.05 joules per square centimeter to 1.0 joules per square centimeter, it is most likely to be sufficient to heat amorphous silicon to its melting temperature, but not enough to heat crystalline silicon to its melting temperature. It is 0.6 joules per square centimeter.

It should be noted that the isolation element 102 is made of SiO₂The composition, this is actually transparent to the incident 308 nm radiation. Depending on the oxide thickness, thermally incident light is selectively absorbed in the silicon under the oxide isolation element or reflected by the isolation element. This is illustrated graphically in Figure 2b, which shows that the reflectivity of the silicon oxide layer above the silicon is a function of the thickness of the oxide layer. The unreflected light is absorbed by the silicon below. Since the reflectivity of uncovered silicon to incident 308 nm radiation is constant 0.6, an oxide layer of the wrong thickness can almost double the absorption. Suppose SiO₂The isolation element 102 is completely heated by the high-power laser radiation 206 moving through the silicon below the optimal thickness for absorption, and can be melted, resulting in undesired changes in the isolation structure. The solid line contour in Figure 2a contains (1) the thick contour element 208a, which represents a considerable amount of heat absorbed by the upper surface of the silicon perpendicular to the directly incident high-power laser radiation 206, and (2) the thick contour Element 208b represents the heat energy transferred from the isolation element with the best absorption thickness to it.₂The relatively large amount of thermal energy absorbed in the silicon surfaces contacted by the isolation element bottom 102, and (3) the thin profile element 208c, represents a relatively small amount of thermal energy absorbed in those silicon surfaces that are almost parallel to the incident radiation.

Although the height and length of the silicon gate are kept to strict tolerances, SiO₂Large variations in the thickness of the isolation element 102 are common and expected. Therefore, with SiO₂The heat of the silicon surface contacted by the bottom of the isolation element 102 cannot be controlled. The high heat in the isolation region can cause undesired diffusion of dopants in the well and reduce the thermal energy required to melt the source/drain and gate amorphous regions. The degree of threshold reduction depends on the source/drain region and SiO₂It depends on the proximity of the isolation element 102 and the thickness of the oxide isolation element. This thickness determines the difference between the incident 308 nm radiation and the SiO₂The amount absorbed in the silicon contacted by the isolation element 102. This causes the aforementioned melting threshold offset heating problem, in which the device geometry and processing conditions strongly affect the amount of thermal energy required to generate the desired melting depth on the surface of the structure in Figure 2.

The applicant's solution to the aforementioned melting threshold offset heating problem is to cover the structure shown in Figure 2 with an opaque deposition layer of materials such as various metals, metal oxides, metal nitrides, metal carbides, and carbon. The entire upper surface makes the surface absorption of radiation uniform. This layer is a high absorber for all 308 nm radiation incident on it and has a higher melting temperature than silicon. In the preferred embodiment of the present invention shown in Figure 3, the opaque layer of the selected material contains tantalum nitride because of its low reflectivity, high absorption and compatibility with silicon processing. Other suitable materials for the opaque layer are tungsten and tantalum. More specifically, in the preferred embodiment shown in Figure 3, SiO₂The upper surface of the isolation element 102 and the upper surface of the amorphous silicon 200, 202a, 202b, 204a, 204b are first treated with SiO₂Relatively thin layer 310 (15 nm) covered, and then this SiO₂The thin layer is covered by a relatively thick layer 312 (30 nm) of tantalum nitride. Generally, SiO₂The thickness of the layer can range between 5 nm and 50 nm, and the thickness of the tantalum nitride layer is preferably sufficient to absorb all 308 nm radiation incident thereon and can range between 20 nm and 150 nm. Generally, the thickness of the opaque deposition layer of the material should be at least sufficient to cause the material to absorb more than 50% of all laser radiation of the selected wavelength incident on it. In any case, SiO is located between the amorphous silicon and tantalum nitride layer₂The necessity of the layer has resulted in the prevention of silicon contamination that would be caused if the tantalum nitride were in direct contact with the silicon surface.

As is well known, amorphous silicon has a lower thermal conductivity of factor 10 than crystalline silicon, a lower melting temperature of 300°C, and a 30% lower reflectivity. Referring to Figure 3a, the high-power laser radiation 206 incident on the upper surface of the superabsorbent tantalum nitride layer 312 is sufficient to heat the layer 312 to a relatively high temperature. When the heat is passed through the thin SiO₂When the layer 310 is conducted to the upper surface of the amorphous silicon 200, 202a, 202b, 204a, 204b, the heat is enough to melt the amorphous silicon 200, 202a, 202b, 204a, 204b, but not enough to melt under the amorphous silicon. Crystalline silicon under regions 202a, 202b, 204a, and 204b in Figure 3a.

SiO₂It is a very poor thermal conductor and does not directly absorb incident radiation. Therefore, as indicated by the thin solid line 308 in Figure 3a, when the high-power laser radiation 206 is incident on the upper surface of the tantalum nitride layer 312, the silicon in contact with the side of the isolation element 102 is only negligibly heated.

After the melted amorphous silicon layer is allowed to cool, thereby causing recrystallization of this layer, the tantalum nitride layer 312 is stripped off.

The steps described so far in the manufacturing method of the present invention including the LTA procedures shown in Figures 3 and 3a are used to form the very shallow (preferably 30 nm depth) junction of the extension 118. However, similar steps can then be used to fabricate the deep source and drain regions of the CMOSFET shown in Figure 1. In particular, with the manufacture of the extremely shallow extension 118 junction, the sidewall spacer 116 is manufactured. Thereafter, each deep source and drain region between each sidewall spacer 116 and the isolation element 102 is re-amorphized to a desired depth deeper than the original amorphization. This can be done with higher energy (e.g. 40 thousand electron volts) and higher doses (e.g. 6×10¹⁴Atom/cm²) germanium implant to complete. With this re-amorphization, additional doses of dopants are added to the deep source and drain by ion implantation, preferably 1×10¹⁵The total dose of atom/cm2. Since the final deep source and deep junction depths are individually controlled by their amorphization depths, the implantation energy of boron, phosphorus, and arsenic is maintained at 250, 2000, and 5000 eV, respectively. The amorphization step can be performed before or after the dopant implantation step. The final step of fabricating deep source and deep junctions involves reusing the LTA process, which involves depositing a layer of tantalum nitride, exposing its upper surface to 308 nm radiation that effectively melts only amorphous silicon, and afterwards The tantalum nitride layer is stripped so that the source and drain junctions are thus formed to the desired depth individually determined by the depth of the molten silicon of the manufactured CMOSFET. The desired depth is preferably 120 nm, and the desired depth range is between 80 nm and 200 nm.

In the method of the preferred embodiment of the present invention described above, since the very shallow junctions that have been manufactured extend to the sidewall spacer 116 in all directions, the manufacture of the deep source and drain involves the manufactured poles. Amorphization of shallow (ie less than 150 nm depth) junctions. However, it should be understood that the extension of the very shallow junction will be limited to only the location of the extension, so the location of the deep source and drain is not included. In this case, the amorphization of the source and drain locations is independent of the amorphization of the extension portion, so the amorphization of the source and drain locations will occur before or after the amorphization of the extension portion. . Furthermore, the present invention can be used to manufacture only the extension of the MOSFET, or only the deep source and drain of the MOSFET, but not both.

In a nutshell, depositing an absorbing layer on the surface of the silicon wafer ensures consistent absorption of laser radiation across the surface of the wafer. This eliminates the unpredictability that would occur if absorption of laser radiation occurs in the isolation element. Furthermore, the heating source is moved to the surface of the wafer, so there is no heat trapping due to heat absorption in the silicon adjacent to the isolation element. Therefore, the present invention makes the LTA process practical to manufacture a large number of isolated, separated, very shallow junction MOSFETs on a selected area of a silicon wafer.