Reduced voltage input/reduced voltage output tri-state buffers and methods therefor

Three-state buffer and method for reducing voltage input / voltage output

The present invention relates to a snubber circuit. More particularly, the present invention relates to a buffer circuit capable of receiving a reduced voltage input signal and outputting a signal with a reduced voltage to drive an output.

In some circuits or integrated circuits, a buffer circuit can be used to receive an input signal and originate or collect enough current to drive an output conductor (such as a bus conductor), or the input gate of another circuit in response to the signal Enter. A well-known type of snubber circuit is a tri-state snubber circuit. The tri-state buffer circuit has an output terminal, which is tri-state, high or low. This ability to tri-state the snubber circuit is particularly useful when multiple snubber circuits are coupled to the same load, as this allows those snubber circuits that are not in an active state to drive the buses to be decoupled from the buses, so as to avoid Signal competition on the bus.

For ease of discussion, FIG. 1 illustrates a simplified conventional three-phase inverting buffer circuit 100, which includes four transistors 102, 104, 106, and 108 in series. A p-type field effect transistor (p-FET) 102 is coupled to surround V_DD, And can only conduct when the enable signal is high. Please note that unless stated otherwise, all transistors herein are field effect transistors (FETS). The N-type transistor 108 is coupled to ground and is also conductive only when the enable signal is high (ie, when the enable N signal is low). When the enable signal is low, the transistors 102 and 108 are turned off, thereby causing the three states of the output.

When the input signal is high and the enable signal is high, n-FET 106 and n-FET 108 will conduct and pull the output to ground. At the same time, p-FET 104 is turned off to connect the output to V_DDDecoupling. Conversely, when the input signal is low and the enable signal is high, p-FETs 102 and 104 will conduct and pull the output to V_DD. At the same time, n-FET 106 is turned off to decouple the output from ground. It can be observed that the output of the inverted three-state buffer circuit 100 is the inverse of its input value.

Although the snubber circuit of Figure 1 has been around for a long time, it has disadvantages. For example, because the tri-state buffer circuit 100 inverts its input, it needs a series connection structure to obtain a non-inverting tri-state buffer circuit. For serial connection, the output of the inverted tri-state buffer circuit 100 can be serially connected to the input of another inverted tri-state buffer circuit 100 to obtain a non-inverted tri-state buffer circuit.

Furthermore, the use of 4 series transistors (eg, series transistors 102, 104, 106, and 108) in the output stage causes a significant price in size. This is because each device in this pull-up or pull-down path must be quite large so that there is sufficient current in this path to pass through these series-connected devices. This is because if these devices are small, the amount of current output by the snubber circuit may be too low, which may cause unacceptable delays when driving the output load to the desired voltage level.

However, the use of a large device increases the capacitive load of the output conductor, which requires a greater amount of power to drive the snubber circuit in order to properly drive the output load. Because the driving buffer circuit can sense the capacitance of the output electrical conductor connected to the load and the capacitance of other three-state buffer circuits.

Another disadvantage of the structure shown in FIG. 1 is that the tri-state buffer circuit 100 is inverted, and generally cannot operate with a tri-state buffer circuit that reduces the voltage input / voltage output. Reduced voltage input means the input voltage is lower than the full V supplied to the chip_DD. In some cases, this reduced voltage may be sufficiently low (eg, 1 volt) to approach the threshold voltage of the transistor (usually 0.7 volts or more). Similarly, a reduced voltage output means that the output voltage is lower than the full V supplied to the chip_DD. Because a reduced voltage signal (ie, the amplitude of the signal is within the reduced voltage range) is useful in reducing circuit power consumption. The inability to invert the tri-state buffer 100 to operate as a voltage-lowering buffer represents a serious disadvantage.

In order to understand the problems encountered in buffering a reduced voltage signal, consider a scenario in which the input of the inverted tri-state buffer 100 is logic high, but is represented by a reduced voltage signal (for example, about 1 volt). In this case, not only the n-FET 106 conducts as expected, but the p-FET 104 can also be turned on slightly, causing a leakage current to pass through the p-FET 104 (from V_DDVia p-FET102). The occurrence of this leakage current reduces the signal on the output of the buffer circuit (and / or greatly increases the power consumption).

FIG. 2 illustrates another prior art tri-state buffer circuit, which is a non-inverting type. However, the non-inverting tri-state buffer circuit 150 was again found to be unable to operate with a buffer circuit with reduced voltage input / reduced voltage output. In order to understand the operation of the non-inverting tri-state buffer circuit 150 and its disadvantages in this regard, consider a situation when the input signal has a complete voltage range (that is, from ground potential to V_DD). When the EN signal is low on line 152, p-FET 130 is turned on to pull node 154 to V_DDAnd the output p-FET 156 is turned off. At the same time, the node 158 becomes high by the operation of the inverter 160. This high node 158 turns n-FET 162 on to pull node 164 low, thereby turning off output n-FET 166. Therefore, when the enable signal EN goes low, the output 168 is decoupled from the rest of the buffer circuit. As can be seen, a low EN signal causes three states of the buffer circuit 150.

When the enable signal EN goes high and the input 170 is high (for example, at V_DD), This high input 170 causes n-FET 172 to conduct. Therefore, the node 164 is pulled to the ground potential, thereby disconnecting the output n-FET 166 and decoupling the output 168 from the ground. At the same time, this high enable signal EN causes the n-FET 174 to also conduct. Therefore, node 154 is pulled low. Note that when input 170 is high, p-FET 176 is turned off, which connects node 154 to V_DDDecoupling. This low node 154 turns on the output p-FET 156 and causes the output 168 to be pulled to V_DD. Therefore, a high input 170 and a high enable signal EN cause the output 168 to go high to V_DD。

Conversely, when the enable signal EN is high and the input 170 is low (eg, about ground potential), this low input 170 causes the n-FET 172 to turn off and decouples the node 164 from ground. This low input 170 also causes the p-FET 176 to turn on. As p-FET 176 is turned on, node 154 is pulled up and output p-FET 156 is turned off, so outputs 168 and V_DDDecoupling. Because n-FET 174 is already turned on (due to the high enable signal EN), node 164 is pulled up when p-FET 176 is conducting, so turning on n-FET 166 pulls output 168 to ground. Therefore, a low input 170 and a high enable signal EN cause the output 168 to go low.

However, the non-inverting tri-state buffer circuit 150 cannot operate when a step-down input signal needs to be conducted to its output. The disadvantage of this conventional technology buffer circuit is due in part to the fact that this input signal is used to control one or more transistor gates. When used in this way, the reduced voltage range of this input signal causes some p-FETs to turn on slightly, even when this signal is logic high. For example, if a high logic state is represented by a reduced voltage signal (e.g. 1V to 2.5V or the entire V_DDThe higher of the range), this high logic input is represented by, for example, having a reduced voltage of 1 volt at input 170.

With a 1 volt n-FET 172 at input 170 will be turned on, but p-FET 176 may also be turned on although slightly turned on. This is because if 2.5V_DDIt is at the source of p-FET 176, and the threshold voltage of p-FET 176 is 0.7V. This 1V at the gate of p-FET 176 may cause the transistor to turn on slightly. In other words, when it should be off, a leakage current flows through the p-FET 176. When both of these transistors are conductive, the power consumption is unduly increased. As transistors 172 and 176 are both turned on, the voltages at nodes 154 and 164 may be unstable and / or not well defined to turn on p-FET 156 and turn off n-FET 166, and output 168 Pull to the desired high logic value.

From the above, it can be found that it is desirable to have a tri-state buffer circuit, and a manufacturing method thereof, which can be used in applications that reduce voltage signals.

In one embodiment, the present invention relates to a tri-state buffer circuit for receiving an input signal at a buffer input node, and transmitting an output signal to the buffer output node in response to a buffer enable signal. The buffer circuit includes an input stage coupled to a buffer input node. This input stage is designed to receive an input signal when the buffer enable signal is enabled. The buffer circuit further includes a level shift stage coupled to the input stage. This level shift stage is configured to output a set of level shift stage control signals in response to an input signal when the buffer enable signal is enabled. The voltage range of the set of level shift stage control signals is higher than the voltage range related to the input signal. The buffer circuit also includes an output stage coupled to the level shift stage. This output stage is designed to output an output signal at the buffer output node in response to the set of level shift stage control signals when the buffer enable signal is enabled. The voltage range of the output signal is lower than the voltage range of the level shift stage control signals. This output stage decouples the buffer output node from the input stage and the level shift stage when the buffer enable signal is disabled.

In another embodiment, the present invention relates to a method for providing an output signal in response to an input signal. This method includes using one of the input stages of the snubber circuit to receive an input signal. This method further includes forming a level shift stage using a buffer circuit and a set of control signals responsive to the input signal. The voltage range of this group of control signals is higher than the voltage range related to the input signal. In addition, an output stage including a buffer circuit is used to output an output signal in response to the set of control signals. The voltage range associated with this output signal is lower than the voltage range of the control signal.

These and other features of the present invention will be described in more detail in the following drawings and detailed description of the present invention.

<p>100 Inverting tri-state buffer circuit</p><p>102,104,106,108Transistors</p><p>130,176p-field effect transistor</p><p>150, 200, 300 three-state buffer circuits</p><p>152line</p><p>154,158,164,316,318nodes</p><p>156 Output p-field effect transistor</p><p>160,324Inverter</p><p>162,172,174n-field effect transistors</p><p>166Output n-field effect transistor</p><p>168 output</p><p>170Enter</p><p>202,302Input Level</p><p>204,304level shift stages</p><p>206,306Output stage</p><p>208Terminal</p><p>308,310Field Effect Transistor</p><p>312,326conductor</p><p>314Buffered Input Node</p><p>334Buffered output</p><p>346,350V_DDpower source</p><p>392NOR gate</p><p>402Conduction gate</p><p>408,410Control signal</p><p>502,806,808Inverter</p><p>504,506,602Output transistor</p><p>702 three-state inverter</p>

The present invention will be better understood through the drawings and the following detailed description, wherein the same reference numerals represent the same structural elements: FIG. 1 shows a simplified conventional inverting tri-state buffer circuit to Facilitate discussion.

FIG. 2 shows a tri-state buffer circuit of another conventional technology, which cannot be used as a buffer circuit for reducing the voltage input / reducing voltage output.

FIG. 3 shows a simplified tri-state buffer circuit according to one embodiment of the present invention, which represents a tri-state buffer circuit capable of passing a reduced voltage signal.

Figure 4 is shown very carefully, and according to one embodiment of the present invention, a tri-state buffer circuit that can pass a reduced voltage signal.

5 to 12 show various alternative designs of the three-state buffer circuit with reduced voltage input / reduced voltage output according to various embodiments of the present invention.

Detailed description of the invention

The invention will be described in detail with reference to several illustrative embodiments as shown in the accompanying drawings. In the following description, numerous specific details are disclosed in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these special details. In other instances, well-known structures and / or process steps have not been described in detail in order to unnecessarily obscure the present invention.

The present invention relates to, in one embodiment, a very effective reduced voltage input / reduced voltage output tri-state buffer circuit for emphasizing an output signal which has a reduced voltage range in response to an input signal that also has a reduced voltage range. . In one embodiment, the innovative reduced voltage input / reduced voltage output tri-state buffer circuit includes an input stage to receive the reduced voltage input signal, and a quasi-shift stage converts the received reduced voltage input signal into an internal bit. The quasi-shift stage control signal has a higher voltage range and is used to control the output stage of the tri-state buffer circuit.

When the tri-state buffer circuit generates a tri-state by disabling the buffer enable signal, it is basically decoupled from the load. When the circuit is not tri-stated, the output stage outputs in response to an internal level shift stage control signal, which is a buffered output signal that is either a logic high or a logic low in the reduced voltage range.

In some cases, this snubber circuit is configured to eliminate the need for an input signal, which has a reduced voltage range to control the transistor gate of the input stage. This is in contrast to the conventional technique of Figs. 1 and 2, where an input signal is used to directly control the transistor gate. In order to control the output stage, the input signal is preferably raised to a higher voltage level using a level shift stage. Therefore, the input signal may have a voltage range that is not substantially larger than the threshold voltage of the transistor, and this fact does not degrade the performance of the buffer circuit.

The features and advantages of the present invention can be better understood by referring to the following drawings. FIG. 3 illustrates a simplified tri-state buffer circuit 200 according to an embodiment of the present invention, which includes an input stage 202, a level shift stage 204, and an output stage 206. As shown, this buffer enable signal is coupled to the input stage 202 to control the transistors therein. It passes the reduced voltage input signal at the terminal 208 to the level shift stage 204. As shown later here, a buffer enable signal is also used in some embodiments to control signal conduction within the level shift stage 204 and / or the output stage 206.

In the level shift stage 204, the transistor therein shifts the received input signal to a higher voltage range to control the gate of the transistor in the output stage 206. This higher voltage control signal allows the transistors in the output stage 206 to be controlled with a higher driving voltage, thus allowing the transistors in the output stage 206 to originate / collect a large amount of current, thus driving the connection faster The load to the buffer output is reduced to a desired voltage level.

FIG. 4 illustrates and details a three-state buffer circuit 300 according to an embodiment of the present invention. It represents a non-inverting tri-state buffer capable of receiving a reduced voltage input and driving the load with its reduced voltage output. The buffer circuit 300 includes an input stage 302, a quasi-shift stage 304, and an output stage 306. The input shift stage 302 includes two field effect transistors (FETs) 308, and 310, whose gates are controlled by a buffer enable signal ENP on the conductor 312. When the buffer enable signal is enabled (ie, when the signal ENp is high), this reduced voltage input signal is received at the buffer input node 314 and is conducted by the field effect transistors 308 and 310 to the nodes 316 and 318.

It should be noted that although FETs 308 and 310 are replaced by low-critical n-FETs in the figure (this low critical characteristic is represented by a circle around the transistor symbol), this is not a necessary condition as long as these input transistors The threshold voltage is lower than the input voltage range. However, for these transistors, it is preferable (but not necessary) to use a low critical transistor. Generally, a low-critical FET may have a lower threshold voltage (for example, about 0.4V to 0.5V) than a normal FET (which may be around 0.6V to 0.7V).

The level shift stage 304 receives the signal from the input stage 302 and moves the received signal to a higher voltage range to control the gates of the FETs 320 and 322 in the output stage 306. Depending on the value of the reduced voltage input signal at the input node 314, the output stage 306 outputs a logic low (V_SS) Or a logic high (reduce the high value of the voltage range, or V here_reduce). Therefore, a buffer circuit with reduced voltage input / reduced voltage output is formed.

Like transistors 310 and 308, output transistors 320 and 322 are represented in the figure by low-critical n-FETs (this low-critical feature is represented by a circle surrounding the transistor symbol). Although low critical transistors are preferred as output transistors for optimal performance. But it is also possible to use a transistor which may have a more typical threshold voltage range.

In order to facilitate further understanding, the operation of the tri-state buffer circuit 300 will now be described in detail. Imagine a situation where the buffer enable signal is disabled to enable the tri-state buffer to enter the tri-state mode. In the circuit of FIG. 4, when the signal ENp on the conductor 312 is low, the tri-state mode is entered. With the low signal ENp, the n-type FETs 308 and 310 are turned off, thereby preventing the signal from being conducted to the level shift stage 304 at the input node 314.

The inverter 324 causes the signal ENc (which is the inverse of the signal ENp) to go high on the conductor 326, so the tri-state inverter 328 is put into a high-impedance state and the output of the tri-state inverter is decoupled from its input. A high signal ENc also turns n-FET 330 on and pulls node 332 low, thereby turning off n-FET 320. Therefore, the buffer output 334 and the voltage source V_reduce336 Decoupling.

The low signal ENp on conductor 312 turns on p-type FET 338, thus pulling node 318 high to turn n-FET 340 on. When FET 340 is conducting, node 342 is pulled to V_SSTherefore, the p-FET 344 of the level shift stage 304 is turned on. When FET 344 is conducting, node 316 is pulled to V_DD(By V_DDVoltage source 346) and turn off p-FET 348, thus connecting node 342 to V_DDDecouple voltage source 350 and keep node 342 at V_SSLevel (this is due to the FET 340 being conductive).

Because node 342 is low and FET 322 is also off, buffer output 334 and V_SSDecoupling. As FETs 320 and 322 are turned off, buffer output 334 and the rest of the buffer circuit, V_reduce, And V_SSDecoupling. In other words, the buffer circuit 300 is tri-stated and decoupled from the load.

When the buffer enable signal is enabled (ie, when the ENp signal of FIG. 4 is high), the buffer circuit 300 is taken out from the tri-state mode. Therefore, the voltage value on the buffer output 334 will be between 0 ~ V_reduceRange in response to the voltage value at the input node 314.

Imagine a situation when the signal ENp is high and a V_SSThe voltage level appears on the input node 314. This high signal ENp causes FETs 308 and 310 to turn on, turning V_SSThe voltage levels are conducted to nodes 318 and 316, respectively. Because FET 310 is conducting, node 316 goes low to turn on FET 348, thereby pulling node 342 to V_DD(By V_DDVoltage source 350). Because ENp is high and its inverted ENc signal is low, the tri-state inverter 328 conducts the value at node 342 to node 332, causing node 332 to go low (because tri-state inverter 328 will output relative to its input Inverted). This low signal ENc turns FET 330 off, thereby connecting node 332 to V_SSDecoupling. Because node 332 is at V_SS, FET 320 is turned off to connect buffered output 334 to V_reduceThe voltage source 336 is decoupled.

Low node 318 (p-FET 338 is turned off by a high ENp signal to ensure node 318 remains low) turns FET 340 off to connect node 342 to V_SSDecouple and ensure that node 342 remains at V_DDLevel (due to the fact that FET348 is conductive). With node 342 at high V_DDLevel, this complete V_DDVoltage is applied to the gate of output FET 322 to allow FET 320 to source current to the load via buffered output 334 and quickly pull buffered output 334 to V_SSVoltage level. Therefore, the presence of the level shift stage 304 allows the gates of the transistors 320 and 322 to be controlled by the control signal, and the complete voltage range is V._SS-V_DD. As can be seen from the above, when the buffer circuit 300 is not in a tri-state, a signal V is input to one of the input nodes 314_SSResulting in an output signal V appearing at the output node 334_SS。

Imagine a situation when the signal ENp is high (that is, the buffer circuit 300 is not in a tri-state) and a V appears on the input node 314_reduceVoltage level. This high signal ENp causes FETs 308 and 310 to turn on, and turns V_reduceThe voltage levels are conducted to nodes 318 and 316, respectively. Because FET 308 is conductive, V_reduceThe voltage level is conducted to node 318, which turns on FET 340 and pulls node 342 to V_SS. When node 342 is pulled to V_SS, p-FET 344 is fully turned on and pulls node 316 to V_DD(By V_DDVoltage source 346). So 316 is at V_DDAlthough the conductivity of FET 310 only causes V_reduceIt is conducted from the input node 314 to the node 316. Because node 316 is at V_DDVoltage, this complete V_DDA voltage is applied to the gate of the p-FET 348 to completely turn off the FET 348. Thus node 342 and V_DDDecouple voltage source 350 and ensure that node 342 stays at V_SSLevel. It should be noticed that the level shift stage 304 also operates to stabilize the voltage at node 342 at V_SSValue to ensure that FET 322 remains completely off, while buffering output 334 and V_SSDecoupling. Otherwise, when the V_reduceWhen being conducted to node 316 by FET 310, FET 348 may be turned on slightly, and the voltage at node 342 is pulled to the desired V_SSAbove the value, thereby reducing its performance and / or causing the buffer circuit to malfunction and / or consume an inappropriate amount of power.

When the signal ENp is high and its inverted signal EN_CWhen low, V at node 342_SSValue causes node 332 to become V_DD(Because the tri-state inverter 328 outputs the inverted value of its input). This low signal ENc also turns off FET 330 and connects node 332 to V_SSDisconnect. With node 332 at high V_DDLevel, this complete V_DDThe voltage is applied to the gate of the output FET 320, which allows the FET 320 to source current to the load via the buffered output 334 and quickly pull the buffered output 334 to V_reduceVoltage level (by v_reduceVoltage source 336). Therefore, the presence of the level shift stage 304 allows the gates of the transistors 320 and 322 to be controlled by a control signal, which has a voltage from V_SSTo V_DDThe complete voltage range. Therefore, it can be observed from the above description that when the buffer circuit 300 is not in a tri-state, one of the V on the input node 314_reduceThe input signal will cause a V to appear at the output node 334_reduceoutput signal.

Please note that although the buffer circuit 300 is designed as a non-inverting tri-state buffer circuit, this is not necessary. Therefore, the present invention does not need to be limited to the inverting (or non-inverting) features of the tri-state buffer circuit with reduced voltage input / reduced voltage output.

By using the full voltage range (V_SS-V_DD) Control signals to control the gates of output FETs 320 and 322, and obtain a higher exceeding drive voltage to turn these FETs on or off. If this reduced voltage V_reduceUsed to control the gates of these output FETs, these FETs must be larger in order to source / sink the same amount of current in the same amount of time. Because the present invention uses a voltage_SS-V_DD) Control signals to control the gates of the output FETs 320 and 322. These FETs can be made smaller, reducing the space used on the chip.

Reducing the size of the output FET also reduces the capacitive load connected to the snubber circuit. This is advantageous in terms of application, where multiple buffer circuits are used to enhance the signal on a common bus conductor, and multiple buffer circuit output stages can be coupled to the common bus. By reducing the size and capacitance associated with the output FET of the output stage in each snubber circuit, less capacitive load is presented in the snubber circuit that actually drives this bus conductor. With a reduced capacitive load, its potential and power consumption are advantageously reduced.

Figures 5 to 12 describe various alternative embodiments showing various exemplary ways in which an input stage, a level shift stage, and / or an output stage can be designed. In each of these figures, a level shift stage is used to enhance the reduced voltage input signal into a control signal with a larger voltage range to control the output transistor in the output stage. This output transistor is at V_reduceWith V_SSThey are connected in series to output signals within a reduced voltage range. With the higher voltage control signal from the level shift stage, these output transistors are turned on and off. These transistors can advantageously source or pool large amounts of current and drive the load with reduced potential.

In Figure 5, this level shift stage is performed by a NOR gate 392 instead of a tri-state inverter as in the case of Figure 4. In FIG. 6, a conductive gate 402 is used instead of a level shift stage. Conduction gate 402 operates to conduct voltage between nodes 404 and 406 in response to control signals 408 and 410. The level shift stage includes conductive gates 402, transistors 412, 414, and 416 to ensure that node 404 remains low when a logic high signal with a reduced voltage (e.g., 1 volt) appears at the buffered input. The rest of the buffer of Figure 6 operates in a manner substantially similar to the buffer of Figure 4. As a result of this disclosure, the operation of the buffer of Fig. 6 can be easily understood by those skilled in the art.

In Figure 7, an inverter 502 is used in the level shift stage to provide_SSWith V_DDThe control signal of the voltage range between them is given to the output transistor. It shows that two inverters are coupled to the gate of transistor 504 to source enough current to properly control transistor 504. However, they can be omitted if this buffer enable signal can adequately control the transistor 504. There are three output transistors in the output stage, where transistor 504 acts to quickly turn V when the signal ENp is low._reduceThe voltage source is decoupled from the output. However, as an offset, each of the output transistors 504 and 506 may need to be larger to reduce the voltage at V._reduceSeries resistance between voltage source and output. This larger transistor 506 can cause a higher capacitive load, especially when multiple tri-state buffers are connected to the same output. In Figure 8, the output transistor 602 is added to ensure that when ENp signal is low,_SSDecoupled from the output. Again, this offset causes larger transistors 602 and 604 to overcome the series resistance. The rest of the buffers of Figures 7 and 8 operate in a manner substantially similar to the buffers of Figure 4. Because of this disclosure, the operation of these buffers can be easily understood by those skilled in the art.

In Figure 9, a three-state inverter 702 is used in the level shift stage. The tri-state inverter 702 operates in a similar manner as the tri-state inverter 328 of FIG. 4. In Figure 10, the transistors 802 and 804 in the output stage are coupled to the signal ENpx (generated by the inverters 806 and 808 of the level shift stage) to facilitate the output and V_SSAnd V_reduceQuickly disconnect. However, the four series transistors present in the output stage may require larger devices to overcome the series resistance. In Figure 11, the output and V_SSThe unlinking is performed in the same manner as in the buffer of FIG. 4. Output vs. V_reduceDecoupling is done by transistor 902, but its possible cost is that larger devices need to be used for transistors 902 and 904. In Figure 12, the output and V_reduceThe decoupling is performed in the same manner as used in the buffer of FIG. 4. Output vs. V_SSThe decoupling is done by transistor 1002, but its possible cost is that larger devices need to be used for transistors 1002 and 1004. The remaining buffers of FIGS. 9 to 12 operate in a manner substantially similar to the buffers of FIG. 4. And the operation of these buffers can be easily understood by those skilled in the art because of the rest of this disclosure.

Although the present invention has been described by way of several illustrated embodiments, modifications, transformation combinations, and equivalents are also within the scope of the present invention. It should be noted that there are many alternative ways to implement the apparatus and method of the present invention. Therefore, the scope of patent application attached below can be considered to include all these modifications, transformation combinations, and equivalents, and belongs to the spirit and scope of the present invention.