Distributed negative gate power supply

Distributed negative gate power supply

<u style="single">Background of the invention</u>

The present invention relates to a floating gate memory such as an array with a page erase (Page Erase) and a negative voltage gate erase (Nagative Voltage Gate Erase). Device (Floating Gate Memory Devices). In detail, the present invention relates to a method for generating during flash erasing and selectively supplying a relatively high negative pressure to selected half-segments via wordlines in an array of flash EEPROM memory cells The distributed negative gate power supply for the control gate of the memory compartment in the Half-Sector.

In the relevant trial, the US application serial number 07/964,807, titled "Negative Power Supply", also assigned to MA Van Buskirk et al., with an application date of October 22, 1992, stated that it was used in the flash During the erasing period, a regulated potential (Regulated Potential) is generated and supplied through a ZigZag circuit in an array of flash EEPROM memory cells to the negative power supply of the selected memory cell control gate. The application with serial number 07/964,807 is used for reference in this case. In Figure 1 of the '807 application, there is shown a clock circuit 14 used to generate a plurality of clock signals and a charge pump circuit 12 (Charge Pumping Circuit ) Is a block diagram of the negative power supply 10, decoupling the line to the charge pump line to effectively release the threshold voltage from falling into it.

The charge pump circuit 12 of the '807 application is formed by a plurality of charge pumping stages (Charge Pumping Stagec). A negative well circuit 20 (Negative Well Circuit) is coupled to the plurality of charge pump stages to initially prevent a certain number of operation of the plurality of charge pump stages during erasure. The regulator circuit 16 responds to the high negative voltage and the reference potential to generate a negative comparator signal that allows the charge pump circuit to increase the high level of the high negative voltage or decrease the low level of the high negative voltage, and is used to generate an independent power supply The adjusted negative potential of the potential VCC.

The charge pump circuit 12 and the negative well circuit 20 only represent one of 16 charge pump circuits used on an integrated circuit chip containing a flash EEPROM memory grid array. Each charge pump circuit is combined with one of the 8 half-segments in either left or right of the array. Furthermore, the high negative voltage NEGOUT from each pump circuit is coupled to the word circuit via positive channel transistors P9 (P-Channel Transistors) connected with multiple diodes as shown in Figure 4(c) of the '807 application . One disadvantage of this prior art negative power supply using 16 charge pump circuits is that the integrated circuit chip requires a lot of space. Furthermore, it is accompanied by the disadvantages of high power consumption and high heat dissipation. In addition, there is another shortcoming of the voltage drop Vt dependent on the word line voltage due to the diode connected to the transistor during the erasing period.

The present invention demonstrates an effective improvement to the prior art negative power supply of the '807 application described above. The distributed negative gate power supply of the present invention is used to generate and selectively supply a relatively high negative pressure to the control of the memory cells in the selected half section through the ZigZag circuit in an array of flash EEPROM memory cells during flash erasing brake. This distributed negative gate power supply includes a main charge pump circuit used to generate a relatively high main negative voltage and many distributed section pump circuits corresponding to one and a half sections. This distributed section pump circuit is used to selectively connect the main negative voltage to the selected half-section zigzag circuit.

Therefore, the general purpose of the present invention is to provide a distributed negative gate power supply to generate and selectively supply a relatively high main negative voltage to word lines in an EEPROM cell during flash erasing. The control gate of the memory cell in the selected half section, and overcomes many shortcomings of the negative power supply of the prior art.

An object of the present invention is to provide a distributed negative gate power supply for generating and selectively supplying a relatively high main negative voltage and occupying a smaller space on an integrated circuit chip than traditional users.

Another object of the present invention is to provide a distributed negative gate power supply for generating and selectively supplying a relatively high main negative voltage that eliminates the threshold voltage drop Vt dependent on the word line voltage during erasure.

Another object of the present invention is to provide a method for generating and selectively supplying a relatively high main negative voltage, and the main charge pump circuit used to generate the main negative voltage and a plurality of users selectively connect the main negative voltage to the selection The distributed negative gate power supply formed by the distributed section pump circuit of the half section word line.

In accordance with these goals and objectives, the present invention relates to supplying a main negative voltage used to generate and selectively supply a relatively high main negative voltage during flash erasing via a ZigZag circuit in an array flash EEPROM memory cell to a selected half-segment Distributed negative gate power supply for control gate of internal memory. The distributed negative gate power supply includes a clock circuit for generating many clock signals and a main charge pump circuit that reacts to the potential of the external power supply and reacts to the clock signal to generate a relatively high main negative voltage. The section logic circuit is provided to generate a half section selection signal corresponding to the selected half section individually. Most of the distributed section pump circuits respond to this half section selection signal to selectively connect the main negative voltage to the selected half section ZigZag circuit.

These and other objects and advantages of the present invention will be made clearer by the following description and accompanying drawings indicating corresponding parts of the reference numerals. Among them: Figure 1 is a chip wiring diagram illustrating how the distributed negative gate power supply of the present invention is placed on a segment drive circuit of a semiconductor integrated circuit; Figure 2 is a diagram of the main negative pump circuit 16 in Figure 1 Block diagram; Figure 3 is a detailed circuit diagram of a negative charge pump circuit in the main negative pump circuit in Figure 2; Figure 4(a) is a 16-section distributed section pump circuit 18a~18p in Figure 1 The detailed circuit diagram of one of them; Figure 4(b) is a circuit diagram illustrating how the main negative voltage NEGP is coupled to the word circuit; Figure 5 is used to generate 16 of the non-overlapping clock signals and half-segment selection signals The circuit diagram of one of the segment logic circuits; Figure 6 is the circuit diagram of the protection circuit used to generate the protection signal VNPE in Figure 2; Figure 7 is the negative circuit used to generate the signal VNW and NPD in Figure 2 The circuit diagram of the well circuit; Figure 8 is the circuit diagram of the negative regulator circuit in Figure 2; Figure 9 is the detailed circuit diagram of the negative comparator circuit in Figure 8; Figure 10(a)-10(c) It is used to generate a four-phase clock signal (Four Phase Clock Signal) the circuit diagram of the negative clock circuit; Figures 11(a)-11(g) are the timing diagrams of various control signals and clock signals in Figure 10; Figure 12 is to illustrate the states of various signals in Figure 2. It is helpful to understand the timing diagram of the operation of the present invention.

Now referring to all the drawings in detail, in Figure 1 it is illustrated how the distributed negative gate power supply 10 of the present invention is placed on the chip wiring of the relevant section drive circuit 12 and the row decoder 14 (Row Decoder), all of which are formed as Part of a single semiconductor integrated circuit chip (not shown). The distributed negative gate power supply 10 is used to generate and selectively supply a relatively high main negative voltage NEGP to control the gate-to-word line of the memory cell transistor in the selected half section during the operation of the flash erase mode.

The semiconductor integrated circuit chip also includes an array with a large number of flash EEPROM memory cells arranged in an N×M matrix. The external or external power supply potential VCC (not shown), which is usually +5.0V, is supplied to the integrated circuit chip and to the input of the distributed negative gate power supply 10. An array of flash EEPROM memory cells is formed on a substrate to define Columns and Rows. The substrate includes a Common Source Line extending in at least one column and a plurality of rows extending in opposite rows. Bit Line. Each memory cell includes a negative source region (N-type Source Rgeion) coupled to a common source line, a control gate, a floating gate, a channel region, and a negative drain region (N-type source region) coupled to a corresponding bit line. type Drain Region). Furthermore, each memory cell can be superiorly programmed by transferring hot electrons to its floating gate and can be superiorly erased by Tunneling Electrons from its floating gate to its source region.

It should be noted that the memory array is, for example, actually arranged in a matrix of 1024 columns×1024 rows, and a predetermined number of columns can be combined to form a section that defines erasable blocks that can be paged. For example, 1024 columns can be divided into 8 segments each containing an equal number of columns (128 each). However, the techniques of this technique need to understand that each segment can be formed by an unequal number of columns. Furthermore, the line can be divided into segments so that each segment has a left side and a right side (half segment).

Different from the previous negative power supply with application serial number 07/964,807 that uses multiple independent multi-state charge pump circuits (each for half of the section), the distributed negative gate power supply 10 of the present invention includes a separate large main The pump circuit 16 and a plurality of relatively small-sized, single-stage distributed section pump circuits 18a-18p are used to selectively distribute the main negative voltage NEGP. In this form, the amount of chip area required on the integrated circuit is effectively reduced. Furthermore, by implementing distributed section pump circuits, a substantial reduction in power consumption and heat dissipation can be achieved. In addition, the negative gate power supply includes a method for generating a small negative voltage that is initially pulled up to allow the main negative voltage to be fully discharged before the main negative voltage is pulled to the positive external power supply potential to avoid excessive pressure on the oxide The discharge voltage of the device.

In Figure 2, a block diagram of the main pump circuit 16 in Figure 1 is shown. The main pump circuit 16 includes two identical negative pump circuits 20a and 20b, which individually react to a corresponding clock circuit 22a and 22b to generate a relatively high main negative voltage NEGP. It will be noted that the negative pump line 20a is combined with the left side of the array and the negative pump line 20b is combined with the right side. Furthermore, the main negative voltages NEGP on output lines 26a and 26b are combined at node 28. The main pump circuit 16 includes a negative regulator circuit 24 for adjusting the main negative voltage NEG to approach -10.5 volts. The negative pump lines 20a and 20b also respectively generate second negative voltages NEGSL and NEGSR on the corresponding lines 30a and 30b, which are more negative than the main negative voltage NEGP (ie, about -14 volts).

In addition, the main pump circuit 16 has a protective circuit 32 that reacts to the main negative voltage NEGP to generate an intermediate negative protection voltage (approximately -6 volts) to provide oxide protection of the positive channel pull-up device in the section pump circuit. The negative well lines 34a and 34b are used to generate negative well voltages VNWL and VNWR on the respective lines 36a and 36b to ground the negative wells of the main and section pump lines during erasure. Therefore, it can be seen that the lines 20a, 34a, and 22a are combined with all the half-segments on the left side of the array and the lines 20b, 34b, and 22b are combined with the half-segment on the right side of the array. Lines 24 and 32 are used only once for the entire array.

Now that the negative pump lines 20a and 20b are the same in terms of their structure and operation, it is sufficient to describe the pump line 20a. Referring now to Fig. 3, a detailed circuit diagram of the negative pump circuit 20a will be described. This negative pump circuit contains four stages 301, 302, 303 and 304. The output transistor 305 is coupled to the output of the fourth stage 304 to generate a relatively high main negative voltage NEGP on the output line 26a, which approaches -10.5 volts. The output buffer stage 306 is also coupled to the output of this fourth stage 304 to generate a second negative voltage NEGSm, which approaches -14 volts. The input of the pump circuit 20a is located at the input node pmps. The negative channel pump selection transistor 307 has its drain connected to the input node pmps, its gate connected to receive the erase signal ER, and its source connected to the low power supply potential VSS (ground).

The pump circuit 26a is turned on when the erase signal ER is high to turn on the pump selection transistor 307, thereby establishing a current path to the low power supply potential VSS. In the non-erasing mode, the pump selection transistor 307 is turned off (Turn OFF) to prevent any direct current path from the high power supply potential VPP.

The first stage 301 is formed by the positive channel passing transistor P11, the positive channel starting transistor P12, the positive channel precharging transistor P13, and a pair of coupling capacitors C1, C7. The pass transistor P11 has its source connected to the input node pmps, its drain connected to the output/input node BB, and its gate connected to an internal node AA. The starting transistor P12 is a diode-connected transistor, in which its drain and gate are connected to the source of the transistor P11 together. The source of the transistor P12 is connected to the drain of the transistor P11 and the gate to the transistor P13. The drain of the transistor P13 is connected to the internal node AA and the gate to the transistor P11. The source of the transistor P13 is connected to the source of the transistor P11 and the drain of the transistor P12. The negative wells of the transistors P11-P13 are connected to the high power supply potential VPP. The coupling capacitor C1 is coupled between the output node BB and the input node 40 to receive the clock signal PHI1. The coupling capacitor C7 is coupled between the internal node AA and the input node 42 to receive the clock signal PHI2A. Each coupling capacitor C1 and C7 is formed by a MOS transistor.

The second stage 302 is the same in structure as the first stage 301, and includes positive channel transistors P21, P22, and P23 and coupling capacitors C2 and C8. The input of the second stage 302 is located at the output/input node BB and its output is located at the output/input node D. The coupling capacitor C2 is coupled between the output node D and the input node 44 to receive the clock signal PHI2. The coupling capacitor C8 is coupled between the internal node B and the input node 46 to receive the clock signal PHI1A. The third stage 303 is similar in structure to the first stage 301 and includes positive channel transistors P31, P32 and P33 and coupling capacitors C3 and C9. The input of the third stage 303 is located at node D, and its output is located at output/input node G. The coupling capacitor C3 is connected between the output node G and the input node 40 to receive the clock signal PHI1. The coupling capacitor C9 is connected between the internal node E and the input node 42 to receive the clock signal PHI2A. The negative wells of transistors P31, P32 and P33 are coupled to the negative well voltage VNWm instead of the supply potential VPP to prevent junction breakdown.

The fourth stage 304 is very similar in structure to the first stage 301 and includes positive channel transistors P41, P42 and P43 and coupling capacitors C4, C10. The input of the fourth stage is located at node G, and its output is located at output/input node J. The coupling capacitor C4 is coupled between the node J and the input node 44 to receive the clock signal PHI2. The coupling capacitor C10 is connected between the internal node H and the input node 46 to receive the clock signal PHI1A. It should be noted that because the fields at nodes J and H are very high, capacitors C4 and C10 are formed by individual stacking capacitors C4a, C4b and C10a, C10b. The internal node intj is initially coupled to the signal CDIS via the transistor Q1, and the internal node inth is coupled to the ground potential via the diode-connected transistor Q2. The source/drain junctions of transistors P41, P42 and P43 are circled ("donuted") to increase the junction breakdown voltage. The term "donut" refers to the use of silicone to wrap the source/drain junction in a circle.

The source of the output transistor 305 is connected to the output node J and its drain is connected to the output line 26a to generate the main negative voltage NEGP. The gate of the transistor 305 is connected to the internal node K. The negative well of transistor 305 is also connected to the negative well voltage VNWm. The output buffer stage 306 includes a first buffer stage 306a and a second buffer stage 306b, each of which is similar in structure to the fourth stage 304. The first buffer stage 306a is formed by transistors P51, P53 and stacking capacitors C5, C11. The input of stage 306a is at output node J and its output is at output/input node M. The internal nodes intm and intk are started by transistors Q3 and Q4. Similarly, the second buffer stage 306b is formed by the positive channel transistors P61, P62, and P63 and the stacking capacitors C6, C12. The internal nodes into and int are started by transistors Q4 and Q5.

After the erase mode, the high negative voltage must be discharged from the pump line 20a. It should be noted that the signal CDIS (the complement of ERSEL) is used to discharge the intermediate nodes of the capacitors C4-C6 and C10-C12 during the non-erasing mode. However, during the non-erasing mode, the internal nodes M and N will not discharge because the clock signals PHI1 and PHI1A are low. If the output node of a particular pump stage is pulled high, the combined pre-charge transistor will be turned off (Turn OFF), and a negative voltage will be obtained on the intermediate node connected to the pre-charge capacitor. In order to solve this problem, discharge transistors Q6, Q7, Q8, Q9, Q10, Q11 and Q12 are provided to pull up the nodes K, N, and O via the discharge signal NPDm. The discharge signal NPDm is used to discharge the most negative node of the capacitor, otherwise it will be set to a negative voltage and exceed the oxidation breakdown voltage of the transistor. During the discharge, the discharge signal NPDm initially approaches -2.5 volts and is pulled up to the high power supply potential VPP after the pump output node is fully discharged.

The discharge transistors Q6 and Q7 will raise the node M to the potential VPP after the node N is pulled up to the potential VPP. However, transistor P53 will turn off so that node K will not discharge node J. This problem can be solved by providing two transistors Q13a, Q13b that establish a more resistance path between the diode connections between nodes M and J. Furthermore, during the discharge, the transistor Q14 connected between the nodes D and E and the transistor Q15 connected between the nodes G and H will turn on to discharge the nodes E and H. The clock signal remains in the ON state for an extra time after erasing the ER, and the erasing selection signal ERSEL is turned ON so that the pump circuit 20a can be properly discharged.

The operation of the negative pump circuit 20a is the same as the description of the negative pump circuit 12 described in Figure 4(a) of the prior art serial number 07/964,807 mentioned earlier, so it will not be repeated here. Therefore, the output node BB of the first stage 301 will be pulled close to -3 volts by the clock signals PHI1 and PHI2A. The output node D of the second stage 302 is pulled by the clock signals PHI2 and PHI1A to a high negative potential approaching -6 volts. The output node G of the third stage 303 will be reached due to the clock signals PHI1 and PHI2A, even higher than the negative voltage tends to -8.5 volts. The fourth stage 304 will cause its output node J to be pulled close to -11 volts by the clock signals PHI1A and PHI2. The output node J generates a relatively high main negative voltage NIGP (-10.5V) on the output line 26a through the output transistor 305. The output buffer stage 306 is used to further generate a second negative voltage NGESm approaching -14 volts on the output line 30a.

Now that the distributed section pump lines 18a-18p are the same in their structure and operation, it is sufficient to describe only the section pump line 18a. Referring now to Figure 4(a), a detailed circuit diagram of the section pump circuit 18a is shown. This section pump circuit includes a relatively small size, single-stage charge pump 400, which is used to be selected in a section, which is reflected in The selective control voltage SNGm is generated when the second negative voltage NEGSm from the main negative pump circuit 16 is generated. This voltage SNGm is slightly more negative than the second voltage NEGSm. The selection control voltage SNGm is connected to the gates of a plurality of positive channel word line pass transistors P401, each of the word lines (ie, 256 word lines) of each pair segment, as shown in Figure 4(b). The source of the pass transistor P401 is connected to the main negative voltage NEGP, and its drain is connected to one of the corresponding 256-word lines WLnm. Therefore, it can be regarded as the selected control voltage to be used to selectively distribute or pass the main negative voltage NEGP to the selected sector ZigZag line.

The section pump circuit 18a includes a pair of cross-coupled input transistors 401, 402; passing transistors 403, 404; starting transistors 404, 406; output transistors 407, 408; and capacitors C401-C403, C404-C406. One side of the capacitors C401-C403 and C404-C406 is connected to receive another biphase (Biphase) clock signal SCAnm and SCBnm. The other side of the capacitors C401-C403 is connected to the node SN1, and the other side of the capacitors C404-C406 is connected to the node SN2. It should be noted that the negative well (N-well) of the capacitor is also converted by a two-phase clock signal to reduce the parasitic capacitance (Parasitic Capacitance) and enhance the coupling capacitance. The cross-coupled input transistors 401 and 402 connect their sources together and receive the second negative voltage NEGSm on node 410. The input transistor is used to provide the elimination of the threshold voltage drop Vtp across the corresponding pass transistors 403 and 404. Due to the high negative voltages appearing on the nodes SN1 and SN2, it can be seen that the capacitors C402, C403 and C405, C406 are piled up. Transistors 405 and 406 connected to the diodes are used to pre-charge individual nodes SN1 and SN2. Transistor 407 connected to the diode, 408 is used to establish a threshold voltage from the individual nodes SN1 and SN2 down to the output node 412 that provides the selected control voltage SNGnm.

The section pump circuit 18a also includes a diode connection chain 414 formed by transistors 415-418; a junction diode PJTCHL; a protection transistor 419-421; and a transistor chain 422 formed by transistors 423-426 ; And the clamp transistors 426, 427, for the unselected section, the section pump selection signal PSnm will be low, which turns on the transistor 417 so that the node PJD is 0 volts. When the main negative voltage approaches -10.5 volts, because the negative protection voltage VNPE will approach -6 volts, the transistor 424 will turn on to cause the selected control voltage SNGnm on the output node 412 to clamp at about -4 volts. . Transistors 426, 427 are used to clamp node 412 as the selected section pump to avoid becoming too negative. Therefore, the ZigZag line for the unselected section will not fall below -3 volts.

Furthermore, after erasing, the segment selection signal PSnm of all segments will become low. Therefore, a path through the diode connection chain and the transistor chain will also be provided to discharge nodes SN1 and SN2 and to select the control voltage SNGnm. After a part of the output node in the main negative pump circuit 16 is discharged, the second negative voltage NEGSm rises to the power supply potential VCC. As a result, the transistors 419-421 will be turned on so that the node 412 and the selection control voltage SNGnm are pulled up to the power supply potential VCC to discharge the nodes SN1 and SN2. The negative protection voltage VNPE is used to protect the oxide of the specific transistor in the section pump circuit, because the voltages NEGSm and SNGNm will become lower than -13 volts for the selected section pump. The gate of the transistor 420 is connected to the ground potential VSS to close the current path of the unselected section from the supply potential VCC to the node 410 via the nodes PJD and 412.

Figure 5 is a circuit diagram of one of the 16 section logic circuits 501, and each of the logic circuits 501 is combined with one of the 16 pump circuits 18a-18p. The section logic circuit 501 is used to generate the pump selection signal PSnm and the non-overlapping bi-phase clock signals SCAnm and SCBnm for the section pump circuit 18a. The segment logic circuit includes inverter gates 502-504 and NAND logic gates 505-508. One input of the NAND gate 505 is connected to receive the segment selection signal SnOm on the terminal 510, and its other input is connected to receive the negative well voltage VNWm on the terminal 512 of the inverter 502. The output of the NAND gate 505 generates the pump selection signal PSnm through the output of the inverter 503 connected to the terminal 514. One input of the NAND gate 506 is connected to receive the pump selection signal PSnm and its other output is connected to receive the 20 megahertz (MHz) input clock signal OSC on the terminal 516. The cross-coupled NAND gates 507 and 508 are used to generate a bi-phase clock signal SCBnm on the terminal 518 and a bi-phase clock signal SCBnm on the terminal 520. For the selected section, during the erase mode, the signal SnOm will be high and the negative well signal VNWm will be low. Therefore, the pump selection signal PSnm for the selected section will be high. The pump selection signal PSnm is used to allow the input clock signal OSC to pass through the NAND gate 506 to generate non-overlapping clock signals SCAnm and SCBnm. For non-selected segments, the pump selection signal PSnm will be low and non-overlapping clock signals will not be generated.

Fig. 6 is a schematic circuit diagram describing the circuit of the protection circuit 32 in Fig. 2. The protection circuit includes the first alignment drift transistors 601, 602; the first clamp diode connected to the transistor 603; the filter capacitor 604; the second alignment drift transistors 605, 606; the second clamp diode Body-connected transistor 607a; and discharge transistors 607-609. The protection circuit receives the main negative voltage NEGP that generates the protection potential VNPE on the terminal 610 through the transistors 601 and 602 to the output terminal 612. During erasure, the main negative voltage NEGP will be about -10.5 volts and the protection voltage VNPE will be close to -6 volts. This intermediate negative protection voltage VNPE is used to protect the oxides of various transistors whose source/drain falls below -13 volts. After erasing, the signal XTF on the terminal 614 is made high to turn on the transistor 607 and cause the voltage VNPE on the terminal 612 to be discharged. The transistor 603 is used to clamp the terminal 612 to a small positive voltage. The capacitor 604 is used to eliminate any noise caused by the capacitance to avoid disturbance.

Now that the negative well circuit 34a and 34b are the same in their structure and operation, only the negative well circuit 34a needs to be described in detail. The negative well circuit 34a in Fig. 2 is illustrated by the circuit diagram in Fig. 7. The negative well circuit 34a includes pull-up transistors 701, 706; protection transistors 702, 703, 707; pull-down transistors 704; a diode-connected transistor 705; and Transistor 708, 709 formed by the inverter. The gate of the transistor 701 is connected to receive the erase signal ER, and the gate of the transistor 706 is connected to receive the delayed erase selection signal ERSEL of the erase signal ER. During the period when the passing signal ERSEL is high and the erase signal ER is low, the transistors 701-704 will be turned on to cause the discharge signal NPDm on the terminal 710 to approach -2.5 volts, because the voltage VNPE is -6 volts and the voltage NEGP It is -10.5 volts. This is to prevent the node 710 from being pulled up to the power supply voltage VPP immediately. After a predetermined time, the signal ERSEL will go low. During this period, the voltage NEGP on the terminal 712 will discharge and the transistor 705 will use it to pull up the voltage NEGSm on the terminal 714. When the signal ERSEL goes low, the voltage NPDm on the node 710 is pulled up to the power supply potential VPP via the transistor 708. It should be noted that the supply potential VPP will be the same as the supply potential VCC (ie, +5 volts).

During the erasing period, it should also be noted that the erasing signal ER supplied to the terminal 716 will be high to pull the terminal 718 of the negative well voltage VNWm to the low power supply potential VSS (0 volts) to reduce the voltage across the junction . After erasing, the second negative voltage NEGSm is pulled to the power supply potential VPP via transistors 708, 706, and 707 to turn off the section pump. Transistor 702 is used to protect the pull-up transistor 701, and transistor 703 is used to protect the pull-down transistor 704, because the voltage NEGSm becomes lower than -13 volts which will cause excessive stress.

The negative adjustment circuit 24 in Fig. 2 is illustrated in the circuit diagram in Fig. 8. The adjustment circuit is used to adjust the erase field by controlling the main negative voltage NEGP on the node 28 to make it independent of the external power supply potential VCC. The adjustment circuit includes a reference circuit 801, a precharge circuit 802, a differential comparator 803, a pull-up transistor 804, and transistors 805 and 806 connected to the diode. During the erasing period, the voltage VCCDIV will be generated on the node 808, and the voltage NEGDIV will be generated on the node 810. The differential comparator 803 compares the voltage NEGDIV with the voltage VCCDIV and generates a negative comparison output signal NEGCOMP on the line 812. When the voltage NEGDIV is greater than the voltage VCCDIV, the comparison output signal NEGCOMP will be high and thereby the positive channel is closed and the transistor 804 is pulled up. When the voltage NEGDIV is less than the voltage VCCDIV, the output signal NEGCOMP will be low to turn on the transistor 804 to cause the terminal 814 to be connected to the power supply potential VCC. As a result, the negative voltage NEGP of the main pump circuit 20a will be pulled up.

In Figure 9, the circuit diagram of the differential comparator in Figure 8 is shown in detail. The differential comparator includes current source transistors 901, 902; input transistors 903, 904; and load transistors 905, 906. The gate of the input transistor 903 is connected to the node 808 to receive the voltage VCCDIV, and the gate of the input transistor 904 is connected to the node 810 to receive the voltage NEGDIV. The output terminal 908 of the differential comparator 803 provides an output signal NEGCOMP.

In Figures 10(a)-10(c), there is a circuit diagram of the negative clock circuit 22a in Figure 2. The negative clock line 22a is used to generate clock waveforms PHI1, PHI2, PHI1A, and PHI2A that are individually coupled to the nodes 45, 47, 49, and 51 in Figure 2. In Figure 10(a), the signal EROSCB is generated in response to the input clock signal OSC and the erase selection signal ERSEL. The circuit in Figure 10(a) includes NAND logic gate G1 and inverter gates G2, G3. In Figure 10(b), the clock signal PHI1 on the terminal 45a is generated in response to the input signals PHI2, EROSCB and PHI2A, and the clock signal PHI1A on the terminal 49a is generated in response to the input signals EROSCB and PHI2. The circuit in Figure 10(b) includes AND logic gate G4, NOR logic gate G5, NAND logic gate G6, and inverter gates G7-G12. In Figure 10(c), the clock signal PHI2 at the terminal 47a is generated in response to the input signals PHI1, PHI1A and EROSC, and the clock signal PHI2A at the terminal 51a is generated in response to the input signals EROSC and PHI1. The circuit in Figure 10(c) includes AND logic gate G13, NOR logic gate G14, NAND logic gate G15, and inverter gates G16-G21.

Now referring to the time chart in Figs. 11(a)-11(g) and the waveform in Fig. 12, the operation of the distributed negative gate power supply 10 in Fig. 1 will be described. The negative clock line 22a receives the 20 MHz clock signal on the line 41 (Figure 11(b)) and the erase selection signal ERSEL on the line 43 (Figure 11(a)). In response to these input signals, the waveforms of the clock signals PHI1, PHI2, PHI1A and PHI2A are generated on the output lines 45-51 shown in Figures 11(d)-11(g). The negative well circuit 34a receives the erasure signal ER on the line 52, the erasure selection signal ERSEL on the line 54 and the protection voltage VNPE on the line 56 as inputs. The erasure selection signal ERSEL will be referred to as the delayed erasure signal ER again.

During the erasing mode, the erasing signal ER becomes high as shown at time t1 in Figure 12. This erase signal ER is also supplied via line 58 to the gate of the negative channel transistor 307 in the main pump circuit 20a (Figure 3). As a result, the transistor 307 will turn ON to provide a current path to the low power supply potential VSS (ground). This will alternately cause the negative charge pump circuit 20a in the main pump circuit to act at time t2 and cause the main negative voltage NEGP on the line 26a to become close to -10.5 volts. The second negative voltage NEGS on line 30a will follow the main negative voltage and will charge to approach -13 volts at time t2.

For the selected section, the combined distributed section pump 18a (Figure 4(a)) will act like a pump to generate a selection control signal SNG approaching -14 volts. This selection control signal SNG is supplied to the word line pass gate transistor (Figure 4(b)) to pass the main negative voltage NEGP to the 256 word line WLnm in this section without a threshold voltage drop. The protection circuit 32 receives the negative well voltage VNW and the respective main negative voltage NEGP on lines 60 and 62 as inputs. In response to these input signals, the protection voltage VNPE on the line 64 is pulled below the ground potential during the erasing period to reduce the field across the gate oxide of the transistor in the negative well line 34a. The protection circuit receives the signal XTF on the line 66 and is used to discharge the protection voltage VNPE during the non-erasing mode. It should be noted that the output signal NPD on the negative well line 34a on the line 68 is pulled low (ie, -5 volts) during the erasing period.

Because of the negative voltage NEGP, when the erase signal ER becomes low after erasing at time t3, the signal NPD is pulled up to only approach -2.5 volts at time t3 to protect the gate oxide negative voltage NEGP and NEGS. Is quite high. After the main negative voltage NEGP is allowed to discharge at time t4 to approach -8 volts (or a little higher, that is, -3 volts), the signal NPD will only be pulled up to the final value +5.0 volts at time t5. In this case, the gate oxide of the transistor in the negative pump circuit 20a will not be over-stressed.

From the above detailed description, it can be seen that the present invention provides a distributed negative gate power supply to generate and selectively supply a relatively high main load during flash erasing via a ZigZag circuit in an array of flash EEPROM memory cells. Voltage to the control gate of the memory cell in the selected half section. The distributed negative power supply includes a main charge pump circuit and multiple distributed section pumps. The main charge pump circuit is used to generate the main negative voltage. Each distributed section pump responds to the half section pump selection signal to selectively connect the main negative voltage to the selected half section zigzag line.

A preferred example has been used to illustrate the present invention, but it should be understood that the technique of the present invention can be changed or modified in various ways, or equivalents can be used to replace its elements, but they still do not depart from the present invention. Actual range. In addition, in order to meet special circumstances or material instructions, the present invention can also be modified in various ways without departing from the central scope of the present invention. Therefore, the present invention is not limited to specific specific examples showing the best mode intended to realize the present invention, but the present invention will include all specific examples that fall within the scope of the appended patent application.