Encryption/decryption method and its device

Code decoding method and device

Detailed description of the invention

The present invention relates to a method and apparatus for encoding an uncoded text, and a decoding method and apparatus for decoding an encoded text.

In order to conceal communication or record data, it is known to encode information. This code encodes the information into unrecognizable information, sends the encoded information, or records it in the media. Then, the encoded information is received, decoded, and restored to the original information.

Such coding and decoding can be roughly classified into a secret key encoding method (a conventional key encoding method) and an open key encoding method. In the secret key encoding mode, the encoding and decoding process uses the same key, and the coded party and the decoding party secretly hold the same key.

On the other hand, in the public key encoding method, the coded one uses a different key than the decoded one, and although the key used by the coded one is public, the key used by the decoding side is not an open method.

One of the conventional key encoding methods of the encoding and decoding method is a well-known American standard DES (Data Encryption Stand-ard) encoding algorithm. In this DES mode, the coding algorithm is disclosed, and the coding strength (machine density) is maintained only by the coding key. The reason why the coding algorithm is disclosed is that even if it is publicly disclosed, if there is no coding key, decoding requires a large amount of calculation, and even a high-speed calculation device is expected to take hundreds or even thousands of years.

However, the encoding is basically a combination of two methods of transposing the order of the characters, and replacing the words with other words according to certain rules. The order in which the text is changed, or which text is replaced by which one is determined by the encoding algorithm and the key. However, the coding algorithm is not limited to DES but has various algorithms, and is developed in such a way that security and high speed are excellent at all times. For example, the encoding method (MULTI 2 method) described in the specification of the U.S. Patent No. 4,982,429, the U.S. Patent No. 5,103,479, and the Japanese Patent Laid-Open No. Hei 1-276189, etc. know.

In addition, the International Standardization Organization (ISO) is also registered with the ISO9979/0009 encoding method and the ISO/IEC10116 encoding utilization mode.

In the aforementioned encoding method of the MULTI2 mode, the input data length is 64 bits, and the output data length is 64 bits. The 256-bit key required for encoding is generated by a 256-bit system key and a 64-bit data key. . In addition, the number of segments encoded is a positive integer segment.

Figure 12 shows an overview of the encoding algorithm for this MULTI mode. The MULTI mode, as shown in Fig. 12, implements a coding algorithm by using a 64-bit data key Ks plus a 256-bit system key J to generate a 256-bit work key Kw. This process is called key program processing. This key program processing is carried out by means of the coding algorithm implementation means C. The generated work key Kw is supplied to the encoding algorithm execution means F to encode the uncoded text of the input 64-bit block. In addition, the coding algorithm implementation means C and the coding algorithm implemented by the coding algorithm implementation means F may be the same coding algorithm.

Such a coding system is a basic coding algorithm, but there is also a risk in using this method. For example, the probability of occurrence of a word or a word is statistically processed in advance, and the probability distribution of the type of the character string of the obtained code is compared. It is possible to presume (interpret) the original text before encoding.

Here, there is also a method of making an encoded text by interpolating the encoded 64-bit code block and the 64-bit input data that is subsequently input. The mode of encoding using this method is called CBC (Cipher Block Chaining) mode. Further, the above-described encoding algorithm implements the means F, and performs the encoding algorithm of such a CBC mode.

In addition, there is also a communication method for the unit length of the data that is determined in advance, such as packet communication, in the block coding mode of 64-bit bl-ock, which cannot be input by one block. When the number of bits in the block is divisible by the number of bits, the number of bits of less than one block will be ran out. Here, the end number processing is processed in the OFB (Output Feedback) mode.

That is, when the data has a terminal number, the end portion of the data is supplied to the encoding algorithm execution means G, and the method of encoding using the random number generated by the work key Kw is called the OFB mode. Thereby, when 64-bit is used as a block, an encoded text of less than 64-bit data can be obtained. Further, the CBC mode and the OFB mode are referred to as an encoding utilization mode.

Further, Fig. 13 is a view showing a schematic configuration of a decoding algorithm of the MULTI2 method. As shown in Fig. 13, the coding algorithm is used to generate a 256-bit work key Kw using a 64-bit data key plus a 256-bit system key J. The generation of this work key is performed by a key program of the same coding algorithm as the coded party. This coding algorithm is implemented by the coding algorithm implementing means c. The generated work key Kw is supplied to the decoding algorithm execution means f to decode the input 64-bit encoded text.

In this decoding algorithm, the encoding algorithm implements the encoding algorithm of means f, and the transposition and transposition algorithms are performed in reverse order.

Further, the encoded text encoded in the OFB mode is supplied to the encoding algorithm execution means g, and is decoded using the random number generated by the work key Kw. Thereby, the encoded text of 64 blocks of 1 block can be interpreted to obtain the uncoded text of the 64-bit block. In addition, the decoding algorithm implementation means f is arranged to perform a decoding algorithm of the CBC mode.

Here, the coding use mode will be described with reference to Fig. 14, (a) of Fig. 14 shows a schematic configuration of codec decoding in the CBC mode, and Fig. 14(b) shows a schematic configuration of codec decoding in the OFB mode.

In the CBC mode, as shown in Fig. 14(a), the i-th uncoded block M(i) is input to the mutex circuit 101, and before the block 1 delayed by the buffer (REG) 103 is fed back. The coded block c(i-1) performs a mutually exclusive calculation. The data of the calculation result is encoded by the coding algorithm execution means 102 by a work key generated based on the data key Ks. The encoded i-th encoded block C(i) is C(i)=EKs(M(i), EOR, C(i-1))

Said. Among them, EKs(m) means that m is encoded in Ks, and EOR is a mutually exclusive calculation.

Then, the coded block C(i) is sent out and received on the receiving side. The received encoded text C(i) is decoded by the decoding algorithm execution means 111 using the work key generated based on the data key Ks, and supplied to the exclusive circuit 113. The mutex circuit 113 is delayed in the register (REG) 112, and the encoded block C(i-1) before the block is input, and the two are mutually exclusive. At this time, the data key of the transmitting side and the receiving side is equal, whereby the i-th uncoded block M(i) is interpreted by the mutex circuit 113. The i-th uncoded text M(i) can be expressed by the following formula. .

M(i)=DKs(C(i), EOR, C(i-1))

Among them, DKs(c) indicates that c is decoded by Ks.

Further, in the OFB mode, the i-th uncoded block M(i) is supplied to the exclusive circuit 105. The mutex circuit 105 is supplied with an output of the encoding algorithm execution means 104 which is randomized by the work key generated by the data key Ks. Further, the output of the encoding algorithm execution means 104 delays the 1 block by the temporary memory 103, and the encoding algorithm execution means 104 delays the 1 block and is returned.

Thereby, the encoded block C(i) encoded by the random number is outputted by the mutex circuit 105. Then, the coded block C(i) is sent out and received by the received party. The received encoded block C(i) is supplied to the exclusive circuit 114. In this exclusive circuit 114, the encoding algorithm execution means is supplied with an output which is randomized based on the work key generated by the data key Ks. The output of the encoding algorithm execution means 115 is returned to the encoding algorithm execution means 115 by the temporary register (REG) 112 being delayed by one block.

In this case, the random number supplied to the mutex circuit 114 is equal to the random number supplied to the mutex 105, whereby the i-th uncoded block M(i) interpreted by the mutex circuit 114 can be obtained. ).

Fig. 15 is a view showing a schematic configuration of a coding and decoding method having a coding utilization mode as described above.

In this figure, the transmitting side is provided with a scrambler 100 for encoding the data, and the input data is encrypted by the encryptor 100, that is, encoded and sent. The encrypted transmission data is transmitted via the transmission path of the space and received on the receiving side. On the training side, a descrambler 110 is provided, by which the encrypted transmission data is decrypted, that is, decoded, and restored to the original data output.

The encryptor 100 is an encryption device 102 that implements a coding algorithm that encodes input input data (uncoded text), a temporary memory device 103, and a CBC mode coding unit that is formed by a mutual exclusion circuit (EX-OR) 101. And an encoder 104 that encodes the algorithm implementation means and an OFB mode encoding unit that is formed by a mutual exclusion circuit (EX-OR) 105. Further, an encryptor 106 for generating a work key from the data key and the system key is also provided in the encryptor 100. The generated work key is supplied to the encryptors 102, 104.

However, since the encryptor 102, the encryptor 104, and the encryptor 106 can use the same encoding algorithm, it can also be used by one encryptor as three encryptors. The operations of the CBC mode encoding unit and the OFB mode encoding unit are as described above and are omitted here.

In addition, the decryptor 110 provided on the receiving side is a decryptor 111 that implements a decoding algorithm for decoding the input received data (encoded text), a buffer 112, and a mutually exclusive circuit (EX). The OBC mode decoding unit constituted by the -OR) 113, the cipher 115 of the coding algorithm execution means, and the OFB mode decoding unit constituted by the exclusive circuit (EX-OR) 114. Further, an encryptor 116 for generating a work key from the data key and the system key is also provided in the decryptor 110. The generated work key is supplied to the encryptor 115.

However, since the encryptor 115 and the encryptor 116 can use the same encoding algorithm, it can also be used by one encryptor as two encryptors. The operations of the CBC mode encoding unit and the OFB mode encoding unit are as described above and are omitted here.

<p>However, as in the coding and decoding method shown in Fig. 15, the coding algorithm may be implemented on the coding side, but the decoding algorithm must be executed on the decoding side, and the coding algorithm of the work key necessary for the decoding process must be generated. In other words, it is necessary to provide hardware for performing the decoding algorithm and the encoding algorithm on the decoding side. Therefore, the hardware on the decoding side has a larger size than the encoding side.</p><p>Moreover, when the encoding and decoding method is used in a broadcasting system such as satellite television, the cost of the receiving equipment is higher than that of the transmitting side, which hinders the popularity of the broadcasting system.</p><p>Accordingly, it is an object of the present invention to provide an encoded and encoded method encoded by a specified coding algorithm, and a coding and decoding method and apparatus which can be simply decoded on the receiving side.</p>

<p>In order to achieve the above object, the coding method of the present invention is provided with a work key generation step for generating a work key by performing a coding algorithm, and a work key generated by using the work key generation step is specified for the uncoded text. The encoding process of the encoding algorithm is used to create an encoding process of the encoded text.</p><p>Furthermore, the decoding method of the present invention is provided with a work key generation step for generating a work key for use in the encoding process by performing a decoding algorithm, and applying a work key generated by the work key generation step to the coded text The decoding process of the decoding algorithm is performed to obtain a decoding process of the restored unencoded text.</p><p>Further, the encoding and decoding method of the present invention is provided on the encoding side with a work key generation step for generating a work key by performing a coding algorithm, and a work key generated by using the work key generation step of the code for The coded text is encoded by the encoding process of the specified coded algorithm, and the coded processing step is performed. On the decoding side, a decoding work key for generating the work key used in the encoding process is generated by executing the decoding algorithm. a generating step, and a decoding processing step of obtaining the restored unencoded text by using the decoding key generated by the decoding work key generating step to perform decoding processing of the decoding algorithm on the encoded text.</p><p>Furthermore, the encoding apparatus of the present invention has at least a key program means for generating a work key by performing a decoding algorithm using key information, and using a work key generated by the key program means to specify a non-coded text. Encoding processing of the encoding algorithm to create an encoding processing method for the encoded text.</p><p>Further, the decoding apparatus of the present invention has at least a key program for generating a work key for use in encoding processing by executing a decoding algorithm, and applying a work key generated by the key program means to the encoded text. The decoding process of the decoding algorithm described above obtains the decoding means of the original unencoded text.</p><p>Further, in the codec device of the present invention, the coded portion has a code key program for generating a work key by executing a decoding algorithm, and a work key generated by the code key program means for uncoded The encoding processing method of the encoded text is performed by the encoding process of the specified encoding algorithm; and the decoding portion has the following: decoding of the working key used by the encoding processing means by performing the decoding algorithm The decoding processing means for obtaining the unencoded text is obtained by using a key program means and using the work key generated by the decoding key program means for performing decoding processing of the decoding algorithm on the encoded text.</p><p>According to the encoding method and the decoding method of the present invention as described above, the work key necessary for the decoding process can be generated by executing the decoding algorithm. That is, the decoding algorithm execution means for generating the work key can be used in combination with the decoding algorithm execution means for decoding the encoded text, and the configuration on the decoding side can be simplified.</p><p>Further, in the case where the OFB mode is encoded using the random number generated by the decoding algorithm, the encoded text generated in the OFB mode can be decoded using the random number generated by the execution of the decoding algorithm, so the OFB mode is used. The decoding algorithm for generating random numbers can also be used. That is, the configuration of the decoding side can be more simplified.</p>

<p>Since the present invention is constructed as above, a work key necessary for the decoding process can be generated by performing a decoding algorithm. That is, the decoding algorithm generating means for generating the work key can be used in combination with the decoding algorithm executing means for decoding the encoded text, so that the decoding side can simplify the configuration.</p><p>Further, in the OFB mode, when the random number encoding is performed by the decoding algorithm, the encoded text encoded in the OFB mode can be decoded by the random number generated by the decoding algorithm, so the OFB mode is used. The means for implementing the decoding algorithm for generating random numbers can also be used. That is, the configuration of the decoding side can be more simplified.</p><p>Further, when the present invention is applied to a television system, the configuration of the receiving device can be simplified, and the cost can be reduced. Therefore, it is possible to promote the spread of the television system.</p>

Fig. 1 is a view showing a schematic configuration example of an embodiment of a codec device of the present invention which performs a coding and decoding method using a coding utilization mode according to the present invention. Further, the encoding method of the present invention is implemented on the transmitting side, and the decoding method of the present invention is implemented on the receiving side.

In this figure, the sender side is provided with an encryptor 1, and the input data to be transmitted by the encryptor 1 is encrypted, that is, encoded and sent. The encrypted transmission data is transmitted via a transmission route such as a space, and is received on the receiving side. On the receiving side, a decryptor 2 is provided, by which the encrypted message data is decrypted, that is, decoded, and restored to the original data.

In this case, the format of the transmission data (received data) is, for example, a mobile string (TS) specified in ISO/IEC13818. The mobile string has a packet structure of 188 bits, and a packet is usually followed by a 184-bit pay-load at the beginning of the 4-bit, and in order to perform error correction for the transmission error, there is a parity of 16-bit. The device is attached to the packet. A mobile string is a string that is repeatedly composed of such a packet.

At the beginning of the mobile string, the content containing the packet containing the packet is composed of image data, or is composed of sound data, or PID (Packet Identific-ation) composed of other data columns. Information, or attribute information of a packet such as TSC (Transport Scrambling Control) information showing whether it is encoded. Further, as a result of the interpretation of the beginning of the packet, when it is judged that it belongs to the uncoded received data, the decryption device only passes through the delay portion, and the moving string is output as it is. The delay time of the delay section is the time required for the decryptor 2 to decrypt.

Here, the encryptor 1 delays the output of the encryptor 12 of the encoding algorithm execution means for encoding the input unencoded text by a block 1 reg 13 and the exclusive repulsion circuit (EX-OR) 11 The CBC mode coding unit is configured, and the decoder 14 that decodes the algorithm execution means and the OFB mode coding unit formed by the exclusive circuit (EX-OR) 15.

Further, a decryption unit 16 that implements a decoding algorithm for generating a work key from a data key and a system key is also provided in the encryptor 1. Here, the generated work key is supplied to the encryptors 12, 14.

Next, the operation of the encryptor 1 will be described. In the case of the CBC mode, both the switching means 30 and the switching means 31 are switched to the side of the connector a, and the input data (uncoded text) of each of the input blocks is input to the exclusive circuit (EX-OR) 11, and The output of the encryptor 12 is delayed by the output of the register 1 (reg) 13 of the block, and the mutual exclusion calculation is performed together. The output from the EX-OR, which is calculated, is input to the encryptor 12 of the encoding algorithm. The unencoded text is encoded at the encryptor 12 using a work key to perform a coding algorithm. The encoded encoded text is sent by the switching means 31.

Further, the input data which becomes the number of ends at the time of tiling is encoded in the OFB mode, and in the OFB mode, the switching means 30 and the switching means 31 are all switched to the side of the connector b, and the input data of each block input is input ( The uncoded text is input to the mutex circuit (EX-OR) 15, and is subjected to mutual exclusion calculation and encoding together with the random number from the decryptor 14. In this case, the decryptor 14 performs a decoding algorithm using the work key and outputs a random number. The encoded encoded text is sent through the switching means 31.

Further, the work keys supplied to the encryptor 12 and the decryptor 14 are generated by using the decryption algorithm 16 using the data key and the system key before the encoding process. However, since the decryptor 14 of the decryptor 14 is not used at the same time in the encoding process, and the decoding algorithms implemented by the decryptor 14 and the decryptor 16 are the same, one decryptor can also serve as the decryptors 14, 16.

In addition, the decryptor 2 provided on the receiving side is a decryptor 21 that implements a decoding algorithm that decodes the input received data (encoded text), and delays the input received data by zone 1. The block buffer 22 and the CBC mode decoding unit constituted by the exclusive OR circuit (EX-OR) 23, the decryptor 25 for decoding the algorithm execution means, and the OFB formed by the exclusive circuit (EX-OR) 24. The mode decoding unit is configured. Further, a decryptor 26 that generates a work key from the data key and the system key is also provided in the decryptor 2. Here, the generated work key is supplied to the decrypter 21 and the decryptor 25.

Next, the operation of the decrypter 2 will be described. When the received data is encoded in the CBC mode, both the switching means 32 and the switching means 33 are switched to the connector a side, and the received data (encoded text) of each of the input blocks is input to the descrambler 21. At the decrypter 21, the same work key as that used for the encoding process generated by the decrypter 26 is supplied, and the encoded key is decoded by executing the decoding algorithm using the work key. The data of each block that is decoded is input to the exclusive exclusion circuit (EX-OR) 23, and is subjected to mutual exclusion calculation together with the received coded text from the temporary register (reg) 22 of the delay 1 block. The result of this calculation is the uncoded text that is decoded. This uncoded text is sent through the switching means 33.

Further, in the case of tiling, the encoded text is encoded in the OFB mode. When the OFB mode is decoded, the switching means 32 and the switching means 33 are switched to the connector b side, and each block of the received signal is received. The data (encoded text) is input to the exclusive circuit (EX-OR) 24, and is subjected to mutual exclusion calculation and encoding together with the random number generated by the decryptor 25. In this case, the decryptor 25 performs the decoding algorithm using the work key generated by the decryptor 26, and creates and outputs the same random number as the transmission side. The decoded unencoded text is sent through the switching means 33.

Further, the work keys supplied to the encryptor 21 and the decryptor 25 are generated by the decryption algorithm 26 using the data key and the system key before the encoding process.

However, in the encryptor 1 and the decryptor 2, the decryptor 14 and the decryptor 25 must be the same decoding algorithm, and the decryptor 16 and the decryptor 26 must also be the same decoding algorithm. Further, when the decryptors 14 and 16 of the encryptor 1 are used in combination, the decryptor 25 and the decryptor 26 of the decryptor 2 have the same decoding algorithm.

Further, the decoding algorithm of the decryptor 14 of the encryptor 1 can be used as the decoding algorithm of the encoding algorithm of the encryptor 12 at the time of decoding, and if so, the decoding calculation of the decryptor 21 and the decryptor 25 at the decryptor 2 is performed. The same algorithm can be used for the method. That is, the decoding algorithms of the decryptor 21, the decryptor 21, the decryptor 25, and the decryptor 26 may be the same.

Further, since the descrambler 21, the descrambler 25, and the descrambler 26 are not used at the same time in the decoding process, these descramblers 21, 25, 26 can be constructed using one descrambler. The present invention is characterized in that a decryptor that is used in combination is used. The present invention can greatly simplify the configuration of the decryptor 2, that is, the decoding means.

Next, a coding algorithm for carrying out the coding method of the present invention will be described with reference to FIG.

Figure 2 shows the encoding algorithm of the present invention. The input data and the output data are both 64-bit blocks. For encoding, 256-bit system keys and 64-bit data keys are used to generate 256 bits. Work key. In addition, the number of encoded segments is a positive integer segment.

That is, the decoding algorithm is implemented by using the 64-bit data key Ks plus the 256-bit system key J to generate a 256-bit work key Kw. This process is called key program processing. This key program processing is carried out by the decoding algorithm execution means E3. The generated work key Kw is supplied to the encoding algorithm execution means E6 to encode the uncoded text of the input 64-bit block. Further, the decoding algorithm implemented by the decoding algorithm E3 can interpret the encoding algorithm implemented by the encoding algorithm execution means E6.

In addition, for the encoded text thus encoded, if the probability of occurrence of a character or a single word is statistically calculated in advance, and the obtained probability distribution of the character string of the encoded text is compared, it is possible to estimate (interpret) the encoding. The original text. Therefore, as described above, a method of creating an encoded text by using a coded algorithm in which the encoded 64-bit code block and the 64-bit input data to be input are mutually exclusive is used. The mode of encoding using this method is called CBC (Cipher Block Chaining) mode. Further, the above-described encoding algorithm executes means E6, and performs a coding algorithm of such a CBC mode.

In addition, there is a communication method of a unit length in which data to be communicated in advance is determined. For example, when encoding is performed with 64 bits as a block, the number of bits that cannot be input into one block is input. When the data unit is divisible, it will run out the number of data of less than one block. Here, the end number processing is processed in the OFB (Output Feedback) mode as described above.

That is, when the data has a terminal number, the end portion of the data is supplied to the decoding algorithm execution means E7, and the method of encoding using the random number generated by the work key Kw of the size of 256 bits is called the OFB mode. . Thereby, when 64-bit is used as a block, an encoded text of less than 64-bit data can be obtained. Further, the CBC mode and the OFB mode are referred to as an encoding utilization mode.

Further, the decoding algorithm execution means E3 for generating the work key Kw as described above is the same as the decoding algorithm of the decoding algorithm of the OFb mode, and the decoding algorithm of the means E7. In fact, one decoding algorithm can be used in combination with two processing methods.

Here, in the fourth diagram, the configuration of the encryptor 1 which is used for one processing by one decoding algorithm and two processes is shown. Further, in Fig. 4, the decryptor 14 and the decryptor 16 shown in Fig. 1 are used as a dual-purpose EX-OR by 11 (15).

In this figure, the 64-bit data key is written into the Data_Key Register 17 in advance, and the system key of the 256-bit system assigned to each system is written into the system key before the encoding process. Register (System_Key Register) 18. Also, in order to increase the coding strength of the data key, it is updated every few seconds to every tens of seconds.

In this state, first, both the switching means 42 and the switching means 43 are switched to the joint a side. Next, at the decryptor 14 (16), the 64-bit data key stored in the data key register 17 is supplied, and the 256-bit system key stored in the system key register 18 is used in the decryptor 14 (16). A 256-bit work key is generated by implementing a decoding algorithm. This work key is written into the Work_Key Register 19.

After the work key is thus generated, the switching means 41 and the switching means 44 are all switched to the joint b side. Next, the input data partitioned into 64-bit blocks is input to EX_OR11 (15), and the encoded data of the 1-block is delayed by the scratchpad 13 to perform mutual exclusion calculation. The calculation result is input to the descrambler 12, and is encoded by the coding algorithm executed by the work key read by the work key register 19 supplied from the encryptor 12. The encoded coded CBC mode encoded text output by the encryptor 12 is output by the switching means 44.

Further, when the power is turned on for initial processing, the register 13 is set to an initial value.

Further, when the number of end data is input, the switching means 42 and the switching means 43 are switched to the joint c side, and the switching means 41 and the switching means 44 are also switched to the joint c side. Thus, the encoded data delayed by the temporary memory 13 is input to the decryptor 14 (16) by the switching means 42, and is read by the work key register 19 supplied to the decryptor 14 (16). The work key implements a decoding algorithm, which in turn is chaotic. The random number generated by the decryptor 14 (16) is input to the EX-OR 11 (15) by the switching means 41, and is mutually exclusive-calculated with the input of the number of terminals, and encoded. The encoded text of the thus encoded OFB mode is output via the switching means.

Next, a decoding algorithm for carrying out the decoding method of the present invention will be described with reference to FIG. The decoding algorithm is implemented by using a 64-bit data key Ks plus a 256-bit system key J to generate a 256-bit work key Kw. The generation of this work key is performed by the key program processing of the same decoding algorithm as the encoding side. This decoding algorithm is implemented by the decoding algorithm implementing means D3. The generated work key Kw is supplied to the decoding algorithm execution means D6 to decode the encoded text of the input 64-bit block.

The decoding algorithm is an algorithm in which the encoding algorithm shown in FIG. 2 performs the transposition and transposition algorithms in the encoding algorithm of the means E6 in reverse order.

Further, the encoded text encoded in the OFB mode is supplied to the decoding algorithm execution means D7, and is decoded by using the random number generated by the work key Kw. Further, the decoding algorithm execution means D7 is the same decoding algorithm as the decoding algorithm execution means E7 shown in FIG.

In addition, the decoding algorithm execution means D3 for generating the work key Kw as described above is the same as the decoding algorithm of the decoding method of the OFB mode, and the decoding algorithm of the means D7 is the same algorithm, and at the same time, the decoding calculation of the encoded text is interpreted. The decoding algorithm of the law enforcement means D6 is also the same. When decoding processing is performed, one decoding algorithm execution means can be used for three items of processing.

Here, in Fig. 5, one decoding algorithm execution means is used for three items of processing. Further, in Fig. 5, the decryptor 21, the decryptor 25, and the decryptor 263 decoders shown in Fig. 1 are represented by 21 (25, 26), and the two EX-ORs are EX-OR23 ( 24) Representation.

In Fig. 5, the 64-bit data key is written into the data key register (Data_Key Register) 27 in advance, and the system key of the 256-bit system assigned to each system is written into the system before the encoding process. Key Register (System_Key Register) 28.

In this state, first, both the switching means 50 and the switching means 51 are switched to the joint a side. Next, the decryptor 21 (25, 26) is supplied with a 64-bit data key stored in the data key register 27, and a 256-bit system key stored in the system key register 28 to the decryptor 21 (25, 26) A 256-bit work key is generated by implementing a decoding algorithm. This work key is written into the Work_Key Register 29.

After the work key is generated and stored in the work key register 29, the switching means 50, the switching means 51, and the changeover switch 52 are switched to the joint b side in the CBC mode. Next, the input data separated by the 64-bit block is input to the decryptor 21 (25, 26) by the switching means 50. The decrypter 21 (25, 26) performs a decoding algorithm by the work key read by the work key register 29, and can decode the received data. The decoded data is input to EX-OR 23 (24), and is mutually exclusive calculated by the switching means 52 with the received data of the delay 1 block from the register 22 of the input EX-OR 23 (24), thereby obtaining CBC. The original text of the pattern after the encoded text has been decoded.

Further, when the number of end data is input, the switching means 50 and the switching means 52 are switched to the joint c side, and the switching means 41 and the switching means 44 are also switched to the joint c side. Thus, the received data delayed by one block by the temporary memory 22 is input to the decryptor 21 (25, 26) by the switching means 50, and the work key supplied to the decryptor 21 (25, 26) is used. The work key read by the register 19 carries out a decoding algorithm and is further randomized. This is input to the EX-OR 23 (24) by the random number generated by the decrypter 21 (25, 26), and is mutually exclusive with the number of terminals input by the switching means 52, and the encoded text of the OFB mode is obtained by decoding. Uncoded text.

As described above, in the decryptor 2 of the decoding apparatus of the present invention using the decoding method of the present invention, since three decrypters can be used by one decryptor that executes the decoding algorithm, the configuration can be greatly reduced.

Next, the details of the decoding algorithm for implementing the decryptor will be described with reference to FIGS. 6 to 11.

Figure 6 shows the encoding algorithm, 64-bit input data, divided into upper 32 bits and lower 32 bits, and input to the first 8 segments encoded by the four segments 60, 61. In the four stages of the calculations 60, 61, different function calculations are performed.

That is, for the data of the upper 32-bit and the lower 32-bit input, the calculation of the function π1 is applied to the initial stage in the 4-stage arithmetic section 60. Next, in the second paragraph, the calculation of the function π2 is applied to the output of the first stage. In this case, the 32-bit work key K1 is input in the second stage, and the second stage calculation is performed using the work key K1.

Further, in the third stage, the calculation of the second stage is subjected to the calculation of the function π3. In this case, the 32-bit work keys K2 and K3 are input in the third stage, and the work keys K2 and K3 are used for calculation. Next, in the fourth paragraph, the calculation of the third segment is subjected to a calculation of π4. In this case, a 32-bit work key K4 is input in the fourth stage, and the work key K4 is used for calculation.

Further, in the initial stage of the calculation section 61 of the calculation section of the remaining four-stage calculation, the calculation of the function π1 is applied to the output of the calculation section 60. Then in the second paragraph, the output of the first stage is calculated by the function π2. In this case, a 32-bit work key K5 is input in the second stage, and the work key K5 is used for calculation.

Further, in the third stage, the calculation of the second stage is subjected to the calculation of the function π3. In this case, the 32-bit work keys K6 and K7 are input in the third stage, and the work keys K6 and K7 are used for calculation. Next, in the fourth paragraph, the output of the third segment is subjected to the calculation of the function π4. In this case, a 32-bit work key K8 is input in the fourth stage, and the work key K8 is used for calculation.

In this way, the 256-bit work key splitting bit is supplied to each of the arithmetic segments by 8 32-bit elements (key K1 to key K8), and the upper 32 bits and the lower 32 bits total 64 bits after the encoding process. The data is then entered into the 8-segment code 62. In the 8-segment code 62, the same calculation is performed as the above-mentioned 8-segment code, and the output data which is further irregularized by the upper 32-bit and the lower 32-bit total 64-bit can be obtained.

As shown in the figure, the number of repetitions of the 8-segment encoding is not limited to two, and the desired number of times can be repeatedly operated. The more the number of repetitions, the more irregular the output data is, and the coding strength can be improved.

In addition, the function calculation performed in each calculus is a transposition calculation in which a certain character is replaced by another character in accordance with a certain rule, and a transposition calculation in which the order of the characters is changed.

Next, Figure 7 shows the decoding algorithm, which is calculated in the opposite direction from the output side of the aforementioned encoding algorithm. That is, for the initial stage of the first four segments of the 8-segment encoding, the encoded input data divided into the upper 32-bit and the lower 32-bit 64-bit is applied using the 32-bit work key K8. The calculus of the function π4. Next, in the second paragraph, the calculation of the function π3 is applied to the output of the initial stage using the work keys K7 and K6. Further, in the third stage, the output of the second stage is subjected to the calculation of the function π2 using the work key K5. Further, in the fourth paragraph, the output of the third segment is subjected to the calculation of the function π1.

The calculation of the four stages is the same for the next four-stage calculation section 64 using the work keys K4 to K1.

Further, the calculation of the eight-segment encoding performs the same processing for the eight-segment encoding 65 that is successively continued, and the output data of the decoded upper 32-bit and lower-order 32-bit total 64-bit can be obtained. Further, the number of repetitions of the 8-segment encoding is the same as the number of repetitions of the 8-segment encoding performed when the encoding algorithm is executed.

Next, the calculation section 60 of the coding algorithm will be described as an example with reference to Fig. 8, and the details of the calculation performed in the calculation section will be described in detail.

In the calculation of the function π1 in the initial stage, the upper bit that is divided into 32 bits and input is directly output without being calculated. On the other hand, the calculation of the exclusive elements of the upper and lower bits is mutually exclusive. It is output as a lower bit.

Then, in the calculation of the function π2 in the second stage, the data x work key K1 of the lower 32 bits is added by the method of 232. First, the calculation x+K1. Next, when x+K1 is used as y, y is rotated to the left by 1 bit, and its value is obtained by adding y-1 to the y-1 after the calculation. Secondly, z is rotated to the left by 4 bits, and its value is mutually exclusive with each bit of z. The calculation results are mutually exclusive calculations with the upper 32-bit elements, and the calculation data as the upper 32-bit elements is output. In this case, the data input by the lower 32-bit system is directly output without calculation.

Further, in the calculation of the function π3 of the third stage, the data x work key K32 of the upper 32 bits is added by the method of 232, so that x + K2 is first calculated. Secondly, when x+K2 is used as y, y is rotated to the left by 2 bits, and for the value 232 is added to calculate y+1 to obtain z. Secondly, z is rotated to the left by 8 bits, and its value is mutually exclusive with each bit of z to obtain a.

Further, for a, the work key K3 is added by the method of 232, and a+K3 is calculated. Next, when a+K3 is b, b is rotated 1 bit to the left, and c is obtained by adding -b to the value by 232. Second, the logical sum of each bit of a and x, and the value after the c is rotated left by 16 bits to the left, performs a mutual exclusion calculation for each bit. The result of this calculation is to perform a mutual exclusion calculation for each bit with the data of the lower 32 bits, and output the data of the lower 32 bits after the calculation. In addition, the upper 32-bit data has not been calculated and directly becomes the output data of the upper 32-bit.

Furthermore, in the calculation of the fourth-order function π4, the data x work key K4 of the lower 32-bit element is added by the method of 232, and x+K4 is first calculated. Secondly, when x+K4 is y, y is rotated to the left by 2 bits, and the value is calculated by 232 as the y+1 calculated. The result of this calculation is mutually exclusive calculation with the upper 32-bit element, and the upper 32-bit data after the calculation is output. In this case, the data of the lower 32 bits is not calculated, and the data directly as the lower 32 bits is output.

In the above calculation, by adding the work keys K1 to K4 to the data, a word-changing process of replacing the characters with other characters is performed, and the transposition processing of the exchange of the character positions is performed by rotating the data. In this way, the uncoded text is encoded by the algorithm of transposing and transposing.

Further, in the case of decoding, the original text can be decoded by executing the algorithm of transposition and transposition opposite to the encoding.

Next, the configuration for performing the above-described function calculation will be described in more detail, and the function π2 is taken as an example of calculation in the ninth diagram.

In Fig. 9, the first 32-bit adder Add80, the lower 32-bit input data x is added to the 32-bit work key K1, and the addition data y is output. This addition data y is left-shifted by one bit in the first left-hand shifter 81, and is added to the output of the first left-hand shifter 81 in the second 32-bit adder 82. This addition result is further added to the third 32-bit adder 84 to calculate -1, and the calculation data z. The output data of this data z66 is subjected to the calculation of the function π4 using the 32-bit wide system key J8, and the output of the lower 32-bit width is output as the work key K4. Next, in the second stage, the output data of the first stage is subjected to the calculation of the function π3 using the 32-bit wide system keys J7 and &amp;6, and the output of the upper 32-bit element is output as the work key K5. Next, in the third stage, for the output data of the second stage, the system key S5 of 32-bit width is used to calculate the function of π2, and the output of the lower 32-bit width is output as the work key K6. Further, in the fourth stage, the output of the function of π1 is applied to the output of the third stage, and the output of the upper 32-bit width is output as the work key K7.

Further, next to the calculation section 68, the output data of the calculation section 67 is subjected to the calculation of the function π4 using the 32-bit wide system key J4, and the output of the lower 32-bit width is output as the work key K8.

However, the cipher implementing the above coding algorithm repeats the basic algorithm of the coding algorithm as in the sixth drawing. Here, if the four-stage arithmetic section shown in FIG. 6 is the core of the encryptor, as shown in FIG. 11(a), the encoding algorithm of the encryptor can be implemented by circulating the encryptor core. In addition, in this case, the work key supplied to the encryptor core is initially supplied with the work keys Ks1 to Ks4, and the second pass of the cycle is supplied to the work keys Ks5 to Ks8.

Further, the decryptor that executes the above decoding algorithm repeats the basic algorithm of the decoding algorithm as in the seventh embodiment. Here, if the four-stage arithmetic section shown in FIG. 7 is the core of the decryptor, as shown in FIG. 11(b), the decoding algorithm of the decryptor can be implemented by circulating the decrypter core. In addition, in this case, the work key supplied to the decrypter core is initially supplied with the work keys Ks8 to Ks5, and the second pass of the cycle is supplied to the work keys Ks4 to Ks1.

Further, such a decryptor core is used for 2 1/4 cycles, and the algorithm for key program processing can be implemented as shown in FIG. In this case, the system key is supplied instead of the work key, and it is of course not necessary to input the data key.

Thus, only the cipher core can implement the encoding algorithm, and only the decryptor core can implement the decoding algorithm and the key program processing algorithm. That is, the size of the hardware can be reduced, especially when the decryptor is mounted on a receiver of the television system, and the receiver equipped with the decryptor can be prepared by each user, and the cost of the receiver can be reduced. Therefore, it is possible to plan the promotion of the popularity of the television system.

In the above description, it has been explained that an uncoded block of a 64-bit block uses a 64-bit data key and a 256-bit system key to generate an encoded text of a 64-bit block, and a 64-bit block The encoded text uses a 64-bit data key and a 256-bit system key to produce the original text of the 64-bit block. However, the present invention is not limited to these bit numbers, and may be any number of bits.

Furthermore, the present invention is not limited to the above-described transcoding and transcoding-like encoding and decoding methods as described above, and other encoding and decoding methods are also applicable.

Furthermore, the present invention can be applied to CATV, satellite communication, network, and the like. In this case, the system key and the data key are transmitted in the communication data, or are obtained by the user using a prepaid card or a telephone, and only the user who has paid for the video can be decoded.

<p>1Encryptor</p><p>2Decryptor</p><p>11, 15, 23, 24, 86Exclusive circuit (EX-OR)</p><p>12Encryptor</p><p>13, 22 register</p><p>14, 16, 21, 25, 26 Decryptors</p><p>17, 27 data key register</p><p>18, 28System Key Register</p><p>19, 29 work key register</p><p>30, 31, 32, 33, 41, 42, 43, 44, 50, 51, 52 means of switching</p><p>60, 61, 62, 63, 64, 65, 66, 67, 68 calculus</p><p>80, 82, 8432 bit adder</p><p>81, 85 Left Swinger</p>

Fig. 1 is a schematic block diagram showing an exemplary configuration of an embodiment of an encoding apparatus and a decoding apparatus of the present invention which performs the encoding method and the decoding method of the present invention.

Fig. 2 is a diagram showing a coding algorithm for carrying out the coding method of the present invention.

Figure 3 is a diagram of a decoding algorithm for implementing the decoding method of the present invention.

Figure 4 is a block diagram showing the construction of an encryptor to which the encoding method of the present invention is applied.

Figure 5 is a block diagram showing the construction of a decryptor to which the decoding method of the present invention is applied.

Figure 6 is a diagram showing the coding algorithm of the coding method and apparatus of the present invention.

Figure 7 is a diagram showing the decoding algorithm of the decoding method and apparatus of the present invention.

Figure 8 is a detailed diagram of the basic functions of the coding algorithm shown in Figure 6.

Fig. 9 is a detailed configuration diagram required for carrying out the function π2 in the basic function shown in Fig. 8.

Figure 10 is a schematic diagram of the algorithm for processing the key program of the present invention.

Figure 11 is a schematic diagram showing the structure of the encryptor core and the decryptor core.

Figure 12 is a schematic diagram of the previous coding algorithm.

Figure 13 is a schematic diagram of the previous decoding algorithm.

Fig. 14 is a view showing the configuration of the coding utilization mode of the CBC mode and the OFB mode.

Fig. 15 is a view showing the constitution of the previous coding and decoding method.