Division circuit of 4/5

Divide 4/5 circuit

The present invention relates to a frequency divider circuit, and in particular to a fast dual-mode frequency divider circuit, which can be applied to the CMOS process and achieves megahertz (GHz) with high processing speed, low power consumption and low operating voltage. ) The above data transmission.

In modern wireless communication systems, a frequency synthesizer with a high-frequency front frequency divider circuit is a very important component. Traditionally, the prescaler is mostly implemented with high-speed bipolar or gallium arsenide (GaAs) semiconductor technology. However, with the advancement of metal oxide semiconductor (MOS) technology, it can provide higher integration density, lower power consumption and faster processing speed, so the metal oxide semiconductor (MOS) pre-installed frequency divider It came into being.

Please refer to Figure 1, which is a circuit block diagram of the divide 128/129 circuit designed using metal oxide semiconductor technology in the prior art. Among them, the divide 128/129 circuit is composed of a high frequency divide 4/5 circuit K1, a low frequency divide 32 circuit K2, and a frequency divider control circuit K3. The high frequency divide by 4/5 circuit K1 is a logic circuit obtained from a state diagram, which is connected to three D-type flip-flops D1, D2, D3 and two inverters NA1, NA2 (as shown in Figure 1 As shown), therefore, the input clock IN can be divided by 4/5 according to a divide by 4/5 control signal MC. The low frequency divide-by-32 circuit K2 is formed by connecting five T-type flip-flops T1, T2, T3, T4, T5 in series (the T-type flip-flop can connect the input (D) and the reverse output of the D-type flip-flop ( Q') is connected), which is used to divide the input clock (that is, the divided 4/5 signal output by the divide by 4/5 circuit K1) by 32. The frequency divider control circuit K3 has a frequency divider control signal MODE and a divide-by-32 circuit K2. The reverse outputs of the five T-type flip-flops T1, T2, T3, T4, and T5 are all 1 (that is, when When the frequency divider control signal is 1 and the divide-by-32 circuit K2 counts one cycle), a signal is sent out as the divide-by-4/5 control signal MC of the divide-by-4/5 circuit K1.

In this circuit, when the frequency division control signal MODE is 0, the division 4/5 control signal MC must be 0. At this time, the division 4/5 circuit K1 executes the division by 4 action, that is, divides the input clock IN by 4. Therefore, the entire divide-by-128/129 circuit performs the division-by-128 action, and the output is OUT in the figure. Conversely, when the frequency divider control signal MODE is 1, at this time, since the divide by 4/5 control signal MC will be converted to 1 every time the divide by 32 circuit K2 counts one cycle, therefore, the divide by 4/5 circuit K1 will The divide-by-32 circuit K2 executes the division by 5 every time it counts one cycle, so that the entire divide by 128/129 circuit executes the division by 129.

Moreover, since the high frequency processing of the entire divide 128/129 circuit is mainly performed in the divide 4/5 circuit K1, the speed of the entire divide 128/129 circuit is limited by the divide 4/5 circuit K1.

In view of this, the main purpose of the present invention is to provide a divide-by-fourth circuit, which can be completed by using half-transparent registers and domino CMOS logic. It is different from conventional bicarriers or gallium arsenide and can be applied to CMOS process. Therefore, it has deep industrial applicability. At the same time, it also has the characteristics of low power consumption, low operating voltage and high processing speed, which can reach Gigahertz (GHz) data transmission.

In order to achieve the above and other objectives of the present invention, the present invention proposes a divide by 4/5 circuit. This divide by 4/5 circuit is composed of a semi-transparent register, a domino metal oxide semi-logic, a buffer device, a divide by 4 circuit and a control circuit.

Among them, the transflective register includes: a third NMOS transistor whose gate and source are respectively connected to an input clock and a negative power supply; a third PMOS transistor whose gate and source are respectively connected Connected to the input clock and a positive power supply; a first inverter, formed by a first PMOS transistor and a first NMOS transistor connected in series, wherein the first PMOS transistor and the first NMOS transistor The gate of the transistor is connected to serve as the input of the first inverter, the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to serve as the output of the first inverter, and , The source of the first PMOS transistor is connected to the positive power supply, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor; and a second inverter is connected to the drain of the third NMOS transistor; Two PMOS transistors and a second NMOS transistor are connected in series. The gates of the second PMOS transistor and the second NMOS transistor are connected to serve as the input of the second inverter. The drains of two PMOS transistors and the second NMOS transistor are connected as the output of the second inverter, and the input of the second inverter is connected to the output of the first inverter, The source of the second PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the second NMOS transistor is connected to the negative power supply.

The domino logic circuit includes: a fourth PMOS transistor whose gate and source are respectively connected to the input clock and the positive power supply; a fourth NMOS transistor whose gate and source are respectively connected to the input The clock and the negative power supply; a first switch, the control terminal of which is connected to the output of the second inverter; and a second switch, connected in parallel to the first switch, both ends of which are respectively connected to the fourth PMOS The drain of the transistor and the drain of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is connected to the input of the first inverter.

The buffer circuit is connected to the drain of the fourth PMOS transistor to output a frequency-divided reference clock. The divide-by-4 circuit includes: a first divide-by-2 circuit for dividing the frequency of the divide-frequency reference clock by 2 to obtain a divide-by-2 reference clock; and a second divide-by-2 circuit for dividing the frequency by 2 The frequency of the reference clock is divided by 2 to obtain an output clock. The control circuit outputs a control signal of a domino logic circuit based on the divide by 2 reference clock, the output clock and a divider control signal, and is connected to the control terminal of the second switch via an output terminal.

Furthermore, in the divide by 4/5 circuit of the present invention, the buffer circuit can be composed of an inverter. The first divide-by-2 circuit can be composed of a D-type flip-flop, and its timing terminal (CLK) and input terminal (D) are respectively connected to the frequency divider reference clock of the buffer circuit and the reverse output terminal of the D-type flip-flop (Q'). The second divide-by-2 circuit can be composed of a second D-type flip-flop, and its timing terminal (CLK) and input terminal (D) are respectively connected to the divide-by-2 reference clock of the D-type flip-flop and the D-type flip-flop The reverse output terminal (Q').

In addition, in the 4/5 division circuit of the present invention, the D-type flip-flop is composed of a fifth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a sixth NMOS transistor, and a It consists of three switches, a seventh PMOS transistor, a seventh NMOS transistor and an inverter.

Wherein, the gate and source of the fifth PMOS transistor are respectively connected to the timing terminal (CLK) of the D-type flip-flop and the positive power supply; the gate and source of the fifth NMOS transistor are respectively connected to the D-type The input terminal (D) of the flip-flop and the negative power supply, the drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor. The gate and source of the sixth PMOS transistor are respectively connected to the timing terminal (CLK) of the D-type flip-flop and the positive power supply; the gate and source of the sixth NMOS transistor are respectively connected to the D-type positive and negative The timing terminal (CLK) of the device and the negative power supply. Two ends of the third switch are respectively connected to the drain of the sixth PMOS transistor and the drain of the sixth NMOS transistor, and the control terminal of the third switch is connected to the drain of the fifth PMOS transistor. The gate and source of the seventh PMOS transistor are respectively connected to the drain and the positive power supply of the sixth PMOS transistor; the gate and source of the seventh NMOS transistor are respectively connected to the timing of the D-type flip-flop Terminal (CLK) and the negative power supply, the drain of the seventh NMOS transistor is connected to the drain of the seventh PMOS transistor to serve as the reverse output (Q') of the D-type flip-flop. The inverter is connected to the drain of the seventh PMOS transistor as the output (Q) of the D-type flip-flop.

Similarly, in the 4/5 division circuit of the present invention, the second D-type flip-flop is composed of a fifth PMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a sixth NMOS transistor, It is composed of a third switch, a seventh PMOS transistor, a seventh NMOS transistor and an inverter.

Wherein, the gate and source of the fifth PMOS transistor are respectively connected to the timing terminal (CLK) of the second D-type flip-flop and the positive power supply; the gate and source of the fifth NMOS transistor are respectively connected to the The input terminal (D) of the second D-type flip-flop and the negative power supply, the drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor. The gate and source of the sixth PMOS transistor are respectively connected to the timing terminal (CLK) of the second D-type flip-flop and the positive power supply; the gate and source of the sixth NMOS transistor are respectively connected to the second The timing terminal (CLK) of the D-type flip-flop and the negative power supply. Two ends of the third switch are respectively connected to the drain of the sixth PMOS transistor and the drain of the sixth NMOS transistor, and the control terminal of the third switch is connected to the drain of the fifth PMOS transistor. The gate and source of the seventh PMOS transistor are respectively connected to the drain and the positive power supply of the sixth PMOS transistor; the gate and source of the seventh NMOS transistor are respectively connected to the second D-type flip-flop The timing terminal (CLK) and the negative power supply, the drain of the seventh NMOS transistor is connected to the drain of the seventh PMOS transistor to serve as the reverse output (Q') of the second D-type flip-flop . The inverter is connected to the drain of the seventh PMOS transistor as the output (Q) of the second D-type flip-flop.

In addition, in the 4/5 division circuit of the present invention, the first switch and the second switch can be composed of a MOS transistor, and the control terminals of the first switch and the second switch are the gates of the MOS transistor. The control circuit is an inverter and the input of the inverter is the divide by 2 reference clock, the output clock and the divide frequency control signal.

In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is specially cited below, and is described in detail as follows in conjunction with the accompanying drawings:

Figure 1 is the circuit block diagram of the conventional divide 128/129 circuit; Figure 2 is the circuit block diagram of the divide 4/5 circuit of the present invention; Figure 3 is the D-type flip-flop in the divide 4/5 circuit of the present invention Circuit diagram; and Figure 4 is the clock diagram of each node of the circuit divided by 4/5 as shown in Figure 2.

Please refer to Figure 2, which is a circuit block diagram of the divided 4/5 circuit of the present invention. Among them, the divide by 4/5 circuit includes a transflective register K4, a domino logic circuit K5, a buffer circuit K6, a divide by 4 circuit K7, and a control circuit K8.

The transflective register K4 is composed of three PMOS transistors and three NMOS transistors, as shown in the figure. The gate and source of the NMOS transistor N3 are respectively connected to the input clock IN and the negative power supply. The gate and source of the PMOS transistor P3 are respectively connected to the input clock IN and the positive power supply. The first inverter is formed by the series connection of PMOS transistor P1 and NMOS transistor N1. The gates of PMOS transistor P1 and NMOS transistor N1 are connected to serve as the input of the first inverter. The drain of the transistor P1 and the NMOS transistor N1 is connected to serve as the output of the first inverter, and the source of the PMOS transistor P1 is connected to the positive power supply, and the source of the NMOS transistor N1 is connected to The drain of the NMOS transistor N3. The second inverter is formed by connecting PMOS transistor P2 and NMOS transistor N2 in series. The gates of PMOS transistor P2 and NMOS transistor N2 are connected to serve as the input of the second inverter. The drains of the PMOS transistor P2 and the NMOS transistor N2 are connected as the output of the second inverter, and the input of the second inverter is connected to the output of the first inverter, and the PMOS transistor The source of the transistor P2 is connected to the drain of the PMOS transistor P3, and the source of the NMOS transistor N2 is connected to the negative power supply.

The domino logic circuit K5, as shown in the figure, includes a PMOS transistor, an NMOS transistor and two switches (which can be achieved by MOS). Among them, the gate and source of the PMOS transistor P4 are respectively connected to the input clock IN and the positive power supply. The gate and source of the NMOS transistor N4 are respectively connected to the input clock IN and the negative power supply. The control terminal of the switch S1 is connected to the output of the second inverter. The switch S2 is connected in parallel to the switch S1, and the two ends are respectively connected to the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4, and the drain of the NMOS transistor N4 is also connected to the input of the first inverter .

In addition, the buffer circuit K6 is connected to the drain of the PMOS transistor P4 to output a frequency-dividing reference clock CK. The buffer circuit K6, such as an inverter I1, is used for impedance matching, so as to make the frequency division reference clock CK more stable.

The divide-by-4 circuit K7 includes: a divide-by-2 circuit D4 (which can be obtained by connecting the input (D) and the reverse output of the D-type flip-flop) to divide the frequency of the frequency-dividing reference clock CK by 2. Thereby, a divide-by-2 reference clock OUT2 is obtained; and a divide-by-2 circuit D5 is used to divide the frequency of the divide-by-2 reference clock OUT2 by two to obtain an output clock OUT.

In addition, a control circuit K8 is needed in the divide 4/5 circuit, which according to the divide 2 reference clock OUT2, the output clock OUT, and a frequency divider control signal MC to output a domino logic circuit control signal MCx, And connected to the control terminal of the second switch via an output terminal. In this embodiment, the control circuit K8 can be completed with a three-input non-and gate NA3, so that when the output divided by 2 reference clock OUT2, the output clock OUT, and the frequency divider control signal are all 1, it sends a positive value to The control terminal of switch S2.

The detailed operation of the divide by 4/5 circuit will be described below based on the input clock IN in Figure 4.

First, when the frequency divider control signal MC is 0 (that is, the operation of dividing by 4 is performed), because the control circuit K8, if the output of the gate NA3 must be 1 and the switch S2 must be ON, the buffer circuit K6 is reversed. The input CKx of the inverter I1 is a negative power supply (logic value 0) when the input clock IN is 1 (NMOS transistor N4 is ON and PMOS transistor P4 is OFF), and when the input clock IN is 1 (NMOS transistor P4 is OFF) When N4 is OFF and PMOS transistor P4 is ON), it is a positive power supply (logic value is 1). That is to say, the buffer circuit K6, such as the input CKx of the inverter I1 and the input clock IN are exactly inverted; the buffer circuit K6, such as the output of the inverter IN (that is, the reference frequency divider clock CK of the circuit K7 is divided by 4). ) Is exactly in phase with the input clock IN.

The divide-by-4 circuit K7, in this embodiment, can be composed of divide-by-2 circuits D4 and D5 formed by two D-type flip-flops. The buffer circuit K6, such as the output CK of the inverter I1, is divided by 2 and divided by 4 in this embodiment. Obtain the divide by 2 reference clock OUT2 and the output clock OUT.

In this case, the role of the transflective register K4 is not important (because the output of the frequency divider control signal MC and the control circuit K8 is always 1), and the node A (that is, the PMOS transistor P1 and the NMOS transistor N1 The logic values of node B (ie, the drain of PMOS transistor P2 and NMOS transistor N2) are also maintained at logic 1 and logic 0, respectively.

However, when the input of the frequency divider control signal MC is changed from 0 to 1 (that is, the operation of dividing by 5 is performed), the situation is completely different. In this case, because the control circuit K8, such as the three-input negation gate NA3, the output MCx is not necessarily 1 (because when the reference clock divided by 2 and the output clock is 1, its output MCx is 0), Therefore, this circuit performs division by 5. The detailed operation is explained as follows.

First, please refer to Figure 4. When the frequency division control signal MC is 1 (ie when MCx is 0) but the reference clock OUT2 is divided by 2 and the output clock OUT is not completely 1, at this time, due to the control circuit K8, For example, the output of the three-input non-and gate NA3 is still 0, so the circuit maintains the division by 4 operation, as described above. The division by 2 reference clock OUT2 and output clock OUT are also shown on the left side of Figure 4, compared to the period of the input clock IN, which are logically [0, 1], [1, 0], [0, 0]. , And the cycle of [1,1]. And when the reference clock OUT2 and the output clock OUT are changed to 1 at the same time:

[The first half cycle t1]

In this half cycle t1, since the input clock IN just changes to logic 1 (the first half cycle), the input CKx and output CK of the buffer circuit K6 are logic 0 and logic 1, respectively. And NMOS transistor N3 is ON, the first inverter (composed of PMOS transistor P1 and NMOS transistor N1) operates, node A is the inversion of CKx (ie logic 1); PMOS transistor P3 is OFF, The two inverters (composed of PMOS transistor P2 and NMOS transistor N2) do not operate, and node B remains at logic 0. At this time, the switches S1 and S2 are both closed, and the PMOS transistor P4 is OFF, so the input CKx of the buffer circuit K6 is maintained at logic 0, and the output CK of the buffer circuit K6 is maintained at logic 1, divided by 4 and the circuit K7 divided by 2 The reference clock OUT2 and the output clock are also maintained at logic [1, 1], and the output MCx of the control circuit K8 is maintained at logic 0, the switch S2 is closed, and the division by 5 is continued.

[The second half cycle t2]

In this half period t2, the input clock IN changes from logic 1 to logic 0. At this time, the NMOS transistor N3 is OFF, the first inverter does not operate, and node A remains at logic 1; the PMOS transistor P4 is ON, the second inverter operates, and node B is the inverse of node A, that is, logic 0. At this time, since the switches S1 and S2 are off and the PMOS transistor P4 is ON, the input CKx of the buffer circuit K6 is a positive power supply (that is, logic 1), and the output CK of the buffer circuit K6 is logic 0 (unchanged). The division by 2 reference clock OUT2 and output clock OUT are maintained at logic [1, 1], while the output MCx of the control circuit K8 is maintained at logic 0, the switch S2 is closed, and the division by 5 is continued.

[The third half cycle t3]

In this half period t3, the input clock IN changes from logic 0 to logic 1 again. At this time, the NMOS transistor N3 is ON, the first inverter operates, and the node A is the inversion of CKx (ie logic 0); the PMOS transistor P3 is OFF, the second inverter does not operate, and the node B remains at logic 0. At this time, since the switches S1 and S2 are off and the PMOS transistor P4 is OFF, the input CKx and output CK of the buffer K6 are maintained at logic 1 and logic 0, except for 2 reference clock OUT2 and output clock OUT are maintained At logic [1, 1], the output MCx of the control circuit K8 is maintained at logic 0, the switch S2 is closed, and the division by 5 is continued.

[The 4th half cycle t4]

In this half period t4, the input clock IN changes from logic 1 to logic 0 again. At this time, the NMOS transistor N3 is OFF, the first inverter does not operate, and the node A remains at logic 0; the PMOS transistor P3 is ON, and the node B is the inverse of node A, that is, logic 1. In addition, since the switch S1 is in the ON state and the NMOS transistor N4 is ON, the input CKx of the buffer circuit K6 is transformed into a negative power supply (ie, logic 0), and the output CK of the buffer circuit K6 is also transformed into a logic 1. At this time, because the input (D) of the divide-by-4 circuit K7 has a rising edge, the divide-by-2 reference clock OUT2 and the output clock OUT obtained by the divide-by-4 circuit k7 change from the logic [1, 1] state It is the logic [0, 1] state, and the output CKx of the control circuit K8 returns to the logic 1 state, and continues to perform the division by 4 action of the previous interrupt.

If so, the division by 4/5 in this embodiment can repeat the actions described earlier, and when the division by 2 reference clock OUT2 and the output clock OUT appear logic [1, 1], the transflective register K4 and domino-type gold-oxygen semi-logic K5 increase the delay of one cycle (two half cycles), and further achieve the effect of dividing by 5 circuits.

In addition, since the operating frequency of the 4/5 circuits is mainly limited by the D-type flip-flops used, most of them are based on the nine transistor TSPC D-type flip-flops proposed by YUAN and SVENSSON. Therefore, the D-type flip-flops D4 and D5 (used in the divide-by-4 circuit K7) in the embodiment of the present invention are implemented by adopting an improved TSPC D-type flip-flop in order to achieve a higher operating frequency. It is mainly composed of PMOS and NMOS, and the circuit diagram is disclosed in Figure 3.

As shown in the figure, the D-type flip-flop (including the first D-type flip-flop D4 and the second D-type flip-flop D5) includes three PMOS transistors (P5, P6, P7), three NMOS transistors (N5, N6, N7), a switch S3 (formed by a MOS transistor) and an inverter I2.

Among them, the gate and source of the PMOS transistor P5 are respectively connected as the timing terminal (CLK) of the D-type flip-flop and the positive power supply. The gate and source of the NMOS transistor N5 are respectively connected to the input terminal (D) of the D-type flip-flop and the negative power supply, and the drain of the NMOS transistor N5 is connected to the drain of the PMOS transistor P5. The gate and source of the PMOS transistor P6 are respectively connected to the timing terminal (CLK) of the D-type flip-flop and the positive power supply. The gate and source of the NMOS transistor N6 are respectively connected to the timing terminal (CLK) of the D-type flip-flop and the negative power supply. The two ends of the switch S3 are respectively connected to the drain of the PMOS transistor P6 and the drain of the NMOS transistor N6, and the control terminal of the switch S3 is connected to the drain of the PMOS transistor P5. The gate and source of the PMOS transistor P7 are respectively connected to the drain of the PMOS transistor P6 and the positive power supply. The gate and source of NMOS transistor N7 are respectively connected to the timing terminal (CLK) of the D-type flip-flop and the negative power supply, and the drain of NMOS transistor N7 is connected to the drain of PMOS transistor P7. As the reverse output (Q') of the D-type flip-flop. The inverter I2 is connected to the drain of the PMOS transistor P7 to output the output (Q) of the D-type flip-flop.

If so, a higher operating frequency can be achieved by eliminating the D-type flip-flop with two MOS transistors, and it is suitable for higher frequency communication systems.

In summary, if the divide 4/5 circuit of the present invention is used in the corresponding position in the conventional divide 128/129 circuit, the simulation result of the HSPICE simulator: when the power supply is 3V, the operating frequency can reach 1.1 megahertz (GHz), the power consumption is 19.2mW, and 51% is consumed by the divide 4/5 circuit; when the power supply is 5V, about 42% of the power consumption is consumed by the divide 4/5 circuit. In addition, this chip can still be operated at an operating voltage of 1.5V, and has good low-voltage toughness.

In addition, since the divide-by-fourth circuit of the present invention can be designed in CMOS technology, it provides higher integration density, lower power consumption and faster operation speed, and at the same time, it is more adopted in the industry. In addition, reducing the use of combinational logic circuits and simplifying the design of the front frequency divider circuit/control circuit are also features of the present invention. By this, the present invention can reduce delays, speed up the speed, and facilitate the difficulty of frequency elimination of the subsequent circuit.

Moreover, since the speed of the divide-by-32/33 circuit, divide-by-64/65 circuit, and divide-by 128/129 circuit is mainly limited by the divide-by-fourth circuit among them. Therefore, the divide by 4/5 circuit of the present invention can also be applied to these circuits to improve their operating frequency.

Although the present invention has been disclosed in a preferred embodiment as follows, it is not intended to limit the present invention. Anyone who is familiar with this technique can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be subject to the scope of the attached patent application.