Data processing device

Data processing device

The present invention relates to a data processing device, which includes a plurality of microprocessor units (hereinafter referred to as "MPU") and a dual-port memory device, which has a plurality of end points for reading (writing) data.

The general operation mode of the above-mentioned data processing device will be explained below.

For example, two MPUs enter and exit the memory device in an asynchronous manner, that is, one MPU reads data from one address (memory unit) in the memory device, and the other MPU is at another address (memory unit) in the memory device. data input.

The effect of the aforementioned entry and exit operation is that the data stored in one address (memory unit) in the memory device is read, and the data supplied from the outside is written to other addresses (memory unit) in the memory device.

However, it must be considered that a single-bit address in the memory device is accessed by two MPUs at the same time, because the above-mentioned memory device is operated in an asynchronous manner. When one of these in and out actions (one MPU in and out) is a read operation and the other in and out (other MPU in and out) is a write operation, there is a possibility of accidents, that is, the read data may be due to data Is written and changed.

Therefore, when multiple MPUs enter and exit a single-bit address in the memory device, it is necessary to make technical improvements.

The object of the present invention is to provide a data processing device capable of reading and writing data in an accurate manner.

Another objective of the present invention is to provide a data processing device whose data processing rate will not be slowed down.

The typical structure of the present invention is as follows.

That is, the data processing device of the present invention includes a memory cell array assembly with multiple memory cells storing data, first and second addressing terminals to receive addressing signals, and a first controller to receive a first A read signal and output a first read control signal, a second controller to receive a second read signal and output a second read control signal, a first lock circuit to save the basis for the first read In response to the control signal, the data output from the memory unit corresponding to the address selection signal sent to the first address selection terminal and a second lock circuit are used to save the data from the corresponding to the second read control signal according to the response to the second read control signal. The data output by the memory unit of the address selection signal sent to the second address selection terminal.

Fig. 1 is a view of a data processing device according to the first embodiment of the present invention; Fig. 2 is a structural example view of components arranged in memory cells; Fig. 3 is a detailed view of the control circuit of the present invention; Fig. 4 is a timing diagram, It is used to illustrate the read operation of the data processing device in FIG. 1; FIG. 51 is a timing diagram to illustrate the write operation of the data processing device in FIG. 1; FIG. Figure 7 is a timing diagram for explaining the operation of the data processing device of the second embodiment of the present invention; Figure 8 is a view of a data processing device of the third embodiment of the present invention; and Figure 91 is a timing diagram, It is used to explain the operation of the data processing device of the third embodiment of the present invention.

<u style="single">The first embodiment</u>

FIG. 1 is a block diagram of a data processing device according to the first embodiment of the present invention, which includes MPUs 20 and 30 and a dual-port random read/write memory RAM 10.

The RAM 10 with two ports is installed between the two MPUs 20 and 30, and is operated asynchronously by the two MPUs 20 and 30. An addressing bus line AB 20 connected to the MPU 20 is connected to a first addressing terminal T of the dual-port RAM 10_AL, And a data bus line DB 20 connected to the MPU 20 is connected to a first data input terminal T_ILAnd a first data output terminal T_OL. An addressing bus line AB 30 connected to the MPU 30 is connected to a second addressing terminal T of the dual-port RAM 10_AR, And the data bus line DB 30 connected to the MPU 30 is connected to a second data input terminal T_IRAnd a first data output terminal T_OR. The address bus lines AB 20 and AB 30 are independently provided to the first and second addresses a20 and a30 for in and out, and output from the MPU 20 and the MPU 30 to a memory unit array assembly 11. The data bus lines DB 20 and DB 30 provide the first and second input data D20 and D30 to the memory cell array module 11 and the first and second output data d20 and d30 transmitted in the memory cell array module 11 To MPU 20 and 30.

Each MPU 20 and MPU 30 can independently generate and supply dual-port RAM 10 first and second read signals OE₂₀/And OE₃₀/, and the first and second write signals WE₂₀/And WE₃₀/. The function of the structure is to put each read signal OE₂₀/And OE₃₀/Supplied separately to the first and second read terminals T of the dual-port RAM 10_r2And T_r3, And put each write signal WE₂₀/And WE₃₀/Supplied individually to the first and second writing terminals T_W2And T_W3。

Addressing terminal T of dual-port RAM 10_ALAnd T_ARThe assembly 11 is connected to the array of memory cells. There is a data input terminal T on the other input side of the component 11 arranged in the memory unit_ILAnd a data input terminal T_IR. The first and second locking circuits 12 and 13 are arranged on the two output sides of the assembly 11 in which the memory cells are arranged. The output side of each locking circuit 12 and 13 are respectively connected to the data output terminal T_OLAnd T_OR. Reading end T_r2And write end T_W2Is connected to the first control circuit 14, the reading terminal T_r3And write end T_W3It is connected to the second control circuit 15. The control circuit 14 reads the signal OE from₂₀/ And write signal WE₂₀/Generate different control signals. The control circuit 14 also has the function of: supplying a read control signal RD_LAnd write control signal WR_LUsed as a component 11 in and out of the memory cell array; supplies a read control signal RD_LTo the locking circuit 12; and supplying a control signal DEL to the output side of the locking circuit 12. The control circuit 15 reads the signal OE from₃₀/ And write signal WE₃₀/Generate different control signals. The function of the control circuit 15 is to supply a read control signal RD_RAnd write control signal WR_RUsed as a component 11 in and out of the memory cell array; supplies a read control signal RD_RTo the locking circuit 13; and supplying a control signal DER to the output side of the locking circuit 13.

FIG. 2 is a block diagram illustrating an example of the structure of the components 11 in the memory cell arrangement in FIG. 1.

A memory cell arrangement 40 includes a large number of arranged memory cells MC, which are arranged inside the assembly 11 of the memory cell arrangement. Each memory cell has the same structure and is connected between the four bit lines and the two word lines in the same way. The memory cell MC in FIG. 2 is connected to four bit lines BL1 to BL4 and two word lines WL1 to WL2. The memory unit MC includes a flip-flop, which is composed of two cross-coupled inverters 41 and 42 whose tail ends are connected to each other to form a loop. N1 of one of the two input/output nodes N1 and N2 of the flip-flop is connected to the bit line BL1 via an N-type metal oxide semiconductor (hereinafter referred to as "NMOS transistor") 43, and is connected via an NMOS transistor 44 To bit line BL3. The input/output node N2 is connected to the bit line BL2 via the NMOS transistor 45, and is connected to the bit line BL4 via the NMOS transistor 46. The gates of the NMOS transistors 43 and 45 are connected to a word line WL1 connected to the decoder 47, and the gates of the NMOS transistors 44 and 46 are connected to a word line WL2 connected to the decoder 48. Via the addressing terminal T_ALAnd T_ARThe fed addresses a20 and a30 are supplied to each of the decoders 47 and 48.

The connection method is to connect the data input terminal T_ILThe input data D20 (data sent from the MPU 20) is supplied to the bit line BL1 through two inverters 50 and 51, and is supplied to the bit line BL2 through one inverter 52. The output on the output side of the inverters 50 and 51 is determined by the write control signal WR_LControl, when writing control signal WR_LThe data is sent to the bit lines BL1 and BL2 only when the level of is valid. In addition, the connection method is to connect from the data input terminal T_IRThe input data D30 (data sent from the MPU 30) is sent to the bit line BL3 via two inverters 53 and 54 and sent to the bit line BL4 via an inverter 55. The output on the output side of the inverters 54 and 55 is determined by the write control signal WR_RControl, when writing control signal WR_RWhen the level of is valid, the data is sent to the bit lines BL3 and BL4.

Each bit line BL1 and BL2 is connected to a sense amplifier 60, and each bit line BL3 and BL4 is connected to a sense amplifier 61. Read control signal RD_L(Signal from MPU 20) and RD_R(Signal from MPU 30) are input to sense amplifiers 60 and 61, respectively. Read control signal RD_LThen it becomes the active signal of the sense amplifier 60. At this time, the function of the sense amplifier 60 is to send the output data supplied from the bit lines BL1 and BL2 to the read control signal RD_LDuring the valid period, it is sent to the locking circuit 12 in Fig. 1. Read control signal RD_RThen it becomes the active signal of the sense amplifier 61. At this time, the function of the sense amplifier 61 is to transfer the output data supplied from the bit lines BL3 and BL4 to the read control signal RD_RIt is sent to the locking circuit 13 within the valid time period.

FIG. 3 is a block diagram showing the control circuits 14 and 15 of FIG. 1.

The control circuit 14 is configured with a pulse generating circuit 14-1 connected to the reading terminal T_r2, And a pulse generating circuit 14-2 is connected to the write terminal T_W2. The pulse generating circuit 14-1 generates the read control signal RD_L, As the setting time sequence and time interval, to read the data in the lock circuit 12 from the memory cell MC in the assembly 11 of the memory cell arrangement, and also generate a control signal DEL to set the time interval to store the data in the lock circuit The data of 12 is transferred to MPU 20. The pulse generating circuit 14-2 generates a write control signal WR_LAs the set timing and time interval, the input data D20 supplied from the MPU 20 is written to the memory unit MC.

The control circuit 15 is configured with a pulse generating circuit 15-1 connected to the reading terminal T_r3, And a pulse generating circuit 15-2 is connected to the write terminal T_W3. The pulse generating circuit 15-1 generates the read control signal RD_R, As the setting timing and time interval, to read the data in the lock circuit 13 from the memory cell MC in the assembly 11 of the memory cell arrangement, and also generate a control signal DER to set the time interval to store the data in the lock circuit 13 The data is transferred to MPU 30. The pulse generating circuit 15-2 generates a write control signal WR_RAs the set timing and time interval, the input data D30 supplied from the MPU 30 is written to the memory unit MC.

FIG. 4 is a timing chart showing the read operation of FIG. 1, and FIG. 5 is a timing chart showing the write operation of FIG. 1. Hereinafter, the operation of the data processing device in FIG. 1 will be described with reference to FIG. 4 and FIG. 5.

In the data processing device, from the addressing terminal T_AL, Data output terminal T_OL, Data input terminal T_IL, The reading end T_r2And write end T_W2In and out (that is, in and out on the side of the first port), and from the addressing terminal T_AR, Data output terminal T_OR, Data input terminal T_IR, The reading end T_r3And write to T_W3The entry and exit of the terminal (that is, the entry and exit on the side of the second port) are performed in a non-synchronized manner (that is, independent).

First, explain from the site selection terminal T_AL, Data output terminal T_OL, Data input terminal T_IL, The reading end T_r2And write end T_W2This is the case where the MPU 20 uses the first port side to perform reading. The read memory cell MC is based on the addressing terminal T_ALIt is selected from the address a20 provided by the MPU 20. That is, the level of the word line WL1 connected to the memory cell MC of the reading target is set to "H". When the word line WL1 becomes "H", the NMOS transistor 43 and the NMOS transistor 45 are turned on, so that the memory cell MC is connected to each of the bit lines BL1 and BL2. When MPU 20 then puts the read signal OE₂₀/Set at a valid "L" level, the pulse generating circuit 14-1 in the control circuit 14 will read the control signal RD_LSet to a valid "H" level. That is, the pulse generating circuit 14-1 directly generates signals on the signal OE during a specified period of time.₂₀After the /change, the pulse of "H" level is output, as shown in Figure 4. This "H" level read control signal RD_LIt is applied to the sense amplifier 60 to activate the sense amplifier 60. When the sense amplifier 60 becomes active, the data in the memory cell MC is amplified via the two bit lines BL1 and BL2, and this data is sent to the lock circuit 12. Read control signal RD_LIs also supplied to the lock circuit 12, and the read control signal RD_LBecause it is the "H" period, the data read from the memory cell MC is stored in the lock circuit 12 as the output data d20. The pulse generating circuit 14-1 then puts the control signal DEL to an effective "H" level. The effective period of this control signal DEL is from the effective read control signal RD_LWhen the time period disappears until the valid read signal OE₂₀/The end of the period. The output data d20 is from the lock circuit 12 through the data output terminal T during the effective period of the control signal DEL._OLAnd the data bus line DB 20 are transmitted to the MPU 20. From the site selection terminal T_AR, Data output terminal T_OR, Data input terminal T_IR, The reading end T_r3And write end T_W3The side read operation of the MPU 30, which is the read operation performed by the MPU 30 using the second port side, is implemented in the same way.

The following instructions are from the site selection terminal T_AR, Data output terminal T_OR, Data input terminal T_IR, The reading end T_r3And write end T_W3In the case of side writing, this is the case when MPU 30 uses the second port side to perform reading.

The memory cell MC to be written is based on the addressing terminal T_ARIt is selected from the address a30 provided by the MPU 30. That is, the decoder 48 sets the level of the word line WL2 connected to the memory cell MC of the writing target to "H". The word line WL2 becomes "H", and the NMOS transistors 44 and 46 are turned on, so that the memory cell MC is connected to each bit line BL3 and BL4.

On the other hand, when the MPU 30 sends the write signal WE₃₀/ When set to a valid "L" level, the pulse generating circuit 15-2 in the control circuit 15 writes the control signal WR_RSet to a valid "H" level. That is, the pulse generating circuit 15-2 directly receives this WR signal from the WR during a specified period of time._RAfter the end of the signal change (climbing edge), an "H" level pulse is output, as shown in Figure 5. This "H" level write control signal WR_RIt is applied to the inverters 54 and 55 in the assembly 11 in which the memory cells are arranged, and then each of the inverters 54 and 55 is activated. At this time, the data D30 to be written from the MPU 30 is prepared to be placed on the data bus line DB 30, so the written data D30 is supplied to the inverters 53 and 55. Because the inverters 54 and 55 become active, the information of the written data D30 can be supplied to each bit line BL3 and BL4. The data is therefore written into the write target memory cell MC connected to the bit lines BL3 and BL4 via the individual bit lines BL3 and BL4. From the site selection terminal T_AL, Data output terminal T_OL, Data input terminal T_IL, The reading end T_r2And write end T_W2In the case of side reading, which is the case where the MPU 20 uses the first port side to perform a write operation, it is implemented in the same way.

As described above, the locking is provided in this embodiment, the first circuit 12 and 13 for storing data read from the memory unit the MC, and 15, and a control circuit 14 generates a read access control signal RD_LAnd RD_RAnd write control signal WR_LAnd WR_RFor use. In the read control signal RD generated by the control circuits 14 and 15_LAnd RD_RDuring the valid period of time, the output data is stored in the lock circuits 12 and 13, and then the output data d20 and d30 are output from these lock circuits 12 and 13. In addition, the action of writing to the memory cell is when each writing control signal WR_LAnd WR_RIt is executed when it is valid. Therefore, if a read and write command is also issued to the same memory unit at the same time, the valid period is limited, so that, for example, the read control signal RD_LAnd write control signal WR_RIt is not exactly the same execution tool, so that problems such as reading data and writing data changes will not occur. Effective period, it is used to define the read control signal RD_LAnd RD_RAnd write control signal WR_LAnd WR_R, Can be set to be very short, and perform data reading and writing in accordance with the components 40 arranged in the memory unit, so that the processing rate in the entire data processing device does not need to be reduced. In addition, because only one read or write operation is stopped, there is no need to interrupt the operation of MPU 20 or MPU 30, and other programs of MPU 20 and MPU 30 are therefore not affected.

<u style="single">Second embodiment</u>

In the aforementioned first embodiment, when the same memory cell MC is accessed from two ports, if the read control signal RD_LAnd write control signal WR_RIf the level of "H" occurs in the same time period, the possibility of the output data d20 being changed by the written data cannot be ruled out. In this second embodiment, a configuration is used in which the control circuit generates the read control signal RD_LAnd RD_RAnd write control signal WR_LAnd WR_RWait for each other to monitor each other and implement the control of access to memory.

Fig. 6 shows a data processing device according to a second embodiment of the present invention, in which components common to those in the figure use common component numbers. Here, MPU 20 and MPU 30 are not shown.

In this data processing device, the control circuits 70 and 71 replace the control circuits 14 and 15 in the dual port RAM 10 of FIG. 1. The other parts, namely the assembly 11 of the memory cell arrangement and the locking circuits 12 and 13 have the same structure as the first embodiment.

The control circuit 70 is configured with a pulse generating circuit 70-1 connected to the reading terminal T_r2, And a pulse generating circuit 70-2 is connected to the write terminal T_W2. The pulse generating circuit 70-1, in the same manner as the pulse generating circuit 14-1 of the first embodiment, generates a read control signal RD for the components 11 and the lock circuit 12 arranged in the memory cell._LTogether with a control signal DEL, the read control signal RD is output by a delay circuit 70-3 connected to the end point._L. The pulse generating circuit 70-2 generates a write control signal WR for the memory cell MC_L. The control circuit 71 is configured with a pulse generating circuit 71-1 connected to the reading terminal Tr₃, And a pulse generating circuit 71-2 connected to the write terminal T_W3. The pulse generating circuit 71-1 generates a read control signal RD for the components 11 and the lock circuit 13 arranged in the memory cell._RAnd a control signal DER, which is outputted by a delay circuit 71-3 connected to the end point of the read control signal RD_R. The pulse generating circuit 71-2 generates a write control signal WR for the memory cell MC_R。

Write control signal WR of pulse generating circuit 71-2_RIt is connected as an input of the delay circuit 70-3. Write control signal WR of pulse generating circuit 70-2_LIt is connected as an input of the delay circuit 71-3. Therefore, the control circuits 70 and 71 use these connection methods to monitor the operation of the circuits each other, and use the delay circuits 70-3 and 71-3 to implement the control of access to the memory.

The operation mode of the dual-port RAM 10 in FIG. 6 will be described below.

The operation is the same as that of the first embodiment, according to addresses a20 and a30, read the control signal RD_LAnd RD_R,Write control signal WR_LAnd WR_R, And the control signals DEL and DER are implemented in the memory cell array component 11 and the locking circuits 12 and 13, and they enter and exit the memory from the two ports of the memory cell array component 40 in an asynchronous manner.

Figure 7 is a timing diagram illustrating the situation that occurs in and out of the memory in Figure 6. Hereinafter, referring to FIG. 7, the operation of entering and exiting the memory in the dual port RAM 10 of FIG. 6 will be described.

The pulse generating circuit 71-2 located in the control circuit 71, in the same manner as the pulse generating circuit 15-2 in the first embodiment, follows from the write terminal T_W3Input write signal WE₃₀/ Write the control signal WR in a specified period of time_RSet to a valid "H" level. The pulse generating circuit 70-1 located in the control circuit 70 follows the read signal OE in the same manner as the pulse generating circuit 14-1 in the first embodiment.₂₀/ Also generate a "H" level read control signal RD_L. The control circuits 70 and 71 mutually monitor the operation of the circuits in the RAM 10 at the two ports. For example, the control circuit 70 monitors the write control signal WR_RState, and when the write control signal WR_RWhen it is a valid "H" level, as shown in Figure 7, the delay circuit 70-3 sets the read control signal RD_LFor time delay. When the port end is used for reading and the port end is used for writing, it is implemented in the same way. Based on this method, the write control signal WR_RAnd read control signal RD_LWill not become a valid "H" level and write control signal WR at the same time_LAnd read control signal RD_RWill not become a valid "H" level at the same time.

According to the second embodiment, delay circuits 70-3 and 71-3 are arranged at the positions of the control circuits 70 and 71 to monitor the first port (on the side of the MPU 20) and the second port (on the side of the MPU 30). In and out operations. Read control signal RD output from the control circuit_LAnd RD_R, According to the write control signal WR generated from the control circuit on the opposite side_LAnd WR_RIn this way, the timing of data storage in the lock circuits 12 and 13 is adjusted by making a time delay in itself. That is, the operation of entering and exiting the memory unit MC from the two ports can be controlled by the control circuits 70 and 71. Based on this method, the time period for writing the input data D20 and D30 into one memory cell MC and the timing for reading data from one memory cell MC to the locking circuits 12 and 13 do not overlap. Because data reading is fixed to be executed after writing, uncertain data will not be output as output data d20 and d30.

<u style="single">The third embodiment</u>

Fig. 8 is a block diagram illustrating a data processing apparatus of the third embodiment of the present invention. Here, components common to Figure 1 and Figure 6 use common component numbers. MPU 20 and MPU 30 are not shown.

This data processing device is configured with a memory cell array assembly 11 in the same manner as in the second embodiment of FIG. 6, and locking circuits 12 and 13 are connected to both sides of the memory cell array assembly 11, and include two The control circuits 70 and 71, in addition, an anti-write circuit 80 and an address overlap detection circuit 90 are added.

The anti-write circuit 80 is configured with a dual-input NAND (not and) gate 81, and the output terminal of the pulse generating circuit 71-2 in the control circuit 71 is connected to one of the input terminals of the NAND gate 81, and is configured with one A dual-input AND gate 82. The output terminal of the NAND gate 81 is connected to one of the input terminals of the AND gate 82. The output terminal of the pulse generating circuit 71-2 in the control circuit 71 is connected to one of the input terminals of the component 11 of the memory cell array and the NAND gate 81. The output terminal of the pulse generating circuit 70-2 in the control circuit 70 is connected to the remaining input terminal of the AND gate 82, and the output terminal of the AND gate 82 is connected to the component 11 of the memory cell arrangement, that is, the pulse generating circuit 70-2 is connected to the assembly 11 of the memory cell array via the write-in prevention circuit 80. The address overlap detection circuit 90 detects whether the two addresses a20 and a30 overlap, and the output side of the address overlap detection circuit 90 is connected to the remaining input terminal of the NAND gate 82.

FIG. 9 is a timing diagram illustrating the situation of entering and exiting the memory of the dual-port RAM 10 in FIG. 8.

The dual-port RAM 10 can cause one of the write commands to be valid when multiple write commands occur simultaneously on the same memory cell MC in the assembly 11 of the memory cell arrangement. FIG. 9 shows the operation sequence of entering the memory when multiple write commands occur at the same time in the same memory cell MC.

When the MPU 20 and MPU 30 located on the two port ends of the dual-port RAM 10 supply the information written in addresses a20 and a30 to the component 11 of the memory cell arrangement at the same time, one of the addresses a20 and a30 corresponds to The memory cell MC is selected. The memory cell MC is therefore connected to the bit lines BL1 to BL4 in FIG. 2. On the other hand, the address overlap detection circuit 90 detects that the addresses a20 and a30 are consistent with each other, and outputs an "H" level detection signal to the NAND gate 81. The pulse generating circuits 70-2 and 71-2 then follow the write signal WE₂₀/And WE₃₀/Write the control signal WR_LAnd WR_RSet at the effective "H" level. The output of the NAND gate 81 thus becomes "L" and the output of the AND gate 82 becomes an invalid "L" level. The write control signal WR to be sent to the component 11 of the memory cell array_LTherefore, the write-protected circuit 80 becomes invalid, and the reading operation of a command sent from the side of the MPU 20 cannot be executed. On the other hand, the write control signal WR_RIt is also sent to the assembly 11 of the memory cell arrangement. In the write control signal WR_RWhen it is a valid "H" level, the input data from the side of the MPU 30 is therefore written into the selected memory cell MC.

In this third embodiment, compared to the second embodiment, the dual-port RAM has an anti-write circuit 80 and an address overlap detection circuit 90, which also strengthens the ability of the control circuits 70 and 71 to control the memory in and out. Based on this setting, when a write command is issued to the same memory cell MC at the same time, the write from the side of the MPU 20 becomes invalid. Therefore, the written data does not become uncertain, even when the input data from the MPU 20 and MPU 30 are reversed.

The present invention is by no means limited to the above-mentioned embodiment structure, so there are various possible modifications. The following is an example of modification.

(1) In the above-mentioned embodiment structure, the dual-port RAM of the data processing device adopts a structure in which data in and out of the MPU 20 and MPU 30 are operated in parallel via the data bus lines DB 20 and DB 30. However, dual-port RAM may also use data serial transmission.

(2) In the second embodiment, the time periods for writing and reading are moved regardless of the information at addresses a20 and a30. However, the address overlap detection circuit 90 can also be provided in the second embodiment as in the third embodiment. When the addresses a20 and a30 are the same, the writing and reading periods can be shifted.

(3) In the third embodiment, the writing operation from the side of the MPU 20 is regarded as invalid, but the same effect as described in the above embodiment can be obtained by setting the writing from the side of the MPU 30 to invalid. .

As in the previous detailed description of the present invention, the time period for writing data to the memory cell does not overlap with the time period for reading data from the memory cell. As a result, because the data content will not be changed or become undefinable when entering and exiting the same memory unit from two ports, the reliability of the data processing device is improved. At the same time, there is no need to sacrifice the working speed of the data processing device, because when entering and exiting the dual-port RAM, there is no need to interrupt the operation of the MPU.

In addition, as described in the present invention, the entry and exit operations from the first and second port ends are monitored, and the entry and exit control is implemented at the two port ends. Therefore, if the same memory unit generates a write command from both sides at the same time, or executes writing from one side and reading from the other side, entering and leaving the memory is accompanied by changes in input and output data, but Be put under control to obtain more reliable results than previous technologies.