Method of doping trench sidewalls before trench etching

Method for doping groove sidewall before groove etching

The present invention generally relates to an improved method of forming a trench that is used as an insulating device in an integrated circuit (IC). The present invention relates more particularly to an improved method of doping the sidewall of the trench to isolate the edge of the sidewall Parasitic edge transistors formed at the location.

Various insulating structures used in IC devices in general knowledge. A conventional insulating structure is provided in the trenches in the field area between the IC devices. Recently, the groove width has become smaller and smaller. As a result, these devices suffer from additional missing paths caused by parasitic edge transistors formed at the upper edge of the sidewall of the groove. The parasitic edge transistor is not necessary because it increases the OFF current of the integrated circuit device and increases the sensitivity of latch-up.

Various methods have been developed to isolate the parasitic edge transistors formed at the edges of the trench sidewalls. One solution to this problem is to dope the sidewall surface of the trench. By introducing dopants into the sidewall of the trench, the parasitic edge transistors are isolated, and the known phenomenon of "subthreshold kink" in the Id vs. Vg characteristic curve is suppressed. Additional benefits of introducing dopants into the sidewalls of the trench include a reduction in the turn-off current and a reduction in the initial slope of the activation device formed on the IC.

Figures 1A to 1C show the method of the previous art. The trench 20 is etched from the substrate 10 in Figure 1A. Next, in Figure 1B, the ions 30 are implanted into the upper edge 25 of the groove 20 using a method known as oblique ion implantation. Figure 1C illustrates the groove 20 after the oblique angle ion implantation step.

The disadvantage of the prior art method shown in Figures 1A to 1C is that oblique ion implantation is extremely important for deep and narrow grooves and a large aspect ratio (the aspect ratio is defined as the ratio of the groove height to its width). Narrow grooves (width0.5μm) are extremely difficult.

Figures 2A to 2C show the relative difficulty of ion implantation for trenches with larger aspect ratios. Figure 2A shows the three easiest geometries for ion implantation. Ion implantation is more difficult in the geometry of Figure 2B, and the most difficult in the geometry of Figure 2C. The difficulty of conventional ion implantation depends on the effect of the incident angle α. The larger the incident angle α, the easier the ion implantation.

In Figures 2A to 2C, the incident angle α is based on two independent variables-first, the width (or aspect ratio) of the groove, and second, the thickness of the mask layer (tm, which can be as large as 1 μm) depends on it. Figures 2A and 2B show the effect of decreasing the groove width (or increasing the aspect ratio) on the incident angle α. Figures 2B and 2C show the effect of the increase in the thickness of the mask layer (tm) on the incident angle α, which is called the shadowing effect.

Another disadvantage of the prior art method is that the angle of ion implantation needs to be adjusted according to the groove width. Therefore, the wafer forming the IC device must be tilted to obtain the required incident angle α to one of the sidewalls of the groove. After that, the wafer must be rotated 90 three times to enable implantation of the sidewalls of the groove at the same required incident angle α.

In addition, in the prior art method, the sidewall of the trench is thermally cycled after ion implantation to activate and diffuse the dopants. As a result, the dopants diffuse laterally, and the activation width of the device used to isolate the parasitic edge transistors is greater than required.

The object of the present invention is to provide an improved method for doping the sidewall of a trench to isolate the parasitic edge transistor formed at the upper edge of the sidewall of the trench.

Another object of the present invention is to provide an improved method for doping the side surfaces of extremely narrow grooves.

Another object of the present invention is to provide a method for doping groove sidewalls of various widths with the most ideal incident angle.

Another object of the present invention is to provide a method of doping sidewalls that is independent of the aspect ratio of the trench and does not require oblique angle ion implantation or wafer rotation.

Yet another object of the present invention is to provide a method for doping the sidewall of a trench that can control the degree of lateral diffusion of the doped sidewall region.

The above and other objects of the present invention are accomplished by implanting dopants into the trench area of the IC substrate before the trench is etched in the trench area. In this method, the width of the trench region etched in the trench region is narrower than the width of the doped region of the trench region.

In a preferred embodiment of the present invention, the doped region of the trench region is formed by implanting dopants into the etched openings of the nitride layer on the top surface of the IC substrate, and then treating the implanted The region is heat-treated, so that the dopant diffuses laterally into a region whose width is larger than that of the implanted region. The grooves are formed by reactive ion etching. The remaining nitride layer is used as an etching mask during the trench etching step, so the width of each trench is limited by the width of the etched opening of the nitride layer.

In another preferred embodiment of the present invention, the doped region of each trench region is firstly implanted between a pair of oxide spacers in the pre-defined region of the IC substrate, and then heat-treated the pre-defined region It is formed by lateral diffusion of dopants. During the trench etching step, the pair of oxide spacers is used as an etching mask, so the width of each slot is limited by the width of the opening between the pair of oxide spacers.

Other objects and advantages of the present invention will be disclosed in the following description. The purpose and advantages of the present invention can be achieved by means and combinations specifically pointed out in the scope of the attached patent application.

The present invention will be described in detail with reference to the drawings, in which: FIGS. 1A to 1C show a conventional method of implanting ions into the sidewall of an insulating trench.

Figures 2A to 2C show the relative difficulty of the conventional method of implanting ions into the sidewalls of the insulating trenches.

Figures 3A to 3E show the method of preparing etched openings through the nitride layer placed on the top surface of the IC substrate.

Figures 4A to 4E show a method of implanting ions into the sidewalls of the insulating trench using the processing steps as in the first embodiment of the present invention.

Figures 5A to 5E show a method of implanting ions into the sidewalls of the insulating trenches using the processing steps as in the second embodiment of the present invention.

3A to 3E show the steps of preparing etched openings through the nitride layer 12 placed on the top surface of the substrate 10. These steps can be applied to the first and second embodiments of the present invention.

Initially, a substrate 10 as shown in Figure 3A is provided. Preferably, the substrate 10 is silicon (Si). The surface of the substrate 10 is clean, and a pad oxide layer 11 of 10 to 60 nm is thermally grown on the surface of the substrate 10, preferably silicon oxide (SiO₂), as shown in Figure 3B.

A CVD silicon oxide layer can be used instead of the thermally grown silicon oxide layer as another silicon oxide layer. The advantage of the CVD silicon oxide layer is that it can be about 25% of the thickness of the thermal oxide underlayer, because the CVD silicon oxide layer is more effective in avoiding edge defects. In addition, a cushion layer containing a thin thermal silicon oxide layer and a buffer polysilicon layer can also replace the thermally grown silicon oxide layer.

Secondly, 100 to 200nm thick CVD silicon nitride (Si₃N₄) Layer 12. The function of the pad oxide layer 11 (also referred to as a buffer oxide layer) is to relax the stress transfer between the substrate 10 and the nitride layer 12. The function of the nitride layer 12 is like an oxide mask. Silicon nitride is effective in this function, because oxygen and water vapor diffuse very slowly when passing through silicon nitride, preventing oxide species from reaching the silicon surface under the nitride.

As shown in FIG. 3D, a photoresist mask layer 13 is deposited on the top surface of the nitride layer 12. The area of the nitride layer 12 exposed through the mask layer 13 is dry-etched anisotropically. The field region 22 for subsequent ion implantation is defined through the etched opening of the nitride layer 12 (see FIG. 3E).

In the first preferred embodiment of the present invention, the photoresist mask layer 14 is deposited on the top surface of the nitride layer 12 to expose the field area requiring ion implantation. For example, in terms of complementary metal oxide semiconductor (CMOS), the mask layer 14 is exposed to use such as B, BF₂Or BCl₂During ion implantation of ions or any combination thereof. The field area for the n-channel metal oxide semiconductor (NMOS) process, and the mask layer 14 is exposed to the field for the P-channel metal oxide semiconductor (PMOS) process during ion implantation using, for example, P, Sb, or As ions or any other combination area.

FIGS. 4A and 4B show a situation in which ions are implanted into the substrate 10 through the field region 22 to form an implanted region 23 in the substrate 10. The implanted region 23 is subsequently heat-treated (ie, tempered), and as a result, the dopant diffuses laterally into the doped region 24 having a larger width than the implanted region 23. At this time, the controlled diffusion of the implanted region 23 reduces the amount of diffusion that occurs during the subsequent thermal cycle, thereby allowing it to be used for the purpose of better control of the active width of the parasitic transistor.

Because the width of the doped region 24 shown in FIG. 4C is larger than the width of the field region 22, when the substrate 10 is etched to form the trench 20 as shown in FIG. 4D, a portion 25 of the doped region 24 is left . The trench 20 is formed by reactive ion etching of the substrate 10. The remaining part of the nitride layer 12 functions as a mask during reactive ion etching. After the trench is formed, the nitride layer 12 and the pad oxide layer 11 are removed to form the device of FIG. 4E.

According to the second preferred embodiment of the method of the present invention, the device shown in Figure 3E is also used. In the second preferred embodiment, the CVD oxide layer 15 (shown in Figure 5A), which can be SiO₂Or any other material with an etching selectivity different from that of the silicon substrate and silicon nitride is deposited on the surface of the remaining part of the nitride layer 12 and the exposed area of the pad oxide layer 11. The CVD oxide layer 15 is anisotropically etched to form a pair of oxide spacers 16.

The width of the bottom of each oxide spacer 16 is the same as the thickness of the deposited CVD oxide layer 15, as shown in FIG. 5B. Therefore, the thickness of the deposited CVD oxide layer 15 is determined by the required bottom gap between the oxide spacers 16 equal to the required groove width, because the oxide spacer 16 functions as a mask during the trench etching step screen.

Ions are directly implanted in the area between the oxide spacers 16 to form an implanted area 23. In addition, the photoresist mask layer 14 can be deposited on the top surface of the nitride layer 12 to expose only the field area that requires ion implantation. For example, in terms of complementary metal oxide semiconductor (CMOS), the mask layer 14 is exposed to use such as B, BF₂, Or BCl₂During ion implantation of ions or any other combination, the field area for the NMOS process and the mask layer 14 are exposed during ion implantation using, for example, P, Sb or As ions or any other combination. The field area of the positive metal oxide semiconductor (PMOS) process.

Subsequently, the implanted region 23 is heat-treated to drive the dopant laterally into the doped region 24 having a larger width than the implanted region 23. Because the doped region 24 shown in FIG. 5C has a width greater than that of the implanted region 23, when the substrate 10 is etched to form the trench 20 as shown in FIG. 5D, a portion of the doped region 24 is left Part 25. At this time, the controlled diffusion of the implanted region 23 reduces the amount of diffusion that occurs during subsequent thermal cycles, thus allowing better control of the active width portion for the purpose of isolating parasitic transistors.

The trench 20 is formed by reactive ion etching of the substrate 10. The remaining part of the nitride layer 12 and the oxide spacer 16 function as a mask during the reactive ion etching. After the trench is formed, the nitride layer 12, the pad oxide layer 11, and the oxide spacer 16 are removed to form the device of FIG. 5E.

In the two embodiments, another option for the ion implantation and heat treatment steps is to dope the upper edge of the trench by diffusion (ie, by a gas or some solid source) before forming the trench.

Although the specific embodiments of the present invention have been described and described above, it is clear that the present invention can have various forms and specific embodiments within the scope of the appended patent application.