Surface discharge plasma display apparatus with multiple address lines per column and method of driving the same allowing simultaneous selection of several scan lines

Plasma display panel, driving method thereof and plasma display device

The present invention relates to a surface discharge AC plasma panel, a driving method thereof, and a plasma display device using the same.

A plasma display panel (PDP) has good visibility, is thin, and can be made into a large screen and a high speed display because it produces its own light. For this reason, it has attracted the interest of replacing CRT displays. In particular, a surface discharge AC PDP is suitable for full color display. Therefore, its demand for high-quality images in the field of high vision is increasing. Higher quality images are achieved by black areas that produce higher definitions, higher numbers of gradations, better brightness, lower brightness, and higher contrast. The high definition is achieved by narrowing the pixel distance, the higher number of orders is achieved by increasing the number of sub-fields within a frame, the higher brightness is achieved by increasing the number of sustained discharges, and the darker The lower brightness is achieved by reducing the amount of light emitted during resetting.

Fig. 30 shows a schematic structure of a surface discharge AC plasma display panel (PDP) 10P of the prior art.

On one of the glass substrates facing each other on the side of the observer, the electrodes X1 to X5 are set in parallel and equidistant from each other, and the electrodes Y1 to Y5 are set in parallel with each other, and are formed with the corresponding electrodes X1 to X5. Parallel pairs. On the other glass substrates, the address electrodes A1 to A6 are set in a direction extending at right angles to the aforementioned electrodes, and the phosphorescent material is covered thereon. Between the glass substrates facing each other, the partition walls 171 to 177 and the partition walls 191 to 196 are arranged to intersect each other in a lattice to ensure that there is no erroneous display due to the discharge of one pixel affecting adjacent pixels. And was formed.

The surface discharge PDP has the benefit that since the discharge system occurs on adjacent electrodes on the same surface, it does not degrade the quality due to the influence of ions on the phosphor. However, since a pair of electrode systems are provided for each of the display lines L1 to L5, the extent to which the pixel pitch can be reduced is limited, and this is an obstacle to achieving a high definition. In addition, since it has a high number of electrodes, the size of its driving circuit must be large.

In order to cope with this problem, the PDP 10Q shown in Fig. 31 has been disclosed in Japanese Patent Publication No. 5-2993 and No. 2-220330.

In the PDP 10Q, partition walls 191 to 199 are provided on the center lines of the electrodes X1 to X5 and Y1 to Y4, which are surface discharge electrodes, except for the electrodes X1 and X5 on both sides (ie, the electrodes X2 to X4 and electrodes Y1 to Y4) are used in common by the display lines in the direction in which the address electrodes are adjacent. By this, the number of electrodes is almost halved and the pixel pitch can be lowered to a higher definition than the PDP shown in Fig. 30. In addition, the size of the drive electrode can also be halved.

However, in the above-mentioned publication, since the writing of the display lines L1 to L8 is performed in a linear order, if the partition walls 191 to 199 are omitted, the discharge affects adjacent pixels in the direction of the address electrodes, resulting in The wrong display. Thus, the partition wall cannot be omitted, and this pair appears as an obstacle to achieve a higher definition by reducing the pixel pitch. Furthermore, it is not easy to provide a dividing wall at the center line of the electrodes to provide a dividing wall, and as a result, the production of the PDP 10Q will be expensive. Further, in the above publication, the special type of voltage to be applied to the electrodes is not disclosed, and as a result, the invention has not been put to practical use. In order to make it possible to omit the partition walls extending in the direction of the surface discharge electrodes, the distance between the electrodes on both sides of each of the partition walls 191 to 196 must be increased in the structure shown in Fig. 30 to Reduce the effect of the electric field between these electrodes. As a result, its pixel pitch increases, preventing the achievement of higher definitions. For example, the distance between the electrodes Y1 and X2 (non-display lines) is 300 μm, and the distance between the electrodes Y1 and X2 (display lines) is 50 μm.

In addition, during the reset period, since the full screen (all pixels) is discharged, light is emitted, and the brightness in the black display area is increased, degrading the quality of the display.

Moreover, since the phosphorescent color is white or light gray, the incident light from the outside is reflected on the phosphorescent non-display line when the image of the PDP is observed in a bright position, thereby reducing the contrast of the influence.

In addition, since only one line can be located at a time, its address time cannot be reduced, and it is impossible to achieve a higher degree by increasing the number of subfields or increasing the number of times the sustained discharge is performed to achieve higher brightness. .

Accordingly, it is a comprehensive object of the present invention to provide a plasma display panel, a method of driving the same, and a plasma display device that achieve higher quality images.

To specifically illustrate, a first object of the present invention is to provide a plasma display panel, a method of driving the same, and a plasma display device that achieve a higher definition to further reduce the pixel pitch.

A second object of the present invention is to provide a plasma display panel, a driving method thereof, and a plasma display device which can increase black display by reducing discharge of a full screen (all pixels) during a reset period. quality.

A third object of the present invention is to provide a plasma display panel, a method of driving the same, and a plasma display device for reducing image contrast by reducing reflected light from a non-display line.

A fourth object of the present invention is to provide a plasma display panel, a driving method thereof, and a plasma display device which increase the number of steps and brightness by reducing the address period by simultaneously addressing a plurality of display line locations.

According to a first aspect of the present invention, there is provided a plasma display device comprising: a plasma display panel having a substrate, electrodes X1 to Xn₊₁Formed on the substrate, electrodes Y1 to Yn are formed on the substrate, and address electrodes are formed on the substrate, or another substrate, which faces the substrate at a distance, the electrodes X1 to Xn₊₁Arranged in this order and parallel to each other, an electrode Yi_i=1 to n are disposed between the electrode Xi and the electrode Xi+1, and the address electrodes are configured to be separated by a distance from the electrodes X1 to Xn₊₁And Y1 to Yn intersect; and comprising an electrode driving circuit; wherein the electrode driving circuit comprises: a first field location facility, i = 1 to n, for causing a first address discharge to occur at the electrode Yi Corresponding to the display of the data selected in the first field of a frame between the address electrodes, and for causing a discharge to occur at the electrode Yi and using the first address discharge as a trigger to generate a corresponding The first field displays the first wall charging electrode Xi required for continuous discharge of the data; the first field continues the facility, after the first wall charging has been generated, the odd number 0 between 1 and n An even number e between 1 and n for supplying a first AC sustain pulse between an electrode Yo and an electrode Xo and for supplying a second AC sustain pulse between an electrode Ye and an electrode Xe; a bit location facility, i = 1 to n, for causing a second address discharge to occur between the electrode Yi and the address electrodes selected to display data in a second field of a frame, And used to cause a discharge to occur at the electrode Yi and use the first address discharge as a trigger to Generating between the electrodes Xi+1 corresponding to the second wall charging required for the sustained discharge of the data displayed in the second field; and the second field continuing facility, after the second wall charging has been generated, An odd number 0 between n and an even number e between 1 and n for supplying a third AC sustain pulse between an electrode Yo and an electrode Xo+1 and for supplying between an electrode Ye and an electrode Xe+1 A fourth AC continues to pulse.

In the first aspect of the present invention, since the display lines in the odd fields and the display lines in the even fields can be mutually affected without being affected by the discharge, they do not have to follow the plasma display panel. The electrodes X1 to X on_n+1A partition wall is provided on the center line of the electrodes Y1 to Yn. Thus, the production of the plasma display panel is promoted, the production cost is lowered, and the pixel pitch is lowered, and a higher definition can be achieved.

In the first mode of the first aspect of the present invention, the first field continues to supply the first and second AC sustain pulses, and ensures that the voltage waveforms applied to the electrodes Yo and Xe have the same phase with each other. The voltage waveforms applied to the electrodes Ye and Xo have the same phase with each other, and the first and second AC sustain pulses have phases opposite to each other; and the second field continues to supply the third and fourth AC sustain pulses, While ensuring that the voltage waveforms applied to the electrodes Yo and Xo have the same phase with each other, the voltage waveforms applied to the electrodes Ye and Xe have the same phase with each other, and the third and fourth AC sustain pulses have phases opposite to each other.

The first modality is valid because the display lines in the odd fields and the display lines in the even fields can be mutually influential in terms of achievement discharge.

In the second mode of the first aspect of the present invention, the first fixed field address device applies a DC voltage to all of the X1 to Xn in a first period.₊₁An odd number of electrodes between the electrodes, and applying one of the opposite polarity voltages to the DC voltage to the electrode Yo, and applying the DC voltage to all of the X1 to X during a second period_n+1An even number of electrodes, and applying one pulse of opposite polarity to the DC voltage to the electrode Ye; and the second fixed field address device applies a DC voltage to all of the X1 to Xn during a third period₊₁An even number of electrodes between the electrodes, and applying one of the opposite polarity voltages to the DC voltage to the electrode Yo, and applying the DC voltage to all of the X1 to X during a fourth period_n+1An odd number of electrodes are interposed and a pulse of one of the opposite polarity is applied to the DC voltage to the electrode Ye.

In the second mode, only a pulse having a large width is required to provide the odd-numbered fields and the even-numbered fields to the electrodes X1 to X during each address period._n+1Each of the odd and even groups. Thus, the power consumption must be reduced compared to the case where the pulse is supplied to the groups for each of the Y1 to Yn scans. Further, the structure of the electrode driving circuit can be simplified.

In a third mode of the first aspect of the present invention, the first field location facility applies a voltage having opposite polarities to the electrodes Yi and Xi when causing a discharge between the electrode Yi and the electrode Xi to occur; and The second field positioning device applies a voltage having a polarity opposite to each other to the electrodes Yi and Xi when causing a discharge between the electrode Yi and the electrode Xi to occur.₊₁。

In the third mode, since only the required pulses are supplied to the electrodes X1 to X during the address period_n+1The power consumption must be supplied to the electrodes X1 to X in common to the pulses._n+1The case of odd groups and even groups is reduced.

In the fourth mode of the first aspect of the present invention, the first and second field location facilities include: a first continuous circuit for outputting a first voltage waveform of a DC pulse train; and a second continuous The circuit is configured to output a second voltage waveform with a phase offset from the phase of the first voltage waveform by 180° C. a switching circuit having a switching component for selectively supplying the first or second voltage waveform to the electrodes Yo, Ye, Xo and Xe; and a control circuit for controlling the switching element of the switching circuit in such a manner that after the first wall charging has been generated, the first voltage waveform is supplied to the electrodes Yo and Xe And the second voltage waveform is supplied to the electrodes Ye and Xo, and after the second wall charging has been produced, the first voltage waveform is supplied to the electrodes Ye and Xo and the second voltage waveform is supplied to The electrodes Ye and Xo.

In the fourth mode, since the voltage waveforms from the first sustaining circuit and the second sustaining circuit are selectively supplied to the electrodes Yo, Ye, Xo and Xe; the structure of the electrode driving circuit can be simplified. .

In the fifth mode of the first aspect of the present invention, the first field and the second field comprise a plurality of sub-fields, having a plurality of sustain discharge pulses different from each other, and the electrode driving circuit further The method includes: a first field resetting facility, before the first address of the first field of the first field is discharged, and i=1 to n, for causing a discharge to occur at the electrode Yi and the electrode Between Xi and the electrode Yi and the electrode Xi, the wall discharge is eliminated for all the pixels or the wall discharge is generated for all the pixels; and before the first address of the remaining fields of the first field is discharged, and 1 to n The odd number o and the even number between 1 and n have been used to cause a discharge D1 to occur between the electrode Yo and the electrode Xo, and a discharge D2 to have a time difference from the discharge D1 between the electrode Ye and the electrode Xe. Eliminating or generating wall discharges only for pixels in the first field; and second field resetting facility, before the second address of the first field of the second field is discharged, and i=1 Up to n, for causing a discharge to occur between the electrode Yi and the electrode Xi and between the electrode Yi and the electrode Xi There are pixels to eliminate wall discharge or to generate wall discharge for all pixels; before the second address of the remaining field in the second field is discharged, and the odd number between 1 and n and the even number between 1 and n have been Used to cause a discharge D3 to occur at the electrode Yo and the electrode Xo₊₁Between each discharge D4, a time difference from the discharge D3 occurs at the electrode Ye and the electrode Xe.₊₁In the meantime, the wall discharge is eliminated or generated only for the pixels in the first field.

In the fifth mode, since the unnecessary light emission is reduced, the brightness of the black display is lowered to improve the quality of the black display.

In the sixth mode of the first aspect of the invention, the electrodes X1 to Xn₊₁Each of Y1 to Yn includes: a transparent electrode is disposed on the substrate; and a metal electrode is disposed on the transparent electrode along a center line of the transparent electrode at a smaller width than the transparent electrode.

In the sixth mode, the configuration of each display line is made identical.

According to a second aspect of the present invention, there is provided a plasma display device comprising: a plasma display panel having a substrate, electrodes X1 to X2n being formed on the substrate, electrodes Y1 to Yn being formed on the substrate, and An address electrode is formed on the substrate or another substrate that faces the substrate at a distance, the electrodes Xo, Yi and Xe being arranged in this order and parallel to each other, wherein o=2i-1, e=2i and i=1 to n, the address electrodes are configured to intersect the electrodes X1 to X2n and Y1 to Yn at a distance; and an electrode driving circuit; wherein the electrode driving circuit comprises: an odd frame positioning device, o=2i-1 and i=1 to n for causing a first address discharge to occur between the electrode Yi and an address electrode selected to display data in an odd frame and to cause a discharge Occurring between the electrode Yi and the electrode Xo, using the first address discharge as a trigger corresponding to displaying data in an odd frame to generate a first wall charge for a sustained discharge; odd frame continuous facility , on o=2i-1 and i=1 to n, for charging on the first wall has been generated Thereafter, a first AC continuous pulse is supplied between the electrode Yi and the electrode Yo; and an electrode driving circuit; wherein the electrode driving circuit comprises: an even-numbered frame location facility, where o=2i and i=1 to n, To cause a second address discharge to occur between the electrode Yi and the address electrode selected to correspond to the display of data in an even frame, and to cause a discharge to occur between the electrode Yi and the electrode Xe, the use thereof The second address discharge acts as a trigger corresponding to the display of data in an even frame to generate a second wall charge for a sustained discharge; the even frame continues the facility, ie o=2i and i=1 to n, After the first wall charging has been generated, a second AC sustain pulse is supplied between the electrode Yi and the electrode Ye.

In the second aspect of the present invention, since the display lines in the odd fields and the display lines in the even fields can be mutually affected without being affected by the discharge, they do not have to follow the plasma display panel. The electrodes X1 to X on_n+1A partition wall is provided on the center line of the electrodes Y1 to Yn. Thus, the production of the plasma display panel is maintained, the production cost is reduced, and the pixel pitch is allowed to be lowered, which supports a higher definition.

At the same time, since the two display lines are formed with three parallel electrodes, the pixel pitch can be lowered by forming a parallel electrode than the conventional display circuit, and it is possible to achieve a higher definition. Further, since it is not necessary to divide the electrodes Y1 to Yn into even and odd groups, the configuration thereof is simplified.

Moreover, under the inter-frame strip scan, the address period can be reduced by half compared to the length of the non-interlace scan for a sustained discharge period. This makes it possible to increase the number of gradations by increasing the sub-frame, or to make it possible to achieve a higher brightness by increasing the number of times the sustain discharge is performed.

In the first mode of the second aspect of the present invention, the electrodes Xo, Yi and Xe have an actual symmetrical form with respect to the center line of the electrode Yi; each of the electrodes has a transparent electrode formed on the substrate And a metal electrode is formed on the transparent electrode with a width smaller than the transparent electrode; and the metal electrodes of the electrodes Xo, Xe are disposed on a side away from the electrode Yi.

In the first mode, since a voltage is applied between the electrodes Xo and Yi, for example, the electric field on the Xo becomes stronger on the side of the metal electrode, and the pixel pressure thereof is higher than the metal electrode The case where the transparent electrode is formed can be fundamentally increased, and even its electrode pitch is lowered to achieve a higher definition. Since the sides of the electrodes Xo and Xe opposite to the electrode Yi are non-display lines, there is no problem, and since the non-display line can be substantially narrowed, this is desirable.

In the second mode of the second aspect of the present invention, the electrodes Xo, Xi and Xe have an actual symmetrical form with respect to the center line of the electrode Yi; the electrode Yi is a metal electrode formed by the substrate; the electrodes Each of the metal electrodes has a transparent electrode formed on the substrate, and a metal electrode is formed on the transparent electrode at a width smaller than the width of the transparent electrode; and the metal electrodes of the electrodes Xo, Xe are disposed away from the electrode Yi The side.

In this second mode, since the width of the electrode becomes small, the power consumption of supplying the scan pulse to the electrode Yi is lowered. In addition, it is possible to further reduce its pixel pitch.

In a third aspect of the invention, there is provided a plasma display panel comprising a substrate continuous electrode for sustained discharge, which is formed in parallel with each other, and an address electrode is formed on the substrate or another a substrate facing the substrate at a distance, the address electrodes being configured to intersect the continuous electrodes in parallel with each other at a distance, the plasma display panel further being between the adjacent electrodes of the continuous electrodes The non-display line includes a light blocking member.

Under the use of the light-disscision member on the third level, the degradation of the black display quality caused by the discharge of the discharge light on the non-display line can be reduced.

In a first mode of the second aspect of the invention, the address electrodes are covered with phosphorescence, and the next viewer side of the light blocking member has a darker color than the adjacent light.

In the first mode, since the incident light from the outer side to the phosphorescent material on the non-display line is absorbed by the light blocking member, one of the PDPs affects the contrast in the bright portion, and the outer side to the phosphorescent material is in the non- The situation in which the incident light of the display line is reflected and enters an observer's eye is increased a lot.

In a fourth aspect of the present invention, there is provided a plasma display device comprising: a plasma display panel having a substrate, electrodes X1 to Xn being formed on the substrate, and electrodes Y1 to Yn being formed on the substrate, The address electrode is formed on the substrate or another substrate, which faces the substrate at a distance, and a light blocking member interposed between the electrodes Yi and Xi₊₁Where i = 1 to n-1, the electrodes Xi and Yi are arranged in parallel in groups of three, wherein i = 1 to n; and an electrode driving circuit; wherein the electrode driving circuit comprises: a resetting facility i=1 to n-1 for causing a discharge to occur at the electrode Yi and the electrode Xi₊₁And ensuring that the voltage waveforms applied to the electrodes Xi and Yi are in the same phase with each other, and the voltage waveforms applied to the electrodes Xn and Yn are in the same phase with each other during a reset period; i=1 to n, which is used to cause a single address discharge to occur between the electrode of the address selected by the electrode Xi or Yi and the corresponding display material and cause a discharge to occur between the electrode Xi and the electrode Yi. The address is discharged as a trigger to generate a wall discharge corresponding to the display data in the address period during the reset period, and a continuous discharge, i=1 And n, for supplying an AC continuous pulse to the electrode Xi and the electrode Yi after the address period has elapsed.

Under the use of the light beam breaking member at the third level, the reduction in black display quality caused by discharge light emission on the non-display line during a reset period can be reduced. Although the light blocking member slightly prevents the achievement of a higher definition in comparison with the configuration of the prior art shown in Fig. 30, since it is not necessary to form the partition walls 191 to 196, the production thereof can be promoted, and the pixel thereof The distance can be further reduced.

In a fifth aspect of the invention, there is provided a plasma display panel comprising a substrate, an address electrode beam being formed along the substrate, and a scan electrode for the address electrode bundles and the like Discharging is caused between the scan electrodes to produce a wall discharge required to sustain discharge corresponding to the display data, the scan electrodes intersecting the address electrode bundles at a distance, wherein each of the address electrode bundles comprises: m Address electrodes (m2) corresponding to a monochromatic pixel row being formed on the substrate along each other; the spacers are disposed along the longitudinal direction of the address electrodes corresponding to each of the monochromatic pixels, the pads The pads are above the m address electrodes with respect to the base system; and the contacts are used to connect a pad to one of the address electrodes along the longitudinal direction of the address electrodes in a normal manner.

In the fifth layer, selecting m scanning electrodes to simultaneously intersect the pads connected to the m address electrodes; and simultaneously applying a voltage corresponding to the display data to the m address electrodes; scanning electrodes The scanning is performed in units of m lines.

Under this fifth level, several lines can be located at the same time, narrowing down the address, and therefore, a higher number of gradations becomes possible by increasing the number of sub-fields, or by increasing the sustained discharge. It is possible to achieve a higher brightness with the number of rows.

1 is a schematic view showing the configuration of a surface discharge PDP in the first embodiment according to the present invention; and FIG. 2 is a perspective view showing a state in which the opposite surface of the color pixel in the PDP shown in FIG. 1 is shown. The area between the three; FIG. 3 is a longitudinal cross-sectional view of the PDP along the first electrode ×1; one color pixel; FIG. 4 is a block diagram showing theThe pictorial configuration of a plasma display device in the first embodiment; the fifth diagram shows the construction of a frame; and the sixth (A) and 6 (B) diagrams show the order in which the display lines are scanned during the address period. Figure 7 is a waveform diagram of the voltage applied to the electrodes in an odd field for illustrating the method of driving the PDP in the first embodiment of the present invention; and Figure 8 is the voltage applied to the electrodes in an even field. a waveform diagram for explaining a method of driving a PDP according to the first embodiment of the present invention; and FIG. 9 is a block diagram showing a schematic configuration of a plasma display device according to the second embodiment of the present invention; Figure 10 is a waveform diagram of the voltage applied to the electrodes in an odd field for illustrating the method of driving the PDP in accordance with the second embodiment of the present invention; and Figure 11 is a diagram of the voltage applied to the electrodes in an odd field. Waveform diagram for explaining a method of driving a PDP according to a second embodiment of the present invention; FIG. 12 is a block diagram showing a pictorial diagram of a plasma display apparatus according to the third embodiment of the present invention; FIG. a block diagram showing the fourth embodiment in accordance with the present invention. Fig. 14 is a diagram showing the waveform of the output voltage of the sustain circuits 31 and 32 in Fig. 13 and the voltage waveform applied to the address electrodes in the odd field in Fig. 7; Fig. 15 A block diagram showing a schematic configuration of a plasma display device in a fifth embodiment according to the present invention; and FIG. 16 is a waveform diagram of a voltage applied to an electrode in an odd field for explaining a driving basis A method of inventing a PDP in a sixth embodiment; FIG. 17 is a waveform diagram of a voltage applied to an electrode in an even field for explaining a method of driving a PDP according to a sixth embodiment of the present invention; a block diagram showing a schematic configuration of a plasma display device in a seventh embodiment according to the present invention; and a 19th view showing a longitudinal cross-sectional view of a portion of the PDP along the address electrodes shown in FIG. 18; FIG. Shows the order in which the display lines are scanned during the address period; Figure 21 shows the structure of a frame; Figure 22 shows a waveform of the voltage applied to the electrodes in an odd field to illustrate the basis of the drive. Method of PDP in seventh embodiment of the present invention; 23 is a waveform diagram of a voltage applied to an electrode in an even field for explaining a method of driving a PDP according to a seventh embodiment of the present invention; and FIG. 24 is a portion of the PDP in the eighth display along the same Longitudinal cross-sectional view of the address electrode; Fig. 25 shows a schematic configuration of a surface discharge according to the ninth embodiment of the present invention; and Fig. 26 is a schematic voltage waveform diagram applied to the electrodes, illustrating driving according to the present invention In the nine embodiments

Referring now to the drawings in which like reference numerals refer to the

Figure 1 shows a PDP 10 in accordance with a first embodiment of the present invention. In the first figure, the pixel is only indicated by a broken line on the display line L1. To simplify the explanation, the number of pixels of the PDP 10 is 6 × 8 = 48 monochrome pixels. The present invention is applicable to color and monochrome pixels, and three color pixels correspond to one color pixel.

In order to promote production and achieve a higher definition by reducing the pixel pitch, the PDP 10 has a structure in which the partition walls 191 to 199 in the PDP 10Q as shown in Fig. 31 are removed. In order to ensure that the erroneous discharge between adjacent display lines does not occur in addition to the partition walls, the strip scanning is carried out by performing a surface discharge between the electrodes L1 to L8 which will be explained later. The waveform phases of the continuous pulse voltages of the odd-numbered lines and the even-numbered lines are opposite to each other (in the strip scanning of the prior art, since the lines L2, L4, L6, and L8 are non-display lines, the lines L1 and L5 are in the odd-numbered fields. Scan and lines L3 and L7 are scanned in even fields).

Fig. 2 shows a state in which the distance between the opposite surfaces of a color pixel 10A is enlarged. Fig. 3 shows a longitudinal cross section of the color pixel 10A along the electrode X1.

On a surface of a glass substrate 11 (a transparent substrate as an insulator), transparent electrodes 121 and 122 made of an ITO film or the like are provided in parallel with each other to cause voltages of the transparent electrodes 121 and 122 along the longitudinal direction. When the reduction is minimized, metal electrodes 131 and 132 made of copper or the like are formed along the center lines of the transparent electrodes 121 and 122, respectively. The transparent electrode 121 and the metal electrode 122 constitute the electrode X1, and the transparent electrode 122 and the metal electrode 132 constitute the electrode Y1. A bipolar substrate 14 for holding wall charges covers the glass substrate 11 and the electrodes X1 and Y1. The bipolar substrate 14 is covered by the MgO protective film 15.

On the surface of the glass substrate 16 of the MgO protective film 15, the address electrodes A1A2 and A3 are formed in a direction extending at right angles to the electrodes X1 and Y1, and are partitioned by the partition walls 171 to 173. When ultraviolet light is generated during discharge and enters the phosphor, a phosphor 181 emitting red light, a phosphor 182 emitting green light, and a phosphor 183 emitting blue light blue cover the partition wall 171 and the partition wall, respectively. 172, partition wall 172 and partition wall 173 and the area between partition wall 173 and partition wall 174. The discharge space between the phosphorescent materials 181 to 183 and the MgO protective film 15 is filled with, for example, a Penning gas mixture of Ne + Xe.

The partition walls 171 to 174 prevent the ultraviolet light generated at the time of discharge from entering the adjacent pixels, and also function as a spacer forming the charging space. If the phosphors 181 to 183 are composed of the same substrate, the PDP will be a monochromatic display.

Fig. 4 is a view showing the structure of the plasma display device 20 of the PDP having the above structure.

A control circuit 21 converts the display data DATA supplied from the outside into the data for the PDP 10, supplies it to the shift register of the address circuit 22, and provides a clock signal CLK and a vertical sync signal VSYNC according to the outside world. Various control signals are generated with a horizontal synchronizing signal HSYNC, which are supplied to the elements 22 to 27.

In order to apply voltages having waveforms shown in FIGS. 7 and 8 to the electrodes, voltages Vaw, Va and Ve are supplied to the address circuit 22 and voltages -Vc, -Vy and Vs are supplied to an odd number. Y continuation circuit 24 and an even Y continuation circuit 25, and voltages Vw, Vx and Vs are supplied to an odd X continuation circuit 26 and an even X continuation circuit 27, all of which are supplied by a power source circuit (power supply circuit) 29 Come.

Figure 4 shows the values in shift register 221 used to identify elements that are structurally identical to each other. For example, 221(3) represents the third bit of shift register 221, which is also applied to other components. element.

In the address circuit 22, when the display material corresponding to a line has been supplied to the shift register 221 in series by the control circuit 21 during the address period, the bit 221(1) to the bit 221 ( 6) switching elements (not shown) in bits 222(1) through 222(6) of latch circuit 222, respectively, and corresponding to their values, in drivers 223(1) through 223(6) ) is controlled by ON/OFF, and a two-shift voltage model (whose voltage is Va or OV) is supplied to the address electrodes A1 to A6.

A scan circuit 23 is provided with a shift register 231 driver 232. During an address period, 1 is supplied to the serial data input of shift register 231 to initiate an address period only for each VSYNC period, and then it is shifted in synchronization with the address period. Bit. The ON/OFF control is implemented by the switching elements (not shown) in the drivers 232(1) to 232(6) in the values of the bits 231(1) to 231(4) in the shift register 231, and are The selected voltage -Vy or the unselected voltage -Vc is applied to the electrodes Y1 to Y4. In other words, the electrodes Y1 to Y4 are sequentially selected by the shift operation of the shift register 231, and the selected voltage -Vy is applied to the selected electrode Y, and the unselected voltage -Vc is applied to the unselected Select electrode Y. These voltages -Vy and -Vc are provided by an odd Y continuation circuit 24 and an even Y continuation circuit 25. During a duration, a first sustain pulse train is supplied by the odd-numbered continuation circuit 24 to the odd-numbered electrodes Y1 and Y3 of the Y electrode via drivers 232(1) and 232(3), and one phase is caused by the first sustain pulse The trainer is shifted by an even Y continuous circuit 25 in a second sustain pulse of 180 ° C, supplied to the even electrodes Y2 and Y4 of the Y electrode via drivers 232 (2) and 232 (4).

In the circuit for the X electrode, during the duration, the second sustain pulse is supplied from the odd X sustain circuit 26 to the odd electrodes X1, X3 and X5 of the X electrode, and the first sustain pulse is an even X continuous circuit 27 is supplied to the even electrodes X2 and X4 of the X electrode. During a reset period, a full screen (all pixels) write pulse is supplied to the electrodes X1 to X5 in common by the X sustain circuits 26 and 27, respectively. In the case of an address period, corresponding to the scan pulse, a pulse train is provided for two address periods, and the odd-numbered X sustain circuit 26 supplies the odd-numbered electrodes X1, X3 and X5 of the X electrode, and one phase thereof is as described above. The pulse trainer is shifted by a pulse train of 180 ° C, and is supplied from the even X sustain circuit 27 to the even electrodes X2 and X4 of the X electrode.

The above circuits 223, 232, 24, 25, 26 and 27 are switching circuits for switching the ON/OFF voltage supplied from a power source circuit 29.

Figure 5 shows the structure of one of the frames of the display image.

This box is split into two fields, an even field and an odd field, and each field contains the first to third sub-fields. For each subfield, the voltage having the waveform shown in Fig. 7 is supplied to the various electrodes of the PDP 10 in the odd field to the display lines L1, L3, L5 and L7 shown in Fig. 1. And the voltage having the waveform shown in Fig. 8 is supplied to the various electrodes of the PDP 10 in the even field to the display lines L2, L4, L6 and L8 shown in Fig. 1. The durations in the first to third subfields are T1, 2T1 and 4T1, respectively, and in each subfield, the number of times the sustained discharge is performed corresponds to the length of the duration. Under this, its brightness will have eight gradations. Similarly, in the case where the number of subfields is 8 and the duration is 1:2:4:8:16:32:64:128, the brightness award has 256 gradations.

At the time of the address period, the scanning of the display line is carried out in the order of the number assigned in the sixth (A) diagram. That is, in the case of odd fields, scanning is performed in the order of display lines L1, L3, L5, and L7, and in the case of even fields, scanning is performed in the order of display lines L2, L4, L6, and L8.

Next, the job in the odd field is explained with reference to FIG. In Fig. 7, W, E, A and S represent the time points at which full-screen write discharge, full-screen self-wipe discharge, address discharge and continuous discharge occur, respectively. Thereafter, for the sake of simplicity, the following overall items are used:

X electrode: electrode X1 to X5

Odd X electrodes: electrodes X1, X3 and X5

Even X electrodes: electrodes X2 and X4

Y electrode: electrodes Y1 to Y4

Odd Y electrode: electrodes Y1 and Y3

Even Y electrodes: electrodes Y2 and Y4

Address electrode: address electrode A1 to A6

and,

Vfxy: discharge starting voltage between adjacent X electrodes and Y electrodes.

Vfay: The discharge starting voltage between the address electrodes and the ones provided by Y facing each other.

Vwall: The voltage (wall voltage) between the positive wall charging and the negative wall charging due to wall charging due to discharge between adjacent X electrodes and Y electrodes.

Examples are Vfxy=290V and Vfxy=180V. Further, a region between the address electrode and the Y electrode is referred to as a region between the AY electrodes, and this reference system is applied to a region between other electrodes.

During a reset period, the voltage waveforms of the X electrodes supplied to the full screen write pulse are the same as each other, and the voltage waveforms supplied to the Y electrodes are identical to each other at OV, and are supplied to the address of the intermediate voltage pulse. The voltage waveforms of the electrodes are the same as each other.

Initially, the voltage applied to each electrode is set to OV, due to the last sustaining pulse of the duration during the reset period, positive pixel charging occurs near the X electrode for the illuminated pixel ( On the side of the X-electrode, the MgO protective film 15 is charged with a negative wall charge on the MgO protective film 15 near the Y electrode (on the side of the Y-electrode). A pixel that is illuminated by almost no wall charging appears on the side of the X-electrode or on the side of the Y-electrode.

At atb, a reset pulse of voltage Vw is supplied to the X electrode and an intermediate voltage pulse of a voltage of Vaw is supplied to the address electrode. An example is Vw=310V and Vw>Vxyo, regardless of whether it has any wall charging, a full screen write discharge W is generated between adjacent XY electrodes (ie, between the XY electrodes showing lines L1 to L8)^-The resulting electron is absorbed by the electric field caused by the voltage Vw between the positive ion XY electrodes to generate wall discharges of opposite polarity. This reduces the electric field strength in the discharge space to suspend the discharge for 1 to several μs. The voltage Vaw is approximately Vw/₂And since the absolute values of the voltage between the AX electrodes and the voltages of the AY electrodes which are opposite in phase are almost equal to each other, the average wall charge remaining on the phosphor due to the discharge is about zero.

When the reset pulse falls at t=b, that is, when the applied voltage having the opposite polarity to the wall voltage is dissipated, the wall voltage Vwall between the XY electrodes becomes larger than the discharge start voltage Vfxy to cause a full screen self-wiping Discharge E. At this time, since the X electrode, the Y electrode, and the address electrode are both 0, almost no wall charge is generated by the discharge, and ions and electrons are combined in the discharge space to be one and are almost neutralized in the space. . Some residual floating charge may be maintained, but the function of this floating space charge is to charge and discharge the storage element to a potential suitable for writing, which results in easier discharge at the next address discharge. This is known as the Priming effect.

During the address period of one address, the voltage waveforms applied to the X electrodes of the field are the same as each other, the voltage waveforms applied to the even X electrodes are identical to each other, and the voltage waveform applied to the unselected Y electrodes is - The voltage of Vc is the same as each other. The Y electrodes are selected in the order of Y1 to Y4, and a scan pulse of a voltage of -Vy is supplied to the selected electrode, and a voltage of the unselected electrode is set to -Vc. An example of this is Vc = Va = 50V and Vy = 150V.

(ctd) A scan pulse having a voltage of -Vy is supplied to the electrode Y1 and a pixel having a voltage of Va is supplied with a pulse to be supplied to each of the address electrodes.

The following relationship: Va + Vy > Vfay is satisfied, and the address discharge occurs only for the pixel to be lit, and the discharge is terminated by a generated wall charging with an opposite polarity. At the time of discharge of this address, the pulse of voltage Vx is supplied only to the electrodes X1 and X2 adjacent to the electrode Y1. If the discharge start voltage between XY triggered by the discharge of this address is represented by Vxyt, the following relationship: Vx+Vc<Vxyt<Vx+Vy<Vfxy is satisfied, and a discharge discharge X1-Y1 in the display line L1 is satisfied. The interelectrode occurs. The discharge is then terminated by a generated wall charge which is insufficient to cause self-discharge and has opposite polarity between the X1-Y1 electrodes. On the other hand, the write discharge does not occur between the X2-Y1 electrodes in the display line L2.

(dte) A scan pulse having a voltage of -Vy is supplied to the electrode Y2, a supply of voltage Vx is supplied to the even X electrode, and a write supply of a voltage of Va is turned on. The pixels are supplied to the address electrodes. Below this, in the same manner as described above, a write discharge occurs between the X2-Y2 electrodes in the display line L3, and no discharge occurs between the X3-Y2 electrodes in the display line L4.

Subsequently, the same operation as described above is carried out by etg.

Therefore, the write discharge of the display data will occur in the order of the display lines L1, L3, L5 and L7, and a positive wall charge is generated on the Y-electrode side and a negative wall charge is generated in X- Electrode side.

During a duration, the sustain pulses having the same phase and the same voltage Vs are periodic, or the first sustain supply column is supplied to the odd X electrodes and the even Y electrodes, and the phase of the first sustain column is shifted A second sustain pulse train generated at 180 ° C (1/2 cycle) is supplied to both the even X electrode and the odd Y electrode. Furthermore, in synchronization with the rise of the first sustain pulse, the voltage is supplied to the address electrodes, which is continued until the end of the duration.

(htp) A continuous pulse of voltage Vs is supplied to the odd Y electrode and the even X electrode. The effective voltage of the pixel between the odd Y electrode and the odd X electrode is Vs+Vwall, the effective voltage of the pixel between the even Y electrode and the even X electrode is Vs-Vwall, and the odd X electrode and the even Y electrode The effective voltage of the pixel between the two and the effective voltage of the pixel between the even X electrode and the odd Y electrode is 2Vwall.

The following relationship: Vs < Vfxy < Vs + Vwall, 2 Vwall < Vfxy is satisfied, a sustained discharge occurs between the odd Y electrode and the odd X electrode, and wall charging having the opposite polarity is generated to end the discharge. Continuous discharge does not occur between other electrodes. As a result, it is shown that only the odd display lines L1 and L5 in the odd field are valid. The sustained discharge between the even Y electrodes and the even electrodes does not occur at this time.

(qtr)

A continuous pulse of voltage Vs is supplied to the odd X electrode and the even Y electrode. The effective voltage of the pixel between the odd X electrode and the odd Y electrode is the Vs+Vwall of the effective voltage of the pixel between the even Y electrode and the even X electrode, and the odd Y electrode and the even X electrode The effective voltage of the pixel between the pixel and the effective voltage of the pixel between the odd X electrode and the even Y electrode are. Below this, a sustained discharge occurs between the odd X electrode and the odd Y electrode and between the even Y electrode and the even X electrode, and wall charging having the opposite polarity is generated to end the discharge. Continuous discharge does not occur between other electrodes. Subsequently, the display of all odd lines L1, L3, L5 and L7 in the odd field becomes effective immediately.

Subsequently, the sustained discharge is repeated in the above manner. At the time of the description, it is obvious that the wall shown in Fig. 7 is charged, and it is obvious that between the odd-numbered Y electrode and the even-numbered X-electrode in the non-display line and between the odd-numbered X-electrode and the even-numbered Y-electrode The effective voltage of the pixel is zero. The last sustained discharge during this duration is implemented in such a way that the polarity of charging of the wall is at its initial state during the more described reset period.

Next, the assignments in the even field are interpreted.

In Fig. 1, the display of the display lines L1, L3, L5 and L7 is valid in the odd field as explained above, and the display lines are composed of pairs of electrodes, namely electrodes Y1 to Y4 and The electrodes Y1 to Y4 are adjacent to each other and are formed adjacent to the electrodes X1 to X4 facing the upper side in the first drawing. In the even field, the display of the display lines L2, L4, L6 and L8 must be valid. The display lines are adjacent to the electrodes Y1 to Y4 and to the electrodes Y1 to Y4 and are oriented downward in the first figure. The side electrodes X2 to X5 are formed. This is achieved by reversing the roles of the electrodes X1 and X2 with respect to the electrode Y1 and reversing the roles of the electrodes X2 and X3 with respect to the electrode Y2. In other words, it is achieved by reversing the voltage waveform supplied to a group of odd-numbered X electrodes and even-numbered X electrodes. Figure 8 shows the voltage waveforms applied to these electrodes in even fields.

The operation performed in the even field is explained by the explanation up to now, and is also clear by referring to FIG. In short, during a reset period, a full screen write discharge W and a full screen self-wipe discharge E are implemented, and during the address period, the electrodes Y1 to Y4 are sequentially selected and a display data is written. The discharge is performed in the order in which the lines L2, L4, L6 and L8 are displayed, and at the same time, a simultaneous sustain discharge is repeated in these display lines L2, L4, L6 and L8.

According to the driving method in the first embodiment of the present invention, since the display lines in the odd field and the display lines in the even fields do not affect each other in terms of discharge, the PDP can utilize the PDP 10Q in FIG. The partition walls 191 to 199 are removed to facilitate the production of the PDP 10 at a reduced production cost and to achieve a higher definition by reducing the pixel pitch.

If the number of pulses in Figures 7 and 8 can be reduced, the power consumption can also be reduced. At the time of the address period, if the pulses supplied to the odd X electrodes and the even X electrodes are made continuous, the number of pulses can be lowered. This can be achieved by performing scanning in the order shown in Figure 6(B). More specifically, the display lines L1, L3, L5, and L7 in the odd field must be further divided into odd lines and even lines, and after sequentially scanning a group, the other groups must be sequentially scanned. The same procedure is implemented for even fields.

Fig. 9 shows a schematic configuration of a plasma display device 20A for carrying out this method in the second embodiment.

During the one address period, in order to perform scanning in the order of electrodes Y1, Y3, Y2 and Y4, the output of the driver 232(2) is connected to the electrode Y3, and the output of the driver 232(3) is connected to the electrode Y2. The scanning circuit 23A is different from the scanning circuit 23 shown in Fig. 4 in that the output of an odd-numbered Y-continuation circuit 24 is connected to the input of the driver 232(1) and the driver 232(2), and the output of an even-numbered Y-continuation circuit 25 It is connected to the input of driver 232 (3) and driver 232 (4). In response to this, an odd-numbered X-continuation circuit 26A and an even-numbered X-continuation circuit 27A output signals to ensure that the voltage waveforms applied to the odd-numbered X electrodes and the even-numbered X electrodes are as shown in Figures 10 and 11.

Each odd-numbered X-electrode and even-numbered X-electrode need only one pulse having a large width to be supplied during each of the odd-numbered fields or even-numbered fields, resulting in lower power consumption than the configuration shown in FIG. . Further, the configuration of the odd-numbered X-continuation circuit 26A and the even-numbered X-continuation circuit 27A is simplified as compared with the odd-numbered X-continuation circuit 26 and the even-numbered X-continuation circuit 27 shown in FIG.

Other features of the second embodiment are the same as those of the first embodiment.

In Fig. 7, a common pulse of voltage Vx is supplied to the electrodes X1, X3 and X5, and a common pulse of the voltage Vx is supplied to the electrodes X2 and X4. However, when the electrodes Y1 to Y4 are sequentially selected, it is sufficient to supply a pulse of voltage Vx to the sequentially selected electrodes X1 to X4. In this manner, the number of pulses supplied to the electrodes is reduced, and power consumption is also reduced.

In order to achieve the above-described one of the plasma display devices of the third embodiment, a sweep voltage waveform is also supplied to the X electrodes as shown in Fig. 12. The scanning circuit 30 differs from the scanning circuit 23 only in that the number of elements thereof is large only by the equivalent of one electrode.

During the address period, Bit1 is supplied to the data input in the odd field 301(1), and 1 is evenly fieldd by a control circuit 21A in a shift register 301. Bit 301(2) is provided to the data input. The output from the shift register 301 is set to zero during a reset period and a duration.

Other features of the third embodiment are the same as those of the first embodiment.

In the third embodiment according to the present invention, only pulses are supplied to the X electrodes during the address period, and power consumption can be reduced as compared with the first embodiment.

Since some of the driving voltage waveforms shown in FIGS. 7 and 8 are the same, if the control signals for obtaining the same driving voltage waveform can be output from a common circuit, the circuit configuration can be simplified.

To achieve this, in the fourth embodiment according to the present invention, a plasma display device 20C is constructed as shown in Fig. 13. In this unit, the odd-numbered Y-continuation circuit 24, the even-numbered Y-continuation circuit 25, the odd-numbered X-continuation circuit 26, and the even-numbered X-continuation circuit 27 in Fig. 4 are replaced by the sustain circuits 31 and 32 and a switching circuit 33 by the sustain circuits. As shown in Fig. 14, the waveforms S1 and S2 of the output voltages of the sustain circuits 31 and 32 are the same as those applied to the odd X electrodes and the even X electrodes as shown in Fig. 7. In Fig. 13, the switching circuit 33 is provided with switching switching elements 331 and 332 which are mutually locked, switching switching elements 333 which are locked to each other, and switching switching elements 335 and 336 which are mutually locked. These conversion switch files can be constructed with FETs on the examples. The switching control for the switching circuit 33 is performed by a control circuit 21B.

In the state shown in Fig. 13, OV is supplied to the inputs of the drivers 231(1) to 232(4), and the voltage waveforms S1 and S2 are supplied to the odd-numbered X electrodes and the even-numbered X electrodes, respectively. This corresponds to the reset period and address period in Figure 7. During this address period, the scanning circuit 23A determines the voltage waveform supplied to the Y electrodes. If the switching elements 335 and 336 are switched up, this corresponds to the reset period and the address period of FIG.

Then, the switching switching elements 331 and 332 are switched upward by the state shown in FIG. 13, and the voltage waveforms S2 and S1 are respectively supplied to the odd-numbered elements of the driver 232 and the even-numbered elements of the driver 232 and the even-numbered elements of the driver 232, and this corresponds to the Figure 7 shows the duration of the display.

Next, when the switching switching elements 335 and 336 are switched up in this state, the voltage waveforms S2 and S1 are supplied to the even and even X electrodes of the odd X electrode and the driver 232, respectively, and this corresponds to the duration of the display shown in FIG.

In the plasma display device 20C of the fourth embodiment, the same operation as that performed by the unit shown in Fig. 4 can be carried out by the simple structure of the unit shown in Fig. 4.

The characteristics of the unit shown in Fig. 13 can be applied to the plasma display device shown in Fig. 12. Fig. 15 shows a plasma display device in which these features are employed as the fifth embodiment in accordance with the present invention.

The sustain circuits 31 and 32 and the switching circuit 33 perform the same operations as those of Fig. 13 based on the control signals from the control circuit 21C.

In the plasma display device 20D of the fifth embodiment, the same operation as that performed by the unit shown in Fig. 12 can be carried out with a simpler structure than the unit shown in Fig. 4.

In the embodiment described so far, even if the even field is not displayed in the sub-field of the odd field shown in FIG. 5, a full screen write discharge W and a full screen self-wiping discharge E are in the weight. It is implemented during the period of the set. This may result in a decrease in the quality of the black display due to the unwanted emission of light. The same can be applied to the even field as well. In the sixth embodiment, in order to reduce the unnecessary light emission, a voltage having a voltage waveform shown in Figs. 16 and 17 is supplied to the electrodes.

The first subfield in Fig. 16 is the same as in Fig. 7, and during the reset period, the light emission due to the full screen discharge W and the full screen self-wiping discharge E also occurs on the non-display line. . This is necessary since the wall charging that is implemented in the previous even field must be eliminated. However, since no discharge occurs during the address period and a duration, it must cause a write discharge and self during the reset period in the second and subsequent subfields of the odd field. Wipe discharge E.

Therefore, when a reset period in the second and subsequent subfields of the odd field is used, under the cancel pulse PC of the supply voltage Vs to the even Y electrode adjacent to the odd X electrodes, The voltage between the odd X electrode and the even Y electrode is kept lower than Vfxy-Vwall to prevent discharge. At this time, if a write pulse having a voltage of Vw is supplied to the even X electrodes, the discharge does not occur between the even X electrodes and the even Y electrodes constituting any of the display lines. Therefore, the application time of this write pulse is shifted from atb to ctd. Below this, the discharge occurs between the odd-numbered Y electrodes and the even-numbered X electrodes constituting the non-display line. Thus, a cancel pulse PC having a voltage of Vs is further supplied to the odd-numbered Y electrodes. Since this cancel pulse PC is biased on the time axis by the write pulse supplied to the odd-numbered X electrodes, it does not affect the write discharge occurring between the odd-numbered X electrodes and the odd-numbered Y electrodes.

At t=a to b and t=c to d, a pulse of voltage Vaw is supplied to the address electrodes supplied in response to a write voltage supplied between the odd X electrodes and the even X electrodes . Subsequent operations from t=d are the same as when the cancellation pulse PC is not supplied as described. The reset period in the third or subsequent subfield of the odd field is also the same as the reset period of the second subfield.

The situation in which the even field and the odd field are the same is shown in FIG. In the case of the even field, as with the reason explained earlier in the first embodiment, the voltage waveforms supplied to the odd X electrode and the even X electrode in Fig. 16 need only be switched to each other. Inverse.

Figure 18 shows a plasma display device 20E in a seventh embodiment in accordance with the present invention.

The schematic configuration of the PDP 10A is the same as that of the PDP 10 shown in Fig. 1. However, the use of its electrodes is different from that shown in Figure 4. That is, the electrodes Y1, Y2 and Y3 are not distinguished into odd and even groups, but the electrodes X1, X3 and X5 adjacent to the electrodes Y1 to Y3 on one side are designated as odd X electrodes, and on the other side and the electrode Y1 The electrodes X2, X4 and X6 adjacent to Y3 are designated as even X electrodes. The strips show the odd-numbered display lines and the paired electrodes (Y1, X2), (Y2, X4) and (Y3, which are formed by pairs of electrodes (Y1, X1), (Y2, X3) and (Y3, X5). The even number display line formed by X6) is executed.

Although the line between the even X electrode and the odd X electrode is a completely non-display line, since the two display lines are formed by three parallel electrodes and the partition walls for surface discharge parallel to the electrodes are not provided, the pixels thereof The configuration shown in Fig. 30 can be shortened, making a higher definition possible, in which the second display line is formed by four parallel electrodes and a partition wall for surface discharge parallel to the electrodes is provided. . Further, since the electrodes Y1 to Y3 are not distinguished into an even group and an odd group, the configuration is simplified as compared with the first embodiment.

Figure 19 is a longitudinal cross-sectional view of the PDP 10A along the address electrode in Figure 18.

This configuration is different from the structure shown in Fig. 2 in that, with respect to the electrodes X1 and X2 on both sides of the electrode Y1, the metal electrodes 131 and 133 are formed toward the side farthest from the Y1 on the transparent electrodes 121 and 123, respectively. . This structural feature is employed on both sides of each of the electrodes. This causes the electric field on the metal electrode 131 side to be stronger above the electrode X1 when a voltage is supplied between the X1-Y1 electrodes, so that even if the electrode pitch is lowered to achieve a higher definition, the pixel region is closer to the metal electrode 131. The configuration in which the center line of the transparent electrode 121 is formed can be fundamentally increased. Since the line on the opposite side electrodes X1 and X2 with respect to the electrode Y1 is a non-display line, this does not cause any problem, and since the non-display lines can be made narrow at all, it is desirable. In Fig. 19, although the width of the transparent electrode 122 is made equal to the width of the transparent electrodes 121 and 123, the width of the electrode Y1 to which the scanning pulse is supplied can be made narrow to reduce power consumption.

In Fig. 18, a scanning circuit 23B, an odd-numbered continuous circuit 26B and an even-numbered continuous circuit 27B correspond to the scanning circuit 23, the odd-numbered X-continuation circuit 26 and the even-numbered X-continuation circuit 27 shown in Fig. 4, respectively. Comparing the configuration of Fig. 4, a single Y continuation circuit 24A can replace the odd Y continuation circuit 24 and the even Y continuation circuit 25 to simplify its construction.

Figure 20 shows the sequence in which the display lines are scanned during an address. Since the line between the odd X electrode and the even X electrode is a completely non-display line, if a frame is to be distinguished from an odd field and an even field as shown in FIG. 6(A), the display lines will be in each The field is diluted by a ratio of 1 to 3, which is unwilling to maintain the quality of the display. This problem sequentially scans the display lines L1, L3, and L5 with display data in which only odd-numbered fields are written in an odd-numbered frame, and sequentially scans the display lines L2, L4 by using display data in which only even-numbered fields are written in even-numbered frames. Solved with L6. In this case, the configuration corresponding to the frame shown in Fig. 5 is as shown in Fig. 21.

Fig. 22 shows voltage waveforms applied to the electrodes in the odd frame in the case where the number of Y electrodes is 4.

During a reset period, a full screen write discharge W and a full screen self wipe discharge E occur on display lines L1 to L6 in Fig. 20. However, since the voltage between the even X electrode and the odd X electrode is zero, no discharge occurs in the completely non-display lines. This is the difference from the situation in the diagram in Figure 7.

During the address period of one address, since the electrodes Y1 to Y4 are sequentially scanned, a pulse having a large width is supplied to the odd-numbered X electrodes, making it possible to reduce power consumption compared to the case of Fig. 7.

During a duration, a continuous pulse of voltage Vs is periodically supplied to the Y electrodes, a string is used to shift the Y electrode pulse train by 180°, and the resulting pulse train is supplied to the odd X electrodes. . Thus, an AC sustain pulse is supplied between the odd X electrodes and the Y electrodes, and the sustain discharge occurs in the same manner as in the first embodiment. Since the even X electrodes are set to OV, the AC voltage is not supplied to the non-display lines between the even X electrodes and the Y electrodes and the even X electrodes and the odd X electrodes, and the discharge thus does not occur between these electrodes.

Figure 23 shows the voltage waveform supplied to the electrodes in the even frame. These waveforms are obtained by reversing the voltage waveforms supplied to the odd-numbered X electrodes and the even-numbered X electrodes in Fig. 22 from each other.

In the seventh embodiment, since the strip scanning between the odd frame and the even frame is performed by manual execution, the address period can be halved compared to the non-interlace scan, and the sustain discharge period can be lengthened. In this way, it is possible to increase the number of sub-fields to achieve a higher number of gradations, or to increase the number of times the continuous discharge is performed to make it possible to achieve higher brightness.

Figure 24 is a longitudinal cross-sectional view showing the portion of the PDP 10B along its address electrode in accordance with an eighth embodiment of the present invention.

This differs from the configuration shown in Fig. 19 in that the transparent electrode is omitted by constituting the electrode Y1 only with the metal electrode 132. This also applies to all other Y electrodes. Below this, as described earlier, when a scan pulse is supplied to the Y electrodes, power consumption is reduced. And it may further reduce its pixel pitch.

The effect of discharging the discharge performed to eliminate wall charging during a reset period by charging and discharging it to a suitable writing potential makes address discharge easier to occur, making it possible to lower the address discharge voltage. However, since the discharge of the discharge light occurs over the entire surface, the quality of the black display region becomes lowered. Therefore, in the ninth embodiment, the PDP 10C as shown in Fig. 25 is applied to reduce unwanted light emission.

In the PDP 10C, the alternate lines between the electrodes in the PDP 10 in Fig. 1 are the blind lines B1 to B3. Since the blind lines B1 to B3 are completely non-display lines, the non-interlace scanning shows that the lines L1 to L4 are implemented.

For example, blind films (light blocking shields) 41 to 43 are formed on the portion between the transparent electrode 121 and the transparent electrode 122 in FIG. 2 or on the surface of the portion of the glass substrate 11 to ensure the blind line B1 to B3's undesired light emission does not leak to the observer.

Figure 26 shows the voltage waveform supplied to the electrodes during a reset period and during a duration, and the address period is omitted. In the figure, PE represents a wipe pulse, PW represents a write pulse, and PS represents a sustain pulse.

During a reset period, a wiping pulse PE having a voltage less than a sustain pulse is supplied to the odd X electrode and the odd Y electrode to perform wiping discharge for charging all the blind lines B1 to B3 for the wall. Then, the write pulse PW whose voltage is higher than the sustain pulse is supplied to the even X electrode and the even Y electrode to perform write discharge at all the blind lines B1 to B3, and the wall charge becomes almost fixed at all the blind lines B1 to B3. of. The voltage of the write pulse PW is equal to or greater than the discharge start voltage, but lower than the voltage Vw in Fig. 7, and a self-scratch discharge occurs after the write pulse PW falls. Therefore, the wiping pulse PE is again supplied to the odd-numbered X electrode and the odd-numbered Y electrode to perform wiping discharge for charging all the blind lines B1 to B3 for the wall. In this way, under the discharge which is implemented during the reset period, the floating space which has not been reintegrated is charged into the display lines L1 to L4, so that the address discharge is more likely to occur during the address period. During a reset period, since the voltage between the XY electrodes of all of the display lines L1 to L4 is OV, the discharge is not performed, and the quality of the black display area is prevented from being lowered by the undesired generation of light emission.

The voltage waveform supplied to the electrodes during the address period is the same as the conventional technique for displaying the lines L1 to L4, or the odd field in Fig. 7 is regarded as a frame.

Although the blind lines B1 to B3 are made higher than the definition of the first embodiment in the configuration of the prior art of FIG. 30, since it is not necessary to form the partition walls 191 to 196, the production is promoted and the pixels are promoted. The distance can be further reduced.

It is also feasible to perform a full screen write discharge and a full screen self wipe discharge during the same reset period as during the reset period shown in FIG.

It will be noted that even if the PDP is of the drive type, it is not discharged on the blind lines B1 to B3, and is darker than the phosphor (better of black) to the side of the viewer who blinds the films 41 to 43. Absorbing the incident light from the outside to the blind lines B1 to B3, the image contrast on the PDP in the bright portion is reflected from the incident light of the phosphorescent material from the outside to the blind lines B1 to B3 and enters an observer's eye. The situation has to increase a lot.

The 27(A) to 27(E) drawings show the address electrodes in the tenth embodiment of the present invention. Fig. 27(A) is a plan view and Figs. 27(B) to 27(E) are cross-sectional views taken along line BB, CC, DD and EE of Fig. 27(A), respectively. In the 28th (B) and 28(E) drawings, the configuration around the address electrodes is also shown, which helps to understand the configuration of the other portions of Fig. 2 of the present invention.

A pair of address electrodes A11 and A21 are formed on a glass substrate 16 under the address electrodes corresponding to those in FIG. 2, that is, corresponding to a single color pixel. Above the glass substrate 16 and in the phosphorescent cause, pads B11, B21 and B31 are formed to correspond to individual monochromatic pixels. The address electrode A11 is connected to the pad B11 via a contact C21, and the address electrode A21 is connected to the pads B11 and B11 and B31 via contacts C11 and C31, respectively. In other words, the loaders are arranged in a column array and are alternately connected to the address electrode A11 and the address electrode A21. This applies to other address electrodes Akj, pad Bij and junction Cij, where k=1, 2, i=1 to 3, and j=1,3.

In this configuration, a specific odd-numbered line and a specific even-numbered line, that is, a line composed of, for example, pads B11 to B13 and a line formed by pads B21 to B23 can be simultaneously selected, and pads B21 to B23 are simultaneously selected. Address pulses of the constituent lines can be supplied to the address electrodes A11 to A13, and address pulses of the lines formed by the pads B11 to B13 can be simultaneously supplied to the address electrodes A21 to A23.

As a result, the address period is halved compared to the skilled artisan. Therefore its duration is increased. In this way, it is possible to increase the number of subfields to achieve a higher number of gradations, or to increase the number of times the sustained discharge is implemented and achieve a higher brightness.

The tenth embodiment according to the present invention can be employed in various types of PDPs.

Fig. 28 shows an address electrode in the eleventh embodiment of the present invention. Fig. 28(A) is a plan view and Figs. 28(B) to 28(E) are cross-sectional views taken along lines BB, CC, DD and EE, respectively, in Fig. 27(A). Figure 28(B) also shows the construction of the surrounding areas of the address electrodes.

In this embodiment, four address electrodes are formed in each of the regions between the partition walls, and above the address electrodes, the spacers are formed in the phosphor and are sequentially connected to the row of pads to Four electrode lines. In Fig. 28, reference letters A11 to A43 represent address electrodes, reference letters B11 to B43 represent pads, and reference letters C11 to C43 represent contacts.

Under the construction of the address electrodes in this manner, any two odd-numbered lines and any two even-numbered lines can be selected simultaneously to supply an address pulse.

Fig. 29 is a view showing the schematic configuration of an address electrode according to a twelfth embodiment of the present invention.

In this embodiment, the display display table is divided into two parts, namely, regions 51 and 52, and the pads in which the address electrodes A11 are connected to the regions 51 and the address electrodes A21 are connected to the pads in the regions. . The same applies to all other address electrodes and pads.

In this configuration, any of the display lines in region 51 and any of the display lines in region 52 can be simultaneously selected to supply an address pulse.

While the preferred embodiment of the present invention has been described, it is understood that the invention is not limited thereto, and various changes and modifications may be made without departing from the spirit and scope of the invention.

For example, although in the embodiments described so far, the address electrodes and the X electrodes and the Y electrodes are formed on a glass substrate that faces each other across the discharge space, the present invention is also applicable to the fact that they are all formed. In the construction of the same glass matrix.

In addition, although in the embodiments described so far, the full screen wiping of the wall charging is performed during the reset period, and the pixels that are to be lit during the address erasing during the erasing of the charging are implemented. The invention can also be implemented in a configuration in which the full screen is written to erase the pixels that are turned off during the reset period during which the wall charging is performed and the wall charging is reset.

Moreover, in FIG. 1, the metal electrode 131 may be formed on the opposite surface or both surfaces of the transparent electrode 121 or formed in the transparent electrode 121. The same applies to all other metal electrodes in Figures 1, 19 and 24.

<p>10Plastic display panel, PDP</p><p>10A, 10B, 10C, 10P, 10Q color pixels</p><p>11 glass substrate</p><p>14Bipolar matrix</p><p>15MgO protective film</p><p>16 glass substrate</p><p>20, 20A, 20B, 20C, 20D, 20E plasma display device</p><p>21, 21A, 21B, 21C, 21D control circuit</p><p>22 address circuit</p><p>23,23A, 23B, 30 Scanning circuit</p><p>24,24Aodd Y continuous circuit</p><p>25 Even Y continuous circuit</p><p>26,26A,26Bodd X continuous circuit</p><p>27,27A,27Beven X continuous circuit</p><p>29Power source circuit (power circuit)</p><p>31,32Continuous circuit</p><p>33Switching circuit</p><p>41,42,43Blind film</p><p>51, 52 area</p><p>121,122,123 transparent electrode</p><p>131,132,133Metal electrodes</p><p>171,172,173,174,175,176,177,191,192,193,194,195,196,197,198,199 partition wall</p><p>181,182,183phosphorescent</p><p>221,231,231AShift register</p><p>222Latch circuit</p><p>223,232,232A drive</p><p>301,302bit/shift register</p><p>331,332,333,334,335,336Transfer switching elements</p>