Semiconductor integrated circuit device and microcomputer

Semiconductor integrated circuit device and microcomputer

The present invention relates to a semiconductor integrated circuit, in particular to a semiconductor integrated circuit device and a microcomputer suitable for high-speed and low-voltage operation, and a microcomputer system used by the same.

When the MOS transistor is operated at a low power supply voltage of about 1V, in order to improve the driving ability and the operating speed of the circuit, the threshold value of the MOS transistor needs to be set low. However, as described in 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 45-46 (May 1993), if the critical value is set too low, the subthreshold characteristics of the MOS transistor (tailing) (Characteristics), the transistor cannot be completely turned off, so a subcritical leakage current will be generated, and the power consumption will increase, which is a problem.

In addition, as described in 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 13-14 (June 1994), with the miniaturization of MOS transistors, the basics of MOS transistors, such as critical values due to process variations, Changes in parameters also become larger.

FIG. 15 shows the change with respect to the critical value of the gate length Lg of the MOS transistor. The shorter the gate length Lg, the larger the change in the critical value caused by the variation in the processing size of the gate length.

Assuming that the lower limit of the critical value when the subcritical leakage current is limited to a certain value or less is 0.2V, and the critical value change caused by the above process variation is ± 0.15V, the actual lower limits of the critical value are 0.2V and 0.15V Sum 0.35V

As mentioned above, the conventional integrated circuit cannot set the critical value too low. Especially at low power supply voltages, in order to make the MOS transistor operate in a region that is not fully saturated, the operating speed of the MOS transistor circuit will be rapidly slowed down due to a slight increase in the threshold value. In other words, using a known design method will It is difficult to obtain the desired performance.

The purpose of the present invention is to solve the problems of the conventional circuit described above.

That is, the object of the present invention is to provide a semiconductor integrated circuit device composed of a MOS transistor, that is, a semiconductor integrated circuit device suitable for reconciling the increase in power consumption caused by subcritical leakage current and the operating speed of the MOS transistor. .

In addition, in order to reconcile the power consumption and operating speed, a semiconductor integrated circuit device suitable for control of a threshold voltage is provided.

In addition, a semiconductor integrated circuit device capable of easily controlling the threshold voltage by using the frequency of an external clock is provided.

In addition, when a semiconductor integrated circuit device is operated at a plurality of operating frequencies, a semiconductor integrated circuit device capable of controlling a critical value corresponding to the operating frequency is provided.

In addition, a semiconductor integrated circuit device capable of performing the most suitable control of the threshold value of each transistor even when the threshold value of the MOS transistor is changed is provided.

In addition, a microprocessor using the above-mentioned semiconductor integrated circuit device is most suitable for the harmonic control of power consumption and operation speed, and a microprocessor system using the microprocessor.

According to the present invention, in order to solve the above problems, a MOS transistor constituting a main circuit and a corresponding MOS transistor for delay characteristic detection are provided, and the MOS transistor and the MOS transistor for delay characteristic detection constituting the main circuit are arranged in Under the corresponding substrate bias. The operating speed (i.e., the delay characteristic) of the circuit of the MOS transistor for delay characteristic detection is based on the signal obtained from the MOS transistor for delay characteristic detection and the clock signal or a specific reference signal which is regarded as a reference of the delay characteristic like a timing signal. To detect. The substrate bias level is controlled based on the detection result. The substrate bias level control is regarded as a type of monitoring control using a delay characteristic detection MOS transistor and a reference signal. By controlling the bias level of the substrate, the MOS transistor constituting the main circuit can be controlled to a desired threshold value.

The difference between the delay characteristic reference and the delay characteristic obtained from the actual circuit can be calculated from the timing difference between the signal obtained from the MOS transistor for delay characteristic detection and the reference signal and even the phase difference.

However, a preferable example is that the MOS transistor for delay characteristic detection constitutes an oscillation circuit and determines the frequency of the oscillation circuit. In this case, the delay characteristic is detected based on the frequency information of a continuous signal pattern like a sampled oscillation signal.

According to a representative embodiment of the present invention, in order to achieve the above object, a logic circuit of the main circuit is connected with a substrate bias-dependent oscillation circuit that shares the substrate bias of the main circuit and the substrate bias, and uses an operation mode An operating mode dependent oscillation circuit that changes the oscillation frequency; the oscillation output of the two oscillation circuits is used to perform comparison control by the substrate bias control circuit, and the two oscillation outputs are synchronized to control the substrate bias of the main circuit.

In addition, a semiconductor integrated circuit device according to a representative embodiment of the present invention is characterized by: a logic circuit that performs a specific process; a control circuit that controls a critical value of a transistor constituting the logic circuit; and a variable oscillation output frequency The logic circuit is composed of a MIS transistor formed on a semiconductor substrate. The oscillation output of the oscillation circuit is supplied to the control circuit. The control circuit is supplied with a reference clock having a specific frequency. The control circuit outputs the first 1 The control signal is controlled so that the frequency of the oscillation output of the oscillation circuit becomes a value corresponding to the frequency of the reference clock, and the threshold voltage of the MIS transistor forming the logic circuit is controlled by the second control corresponding to the first control signal. Signal to control.

In addition, a semiconductor integrated circuit device according to a representative embodiment of the present invention includes: a logic circuit including a MIS transistor formed on a semiconductor substrate; and a threshold value for controlling the MIS transistor constituting the logic circuit. And a oscillating circuit including a MIS transistor formed on the semiconductor substrate and having a variable oscillation output frequency; the control circuit is supplied with a clock signal having a specific frequency and the oscillation of the oscillation circuit Output; the control circuit is used to compare the frequency of the oscillating output and the frequency of the clock signal and generate a first control signal; the oscillating circuit is controlled through the first control signal to the frequency of the oscillating output corresponding to the frequency of the clock signal Frequency; the control of the frequency of the above-mentioned oscillating output is controlled by the above-mentioned first control signal to control the threshold voltage of the above-mentioned oscillating circuit; the above-mentioned logic is controlled by the second control signal corresponding to the above-mentioned first control signal The threshold voltage of the MIS transistor of the circuit. In addition, a semiconductor integrated circuit device according to a representative embodiment of the present invention includes a logic circuit including a P-channel MIS transistor and an N-channel MIS transistor, and a P-channel MIS transistor and A variable first oscillation frequency formed by an N-channel MIS transistor; a control circuit for generating a control signal to control the threshold voltage of the P-channel MIS transistor and the N-channel MIS transistor; and A second oscillation circuit that outputs a plurality of reference clock signals with different frequencies according to different operation modes; and the control circuit inputs the reference clock signal and uses the control signal to oscillate the oscillation frequency and the reference clock signal of the first oscillation circuit The frequency is controlled as the counterpart.

A semiconductor integrated circuit device according to a representative embodiment of the present invention includes: a logic circuit including at least first and second circuit blocks; first and second oscillation circuits having variable oscillation frequencies; and A first control circuit for controlling a threshold voltage of the MIS transistor constituting the first circuit block and the first oscillation circuit; and a first control circuit for controlling the threshold voltage of the MIS transistor constituting the second circuit block and the second oscillation circuit A second control circuit; and a clock signal supply circuit for supplying a clock signal of a specific frequency shared by the first and second control circuits; the first control circuit controls the components of the first circuit block and the first oscillation circuit; The threshold voltage of the MIS transistor is such that the frequency of the clock signal is consistent with the frequency of the oscillation output of the oscillation circuit; the second control circuit controls the critical value of the MIS transistor constituting the second circuit block and the second oscillation circuit. The voltage is such that the frequency of the clock signal is consistent with the frequency of the oscillation output of the oscillation circuit.

Furthermore, the microcomputer of the representative embodiment of the present invention is characterized by having a load detection device for detecting a processing amount of a logic circuit in the semiconductor integrated circuit device, and the load detection device changes the clock signal according to the processing amount. Frequency.

According to the representative embodiment of the present invention, the substrate bias-dependent oscillation circuit provided in the circuit operates synchronously with a known frequency determined by the operation mode of the logic circuit of the main circuit, so the component substrate can be configured according to the operation mode. The critical value of the MOS transistor of the bias-dependent oscillation circuit is optimally controlled. Furthermore, since the substrate bias of the substrate bias-dependent oscillation circuit and the substrate bias of the main circuit are made common, the critical value of the MOS transistor constituting the main circuit can be controlled to be optimal according to the operation mode. In this way, the increase of the consumption current caused by the subcritical leakage current can be suppressed to a minimum. In addition, the oscillating circuit is synchronized to a known frequency determined by the operation mode, so the delay time of the MOS transistor of the main circuit can be easily estimated, making the design of the main circuit easy.

In addition, according to the representative embodiment of the present invention, since the threshold value of the transistor can be controlled by a specific reference clock, a simple circuit can be configured to control the threshold value of the transistor to realize the high-speed operation and the reconciliation of power consumption. .

In addition, according to a representative embodiment of the present invention, since the frequency control of the oscillating circuit controlled to be synchronized with a specific reference clock frequency is performed by the control of the threshold voltage, the threshold voltage of the internal logic circuit can be effectively controlled.

In addition, according to the representative embodiment of the present invention, since the critical value of the internal logic circuit can be changed according to the operation mode, the logic circuit can be controlled with the most appropriate operation speed according to a specific operation mode.

In addition, according to the representative embodiment of the present invention, since the logic circuit is divided into a plurality of blocks to perform the above-mentioned control, a threshold voltage control can be performed to compensate for component variations caused by the manufacturing process.

In addition, according to the representative embodiment of the present invention, a microcomputer can be obtained, which can detect the processing amount of the above-mentioned logic circuit and control the operating speed of the logic circuit accordingly.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a first embodiment of the present invention.

LOG0 is a main circuit such as a logic circuit, OSC0 is a frequency-variable frequency-type oscillation circuit, and CNT0 is a control circuit.

The oscillation circuit OSC0 is used to input a control signal B1 from the control circuit CNT0 and change the oscillation frequency according to the value of the control signal B1. The control circuit CNT0 inputs the external clock signal CLK0, and inputs the oscillation output S0 of the oscillation circuit OSC0, and forms control signals B0, B1 which are proportional to the frequency difference between the external clock signal CLK0 and the oscillation output S0. The control signal B0 is supplied to the main circuit LOG0, and the control signal B1 is supplied to the oscillation circuit OSC0. Here, the frequency-variable oscillating circuit OSC0 and the control circuit CNT0 for controlling the input S0 thereof constitute a negative feedback type closed-loop system. As can be understood from the description below, this closed loop system is constituted as a stable negative feedback type circuit system (that is, a negative feedback is generated by the output S0 of the frequency variable oscillation circuit OSC0). By this negative feedback type closed loop system, the frequency of the oscillation output S0 of the frequency-variable oscillation circuit OSC0 becomes a frequency corresponding to the frequency of the external clock CLK0. For example, the frequency of the oscillation output S0 and the frequency of the external clock CLK0 become synchronized The same frequency.

As described later, the oscillation circuit OSC0 is composed of an N-channel MOSFET and a P-channel MOSFET formed on a semiconductor substrate, and the control voltage from the control circuit CNT0 can change the substrate bias of the MOSFET. As the substrate bias changes, its threshold voltage also changes, and its oscillation frequency changes.

In addition, the main circuit LOG0 inputs a control signal B0 from the control circuit CNT0. The control signal B0 enables the substrate bias of the MOS transistor constituting the main circuit LOG0 to be controlled, that is, the threshold voltage of the MOSFET is controlled . With this configuration, the threshold voltage of the main circuit of the internal circuit can be controlled by the external clock CLK0, that is, the threshold voltage of the internal circuit can be extended according to the frequency of the external clock to the power consumption and the operating speed. change.

That is, the oscillation circuit OSC0 is a control signal B1 output from the input control circuit CNT0 to oscillate at a specific frequency. Therefore, when the frequency of the oscillation output S0 of the oscillation circuit OSC0 does not correspond to the frequency of the external clock CLK0, the frequency of the oscillation output S0 is controlled to correspond to the frequency of the external clock CLK0 by the control signal B1. That is, because the control signal B1 is configured to control the critical value by changing the substrate bias voltage of the MOS transistor constituting the oscillation circuit OSC0, the MOS transistor system of the oscillation circuit OSC0 is controlled to be at the external clock CLK0. The oscillation output at the oscillation frequency corresponding to the frequency operates at the possible operation speed. In this way, the substrate bias of the MOS transistor constituting the oscillation circuit OSC0 can be controlled at a value corresponding to the frequency of the external clock CLK0. Therefore, if the signal corresponding to the signal B1 used to control the substrate bias of the oscillation circuit OSC0 is corresponding to the signal If B0 is used to control the substrate bias of the main circuit LOG0, the threshold voltage of the MOS transistor constituting the main circuit LOG0 can be controlled to operate at the operating speed corresponding to the frequency of the external clock CLK0.

The control circuit CNT0, which is not shown in detail, is a frequency and phase detection circuit for detecting a frequency difference between the external clock signal CLK0 and the oscillation output S0, and the output of the frequency and phase detection circuit is responsive to the frequency and phase detection circuit and is formed to be added to The control signals for the control signals B0 and B1 of the substrate bias of the MOSFET substrate gate in the main circuit LOG0 and the oscillating circuit OSC0 are formed by a control signal forming circuit. The above frequency phase detection circuit can be regarded as having a delay time characteristic detection function or even an operation speed detection function, and outputs the delay time characteristic or the operation speed characteristic of the main circuit LOG0 and the oscillation circuit OSC0 as frequency difference information. In addition, in the present invention, when the delay time characteristic or the operation speed characteristic of any one of frequency and phase corresponds, it can be understood as a homogeneous characteristic from a large viewpoint. However, as can be seen from the following description, if it is considered that the actual phase control can be performed at the same time as the frequency control, the frequency and phase can be distinguished from the micro level.

Control signals B0, B1. If the frequency of the oscillation output S0 corresponds to the frequency of the external clock signal CLK0, set it to a specific reference level. If the frequency of the oscillation output S0 is greater than the frequency of the external clock signal CLK0, change to make the substrate The bias level is deepened. On the contrary, if the frequency of the oscillating output S0 is smaller than the frequency of the external clock signal CLK0, it changes to make the substrate bias level shallow.

As is well known, a deeper substrate bias level will increase the threshold voltage of the MOSFET input to the substrate bias and reduce its conductance. When the control signal is supplied with a deeper substrate bias level, the conductance of the MOSFET constituting the oscillation circuit OSC0 is relatively reduced, and the time constant formed by the MOSFET and the parasitic capacitance in the oscillation circuit OSC0 is increased. . That is, when the oscillation frequency is high, a control operation is performed to reduce the oscillation frequency.

Conversely, with a shallower substrate bias level, the threshold voltage of the MOSFET will decrease, the conductance will increase, and the oscillation frequency of the oscillation circuit OSC0 will increase. That is, when the oscillation frequency is low, a control operation for increasing the oscillation frequency is performed. As such, the above-mentioned threshold control is performed.

In the embodiment of FIG. 1, the above-mentioned control signal forming circuit is configured and can form two control signals B0 and B1. Therefore, it is easy to obtain the desired circuit configuration, signal level, response characteristics, etc.

That is, if the above control signal forming circuit is constituted as a unit circuit configuration, it is necessary to supply the control signal as a sufficient reference bias voltage to the main circuit LOG0 and the oscillation circuit OSC0 in order to avoid as much as possible between the main circuit When unnecessary electrical coupling of the substrate gates between LOG0 and the oscillating circuit OSC0 is made, the above-mentioned control signal forming circuit can be respectively composed of two circuits for the control signal B0 forming circuit and the control signal B1 forming circuit. At this time, by supplying the output of the frequency phase detection circuit to the two control signal forming circuits, the control signals B0 and B1 output by the two control signal forming circuits can be made equal to each other.

In addition, two control signal forming circuits for forming the control signals B0 and B1 may be formed to be different from each other.

That is, for example, when the main circuit LOG0 has two states of an operation state and a standby state, it is not affected by the detection level of the frequency phase detection circuit described above, and the standby state is changed by an appropriate signal indicating the standby state. The control signal B0 at the time is forcibly controlled at a level for supplying a deeper substrate bias. At this time, if the control signal B1 is set to respond to the output of the above-mentioned frequency and phase detection circuit, the oscillation circuit OSC0 will be placed under appropriate control. In this way, the operating current of the main circuit LOG0 in the standby state can be sufficiently reduced. In addition, when returning from the standby state to the operating state, the control signal B0 added to the main circuit LOG0 can be restored to the desired control at an earlier timing. Level.

Generally speaking, high-speed operation can be performed when a higher oscillation frequency is obtained. In this case, instead of reducing the absolute value of the threshold voltage, the power consumption caused by the subcritical current will increase. Conversely, during low-frequency operation, the absolute value of the threshold voltage is set to be high, the operation speed is reduced, and the power consumption is also reduced. If the main circuit LOG0 is a logic circuit operating with the external clock CLK0 as a reference clock, by adopting the above configuration, the threshold voltage of the MOS transistor constituting the main circuit LOG0 can be controlled to have an operation corresponding to the external clock CLK0 speed. In addition, when the operating speed is low, the threshold voltage is controlled to reduce the power consumption.

In the example described above, the frequency of the oscillation output S0 is controlled by controlling the substrate bias of the oscillation circuit OSC0. However, it is not limited to this. If the operating speed of the MOS transistor is made variable according to the frequency of the external clock CLK0, other control means may be used. In this case, in order to detect the necessary threshold voltage of the main circuit LOG0 as a monitoring device to obtain the operating speed corresponding to the frequency of the external clock CLK0, the oscillation circuit OSC0 must control the oscillation frequency of the oscillation circuit OSC0. The signal B1 is converted into a signal B0 that controls the threshold voltage of the main circuit LOG0.

In this embodiment, an example of a method for changing the substrate bias voltage for controlling the threshold voltage of the transistor constituting the main circuit LOG0 will be described. However, the method is not limited to substrate bias control, as long as it is a method capable of controlling the threshold voltage of the transistor.

In addition, the conventional frequency-variable oscillating circuit is generally configured by adding a transistor to control the current supplied to the inverter circuit in order to make the operating speed of the inverter circuit constituting the ring oscillator variable. However, if the oscillating frequency is changed by the variation of the substrate bias as in the present embodiment, the components such as the current control transistor described above may be omitted. At the same time, the current control component does not exist. When the power supply voltage is lost and supplied to the inverter circuit, etc., the upper limit of the oscillation frequency can be increased, and the range of the variable frequency can be increased.

In addition, it can synchronize with the frequency of the clock signal of the oscillation frequency supplied from the external oscillation circuit, so even when the frequency of the externally supplied clock signal is high, it can be configured as a PLL (Phase Locked Loop) that can follow its frequency Circuit.

FIG. 2 is another embodiment of the present invention.

The main parts are the same as those of the first embodiment described with reference to FIG. 1, and the description is omitted. This embodiment is different from the embodiment of FIG. 1 in that the signal B0 for threshold control and the signal B1 for frequency control are set as a common control signal B3. In this embodiment, the control of the oscillation frequency of the oscillation circuit OSC0 is performed by using the control signal B3 from the control circuit CNT0 to change the substrate bias. Similarly, the control signal B3 is used to control the substrate bias of the main circuit LOG0.

This embodiment can also produce the same effect as the embodiment of FIG. 1, and since the control signal B3 of the control circuit CNT0 is shared, the circuit configuration can be simplified.

In addition, in this case, an oscillating circuit with a wide range of oscillating frequency and a PLL circuit that can follow an external clock signal of a higher frequency can be obtained as described above. In addition, the frequency of the external clock can be used to control the operating speed and power consumption of the main circuit.

FIG. 3 is another embodiment of the present invention.

This embodiment is described in the case where the substrate bias of a MOS transistor is used as the threshold control terminal of the transistor.

It has a main circuit LOG1 and a substrate bias-dependent oscillation circuit OSC1 which changes the oscillation frequency by using a substrate bias. The substrate bias BP1 and BN1 of the main circuit LOG1 are generated by the substrate bias control circuit CNT1 by using the oscillation output S1 of the substrate bias dependent oscillation circuit OSC1 and the oscillation output CLK1 of the oscillation circuit VCLK1 dependent on the operation mode.

Although not particularly limited, the oscillating circuit OSC1 of this embodiment is configured as a ring formed by connecting a plurality of segments of a converter circuit composed of a P-channel MOSFET and an N-channel MOSFET formed on a semiconductor substrate. Oscillator. The main circuit LOG1 is also composed of a P-channel MOSFET and an N-channel MOSFET, which is a so-called CMOS logic circuit. Therefore, the substrate bias BP1 is the substrate bias applied to the PMOS transistor of the main circuit LOG1, and the substrate bias BN1 is the substrate bias applied to the NMOS transistor of the main circuit LOG1. Here, the substrate biases BP1 and BN1 represent the potentials of the n-substrate electrode (or n # electrode) supplied to the P-channel MOSFET and the p-substrate electrode (or p # electrode) of the N-channel MOSFET, respectively.

The operation mode dependent oscillation circuit VCLK1 uses the system clock SCLK1 as a reference clock, and outputs an oscillation output CLK1 depending on the frequency of the operation mode according to a signal MODE1 indicating an operation mode generated outside or inside the system. Although not particularly limited, the main circuit LOG1 is constituted by a logic circuit that operates with the oscillation output CLK1 as a clock.

The substrate bias voltages BP1 and BN1 are also supplied to a closed-loop system consisting of the substrate bias-dependent oscillation circuit OSC1, the substrate bias-dependent oscillation circuit OSC1 and the substrate bias control circuit CNT1 for inputting its output S1, The system is designed so that the negative feedback between them is stable (ie, the negative feedback is generated by the output S1 of the substrate bias-dependent oscillation circuit OSC1. In this way, the oscillation frequency of the output S1 of the substrate bias-dependent oscillation circuit OSC1, It is synchronized with the oscillation output CLK1 of the operation mode dependent oscillation circuit VCLK1.

Here, the operation mode is not particularly limited, and it may be a mode in which the main circuit LOG1 operates at a high speed, a mode at a lower speed, a standby mode, or the like, and is set in advance through the relationship between the operation speed and power consumption required by the main circuit .

With this structure, both the substrate bias of the substrate bias dependent oscillation circuit OSC1 and the substrate bias of the main circuit LOG1 are controlled by the outputs BP1 and BN1 of the substrate bias control circuit CNT1 at the same time, so the operation mode dependent oscillation can be used. The oscillation output CLK1 of the circuit VCLK1 controls the substrate bias of the main circuit LOG1. The threshold value of the MOS transistor will change due to the substrate bias. Therefore, by changing the operation mode signal MODE1, the threshold value of the MOS transistor constituting the main circuit LOG1 can be changed, and the most appropriate threshold value can be controlled according to the operation mode. As mentioned above, with the change of the threshold value, the operating speed and power consumption of the main circuit LOG1 will change. Therefore, the frequency of the clock signal CKL1 supplied to the control circuit CNT1 can be changed according to the operation mode signal MODE1, and a suitable operation mode can be performed. Control of the operating speed and power consumption of the main circuit LOG1.

This embodiment and the embodiments shown below change the oscillation frequency of the operation mode dependent oscillation circuit VCLK1 by the operation mode indication signal to obtain the oscillation output CLK1. However, as shown in FIG. 1 or FIG. 2, a clock signal output control circuit CNT1 directly from the outside may be configured. In this case, if the frequency of the external clock (system clock) is changed by the operation mode in advance, the operation speed and power consumption of the main circuit LOG1 of the internal circuit can be controlled in the same way, and the operation mode dependent oscillation circuit VCLK1 becomes inactive. It is necessary to realize a simpler circuit configuration than the above-mentioned embodiment.

In this embodiment, the substrate bias of both the N-type MOSFET and the P-type MOSFET is controlled by BP1 and BN1. However, it is also possible to use either BP1 or BN1 to change the substrate bias voltage of one of the MOSFETs.

Hereinafter, the specific circuit configuration of the above embodiment will be described in more detail with reference to FIGS. 4 to 6. The overall structure of the circuit shown in FIG. 4 is the same as that of FIG. 3. In FIG. 4, the substrate bias-dependent oscillation circuit OSC1 of FIG. 3 is commutated with a 5-stage CMOS (the P-channel and the N-channel MOSFET constituting the CMOS are set to, for example, a gate length of 0.25 μm and a gate width of 5 μm). Ring oscillator structure. The substrate electrode (or #electrode) of the MOS transistor constituting the ring oscillator is used as a control source for changing the oscillation frequency. It is not particularly limited. However, the main circuit LOG1 is a CMOS logic circuit formed by a two-input NAND gate (a gate length of 0.25 μm and a gate width of 5 μm) with signals A and B as inputs and signal C as output. In addition, in FIG. 4, the substrate bias control circuit CNT1 of FIG. 3 is composed of a substrate bias generating circuit BGEN1, a low-pass filter LPF1, and a frequency phase comparator PFD1. The frequency phase comparator PFD1 may be configured by, for example, the circuit of FIG. 5A . In addition, the low-pass filter LPF1 may be constituted by, for example, a lag lead filter as shown in FIG. 5B.

The frequency and phase comparator PFD1 of FIG. 5A has a general structure, so its explanation is omitted. It is structured by taking the signal REF1 of the reference frequency and the signal S1 of the specific frequency as inputs, and taking the phase difference between the two signals as the output signal S2. In addition, the low-pass filter LPF1 in FIG. 5B is also a lag-lead filter using extremely general resistors and capacitors, and therefore description thereof is omitted.

The substrate bias generating circuit BGEN1 is a DC-DC converter that converts the voltage output S3 of the low-pass filter (lag lead filter) LPF1 into a voltage level most suitable for the substrate bias. The control signal BP1 output by the substrate bias generating circuit BGEN1 is set to a high level signal higher than the power supply voltage Vdd level, and the control signal BN1 is set to a signal lower than the ground potential Vss of the circuit.

The relationship between the control signals BP1, BN1 and the voltage output S3 of the low-pass filter will be described in detail below. That is, the voltage output obtained through the low-pass filter LPF1 constructed in FIG. 5B and the detection signal S3 are the output S2 of the frequency phase comparator PFD1 constructed in accordance with FIG. 5A. When the frequency is lower than the frequency of the clock signal CLK1 as the reference signal REF1, it is set to a lower level close to the ground potential Vss according to it.

When the detection signal S3 is set to a lower level, the control signal is accordingly set to a lower level close to the power supply potential, and the control signal BN1 is set to a lower level close to the ground potential Vss.

On the other hand, when the frequency of the oscillation signal S1 is higher than the frequency of the clock signal CLK1, the detection signal S3 is set to a higher level close to the power supply potential Vdd accordingly.

When the detection signal S3 is set to a higher level, the control signal is set to a higher level than the power supply voltage Vdd, and the control signal BN1 is set to a higher level that is away from the negative level of the ground potential Vss level.

As described above, the inductance of the MOSFET is controlled by the control of the substrate bias voltage, and the oscillation circuit and the main circuit LOG1 are operated to the desired characteristics accordingly.

The control signals BP1 and BN1 are set to a level exceeding the range of the operating voltage Vdd-Vss of the circuit as described above, and at the same time, corresponding levels are changed according to the detection signal S3. The substrate bias generating circuit BGEN1 forming such control signals BP1 and BN1 may be constituted by a relatively simple circuit itself.

The substrate bias generating circuit BGEN1, which is not shown in detail, may be, for example, a substrate bias oscillation circuit composed of a plurality of CMOS inverter circuits, a level control circuit, a positive charge pump circuit, and a negative charge pump circuit. Make up.

The level control circuit controls the level of the oscillation signal supplied to the positive charge pump circuit and the negative charge pump circuit by the output S3 level of the low-pass filter LPF1. The level control circuit is constituted by a voltage coupler circuit composed of, for example, a MOS operational amplifier (OP) for inputting the output S3 of the low-pass filter LPF1. The output of the voltage coupler circuit constituting the level control circuit is not particularly limited. However, it can be set as one of the internal power sources, at least as the power source of the oscillation signal output circuit in the above-mentioned substrate bias oscillation circuit. With this structure, the level of the oscillating signal obtained by the above-mentioned oscillating signal output circuit can be determined by the power supply voltage, and it can be controlled that the oscillating signal has the output S3 level corresponding to the low-pass filter LPF1.

The positive charge pump circuit is, for example, a capacitor for a positive charge pump formed by combining one terminal with the MOS capacity of the output terminal of the oscillation signal output circuit; and the source is connected to the power supply terminal Vdd, and the gate and the drain are connected to the above. The first rectifier element composed of a P-channel MOSFET connected to the other terminal of the capacitor for the positive charge pump capacitor; and the source terminal connected to the other terminal of the capacitor, and the gate and the drain connected to form the main circuit. LOG1 and a second rectifier element composed of a P-channel MOSFET connected to a diode of a substrate gate of the P-channel MOSFET of the oscillation circuit OSC1. The positive charge pump circuit configured in this manner periodically supplies positive charge to the substrate gate of the P-channel MOSFET based on the oscillation signal of the above-mentioned substrate bias oscillation circuit. This positive charge is flattened by a parasitic capacity such as the joint capacity existing on the substrate gate, and a bias potential of the control signal BP1 is supplied to the substrate gate.

The negative charge pump circuit is, for example, a capacitor for a negative charge pump formed by combining one terminal with the MOS capacity of the output terminal of the oscillating signal output circuit; and a gate and a drain connected to the other terminal of the negative charge pump capacitor. A third rectifying element composed of an N-channel MOSFET whose source is connected to the ground potential terminal Vss and a diode; and a gate and a drain which are connected to the other terminal of the above negative charge pump capacitor, and the source is connected to constitute the above The main circuit LOG1 and the oscillation circuit OSC1 are constituted by a fourth rectifier element composed of an N-channel MOSFET connected to the gate electrode of the N-channel MOSFET substrate.

In addition, when other power supply voltages having an external power supply voltage with a high level of the power supply voltage Vdd or higher are used, a circuit for forming the control signal BP1 in the substrate bias generating circuit BGEN1 may be configured as follows. That is, in this case, the other power supply voltage is set as a level conversion circuit or a level shift circuit as the operating voltage, and the low-pass filter is adjusted by the level conversion circuit or the level shift circuit. The output of LPF1 is converted into the signal or level shift of other power supply voltages mentioned above. Accordingly, the control signal BP1 is obtained. Similarly, when other power supply voltages such as an external power supply voltage with a negative level below the ground potential Vss are used, the same level conversion circuit or level shift circuit can also be used to form the control signal BN1. When using the above-mentioned level conversion circuit or level shift circuit, the number of large-sized components on a semiconductor chip like a capacitor for a charge pump can be limited, and the noise of the power supply wiring system accompanying the charge pump operation can also be limited. The resulting transient current.

In FIG. 4, the operation mode dependent oscillation circuit VCLK1 of FIG. 3 is composed of a frequency multiplier PLL1 and an operation mode control circuit MCL1. The fixed-frequency oscillator CK1 can be used as a reference clock for the operation mode-dependent oscillation circuit VCLK1.

The main circuit LOG1 has the above-mentioned operation mode. The signal MODE is controlled according to the operation mode, and the multiplication rate of the frequency multiplier PLL1 is changed by the operation mode control circuit MCU1. Therefore, each operation mode of the main circuit LOG1 has a different multiplication rate, and the fixed frequency output of the fixed frequency oscillator CK1 is doubled as the oscillation output CLK1 of the frequency multiplier PLL1. Here, the oscillation output CLK1 is a square wave having a frequency of f0 (an arbitrary value in the range of 0 MHz to 100 MHz).

The oscillating output S1 of the CMOS ring oscillator OSC1 is input to the frequency phase comparator PFD1 at the same time as the oscillating output CLK1 of the frequency multiplier PLL1. The output S2 of the frequency phase comparator PFD1 is generated by the low-pass filter LPF1 and is generated by the substrate bias. The circuit BGEN1 generates a substrate bias BN1, BP1. The substrate bias BP1 and BN1 are connected to the CMOS ring oscillator OSC1 and the main circuit LOG1 at the same time. As shown in Figure 4, the substrate bias BN1 is simultaneously supplied to the substrate electrode of the N-type MOSFET (a transistor with a gate direction arrow attached to the channel portion), and the substrate bias BP1 is simultaneously supplied to the P-type MOSFET (in the channel A substrate electrode with an arrow in the opposite direction to the N-type MOSFET is added in part. In addition, although the operating potential point to which the transistor is connected is not particularly limited, it can be configured such that Vdd is about 1V, Vss is at a ground potential, and a low voltage is about 1V.

7A and 7B show the relationship between the substrate bias voltage and the threshold voltage of the MOS transistor. FIG. 7A is a case of NMOS, and FIG. 7B is a case of PMOS.

The threshold voltage of the MOS transistor can be seen from FIG. 7A and FIG. 7B, which changes due to the substrate bias. Generally speaking, the larger the absolute value of the threshold voltage, the lower the current drive capability. Therefore, the CMOS ring oscillator OSC1 in Figure 4 is a voltage-controlled oscillator (VCO) that uses the substrate bias voltages BP1 and BN1 to change the oscillation frequency. Ground action. Therefore, the circuit of FIG. 4 is structured as a phase-locked loop (PLL) as a whole, and the oscillation frequency and phase of the OSC1 of the CMOS ring oscillator are consistent with the frequency and phase of the oscillation output CLK1 of the frequency multiplier PLL1. In addition, the oscillating circuit (VCO) and the PLL circuit of this embodiment are the same as the embodiment shown in FIG. 1, etc., and can obtain a wide range of oscillating frequency range and a high-frequency external clock signal. In addition, the PLL circuit can also control the operating speed and power consumption of the main circuit by the frequency of the external clock.

The PLL circuit is described in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 22, No. 2, (April 1987), pp. 255-261.

In the following, the timing diagram of FIG. 6 is used to explain the changes in the operation mode of the main circuit LOG1, and the changes between the substrate bias voltages BP1, BN1, and the threshold voltage of the MOS transistor constituting the main circuit LOG1. As soon as the operation mode changes, the frequency multiplier of the frequency multiplier PLL1 will change due to the operation mode control circuit MCU1, and the oscillation output CLK1 of the frequency multiplier PLL1 will change. Here, as time progresses, the frequency f0 changes from 75 MHz to 50 MHz. In this way, the potential of the substrate bias BP1 will increase from 1.3V to about 1.6V. The potential of the substrate bias BN1 will decrease from -0.3V to about -0.6V. In this way, the threshold voltage of the MOS transistor becomes larger (refer to FIG. 7A and FIG. 7B), so the oscillation frequency f1 of the substrate bias-dependent oscillation circuit OSC1 is also reduced, and the oscillation frequency CLK1 of the frequency multiplier PLL1 is reduced accordingly. The frequency f0 (50 MHz) is consistent. In addition, the phase is also consistent with the phase of the oscillation output CLK1 of the frequency multiplier PLL1.

Conversely, when the operating mode MODE changes, the frequency f0 of the oscillating output CLK1 of the frequency multiplier PLL1 increases from 50MHz to 100MHz, and the potential of the substrate bias BP1 decreases from 1.6V to about 1.0V. The potential of the substrate bias BN1 is increased from -0.6V to about 0V. In this way, the threshold voltage of the MOS transistor will become smaller (refer to FIG. 7A and FIG. 7B), so the oscillation frequency f1 of the substrate bias-dependent oscillation circuit OSC1 will gradually increase, and the oscillation output CLK1 of the frequency multiplier PLL1 The frequency f0 (100 MHz) agrees.

FIG. 8 shows the relationship between the frequency f0 of the oscillation output CLK1 of the frequency multiplier PLL1 and the substrate bias voltages BP1 and BN1. In this way, the oscillating output CLK1 of the frequency multiplier PLL1 can change the substrate bias of the MOS transistor constituting the substrate bias-dependent oscillation circuit OSC1, that is, the threshold voltage of the MOS transistor can be changed.

Although the frequency f0 of the oscillating output CKL1 shown above has three types such as 50 MHz, 75 MHz, and 100 MHz, the present invention is not limited to this. As long as the threshold voltage can be controlled to an appropriate value, an arbitrary oscillation frequency can be selected.

In addition, in this embodiment, the oscillation frequency f1 of the CMOS ring oscillator OSC1 can be made consistent with the set value according to the operation mode of the main circuit LOG1. In this way, according to the operation mode of the main circuit LOG1, it is easy to estimate the transmission delay time of the MOS transistor constituting the main circuit.

FIG. 9 shows the gate voltage dependence in the subcritical region of the drain current of the MOS transistor. Generally speaking, the smaller the threshold voltage of the MOS transistor is, the greater the driving capacity is, and high-speed operation becomes possible. However, it can be confirmed from the comparison between point A and point B in FIG. 9 that the smaller the ON-OFF ratio of the MOS transistor, the subcritical current will increase, and the current consumption of the circuit will also increase.

According to the circuit configuration of the present invention, when high-speed operation is necessary, the criticality of the MOS transistor constituting the main circuit LOG1 can be reduced by selecting an operation mode for increasing the oscillation frequency of the oscillation output CLK1 of the operating frequency multiplier PLL1 from the outside. Value voltage. In this case, although the subcritical current will increase and the power consumption of the main circuit LOG1 will also increase, high-speed operation is possible. On the other hand, when low-speed operation is necessary, the threshold voltage of the MOS transistor constituting the main circuit LOG1 can be increased by selecting an operation mode that can reduce the oscillation frequency of the oscillation output CLK1 of the operating frequency multiplier PLL1 from the outside. . In this way, the sub-critical current can be reduced, and the power consumption of the main circuit LOG1 can be reduced. This situation is shown in Figure 10. P2 in FIG. 10 shows the change of the power consumption of the main circuit LOG1 when the change operation mode MODE changes the frequency f0 of the oscillation output CLK1 of the operation frequency multiplier PLL1. The main circuit LOG1 is an example of operating at the same frequency (= f0) as the frequency f0 of the oscillation output CLK1 of the operating frequency multiplier PLL1. In FIG. 10, P0 represents the state where the consumption current T0 generated by the subcritical current does not exist, and P1 represents the power consumption of the main circuit LOG1 in the state where the subcritical current exists. As such, the power consumption of the main circuit LOG1 has a linear relationship with respect to its operating frequency f0. In addition, since the subcritical current does not depend on the operating frequency f0, P1 is parallel to P0. P2 to which the present invention is applied, because the critical voltage and the operating frequency f0 related to the subcritical current change at the same time, the operating mode also changes. As the operating frequency f0 becomes lower, the consumption current T0 generated closer to the subcritical current does not change. The value of the power consumption P0 in the existing state. In this way, the main circuit LOG1 can operate under the power consumption state of the minimum secondary critical current required when the operating frequency f0 operates. This effect is particularly effective in the case of a low-voltage operation of about 1 V where the subcritical current is a problem, or when the degree of accumulation becomes high.

In addition, according to the operation mode of the main circuit LOG1, the critical value of the main circuit LOG1 can be automatically set to a set value, so it can automatically provide external follow-up from the characteristics change, temperature change, and power supply voltage change of the MOS elements constituting the main circuit. Circuit of the variation factor.

Although FIG. 4 shows an example of a NAND gate corresponding to the 2 input of the main circuit LOG1 of FIG. 3. However, it is not limited to logic gates such as NAND gates, inverters or NORs, or logic gate groups formed by a plurality of these sets. In addition, the circuit configuration of the main circuit LOG1 is not limited to a CMOS structure, and only a NMOS transistor, or only a PMOS transistor, or a circuit composed of both, or a circuit including a bipolar transistor may be used. In addition, the ring oscillator OSC1 of FIG. 4 is not limited to the CMOS ring oscillator, as long as it is an oscillation circuit whose oscillation frequency of the substrate bias can be changed.

FIG. 11 is a cross-sectional view showing a CMOS structure for implementing the embodiment of FIG. 4. FIG. N # 109 and p # 110 are formed on a part of the surface layer of the p-type Si substrate 111. Formed by p on the surface of n # 109⁺PMOS transistors formed by the source, drain diffusion regions 103, 104, gate 107, and gate oxide film 112 are formed on the surface of p # 110 by n.⁺Type NMOS transistor composed of source, drain diffusion regions 105, 106, gate 108, and gate oxide film 113. Element isolation insulating films 100, 101, and 102 are formed between the PMOS transistor and the NMOS transistor. Although not shown, in order to supply the substrate with a bias to the PMOS transistor and the NMOS transistor, the above-mentioned BP1 and BN1 are connected to respective # regions.

The above example uses a p substrate, but an n substrate may be used. In addition, in FIG. 11, the structure is designed to use the double # structure of both n # 109 and p # 110. However, it is also possible to design the substrate to share the single # structure of either n # 109 or p # 110. Or use MOS transistor with triple # structure described in ISSCC Digest of Technical Papers, (Feb. 1989), pp. 248-249, or MOS transistor with SOI structure described in 1992 IEDM Technical Digest, pp. 35-38 Crystal.

In the above embodiment, the value of the substrate bias is supplied to a potential of 0 V or less for the NMOS transistor system, and a potential of more than the power supply voltage (for example, 1.0 V) of the main circuit to the PMOS transistor. However, a forward bias may be applied in the direction of the PN junction between the diffusion layer of the NMOS transistor or the PMOS transistor and the substrate. In particular, when the forward bias value of the power supply does not exceed the diffusion potential (about 0.6V), the leakage current between the diffusion layer and the substrate is small, so the increase in power consumption is extremely small, and a forward bias can be applied.

In this case, in general, the substrate bias coefficient of the critical value (the coefficient of variation of the threshold voltage relative to the substrate bias voltage) becomes larger in the above-mentioned substrate bias region, so the MOS transistor can be controlled very effectively. Critical value. Furthermore, the potential applied to the substrate bias voltage can be set within the range of the power supply voltage, so that it is not necessary to design a special circuit for the substrate bias for forming a circuit such as a negative voltage, which is an advantage.

Furthermore, in the above embodiment, the threshold value of the MOS transistor constituting the main circuit is controlled by using the substrate bias. However, the main circuit may be constituted by a MOS transistor having a terminal capable of controlling a critical value (for example, an SOIMOSFET having an SOIMOSFET having an electrode electrically insulated from the silicon substrate on the silicon substrate on the silicon substrate) to constitute the main circuit, and the circuit may be applied by The voltage is applied to the terminal to control the critical value, that is, the voltage is applied to the terminal that can control the critical value of the main circuit.

FIG. 12 is a circuit block LOG10 to LOG30 in which one main circuit LOG1 is decomposed into a plurality, which is an example applicable to this embodiment. The oscillation output CLK10 of one operation mode dependent oscillation circuit VCLK10 is used to control the substrate biases BP10 to BP30 and BN10 to BN30 of most circuit blocks LOG10 to LOG30. The oscillation output CLK10 of the operation mode dependent oscillation circuit VCLK10 is simultaneously supplied to the control circuit CNT. At the same time, the control circuit CNT and the oscillation circuit OSC are arranged corresponding to the circuit blocks LOG10 to LOG30. The operation mode dependent oscillation circuit VCLK10, the control circuits CNT10, 20, and 30, and the oscillation circuits OSC10, 20, and 30 can be configured as shown in FIG.

In this embodiment, the substrate bias of the circuit blocks LOG10 to LOG30 are independently controlled by the oscillation output CLK10 of the operation mode dependent oscillation circuit VCLK10. Therefore, between the circuit blocks LOG10 to LOG30, even if the threshold value of the MOS transistor or the substrate bias characteristic of the threshold value is different, the change can be corrected. For example, when the MOS transistor constituting other circuit blocks is changed due to the manufacturing of the critical value of the MOS transistor constituting the main circuit LOG10, it can be considered that the critical value of the MOS transistor constituting the oscillation circuit OSC10 also changes. Therefore, proper control can be made to make the substrate bias voltage corresponding to the clock CLK10. In this way, for example, when it is known that the threshold value variation between the circuit blocks LOG10 to LOG30 is about 0.15V, it can be reduced to about 0.05V in this embodiment.

The variation of the manufacturing process is related to the location and location of the semiconductor wafer constituting the semiconductor integrated circuit, so it is preferable to arrange the above-mentioned circuit block LOG in close proximity to its corresponding oscillation circuit. When the main circuit is divided into circuit blocks, similarly, it is preferable to arrange the transistors located in close proximity to each other in the same block, and to divide the semiconductor wafer into four parts in the vertical and horizontal directions.

As mentioned above, the lower limit of the allowable range of the threshold voltage is determined by the specification of the subcritical leakage current, and the upper limit is determined by the operating speed specification of the circuit. When the variation of the threshold voltage is large, the threshold setting in the setting stage has to be increased, which will hinder the high-speed operation of the circuit. However, according to the method of this embodiment, since the threshold voltage can be reduced to the lower limit of the allowable range, high-speed operation of the circuit is possible.

The effects of these embodiments are particularly effective when the power supply voltage is a low voltage of about 1V.

Although in the above embodiments, the substrate bias value is set to a potential of 0V or less for the NMOS transistor, and the potential of the main circuit voltage (for example, 1.0V) or more is set for the PMOS transistor. However, this can also be applied in the forward bias direction of the PN junction between the diffusion layer of the NMOS transistor or the PMOS transistor and the substrate. In particular, when the forward bias value of the power supply is not greater than the diffusion potential (about 0.6V), the forward bias can be applied because the leakage current between the diffusion layer and the substrate is small and the increase in power consumption is small.

In this case, in general, the substrate bias coefficient of the threshold voltage (the coefficient of variation of the threshold voltage relative to the substrate bias) becomes larger in the above-mentioned substrate bias region, so the MOS transistor can be effectively controlled. Threshold voltage. Furthermore, since the potential to be applied to the substrate bias voltage can be set within the range of the power supply voltage, it is an advantage that it is not necessary to have a special circuit for applying a substrate bias voltage to a negative voltage forming circuit or the like.

In the above-mentioned embodiment, the substrate bias voltage is used to control the threshold voltage of the MOS transistor constituting the main circuit. However, the main circuit may be constituted by a MOS transistor having a terminal capable of controlling a threshold voltage (for example, a SOIMOSFET having an SOIMOSFET having an electrode electrically insulated from the silicon substrate on the silicon substrate on the silicon substrate) to form a main circuit. A voltage is applied to the terminal to control the threshold voltage, and the voltage is applied to a terminal that can control the threshold voltage of the main circuit.

FIG. 12 is an example in which one main circuit LOG1 is decomposed into a plurality (three in the figure) of the circuit blocks LOG10 to LOG30. The oscillation output CLK10 of one operation mode dependent oscillation circuit VCLK10 is used to control the substrate biases BP10 to BP30 and BN10 to BN30 of most circuit blocks LOG10 to LOG30. The oscillation output CLK10 of the operation mode dependent oscillation circuit VCLK10 is supplied to the control circuits CNT10 to CNT30 at the same time. At the same time, the control circuits CNT10 to CNT30 and the oscillation circuits OSC10 to OSC30 are arranged corresponding to the respective circuit blocks LOG10 to LOG30. The operation mode dependent oscillation circuit VCLK10, the control circuits CNT10 to CNT30, and the oscillation circuits OSC10 to OSC30 can be configured as shown in FIG. 4.

In this embodiment, the substrate bias of the circuit blocks LOG10 to LOG30 are independently controlled by the oscillation output CLK10 of the operation mode dependent oscillation circuit VCLK10. Therefore, between each of the circuit blocks LOG10 to LOG30, even if the threshold voltage of the MOS transistor or the threshold voltage is different from the substrate bias characteristic, these changes can be corrected. For example, even if the threshold voltage of the MOS transistor constituting the main circuit LOG10 is changed relative to the MOS transistor constituting other circuit blocks due to the manufacturing process, the threshold voltage of the MOS transistor constituting the oscillation circuit OSC10 can be considered the same It can be appropriately controlled so as to be a substrate bias value corresponding to the oscillation output (clock signal) CLK10. In this way, for example, when it is known that the variation of the threshold voltage between the circuit blocks LOG10 to LOG30 is about 0.15V, this embodiment can be used to reduce it to about 0.05V.

The variation of the manufacturing process is related to the location on the semiconductor wafer constituting the semiconductor integrated circuit, so it is better to place the oscillation circuits OSC10 to OSC30 corresponding to the above-mentioned circuit blocks LOG10 to LOG30, respectively. In addition, even when the main circuit is divided into a plurality of circuit blocks, it is preferable to similarly divide, for example, a semiconductor wafer in four directions in the vertical direction and the horizontal direction so that the transistors located in close proximity to each other can be in the same block.

As mentioned above, the lower limit of the allowable value of the threshold voltage is determined by the specification of the subcritical leakage current, and the upper limit is determined by the operating speed specification of the circuit. When the variation of the threshold voltage is large, the threshold voltage setting in the specification setting stage has to be increased, so it will hinder the high-speed operation of the circuit. However, according to the method of this embodiment, since the threshold voltage can be lowered to the lower limit of the allowable value, high-speed operation of the circuit is possible.

The effects of these embodiments are even more effective when the power supply voltage is a low voltage of about 1V.

FIG. 13 shows the change of the drain current when the threshold voltage changes with respect to the gate voltage applied to the gate. When the power supply voltage is higher than VDD1 = 2.0V, the change of the drain current caused by the change of the threshold voltage is almost nonexistent between points A1 and B1. When the power supply voltage is lower than VDD2 = 1.0V, the critical The variation of the drain current caused by the change of the value voltage is as large as the difference between points A2 and B2. When the power supply voltage is below 1V, the difference between points A2 and B2 becomes larger.

In the embodiment of FIG. 12, the oscillation output CLK10 of the same operation mode dependent oscillation circuit VCLK10 is simultaneously provided in each of the circuit blocks LOG10 to LOG30. However, as shown in FIG. 14, the operation mode dependent oscillation circuits VCLK20 and VCLK30 may be set for each circuit block.

In FIG. 14, two operation mode dependent oscillation circuits (VCLK20 and VCLK30) are provided, and each is supplied with SCLK20 and a mode signal MODE20 as a reference system clock. In addition, each of the circuit blocks LOG10 to 30 has an oscillation circuit OSC10 to OSC30 and a control circuit CNT10 to CNT30. The control circuits CNT10 and CNT20 are provided with the oscillation output CLK20 of the oscillation circuit VCLK20, and the control circuit CNT30 is provided with the oscillation circuit VCLK30. Oscillation output CLK30. The operation mode dependent oscillation circuits VCLK20, VCLK30, control circuits CNT10, CNT20, CNT30, and oscillation circuits OSC10, OSC20, and OSC30 can adopt the structure shown in FIG. 4. In addition, the point that a plurality of circuit blocks LOG10 and LOG20 are simultaneously controlled by one operation mode dependent oscillation circuit VCLK20 is the same as that in the case of the embodiment of FIG. 12, and the same effect can be obtained.

By adopting this structure, each circuit block can be controlled by independent operation mode dependent oscillation circuits VCLK20 and VCLK30, for example, circuit blocks LOG10 and LOG30, so it is possible to control the substrate bias suitable for each circuit block. Even in the same operation mode, each circuit block can be operated with different substrate bias value. For example, high-speed operation is a necessary circuit block. Although the subcritical leakage current is large, it can be operated at high speed. The circuit block necessary for low-speed operation can be operated at low-speed and low subcritical leakage current, that is, the most appropriate threshold voltage can be set in each circuit block.

In this embodiment, which is suitable for a case where the required operating speed of each circuit block is different, if the point of variation of the threshold voltage described in the embodiment of FIG. 12 is considered to be corrected, in the case of this embodiment, it is better to When forming a main circuit on a semiconductor wafer, the main circuit is divided into a plurality of circuit blocks at a required operating speed, and the transistors constituting the divided circuit blocks are arranged close to each other on the wafer.

In addition, although the operation mode signal MODE20 is simultaneously supplied to the oscillation circuits VCLK20 and 30 in FIG. 14. However, the operation mode signal can be supplied to each oscillation circuit independently, so that the oscillation outputs of the oscillation circuits VCLK20 and VCLK30 have different frequencies. With this configuration, it is possible to control only specific circuit blocks to operate at a high speed (or a low speed) based on the content of the logical operation processing in the main circuit. For example, the main circuit is a microprocessor with a floating decimal point arithmetic unit. When the floating decimal point arithmetic unit is set to one circuit block (for example, LOG30), when the floating decimal point arithmetic is necessary, use this dedicated mode. The signal is controlled to make only this unit (circuit block LOG30) operate at high speed, and when the unit is not in use, it can be controlled to cause other circuit blocks to operate at high speed and cause circuit block LOG30 to operate at low speed.

Also, although in this embodiment, the circuit blocks LOG10 and 20 are controlled by the oscillation output CLK20 of the operation mode dependent oscillation circuit VCLK20. However, it can also be controlled by the oscillation output of the independent operation mode dependent oscillation circuit. In this case, the circuit configuration of only this part becomes complicated, and the occupied area of the operation mode dependent oscillation circuit may increase. Therefore, it is necessary to divide into the appropriate number of blocks according to the required performance of the circuit blocks.

12 and 14 are divided into three circuit blocks to apply the present invention, but they can also be divided into more circuit blocks. The smaller the circuit unit, the more significant the above effects.

In addition, the circuit blocks LOG10 to LOG30 may be formed on one LSI chip, or may be formed on a plurality of LSI chips, respectively, without particular limitation. However, when formed separately on most wafers, a control circuit (CNT10, etc.) and an oscillation circuit (OSC10, etc.) that depend on the substrate bias are formed on each wafer. The operation mode-dependent oscillation circuit can be adopted. A structure that is provided on most wafers at the same time. In particular, in order to appropriately control the threshold voltage of the main circuit, it is preferable to form an oscillation circuit (such as OSC10) that monitors the threshold voltage of the main circuit on the same chip as the corresponding main circuit.

FIG. 16 shows an embodiment where the present invention is applicable to a microcomputer. The fixed oscillation frequency output 502 and the operation mode signal 503 of the crystal oscillator 501 are input to the microcomputer 500. The microcomputer 500 is not particularly limited, and can be formed using a circuit technology such as CMOS on a single semiconductor substrate. Here, the operation mode signal 503 for controlling the operation mode is a signal line with a signal width of 1 bit or more, and is output by the load detector 505 in the microcomputer 500. The load detector 505 is used to detect the processing amount of the microcomputer 500 and output an operation mode signal 503 in order to control the operation mode and determine the operation speed according to the processing amount.

The load detector 505 may be constituted by a semiconductor circuit provided in the microcomputer 500, or may be implemented by a program executed on the microcomputer 500. In addition, in addition to the microcomputer 500, there may also be a person monitoring the load of the microcomputer 500.

When the load applied to the microcomputer 500 is small, the load mode signal is set to a corresponding smaller value by the load detector 505. In this way, the oscillation circuit VCLK1 for outputting the oscillation output corresponding to the oscillation frequency of the operation mode is controlled, and the operation frequency 504 inside the microcomputer becomes lower, which can be adapted to the operation speed of the load. Action under power consumption. Conversely, when the load applied to the microcomputer 500 becomes large, the operation mode signal is set to a correspondingly large value by the load detector 505. In this way, the operating frequency 504 in the microcomputer 500 becomes higher, and the operating speed can be adapted to the load. Action under power consumption. That is, the microcomputer 500 can be caused to operate at the most appropriate operating frequency to suit the load.

In addition, the action mode signal can be a digital signal or an analog signal.

FIG. 17 shows an embodiment when a microcomputer system is constructed using the microcomputer shown in FIG. 16. The microcomputer system 600 is connected to a system bus 602 controlled by the microcomputer 500 with an input device 601 such as a keyboard or a mouse. The microcomputer 500 is configured as shown in FIG. 16.

The load detector 505 monitors the operating time of the input device 601, determines the operation mode signal 503, and outputs it. Therefore, for example, when the operation frequency of the input device 601 is high, the operation frequency of the microcomputer 500 is set to an operation mode that becomes higher by the operation mode signal 503. Conversely, when the operation frequency of the input device 601 is low, an operation mode in which the operation frequency of the microcomputer 500 becomes smaller is set. Generally speaking, when the operating time of the input device 601 is short, it indicates that the load of the microcomputer 500 is small, and the load applied to the microcomputer 500 can be effectively evaluated. With this load detection method, the power consumption can be reduced without reducing the effective operating speed of the microcomputer system.

Although FIG. 17 shows an input device 601 such as a keyboard or a mouse as the load detection method, other methods may be used. Anyone who can detect the CPU time of the user of the microcomputer 500 may be used. In other words, as long as the load detector can make the execution time of the to-be-processed tasks of the microcomputer 500 within the time that can be satisfied by the user of the microcomputer system 600, it is sufficient. In addition, the setting of the operation mode may be configured by an input device 601 and a user of the computer to perform the operation externally.

As described above, as a representative embodiment of the present invention, the threshold voltage of the MOS transistor constituting the main circuit LOG1 can be controlled by the operation mode signal MOD1. That is, when high-speed operation is necessary, by selecting the operation mode, the frequency of the oscillation output CLK1 of the operation mode-dependent oscillation circuit VCLK1 can be set to be high from the outside, so that the MOS power of the main circuit LOG1 can be reduced. The threshold voltage of the crystal. In this case, although the sub-critical current increases and the power consumption of the main circuit LOG1 also increases, high-speed operation of the main circuit LOG1 is possible. Conversely, when low-speed operation is necessary, by selecting the operation mode so that the frequency of the oscillation output CLK1 of the operation-dependent oscillation circuit VCLK1 is set to be low from the outside, the critical value of the MOS transistor constituting the main circuit LOG1 can be increased Voltage. In this case, the subcritical current can be reduced, and the power consumption of the main circuit LOG1 can be reduced.

Fig. 1: Circuit structure of an embodiment of the present invention.

Fig. 2: Circuit structure of another embodiment of the present invention.

Fig. 3: Circuit structure of still another embodiment of the present invention.

Fig. 4: A more specific circuit configuration of the embodiment shown in Fig. 3.

5A and 5B are specific circuit configuration examples of the frequency phase comparator PFD1 and the low-pass filter LPF1 of FIG. 4, respectively.

FIG. 6 is a timing diagram of the relationship between the operating frequency and the substrate bias in the embodiments shown in FIGS. 3 and 4.

FIG. 7A and FIG. 7B are the relationship between the substrate bias voltage and the threshold voltage in the NMOS transistor and the PMOS transistor, respectively.

Figure 8: The relationship between the operating frequency of the MOS transistor and the substrate bias.

Figure 9: The relationship between the gate voltage and the drain current of a MOS transistor.

FIG. 10 is a relationship diagram between an operating frequency and power consumption according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view showing an example of the element structure in the embodiment of the present invention.

Fig. 12 is a structural diagram of another embodiment of the present invention.

FIG. 13 is a graph showing the relationship between the gate voltage and the drain current of the present invention.

FIG. 14 is a structural diagram of another embodiment of the present invention.

FIG. 15 is a graph showing the relationship between the gate length and the threshold voltage of the present invention.

FIG. 16: A structural diagram of an embodiment of the present invention applicable to a microcomputer.

FIG. 17 is a structural diagram of an embodiment of the present invention applicable to a microcomputer system.