Delay circuit device

Delay loop device

Background of the invention

The present invention relates to a semiconductor loop device, and more particularly to a delay loop device for generating a synchronization signal (hereinafter referred to as a "clock pulse") for transmission or control.

As shown in FIG. 1, according to a known technique, a semiconductor circuit device using a clock pulse receives an external clock pulse 401 in a receiving circuit 402, amplifies the clock pulse in an amplification circuit 403, and generates an internal clock pulse 405 for the circuit 404. As a result, when receiving processing is performed on the receiving circuit 402 and amplification processing is performed on the amplification circuit 403, as shown in FIG. 2, a delay time 406 is generated between the external clock 401 and the internal clock 405. The delay time 406 increases as the circuit scale of the semiconductor circuit device increases. The increase in the circuit scale is facilitated by the advancement of manufacturing technology and the increase in the diameter of the semiconductor substrate. In addition, as the operating speed of a system installed on a semiconductor loop device increases, the speed of the loop operation and the clock pulses used also increases. This increase in speed leads to an increase in the delay time 406 relative to the clock cycle 407, which in turn becomes an obstacle in the loop operation.

To solve the above problems, Phase-Locked Loops (hereinafter referred to as "PLL") are used. Figure 3 shows the basic loop structure of a PLL. The phase comparator 504 derives a phase error signal 506 from the phase difference between the external clock pulse 501 entering through the receiving loop 502 and the internal clock pulse 505 passing through the delay loop 503. The delay of the delay loop 503 is equal to the delay of the receiving loop 502. After passing the loop filter 507, the phase error signal 506 becomes a control signal 508, and is then input to a voltage-controlled oscillator 509. The voltage-controlled oscillator 509 generates a clock pulse 510 whose frequency corresponds to the control signal 508. This clock pulse 510 is amplified by the amplification circuit 511 into an internal clock pulse 505 for use by a clock-controlled circuit 512. The control signal 508 controls the voltage-controlled oscillator 509 to eliminate the phase difference between the external clock pulse 503 and the internal clock pulse 505, and controls the voltage-controlled oscillator 509 until no phase difference is detected.

On the PLL, the delay of the internal clock pulses disappears relative to the external clock pulses, and the problem of obstacles to the loop operation caused by the increase of the delay time relative to the clock cycle can also be solved.

As shown in FIG. 4, the configuration using a frequency division loop in the PLL has been used in a semiconductor loop device, which uses a clock pulse having an integer duty ratio or an integer power of a frequency of an external clock.

The phase comparator 504 derives a phase error signal 506 from the phase difference between the external clock pulse 503 entering through the receiving loop 502 and the internal clock pulse 505 entering through the delay loop 503. The delay of the delay loop is equal to the delay of the receiving loop 502. After the phase error signal 506 passes through the loop filter 507, it becomes a control signal 508, and is then input to a voltage-controlled oscillator 509. The voltage controlled oscillator 509 generates a day clock pulse 510 whose frequency corresponds to the control signal 508. When the clock pulse 510 passes through the frequency dividing circuit 513, that is, the frequency is divided horizontally, the clock pulse 510 becomes a clock pulse 514. This clock pulse 514 is then amplified by the amplification circuit 511 and becomes an internal clock pulse 505 for use by the clock control circuit 512. The clock pulse 510 is further amplified by the amplification circuit 515 and becomes an internal clock pulse 516 for use by the clock control circuit 512. The control signal 508 controls the voltage-controlled oscillator 509 to eliminate the phase difference between the external clock pulse 503 and the internal clock pulse 505. Thereby, the internal clock pulse 505 becomes a clock pulse having the same phase and period as the external clock pulse 503, and has an integer duty ratio. The clock pulse 516 has the same frequency as the internal clock pulse 505 before the horizontal frequency division. Therefore, it becomes a clock pulse with a frequency divided inverse frequency relative to the external clock pulse 503.

The present invention provides a delay loop device that solves the following loop shortcomings, which are those of the above-mentioned PLL.

1. It takes time (more than tens of cycles) to eliminate the phase difference between the internal clock pulse and the external clock pulse.

2. As a result of the above-mentioned first disadvantage, the PLL must be constantly operated to provide an internal clock pulse having no phase difference from the external clock pulse at a desired timing, thereby increasing power consumption.

3. Because the voltage controlled oscillator uses voltage to control the oscillator, the amplitude of the control voltage will decrease as the power supply voltage decreases, thus reducing the accuracy of the controlled frequency.

4. When the control clock pulse covers a wide range of frequencies, and to maintain the accuracy of the fixed controlled frequency, most voltage-controlled oscillators with different frequency ranges must be used, and it takes time to switch the voltage-controlled oscillator Eliminate the phase difference.

5. Because conditions for eliminating phase differences are limited (voltage, device conditions), it is often necessary to perform an initial investigation of the problem.

6. Because there are many different circuits, it is not easy to deal with bad circuits.

According to the present invention, there is provided a delay loop device including a first delay loop string capable of leading out an output at any position on a signal transmission path and a second delay loop capable of introducing an input at any position on a signal transmission path Tandem, and a control loop with one of the signal's input terminal, output terminal, and input / output control terminal; wherein the first delay loop string and the second delay loop string are configured so that their signal transmission paths are in opposite directions The output of the first delay loop train and the input of the second delay loop train pass through the control loop and depend on the input side close to the first delay loop train and the output side close to the second delay loop train. Sequences are connected to each other; the first signal is input to the first delay loop series, and the second signal is input to the control loop at any subsequent time to transfer the first signal of the first delay loop series to the second delay loop series.

According to an embodiment of the present invention, the second signal is input to the control loop to transfer the first signal on the first delay loop train to the second delay loop train and remove it from the first delay loop train.

According to another embodiment of the present invention, the first delay loop series and the second delay loop series are configured so that the delay times of the two series are equal.

According to another embodiment of the present invention, the voltages supplied to the first delay loop series and the second delay loop series are from a constant voltage power source.

According to another embodiment of the present invention, on a circuit having a plurality of voltage sources, the voltages supplied to the first delay loop series and the second delay loop series are from a relatively high voltage power source.

According to another embodiment of the present invention, the delay loop device includes an external signal receiving loop, an amplification loop, a first delay circuit having a delay time equal to the delay time of the receiving loop, and a second delay circuit having a delay time equal to the amplification Delay time of the loop; one of the first signals passes through the receiving loop, the first delay loop, and the second delay loop in sequence and enters the first delay loop string; the first signal is input into the control loop after passing through the receiving loop ; And the output of the second delay circuit series is an input amplification circuit.

According to another embodiment of the present invention, the first signal and the second signal are composed of synchronization signal pulses having a fixed period within a predetermined allowable error range; the second signal is a pulse that lags behind the first signal by a predetermined number of pulses.

According to another embodiment of the present invention, the delay loop device includes a third delay loop capable of selecting one of most delay times by a majority of control signals and a fourth delay loop having the same configuration as the third delay loop; the third delay loop is connected in series with the third delay loop. 1 on the input path of the delay loop; the 4th delay loop is connected in series on the output path of the second delay loop; and the 3rd delay loop and the 4th delay loop are controlled to have the same delay time.

According to an embodiment of the present invention, the first delay loop series and the second delay loop series are composed of a reverse gate and a NANDS gate in principle.

According to another embodiment of the present invention, the internal circuit of the first delay circuit series and the internal circuit of the second delay circuit series are configured by a circuit configuration having a mirror-image relation.

According to another embodiment of the present invention, the first signal and the second signal are synchronization signals or clock pulses.

According to another embodiment of the present invention, the sum of the delay times of the first delay loop and the second delay loop is set as the time after subtracting the signal width of the external signal from the sum of the delay time of the receiving loop and the delay time of the amplification loop; 1 signal passes through the receiving loop in sequence, the first delay loop and the second delay loop are input to the first delay loop series; the first signal is input to the control loop after passing through the receiving loop; the output of the second delay loop series is inverted Enter the amplification circuit after reversing.

According to another embodiment of the present invention, the delay circuit device is configured to adjust the delay time of the first delay circuit by an electrical signal, and it includes a fuse circuit for generating an electrical signal.

According to another embodiment of the present invention, the delay loop device further includes a switching loop for when the interval between the first signal and the second signal is greater than the maximum delay time of the first delay loop series, and the delay time of the delay loop of the first delay loop. And the delay time of the second delay loop, the signal path is switched to the path that directly passes from the receiving loop to the amplification loop without going through the first delay loop train, the second delay loop train, the first delay loop, and the second delay. Loop; and when the interval between the first signal and the second signal is less than the sum of the maximum delay time of the first delay loop, the delay time of the first delay loop, and the delay time of the second delay loop The receiving circuit is switched directly through the path of the amplification circuit to the path of the first delay circuit series, the second delay circuit series, the first delay circuit and the second delay circuit.

According to another embodiment of the present invention, the switching circuit includes a hysteresis.

According to another embodiment of the present invention, the delay circuit device includes an actuation circuit for generating a first actuation signal and a second actuation signal; wherein the first actuation signal operates a receiving circuit; the second actuation signal operates a first delay circuit series, The second delay loop sequence, the first delay loop, and the input of the second delay loop; and when any of the first or second actuation signals is in a non-operation state, those in the first delay loop sequence are removed. All signals.

According to another embodiment of the present invention, the aforementioned operating circuit is controlled by any of an operating signal or a power-off signal of the synchronous memory circuit device.

According to another embodiment of the present invention, the delay loop device further includes a clock pulse output control loop for generating an output control signal; wherein the output control signal controls the output of the amplification circuit of the first signal or the second signal; and the output control signal is read It is controlled by the read mode signal, the burst mode signal, and the CAS potential signal of the synchronous memory loop device.

According to another embodiment of the present invention, the delay loop device further includes a clock mode signal generating circuit for generating a clock mode signal; wherein the clock mode signal switches the signal path from the diameter of the receiving circuit through the path of the amplification circuit to the first circuit. Delay loop cascade, the second delay loop cascade, the first delay loop, and the path of the second delay loop.

According to another embodiment of the present invention, the delay loop device is configured to adjust the delay time of the first delay loop by an electrical signal, the electrical signal is a signal that eliminates a phase difference between the external signal and the output of the amplification loop; the delay loop device additionally Contains a phase comparison circuit to generate the electrical signal.

According to another embodiment of the present invention, the delay time of the first delay loop train is set by a load adjustment loop connected to the second delay loop train.

According to another embodiment of the present invention, the load of the load adjustment circuit is controlled by a signal for controlling the load.

According to another embodiment of the present invention, the second delay loop series is composed of a plurality of delay loop series, and each of the plurality of delay loop series constituting the second delay loop series is paired with the first delay loop series. Each column has a prescribed delay time ratio; and the period of the first signal and the second signal to the synchronization signal also has various ratios.

According to another embodiment of the present invention, the fifth delay loop is arranged in the lower section after the second delay loop series; the delay time of the first delay loop series and the delay time of the second delay loop series are set to a predetermined ratio. ; The ratio of the sum of the delay time of the first delay loop and the delay time of the second delay loop to the delay time of the fifth delay loop is set equal to the delay time of the first delay loop series and the delay time of the second delay loop series. Proportion; the output of the 5th delay circuit, the OR output of the output of the 5th delay circuit and the output of the receiving circuit, the RS that resets and sets the action according to the output of the 5th delay circuit and the output of the receiving circuit The output of the flip-flop or the output of the frequency-division OR is the input amplification circuit.

According to another embodiment of the present invention, the fifth delay loop is disposed at a portion after the second delay loop series, and the second delay loop series is composed of a majority of the delay loop series; the delay of the first delay loop series The time and the delay time of the second delay loop are set to a predetermined ratio; the sum of the delay time of the first delay loop and the delay time of the second delay loop and the sum of the delay time of the fifth delay loop and the fifth delay loop The ratio is set equal to the ratio of the delay time of the first delay circuit series to the delay time of the second delay circuit series; the output of the fifth delay circuit, the OR output of the output of the fifth delay circuit and the output of the receiving circuit, according to the first 5 The output of the delay circuit and the output of the receiving circuit are reset and set. The output of the RS flip-flop or the divided output of the OR output is input to the amplification circuit.

According to another embodiment of the present invention, the second delay loop series is composed of two delay loop series; the delay time of the first delay loop series is equal to each of the two delay loop series of the second delay loop series. The listed delay time is set to a ratio of 2 to 1. The ratio of the delay time of the first delay circuit and the delay time of the second delay circuit to the delay time of the fifth delay circuit is set to be equal to the first delay circuit series. The ratio of the delay time to the delay time of the second delay loop series; the output of the first delay loop series is input via the control loop; the OR output of the output of the first delay loop series and the output of the second delay loop series It is the input of the 5th delay circuit; the OR output of the output of the 5th delay circuit and the output of the receiving circuit is based on the output of the 5th delay circuit and the output of the receiving circuit. The frequency division output is input to the amplification circuit.

According to another embodiment of the present invention, the ratio of the delay time of the first delay loop train to the delay time of the second delay loop train is set to the number of loops constituting the first delay loop train and the second delay loop train. The ratio of the number of circuits.

According to another embodiment of the present invention, the first delay loop series and the second delay loop series are formed into a loop; the delay loop device further includes a counter, and this counter is arbitrarily selected after the first signal is input from the first delay loop series. From the time until the control circuit inputs the second signal, it counts the number of times the first signal completes the loop around the first delay loop; and when the control circuit inputs the second signal, the first signal in the first delay loop string surrounds the first The number of 2 delay loop trains is transferred to the second delay loop train. At the same time, whenever the first signal finishes wrapping the second delay loop train, it is subtracted from the counted number of wraps, and when the first signal finishes wrapping the When the number of times of the delay loop sequence is the same as the number of times that the first delay loop sequence is completed, the second delay loop sequence is output.

According to another embodiment of the present invention, the counter includes an adder, a transmitter, and a subtractor, and the adder continuously counts the first signal loop that forms a loop of the first delay loop until the control loop inputs the second signal. The number of repetitions completed; when the control circuit inputs the second signal, the transmitter transfers the first signal on the first delay loop series to the second delay loop series, and simultaneously outputs the number of repetitions counted by the adder, the subtractor Each time the first signal completes the second delay loop sequence, it is subtracted from the number of repetitions of the output, and when the first signal completes the second delay loop sequence and the repetition of the first delay loop sequence is completed When the number of times is the same, it is serially output from the second delay circuit.

According to another embodiment of the present invention, the delay circuit device further includes a switching circuit. When the counter indicates the maximum value, the switching circuit switches the signal path from the receiving circuit to the amplification circuit directly without passing through the first delay circuit series. Delay loop cascade, the path of the first delay loop and the second delay loop; when the counter indicates less than the maximum value and there is a second signal input, the signal path is switched from the path directly from the receiving loop through the amplification loop to the first delay loop Cascade, the path of the second delay loop, the first delay loop, and the second delay loop.

According to another embodiment of the present invention, the switching circuit includes a hysteresis.

According to the present invention, the delay loop device includes a first delay loop series capable of drawing an output at any position on the signal transmission path, a second delay loop series capable of introducing an input from any position on the signal transmission path, and Control circuits for input terminals, output terminals, and input / output control terminals. The first delay loop series and the second delay loop series are configured so that their signal transmission paths are aligned in opposite directions; the output of the first delay loop series and the input of the second delay loop series pass through the control loop and from The input side close to the first delay loop train and the output side close to the second delay loop train are sequentially connected to each other. A first signal is input to the first delay loop train, and a second signal is input to the second delay loop train at any time thereafter to transfer the first signal on the first delay loop train to the second delay loop. String.

The first signal passes through the first delay loop during the difference between the input time of the first signal and the second signal.

Rear After the second signal is input to the control loop and the first signal on the first delay loop series is transferred to the second delay loop series, the first signal is performed in the second delay loop series for a period of time, and this period is equal to the second delay The transfer speed of the serial signal in the loop is divided by the transfer speed of the first delayed serial signal and multiplied by the difference between the input times of the first and second signals. In other words, the delay loop series is designed to have a delay time equal to the difference between the input time of the first signal and the second signal.

Here, the delay loop device is configured so that the transfer speed of the signal of the first delay loop series is equal to the transfer speed of the signal of the second delay loop series; the delay loop device includes an external signal receiving loop, an amplification loop, and has The delay time is equal to one of the delay times of the receiving circuit. The first delay circuit has a delay time equal to one of the delay times of the amplification circuit. The first signal passes through the receiving loop, the first delay loop, and the second delay loop in sequence, and then enters the first delay loop string. The first signal enters the control loop after the second signal passes through the receiving loop, and the second delay loop string. The output of the column is input to the amplification circuit. When the first signal is input with a clock pulse signal with a fixed period, the time difference from the introduction of the first signal to the first delay loop in series to the second signal entering the control loop one cycle after the second signal passes through the receiving loop is made equal to the delay time of the receiving loop. And the delay time of the amplification circuit subtracted from the period of the first signal. The output of the second delay circuit series is an input amplifier circuit.

The output of this amplification circuit provides a signal to the internal circuit. The timing of this signal is substantially equal to the timing of the first signal from the outside. The timing is exactly two times of the first signal from the first signal input receiving circuit. Delays in cycles.

In addition, the fifth delay loop is arranged in the lower section after the second delay loop series. The delay time of the first delay loop series and the delay time of the second delay loop series are set to a predetermined ratio. The first delay loop The ratio of the total of the delay time and the delay time of the second delay circuit to the delay time of the fifth delay circuit is the ratio of the first delay circuit sequence and the second delay circuit sequence; the output of the fifth delay circuit and The OR output of the output of the receiving circuit, the output of the RS flip-flop output or the divided output of the OR output are input to the amplification circuit. This OR output pulse is a pulse with an external input clock pulse period. This clock pulse has the ratio of the delay time of the first delay loop series and the delay time of the second delay loop series, plus

A new clock pulser. When the ratio is 2, the clock pulse which is one half of the external input pulse period but twice the frequency is supplied to the internal circuit in one clock period. The output of the RS flip-flop or the divided output of the OR output provides an internal clock and a clock pulse within two cycles. The clock pulse has a duty cycle equal to the delay time of the first delay loop series and the second delay. The ratio of the delay time of the loop series.

Furthermore, in the delay loop device of the present invention, the ratio of the delay time of the first delay loop series to the delay time of the second delay loop series is set to the number of loops constituting the first delay loop series and the second delay loop. The ratio of the number of loops in a series.

In addition, a counter is arranged on the delay loop device. Furthermore, the first delay loop series and the second delay loop series are formed into a loop; any time after the first signal is input to the first delay loop series. Until the control circuit inputs the second signal, the counter counts the number of repetitions of the first signal to complete the loop, and the first delay loop serial loop repeats; when the second signal is input to the control loop and the transmitter, the first delay loop serial The 1 signal is transferred to the second delay loop sequence. At the same time, the number of repetitions of the counter is decremented every time the sequence around the second delay loop is completed. When the first signal finishes repeating the second delay loop sequence, When it is equal to the number of repetitions around the first delay loop series, it is output from the second delay loop series. In other words, the setting of the counter is to provide an internal clock pulse with no delay time difference from the external clock pulse or a clock pulse with any duty cycle or any period, and even have several times longer than the first delay loop train and the second delay loop train. Clock of the period of the column.

The delay circuit device has a configuration that allows the delay time of the first delay circuit to be adjusted by an electrical signal, and includes a fuse circuit that generates the electrical signal. In other words, the settings can be changed by fuse trimming when changing specifications or when there is a time difference between the external clock and the internal clock after manufacturing.

In addition, the delay loop device includes a switching loop, when the interval between the first signal and the second signal is longer than the maximum delay time of the first delay loop series, the delay time of the first delay loop, and the delay time of the second delay loop. When the sum is made, the signal path is switched to the path directly from the receiving loop through the amplification loop without going through the first delay loop train, the second delay loop train, the first delay loop, and the second delay loop; when the first signal and The interval between the second signals is shorter than the maximum delay time of the first delay loop series, the delay time of the first delay loop, and the delay time of the second delay loop. The path switches to a path that passes through the first delay loop train, the second delay loop train, the first delay loop, and the second delay loop. Because the signal path is switched directly from the path of the receiving circuit through the amplification circuit to the path of switching through the first delay circuit series, the second delay circuit series, the first delay circuit and the second delay circuit, the path also contains hysteresis. Therefore, even if the external clock cycle exceeds the set maximum value of the loop of the present invention, a clock pulse can be provided to the internal loop.

Furthermore, because the delay loop device of the present invention is synchronized with an external clock within two clock pulses, by increasing the number of control loops, it is easy to control the clock pulses with the control signals of the synchronous memory device. Here is an example. The delay circuit device includes an operation circuit that generates a first operation signal and a second operation signal. The first operation signal operates a receiving circuit, and the second operation signal operates in series with the first delay circuit and a second delay circuit in series. , The input of the first delay loop and the second delay loop; when any of the first actuation signal or the second actuation signal is in an inactive state, all signals are removed from the first delay loop series. The operating circuit can be controlled by the action signal or the power-off signal of the synchronous memory circuit device. In addition, a clock output control circuit is included to output a clock output control signal. This clock output control signal controls the output of the first signal or the second signal output from the amplification circuit, and the clock output control signal is received by the read mode signal. Group mode signal and CAS latent signal of synchronous memory loop device. In addition, a clock mode signal generating circuit is included to generate a clock mode signal. The clock mode signal is a signal path directly from the receiving circuit through the path of the amplified circuit number and through the first delay circuit series, the second delay circuit series, Switch between the first delay loop and the second delay loop.

The configuration of the delay circuit device allows the delay time of the first delay circuit to be adjusted by an electrical signal. This electrical signal is used to eliminate the phase difference between the external signal and the output of the amplification circuit. In addition, the delay circuit device contains Phase comparison circuit of one of the signals. In other words, the phase difference between the external clock signal and the internal clock signal can be more accurately matched by the phase comparison loop. However, because there is no phase comparison circuit, the phase is matched in advance, so the phase adjustment using the phase comparison circuit to perform line correction can be completed in a very short time. In addition, the circuit using the phase comparison circuit can control the clock pulse in a wide frequency range.

The invention has the following effects:

1. The phase difference between the external clock pulse and the internal clock pulse can be reduced to less than the delay of the internal amplification. In addition, the internal clock pulse with the specified phase difference can be supplied in a minimum of two cycles.

2. As a result of the first effect, the circuit of the present invention does not need to operate frequently and can use an internal clock pulse with no phase difference from the external clock pulse at a prescribed timing, so it does not increase power consumption.

3. Because the circuit of the present invention uses most of the delay circuits with the same delay characteristics, even if the power supply voltage is reduced, the range of the controlled frequency will not change.

4. By increasing the number of loop sections, it is easy to achieve the accuracy of controlling clock pulses in a wide frequency range while maintaining a fixed control frequency, and when most delay loops are used according to the frequency range, after switching delay loops is completed The phase difference can be eliminated within two full cycles.

5. The conditions (voltage, device conditions) for eliminating the phase difference are not limited, so the initial investigation is no longer necessary.

6. There are fewer types of circuits used, so the defective components are easy to handle.

7.Because the full digital circuit is used, it is easy to use a counter for control, and when controlling a long period of clock pulses, the counter can be used to count the number of clock pulses around the delay circuit, thereby avoiding the sharp increase in the number of circuits to achieve Control over a wide cycle.

8. Ease of control Allows external signals beyond the control range to be switched to a loop that does not pass through the two delay loops of the present invention, thereby avoiding erroneous actions.

9. Because the phase difference can be eliminated in two cycles, the clock signal can be controlled using the command signal or the internal signal of the synchronous memory loop device, and the control action is performed only when needed in the overall circuit of the memory loop device, and in standby During the period, the operation can be stopped to save power.

10. Duty ratio and clock cycle can be easily set by adjusting the ratio of the delay time of the two delay loops in series.

11. By using a phase comparison circuit, the phase difference between the external clock pulse and the internal clock pulse can be more accurately matched. What's more, because the phase is matched in advance even if there is no phase comparison circuit, the phase adjustment using the phase comparison circuit for line correction can be completed in a very short period of time. In addition, a circuit using a phase comparison circuit can perform control over a wide frequency range.

12. Even if a delayed loop device or system installation is made, a fuse or an external signal can be used to set the clock timing.

The above and other objects, features and advantages of the present invention will become clearer from the preferred embodiments described below with reference to the accompanying drawings.

Figure 1 shows the loop diagram of the delay circuit of the conventional technology without PLL; Figure 2 is a waveform diagram illustrating the operation of the delay circuit shown in Figure 1; Figure 3 shows the circuit diagram of the delay circuit of the conventional technology using PLL; Fig. 4 is a circuit diagram showing a delay circuit of a conventional technology using a PLL and a frequency division circuit; Fig. 5 is a circuit diagram showing a first embodiment of the delay circuit of the present invention; and Fig. 6 is a waveform illustrating the operation of the first embodiment FIG. 7 shows a circuit diagram of the second embodiment of the delay circuit device of the present invention; FIG. 8 shows a circuit diagram of the third embodiment of the delay circuit device of the present invention; FIG. 9 Fig. 10 shows a circuit diagram of the fourth embodiment of the delay circuit device of the present invention; Fig. 10 shows a circuit diagram of the delay adjustment circuit 115 of the delay circuit 107 of the fourth embodiment; Fig. 11 shows a fifth embodiment of the delay circuit device of the present invention Fig. 12 shows the circuit diagram of the distributed circuit in the fifth embodiment; Fig. 13 shows the circuit diagram of the clock switching circuit 122 in the fifth embodiment; and Fig. 14 shows the maximum in the fifth embodiment. The circuit diagram of the cycle exceeding the detection circuit 123; FIG. 15 shows the circuit diagram of the clock operation circuit 124 in the fifth embodiment; FIG. 16 shows the circuit diagram of the sixth embodiment of the delay circuit device of the present invention; The circuit diagram of the phase comparison circuit 132 to the delay adjustment circuit 134 of the sixth embodiment is shown. FIG. 18 is a circuit diagram of the seventh embodiment of the delay circuit device of the present invention. FIG. 19 is a diagram illustrating the operation of the seventh embodiment. FIG. 20 shows a circuit diagram of the fourth embodiment of the delay circuit device of the present invention; FIG. 21 shows a circuit diagram of the ninth embodiment of the delay circuit device of the present invention. Fig. 22 is a circuit diagram showing a tenth embodiment of the delay circuit device of the present invention. FIG. 23 shows a circuit diagram of the eleventh embodiment of the delay circuit device of the present invention. FIG. 24 shows a circuit diagram of the eleventh embodiment of the delay circuit device of the present invention. FIG. 25 shows a circuit diagram of the adder 195, the transmitter 196, and the subtractor 197 in the twelfth embodiment; FIG. 26 shows a circuit diagram of the thirteenth embodiment of the delay circuit device of the present invention. FIG. 27 shows a circuit diagram of a delay circuit device 201 according to a thirteenth embodiment of the present invention; FIG. 28 shows a delay circuit device of the thirteenth embodiment mounted on a semiconductor device.

<u style="single">First Embodiment</u>

5 and 6 show a first embodiment of the present invention.

Referring to FIG. 5, this embodiment consists of a delay loop series 101, a delay loop series 102, a control loop 103, a load adjustment element 104, a receiving loop 105, an amplification loop 106, a delay loop 107 and a A delay loop 108 is formed. The delay loop series 101 can lead to an output at any position on the signal transmission path. The delay loop series 102 can lead to an input at any position on the signal transmission path. The control loop 103 has a signal input. The terminal and an output terminal and an input / output control terminal 109. The aforementioned load adjusting element 104 is used to flatten the load of the delay loop series 101 and the delay loop series 102. The aforementioned receiving circuit 105 is used for receiving external signals. 107 has a delay time equal to the receiving circuit 105, and the aforementioned delay circuit 108 has a delay time equal to the amplification circuit 106. The output 303 of the receiving circuit 105 is connected to the delay circuit 107 and the control terminal 109. The output of the delay circuit 107 is connected to the input of the delay circuit 108. The output of the delay loop 108 is connected to the input of the delay loop series 101. The output of the delay loop series 102 is connected to the input of the amplification loop 106.

The internal structure of the delay loop series 101, the delay loop series 102, the control loop 103, and the load adjustment element 104 will be described below. The delay loop series 101 and the delay loop series 102 are composed of inverters and NANDS arranged alternately, and the control loop 103 and the load adjustment element 104 are composed of NANDS. The delay loop series 101 is sequentially connected from the input side of NAND FN1, inverter FI1, NAND force FN2, inverter FI2, ..., NAND FNn, inverter FIn, NAND FNn + 1, Inverter FIn + 1, .... The delay loop series 102 is an inverter RI1, NAND, RNn, an inverter RI2, NAND, RN2, ..., an inverter RIn, NAND RN1, and an inverter RIn + which are sequentially connected from the output side. 1, NAND RNn + 1, ... The control circuit 103 is composed of NAND serial NAND CN1, NAND CN2, ..., NAND CNn NAND CNn + 1, ... having an input terminal connected to the control terminal 109. The load adjusting element 104 is composed of NAND serial NAND GN1, NAND GN2, ..., NAND GNn, NAND GNn + 1, ... having an input terminal connected to the ground line 110.

The interconnection of the delay loop series 101, the delay loop series 102, the control loop 103, and the load adjustment element 104 will be described below for each n-th element. The output of the reverse circuit FIn of the delay circuit series 101 is the other terminal of the two input terminals of the input NAND FNn + 1 and the NAND CNn connected to the control circuit 103. This terminal is not connected to the control terminal 109. The output of the NAND CNn of the control circuit 103 is connected to the other terminal of the two input terminals of the NAND FNn + 2 of the delay circuit series 101. This terminal is not connected to the output of the reverse circuit FIn + 1 and connected to the delay circuit series. The other one of the two input terminals of the 102 NAND RNn. This terminal is not connected to the output delay circuit of the reverse circuit RIn + 1. The output of the 102 NAND RNn is connected to the input of the reverse circuit RIn of the delay circuit. The output of the reverse circuit RIn of the delay circuit series 102 is the other terminal of the two input terminals of the input NAND RNn + 1 and the NAND GNn connected to the load adjustment element 104. This terminal is not connected to the ground line 110. The output of the NAND GNn of the load adjustment element 104 is not connected. In addition, the other terminal of the two input terminals of the NAND FN1 of the delay circuit series 101 which is not connected to the input terminal of the delay circuit series 101 is not connected to the output NAND of the inverter FI1. The other terminal of the two input terminals of FN2, and the other terminal of the two input terminals of the last NAND of the delay loop series 102 of the last NAND output of the control circuit 103 are connected to the power line 111.

The operation of this embodiment will be described below with reference to FIG. 6.

The input clock pulse 301 is a pulse with a low period H (high level) of the leading edge. The clock pulse group 302 represents the clock pulses that pass through the delay loop series 101 and are the output of the entire reverse-reverse brake in the delay loop series 101. The clock pulse 303 is an output of the receiving circuit 105 and represents a clock pulse input to the control terminal 109. The clock pulse group 304 indicates the clock pulses passing through the delay loop series 102 according to the outputs of all the reverse switches in the delay loop series 102. The clock pulse 305 indicates the output of the amplification circuit 106. Because these clock pulses are periodically input to this delay loop device, it is impossible to distinguish their respective pulses during actual use, but in order to simplify the description of the operation, any one of the clock pulses is taken as the m + 1th clock pulse and followed The clock pulse is the m + 2 clock pulse.

After the receiving loop 105, the m-th clock pulse enters the delay loop sequence 101 via the delay loop 107 (the delay time is equal to the delay time of the reception loop 105) and the delay loop 108 (the delay time is equal to the delay time of the amplification loop 106). And through the delay loop series 101, it is represented by the m-th clock pulse group in the clock pulse group 302. The output of the reverse gate which is passed in the delay loop series 101 becomes the m-th clock pulse of the H level and H is maintained during the width of the m-th clock pulse. One clock pulse period after the m-th clock pulse leaves the receiving circuit 105, the m + 1-th clock pulse is input from the receiving circuit 105 to the control terminal 109 and becomes the m + 1-th clock pulse of the clock pulse group 303. At this time, the m-th clock pulse is being passed through the delay loop sequence 101, for example, from the j-th reverse FIj (the first reverse of the H pulse) to the jk-th reverse FIj-k (the last reverse of the H pulse The m-th clock pulse of the gate width is advanced in the delay loop series 101, and the output from the j-th reverse gate FIj to the jk-th reverse gate FIj-k is the H output as described above. Therefore, the NANDs of the control loop 103 connected to the outputs of the reverse gates FIj to FIj-k during the passage of the m-th clock pulse The inputs of CNj to CNj + k are H, and the output becomes L (low level). As a result, although the NANDs inputs in the delay loop series 102 are all stand-by at H, the NANDs R0j to RNj in the delay loop series 102 connected to the NANDs CNj to CNj-k in the control loop 103 One of the two inputs of -k becomes L, so the output is switched from H to L, and the m-th clock pulse advances in the delay loop series 102 with the L pulse, and this L pulse is the m-th in the clock pulse group 304 Clock pulse group. In addition, the two inputs of NANDs FNj + 2 to FNj-k + 2 in the delay loop series 101 and the inputs of NANDs CNj to CNj-k connected to the control loop 103 also become L. As a result, all the inverters are reversed. The outputs FIj + 2 to FIj-k + 2 all become L, and the m-th clock pulse in the delay loop series 101 also becomes L. The m-th clock pulse leaving the delay loop series 102 is output via the amplification loop 106, which is the m-th clock pulse representing the clock pulse group 304.

The delay time will be explained below.

As described above, the delay times of the receiving loop 105 and the delay loop 107 are equal and represented by d1. At the same time, as described above, the delay times of the amplification circuit 106 and the delay circuit 108 are equal and represented by d2. The period of the clock pulse is tCK. The delay between the leading edge of the m-th clock pulse of the input clock pulse 301 and the leading edge of the m-th clock pulse of the input clock pulse 303 of the receiving circuit 105 is d1. The delay between the leading edge of the m-th clock pulse of the output clock pulse 303 of the receiving circuit 105 and the leading edge of the first clock pulse of the m-th clock pulse group of the clock pulse group 302 passing through the delay circuit sequence 101 The delay between the leading edge of the mth clock pulse of the output clock pulse 303 and the leading edge of the m + 1th clock pulse of the output clock pulse 303 of the receiving circuit 105, and this delay is tCK. Therefore, the time required for the leading edge of the clock pulse to pass through the delay loop series 101 is tCK-d₁-d₂, Or the delay time d of the delay loop 107₁And the delay time d of the delay loop 108₂Subtracted from clock cycle tCK. The delay loop of the delay loop series 102 passing by the L pulse leading edge of the clock pulse has the same number of segments as the delay loop of the delay loop series 101 passing the clock pulse leading edge. Therefore, the L pulse of the clock pulse The time that the leading edge passes through the delay loop train 102 is equal to the time that the clock pulse passes through the delay loop train 101. This time is the delay time d1 of the delay loop 107 and the delay time d2 of the delay loop 108. Or the time after tCK-d1-d2. The time required to pass through the amplification circuit 106 as described above is d2. The time through the receiving circuit 105, the delay circuit 107, the delay circuit 108, the delay circuit series 101, the delay circuit series 102, and the amplification circuit 106 is 2tCK. In addition, the m-th clock pulse is the same as the m + 2 clock pulse The timing is output to an internal circuit (not shown).

Moreover, in this embodiment, in order to make the delay time of the delay loop series 101 and the delay loop series 102 equal, the mask patterns of FNn, FIn, and CNn are, for example, masks for RNn, RIn, and GNn. Configure the mapping pair to equalize the load (refer to all the gates and lines connected to the delay loop series 101 and 102, the load loop adjustment element 104 of the delay loop series 102 and the control loop 103 of the delay loop series 101).

The power supply voltage supplied to the delay circuit device of this embodiment is derived from a constant voltage supply circuit mounted on a semiconductor circuit device, and the circuit device of this embodiment is mounted on a semiconductor circuit device. Therefore, the delay time of the delay loop device of this embodiment is independent of the external power supply voltage. In addition, by adjusting the voltage supplied by the constant voltage supply circuit, the number of gate sections in the delay circuit series 101 and the delay circuit series 102 can be adjusted, because when the voltage supplied by the voltage power supply is high, the delay circuit series 101, 102 The internal signal transmission speed is fast, otherwise it is slow.

According to this embodiment, it is possible to have an internal clock pulse that does not have a delay difference from an external clock pulse within exactly two clock pulses.

Although the delay circuit series 101, the delay circuit series 102, the control circuit 103, and the load adjustment element 104 in this embodiment are each composed of NANDs and reverse switches, these components may also be composed of other components. In addition, the error of the external clock 201 is allowable within a range that does not affect the operation of the internal circuit.

<u style="single">Second embodiment</u>

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 7.

As shown in FIG. 7, this embodiment is configured by adding a delay circuit 112 and a delay circuit 113 to the delay circuit device of FIG. 5. The foregoing delay circuit 112 allows a majority to be selected according to a plurality of control signals. 113 has a composition equal to the delay loop 112. The delay loop 112 is configured in series with the input path of the delay loop series 101, and the delay loop 113 is configured in series with the output path of the delay loop series 102. The delay loop 112 and the delay loop 113 The delay time is controlled to be equal.

The operation of this embodiment will be described below.

The operation of this embodiment is basically the same as that of the first embodiment. The difference between the two is that the delay time dV of the delay circuit 112 and the delay circuit 113 is adjusted. Therefore, the delay time will be explained first. As described above, the delay time of the receiving circuit 05 and the delay time of the delay circuit 107 are equal and represented by d1. At the same time, as mentioned above, the delay time of the amplification circuit 106 and the delay circuit 108 are equal and expressed as d2, the delay time of the delay circuit 112 and the delay circuit 113 is dV, and the period of the clock pulse is tCK. Therefore, the time of the leading edge of the clock pulse passing through the delay loop sequence 101 is the delay time d1 of the delay loop 107, the delay time d2 of the delay loop 108 and the delay time dV of the delay loop 112 are subtracted from the clock period tCK, or tCK-d1 Values after -d2-dV. The delay loop sequence 102 passing by the L pulse leading edge of the clock pulse has the same number of constituent sections as the delay loop sequence 101 passing by the clock pulse leading edge. Therefore, the L pulse leading edge of the clock pulse The time required to pass through the delay loop train 102 is equal to the time required for the leading edge of the clock pulse to pass through the delay loop train 101. This time is the delay time d1 of the delay loop 107, the delay time d2 of the delay loop 108, and the delay loop 113. The delay time dV is subtracted from the clock period tCK, or the time after tCK-d1-d2-dV.

As described above, the time when the clock pulse passes through the delay loop series 101 and the delay loop series 102 includes the delay time of the delay loop 112 and the delay loop 113. Therefore, if the clock period tCK is known in advance, dV may be set to be long, or if the clock period tCK is known in advance, dV may be set to be short.

From the above actions, it can be understood that with this embodiment, the required characteristics can be obtained in a wide frequency range without increasing the scale of the delay loop series 101 and the delay loop series 102.

<u style="single">The third embodiment</u>

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 8.

As shown in FIG. 8, this embodiment is provided with a reverse circuit 114 for inverting the input of the amplification circuit 106 to the delay circuit device of FIG. 5. The difference between this embodiment and the first embodiment lies in the delay circuit 107 and The sum of the delay times of the delay circuit 108 is set to a pulse width shorter than the sum of the delay times of the reception circuit 105 and the amplification circuit 106 by one clock pulse 301.

The operation of this embodiment is basically the same as that of the first embodiment. However, in the first embodiment, when the pulse is transmitted from the delay loop series 101 to the delay loop series 102, the H pulse system is inverted into L pulses. In this embodiment, the L pulse system is inverted into H pulses. And output. Because this embodiment also uses the leading edge of the output H pulse, the pulse width tPW needs to be adjusted.

The delay time distribution and output pulse timing will be described below. The sum of the delay times of the delay circuit 107 and the delay circuit 108 is shorter than the sum of the delay time of the reception circuit 105 and the delay time of the amplification circuit 106 by a pulse width tPW of the input clock pulse 301, or d1 + d2-tPW. Therefore, the time when the clock pulse passes through the leading edge of the delay loop series 101 is the sum of the delay time of the delay loop 107 and the delay time of the delay loop 108 d1 + d2-tPW subtracted from the clock period tCK, or tCK-d1-d2 + tPW After the value. The delay loop 102 passing through the leading edge of the L pulse of the clock pulse has the same number of segments as the delay loop passing through the delay loop sequence 101 of the clock pulse. Therefore, the clock pulse The time that the leading edge of the L pulse passes through the delay loop series 102 is equal to the time that the leading edge of the clock pulse passes through the delay loop series 101. This time is d1 + d2-tPW subtracted from the clock period tCK, or tCK-d1-d2 + tPW After the value. In addition, the time that the trailing edge of the L pulse of the clock pulse passes through the delay loop 102 is shorter than the leading edge time-pulse width tPW, or tCK-d1-d2.

From the above actions, it can be understood that with this embodiment, the required characteristics can be obtained in a wide frequency range without increasing the scale of the delay loop series 101 and the delay loop series 102.

<u style="single">Fourth Embodiment</u>

A fourth embodiment will be described below with reference to Figs. 9 and 10.

As shown in FIG. 9, this embodiment adds a delay adjustment circuit 115 and a delay circuit 107 to the delay circuit of FIG. 5. The delay circuit 107 is not a simple delay circuit but a variable delay that can be adjusted by the delay adjustment circuit 115. Circuit.

As shown in FIG. 10, in this embodiment, the delay circuit 107 is composed of a combination of eight capacitor elements 1103 and a transistor 1102. The capacitor element 1103 is connected to the node of the reverse-gate sequence 1101 via the transistor 1102. One of the transistors 1102 is always in a conductive state. As for the other transistors, one is controlled by the signal 1104, two are controlled by the signal 1105, and four are controlled by the signal 1106. The signals 1104, 1105, and 1106 are controlled by the fuse register 1107, the fuse register 1108, and the fuse register 1109 in the delay adjustment circuit 115, respectively. As a result, the capacitance value connected to the transistor 1102 has a level of 2 to 3 power, that is, the 8th order, and the delay loop 1107 has a 8th order delay time. The output levels of the fuse register 1107, the fuse register 1108, and the fuse register 1109 are determined by the connection status and the setting signal 1113 of the fuse 1110, the fuse 1111, and the fuse 1112.

In this embodiment, because the delay time of the delay circuit 107 can be adjusted by a fuse, the clock timing can be set after the semiconductor integrated circuit is completed.

<u style="single">5th embodiment</u>

Hereinafter, embodiments of the present invention applied to a dynamic random access memory (hereinafter referred to as DRAM) will be described with reference to FIGS. 11 to 14.

As shown in FIG. 11, the delay circuit device of this embodiment adds a distribution circuit 121, a clock pulse switching circuit 122, and a maximum period exceeding the detection circuit 123, a clock pulse activation circuit 124, and a clock pulse output control to the delay circuit device of FIG. 5. The circuit 125 and the clock mode signal generation circuit 126 are configured.

The distribution circuit 121 and the clock pulse switching circuit 122 are separated or fed most clock pulse paths, and these paths are controlled by many signals.

The maximum period exceeds the detection circuit 123, the clock pulse actuation circuit 124, the clock pulse output control circuit 125, and the clock pulse mode signal generation circuit 126 are circuits for generating a clock pulse path for controlling the distribution circuit 121 and the clock pulse switching circuit 122. And these circuits are controlled by control signals.

The distribution circuit 121 inputs the output of the receiving circuit 105 as a clock pulse input, and separates and outputs the distribution circuit output 1211 and the distribution circuit output 1212 as a clock pulse output. The distributed circuit output 1211 is input to the delay circuit 107, and the distributed circuit output 1212 is input to the control terminal 109 and the maximum cycle exceeds the detection circuit 1203.

The signals of the control distribution circuit 121 are a clock pulse activation signal 1214, a clock pulse activation signal 1215, and a clock pulse mode signal 1217.

FIG. 12 shows a circuit diagram of the distribution circuit 121. As described above, the output of the receiving circuit 105 is a clock pulse output of H pulses output at a fixed period. When the clock pulse mode signal 1217 is H and the output of the receiving circuit 105 is directed through the distribution circuit 121, the distribution circuit output 1211 and the distribution circuit output 1212 form a clock pulse output. When the clock pulse mode signal 1217 is H and the output of the receiving circuit 105 is not directed through the distribution circuit 121, the distribution circuit output 1211 is fixed at L, and the distribution circuit output 1212 is fixed at L or H. When the clock pulse actuation signal 1214 is H, the distribution loop output 1212 generates a loop equal to the distribution loop output 1211, and when the clock pulse actuation signal 1214 is L, the distribution loop output 1212 is fixed at H. The clock pulse of the receiving circuit 105 input after the clock pulse actuation signal 1215 becomes H is guided through the distribution circuit 121, and the distribution circuit output 1211 and the distribution circuit output 1212 output clock pulses. The clock pulse of the receiving circuit 105 input after the clock pulse actuation signal 1215 becomes L is not directed through the distribution circuit 121, and if the distribution circuit output 1211 is fixed at L, the distribution circuit output 1212 is fixed at L or H. When the pulse output from the receiving circuit 105 passes through the distribution circuit 121, the pulse width is adjusted to the delay width of the four reverse gate sections and one NOR section.

The clock pulse switching circuit 122 is disposed between the delay circuit series 102 and the amplification circuit 106 and inputs the output of the delay circuit series 102 and the output of the receiving circuit 105. In addition, the output of the clock pulse switching circuit 122 is input to the amplification circuit 106.

The signals controlling the clock pulse switching circuit 122 are a clock pulse output control signal 1216, a clock pulse mode signal 1217, and a clock pulse switching signal 1218.

FIG. 13 shows a circuit diagram of the clock pulse switching circuit 122.

After the clock pulse output control signal 1216 becomes H, the clock pulse output of the receiving circuit 105 or the clock pulse output of the delay circuit series 102 is guided through the clock pulse switching circuit 122, and the output of the clock pulse switching circuit 122 generates the H clock pulse output . After the clock pulse output control signal 1216 becomes L, the clock pulse output of the receiving circuit 105 or the clock pulse output of the delay circuit series 102 is not directed to the clock pulse switching circuit 122, and the output of the clock pulse switching circuit 122 is fixed to L. . When both the clock pulse mode signal 1217 and the clock pulse switching signal 1218 become H, the output of the delay loop series 102 can be directed to the clock pulse switching circuit 122, and when one of the clock pulse mode signal 1217 and the clock pulse switching signal 1218 Or, when both become L, the output of the receiving circuit 105 can be directed to the clock switching circuit 122.

When the clock pulse passing through the delay loop series 101 is input with a period longer than the time required to reach the farthest end of the delay loop series 101, and when the maximum period of the output is H pulse exceeds the signal 1213, the input maximum period exceeds the detection loop At 123, the maximum period exceeds the signal 1213, which is input from the leading edge of the first H pulse of the output 1212 of the distribution circuit, and the clock pulse switching signal 1218 is changed from H output to L output by the following H pulse.

Once the clock pulse switching signal 128 becomes L, it has the hysteresis of returning to the H output when the maximum period exceeds the signal 1213 during the H pulse input to the three distributed loop outputs 1212. When the clock switching signal 1218 is H, the clock switching circuit 122 allows the output of the delay loop series 102 to pass, and when the clock switching signal 1218 is L, the output of the receiving circuit 105 is allowed to pass.

The maximum cycle exceeding detection circuit 123 operates in accordance with the clock pulse signal 1215. When the maximum period exceeds the signal 1213 input RS F / F1221, D-LAT1222 and DF / F 1223 (Figure 14), the distributed circuit output 1212 is used.

FIG. 14 shows a logic diagram of the maximum cycle exceeding detection circuit 123. When the maximum period exceeds the signal 1213 and the H pulse is input, the output of RS-R / F1221 becomes the L output until the signal with the delay added to the output of the distribution loop becomes the H pulse next time. The L output of RS-F / F1221 first borrows the leading edge input, whereby the distributed circuit output 1212 becomes H at D-LAT1222, and the H pulse is output from QB of D-LAT1222. The H pulse output from D-LAT1222 is then input through the trailing edge, whereby the distributed loop output 1212 then changes from H to L at DF / F1223 and outputs H from Q of DF / F1223. H of the Q output from DF / F1223 is input by the trailing edge, whereby the distribution loop output 1212 changes from H to L at DF / F1224 after two stages, and H from the Q output of DF / F1224. The H output from the Q of DF / F1224 is input by the trailing edge, thereby changing from H to L at DF / F1225 after two stages, and output H from the Q of DF / F1225. DF / F1233's QB output, DF / F1224's QB output and DF / F1225's QB output are inputs 3-input NAND 1226, 3-input NAND 1226 output is used as the output clock switching signal 1218 whose maximum period exceeds the detection circuit 123 .

During the L output period, the clock pulse actuation signal 1215 fixed the QB output of D-LAF1222 to L, fixed the QB of DF / F1223 to H, fixed the QB output of DF / F1224 to H, and fixed the QB output of DF / F1225 to H and a fixed maximum period exceeding the output clock pulse switching signal 1218 of the detection circuit 123 is H. In addition, during the L output period, the clock pulse actuation signal 1215 fixedly outputs 1212 to H, and at this time, RS-F / F1221 is fixed to H.

The clock pulse operation circuit 124 inputs an operation signal 1219 and a power-off signal 1220, and outputs a clock pulse operation signal 1214 and a clock pulse operation signal 1215. The clock pulse operating circuit 124 is controlled by a clock pulse output control signal 1216.

FIG. 15 shows a circuit diagram of the clock operation circuit 124.

The clock pulse actuation circuit 124 generates the H output of the clock pulse actuation signal 1214 when the output of the actuation signal 1219 is L, and generates the H output of the clock pulse actuation signal 1215 after a set time interval. The output of the actuation signal 1219 as the H clock pulse actuation signal 1214 generates an L output, and the L output of the clock pulse actuation signal 1215 is generated at almost the same time. When the power-off signal 1220 is output as L, the clock pulse actuation signal 1214 generates an L output, and at almost the same time, the clock pulse actuation signal 1215 generates an L output. In addition, when the clock control signal 1216 is H, the clock operation signal 1214 generates an H output, and the clock operation signal 1215 also generates an H output.

When the clock pulse operating signal 1214 becomes H, the receiving circuit 105 operates, and the distribution circuit output 1212 changes from a fixed H to a state where the clock output is allowed. When the clock operation signal 1214 becomes L, the receiving circuit 105 stops, and the distribution circuit output 1212 is fixed at H. When the distributed loop output 1212 is fixed at H, all H pulses passing through the delay loop series 101 are transferred to the delay loop series 102, and all H pulses in the delay loop series 101 are fixed at L.

When the clock pulse actuation signal 1214 generates H, but becomes L after a fixed time interval, the receiving circuit is the action device. After reaching the state capable of outputting a complete pulse, the output of the receiving circuit 105 is placed in a state that allows the distribution circuit 121 to pass. In addition, when the maximum period exceeds the signal 1213 input, the clock pulse switching signal 1218 output from the maximum period detection circuit 123 changes from a fixed H to a state where the clock pulse switching signal 1218 can be synchronized with the announcement circuit output 1212.

The clock mode signal generating circuit 126 outputs a clock signal 1217. This clock pulse mode 1217 is input to the announcement circuit 121 and the clock pulse switching circuit 122. During the H output of the clock pulse mode signal 1217, the clock pulse output by the receiving circuit 105 passes through the distribution circuit 121 and can pass through the delay circuit 107, the delay circuit 108, the delay circuit sequence 101, and the delay circuit sequence 102. During the L output period of the clock mode signal 1217, the clock pulse output by the receiving circuit 105 passes through the distribution circuit 121, but cannot pass through the delay circuit 107, the delay circuit 108, the delay circuit sequence 101, and the delay circuit sequence 102.

The clock pulse output control circuit 125 outputs a clock pulse output control signal 1216 according to the read mode signal 1231, the data group mode signal 1232, and the CAS latent signal 1233. The read mode signal 1213 is a signal for instructing the DRAM to enter a data read cycle period and is input from the outside at a fixed time interval after the actuation signal 1219 becomes H. This fixed time interval must be longer than the time interval between the H output of the pulse actuation signal 1214 and the H output of the clock actuation signal 1215. The data group mode signal 1232 is a signal indicating the number of clock pulses when the DRAM continuously outputs data during a data read cycle. The CAS latent signal 1233 is the number of clock pulses during the period from the input of the read mode signal 1231 to the output of the data. The data group mode signal 1232 and the CAS potential signal 1233 are both preset signals.

After the read mode signal 1231 becomes H, the clock pulse output control signal 1216 is within the interval of the number of clock pulses represented by the data group mode signal 1232 plus the number of clock pulses represented by the CAS latent signal 1233 Output H.

In this example, if the clock pulse frequency becomes longer and the clock pulse has not been transferred to the delay loop series 102 even if the clock pulse has reached the farthest end of the delay loop series 101, that is, the clock pulse is not supplied to the internal In this case, it can be avoided by the output of the input receiving circuit 105 to the amplification circuit 106. Furthermore, frequent changes in the output timing of the clock pulse can be avoided by providing the hysteresis in the clock pulse switching. In addition, by operating the clock pulses in accordance with the operation of the DRAM, in addition to the need, the clock pulses can be stopped to reduce power consumption. In addition, the operating timing of the external clock pulses and the operating timing of the internal clock pulses received by fluctuations can suppress damage occur. Finally, when the clock pulse stops, all the H pulses in the delay loop series 101 are transferred to the delay loop series 202, and the pulses in the delay loop series 101 are fixed to L, thereby eliminating the delay loop series. Unwanted actions in 101 and delay loop series 102.

<u style="single">Sixth embodiment</u>

A sixth embodiment of the present invention will be described below.

As shown in FIG. 16, this embodiment is configured by adding a delay circuit 131, a phase comparison circuit 132, a filter 133, and a delay adjustment circuit 134 to the delay circuit device of FIG. 5.

The delay loop 131 is set to a delay time equal to the delay time of the receiving loop 105. The delay loop 107 is not merely a delay loop but a variable delay loop that can be adjusted by the delay adjustment loop 134. The output of the amplification circuit 106 is input to the delay circuit 131, and the output of the delay circuit 131 is input to the phase comparison circuit 132. The phase comparison circuit 132 inputs the output of the receiving circuit 105. The phase comparison circuit 132 is an output signal based on the phase difference between the output of the delay circuit 131 and the output of the receiving circuit 105. This signal is input to the delay adjustment circuit 134 via the filter 133. The output of the delay adjustment circuit 134 is input to the delay circuit 107. This output adjusts the delay time of the delay circuit 107 to eliminate the phase difference between the output of the delay circuit 131 and the output of the receiving circuit 105.

FIG. 17 shows a circuit diagram from the phase comparison circuit 132, the filter 133, and the delay adjustment circuit 134 to the delay circuit 107 in this embodiment.

In this embodiment, the delay circuit 107 is the same as the delay circuit of the fourth embodiment, and has a combination of eight capacitor elements 1103 and a transistor 1102. The capacitor element 1103 is connected to the node of the reverse-gate series 1101 via the transistor 1102. . One of these transistors 1102 is often in a conductive state. As for the other transistors, one is controlled by signal 1104, two are controlled by signal 1105, and four are controlled by signal 1106. Each of the signals 1104, 1105, and 1106 is controlled in turn by a 3-bit counter in the delay adjustment circuit 134. Therefore, the capacitance value connected to the transistor 1102 has a level of 2 to 3 power, that is, there is an 8th order, and the delay loop 107 has a 8th order delay time. The 3-bit counter in the delay adjustment circuit 134 is controlled by a count-up signal 1303 and a count-down signal 1304 output from the filter 133. The filter 133 is controlled by a rising signal 1301 and a falling signal 1302 output from the phase comparison circuit 132.

In this embodiment, the filter 133 has the structure of a filter with N inductive reactances and M capacitors, where N = 4 and M = 6. The phase comparison circuit 132 is composed of NANDs and outputs a falling signal 1302 when the phase of the output of the delay circuit 131 leads the phase of the output of the receiving circuit 105, and outputs a rising signal 1301 when the phase of the output of the delay circuit 131 falls behind. The delay loop 107 has a delay time of eight steps. In the case of the delay time, the delay time after the addition of the NAND FNn and the reverse circuit FIn of the delay loop series 101 is divided into eight equal time intervals. In this embodiment, the delay time after the addition of the NAND FNn of the delay loop series 101 and the reverse gate FIn is 0.4 × 10.^-9Seconds, so the unit of the 8th order of the delay time of the delay loop is 0.05 × 10^-9second.

According to this embodiment, a clock pulse having a small phase difference between the external clock pulse and the internal clock pulse can be supplied in a relatively short time. In addition, since the phase difference is almost eliminated before passing through the delay loop series 101 and the delay loop series 102, as in the case of the phase comparison loop 132, the clock pulse can be controlled in a wide frequency range. Furthermore, although the filter 133 and the delay adjustment circuit 134 of this embodiment are digital circuits, these circuits can also be configured as analog circuits composed of capacitors and resistors.

<u style="single">Seventh embodiment</u>

An embodiment of the present invention will be described below with reference to FIGS. 18 and 19.

Referring to FIG. 18, in this embodiment, in addition to the delay loop series 141 instead of the delay loop series 101, the delay loop series 142 instead of the delay loop series 102, the control loop 143 instead of the control loop 103, and the load adjustment element 144 instead of the load adjustment element 104, The delay circuit 145 and the OR circuit 147 are arranged between the delay circuit series 142 and the amplification circuit 106, and in addition to RS-F / F148, the pulse width correction circuit 146, and the amplification circuit 149, they are almost the same as those shown in FIG. The circuit is the same.

The delay loop series 142 is composed of a half element of the delay loop series 141 or half of the elements of the delay loop series 102 shown in FIG. 5. Each other unit is half of the output of the delay loop series 141 and is connected to the input of the delay loop series 142 via the control loop 143, because the delay loop series 142 is composed of the delay loop series 141 or the delay loop series of FIG. 5 The delay time composed of half of the components of 102 is half of the delay time of the delay loop series 141 or the delay loop series 102. In addition, the pulse width of the pulses transmitted from the delay loop series 141 is also halved.

The delay circuit 145 has a delay time (d1 + d2) / 2 + tPW / 2. This delay time is one half of the delay time d1 of the delay circuit 107 plus the delay time d2 of the delay circuit 108, or (d1 + d2 / 2), In addition, half of the time of the pulse width tPW of the output of the receiving circuit 105, or tPW / 2. As in the third embodiment, this embodiment uses the output of the delayed loop 142 which has been reversed, so one of the pulse width tPW of the output of the receiving loop 105, that is, tPW / 2 is added to the delay time for timing correction. use.

The pulse width of the pulse width correction circuit 146 is half of the pulse width of the receiving circuit 105.

The OR circuit 147 combines the output of the delay circuit 145 and the output of the pulse width correction circuit 146. The RS-F / F148 outputs a pulse having a pulse width from the leading edge of the output of the pulse width correction circuit 146 to the leading edge of the output of the delay circuit 145.

The operation of this embodiment will be described below with reference to FIG. 19.

The H clock pulse 301 input to the receiving circuit 105 is adjusted by the receiving circuit 105 to a clock pulse width tPW and is output after d1 interval. It passes through the delay circuit 107 and the delay circuit 108 during the time interval d1 + d2, and then enters the delay circuit sequence 141 and The delay loop sequence 141 continues to advance until a clock pulse is input to the control loop 103 under the output of the receiving loop 105. In the case of the leading edge, the time of the H clock pulse passing through the delay loop series 141 is equal to the time (d1 + d2) subtracted from the clock period tCK, that is, tCK- (d1 + d2), and the subsequent value is at the trailing edge. In this case, it is equal to the time (d1 + d2) subtracted from the clock period tCK, that is, tCK- (d1 + d2) -tPW, and the value thereafter. When the next clock pulse output from the receiving circuit 105 is input to the control circuit 143, the H pulse is transferred to the delay circuit series 142 and becomes an L clock pulse.

The leading edge of the L pulse passing through the delay loop series 142 passes through the delay loop series 141 in half of the tCK- (d1 + d2) time, that is, {tCK- (d1 + d2) / 2}. The trailing edge of the L pulse passing through the delay loop series 142 passes through the delay loop series 141 with half of tCK- (d1 + d2) -tPW time, that is, {tCK- (d1 + d2) -tPW} / 2.

The L pulses leaving the delay loop series 142 are in the delay loop 145 and are inverted into H pulses. The delay time of the delay loop series 142 is (d1 + d2) / 2 + tPW / 2. Therefore, the time from the time when the delay loop series 141 is transmitted to the delay loop series 142 until the output from the delay loop 145 is tCK / 1, or as the leading edge of the L clock pulse through the delay loop series 142, is The time {tCK- (d1 + d2) -tPW} / 2 through the delay loop serial 141 plus the time (d1 + d2) / 2 + tPW / 2 through the delay and reverse delay 145.

In addition, the delay time of the pulse width correction circuit 146 is small and is set to be different from the delay time of the delay circuit 145 by tCK / 2.

As a result, the output of the OR circuit 147 is a combination of the clock pulse output of the delay circuit 145 and the output of the pulse width correction circuit 146. The output is a clock pulse whose period is twice larger than the period of the receiving circuit 105. The output of the OR circuit 147 is amplified by the amplification circuit 106 to a desired driving capacity.

The output of RS-F / F148 is a pulse with a pulse width from the leading edge of the output of the pulse width correction circuit 146 to the leading edge of the output of the delay circuit 145. In this case, the pulse width is exactly the pulse width of the clock pulse period One and a half. The output of RS-F / F148 is amplified by the aquarium circuit 149 to the required driving capacity.

If this is not the case, the output of the delay loop series 142 is amplified to its desired value and output, and can be used as a clock pulse having a timing of one-half of the external clock cycle.

Compared with the traditional PLL, which requires tens of cycles to tens of thousands of cycles, as explained above, this embodiment allows a clock pulse with a double period of 50% duty cycle to be generated after one clock pulse. In addition, by combining the loops of the first to sixth embodiments, this embodiment can generate a clock pulse having a period twice as long as a phase difference or a delay difference from an external clock pulse or a clock pulse having a duty cycle of 50%. In addition, combining these embodiments can generate clock pulses of 4 or 8 times the period.

<u style="single">Eighth embodiment</u>

Hereinafter, an eighth embodiment of the present invention will be described with reference to FIG. 20.

Referring to FIG. 20, the delay loop series 152 is almost the same as the circuit of FIG. 18 except that the two sets of delay loops are combined. The odd-numbered output of the delay loop series 151 is connected to one of the delay loops in the delay loop series 152 via the control loop 153. , And the even-numbered output is connected to another group of delay circuits in the delay circuit series 152 via the control circuit 153. Each of the two sets of delay loops in the delay loop series 152 is composed of half of the components of the delay loop series 151, and the delay time is one and a half time of the delay loop series 151 or the delay loop 102. In addition, from the delay loop series 151 The output pulse width is half the width. The outputs of the two sets of delay loops are input to the delay loop 145 after the OR loop 155 performs the OR operation.

This embodiment has the same effect as the seventh embodiment, but the signal decomposition capability can be changed by forming and performing an OR operation on two sets of delay loop series with odd and even outputs of the delay loop series 151.

Compared with the traditional PLL, which requires tens of cycles to tens of thousands of cycles, as described above, this embodiment allows a pulse having a double period of 50% duty cycle to be generated after one clock pulse. In addition, combining the loops of the first to sixth embodiments can generate a clock pulse with a period twice as long as the phase difference or delay difference from the external clock pulse and generate a clock pulse with a duty cycle of 50%. In addition, combining these embodiments can generate clock pulses of 4 or 8 times the period.

<u style="single">Embodiment 9</u>

A ninth embodiment of the present invention will be described below with reference to FIG. 21. In this embodiment, in addition to the second delay loop series, it is clearly divided into two groups of delay loop series, that is, the delay loop series 162A and the delay loop series 162B, and each delay loop series is connected to the load adjustment elements 164A and 164B The margin is almost the same as the circuit of FIG. The delay loop series 162B outputs a clock pulse at the delay loop series 162A. The clock pulse lengthens a delay time of (d1 + d2). This delay time is the delay time d1 of the delay circuit 107 and the delay of the delay circuit 108. The sum of time d2. As a result, d1 + tCK + tCK- (d1 + d2) = 2tCK-d2 is required for the output of the delay loop series 162A from the time when an external clock pulse is input to the reception loop 105 until the output from the delay loop series 162A, but Until the output from the delay loop series 162B, d1 + tCK + {tCK-2 (d1 + d2)} / 2 = tCK + tCK / 2-d2 is required. The same result as in the seventh embodiment is obtained in the case where a clock pulse is used after the inversion. Therefore, the timing difference between the output of the delay loop series 162A and the output of the delay loop series 162B is one and a half times of the clock cycle tCK, and further, the timing is faster than the delay time d2 of the -amplification circuit 106. Therefore, the output of the amplification circuit 106 is a clock pulse composed of a clock pulse with no delay with the external clock and a clock pulse moving one cycle. The output of the amplification circuit 149 via RS-F / F148 becomes a 50% duty cycle and Clock pulses without delay with external clock pulses. The output of the amplifying circuit 1069 is derived from the OR circuit 147. The OR circuit 147 is the output of the delay circuit sequence 162A and the delay circuit sequence 162B output from the pulse width correction circuit 146. The output performs an OR operation.

This embodiment can generate a clock pulse having a period twice as long as a delay difference or a phase difference from an external clock pulse, and generate a clock pulse with a duty cycle of 50% within two periods. In addition, as in the eighth embodiment, an OR operation can be performed on two sets of delay loop series 162A and 162B.

<u style="single">Tenth embodiment</u>

Hereinafter, a tenth embodiment of the present invention will be described with reference to FIG. 22. Referring to FIG. 22, in addition to the load adjustment element 174 in this embodiment, NANDs transistors GM1, ..., GMn, ... and capacitive elements GC1, ..., GCn, ... are used instead of NANDs GN1, ..., GNn, ..., the outside is almost the same as the circuit of FIG. 18, the aforementioned capacitive elements GC1, ..., GCn, ... are connected to the delay circuit series 172 via the NMOS transistors GM1, ..., GMn. Outputs of reverse brakes FI1, ..., FIn, .... The gate electrodes of the NMOS transistors GM1, ..., GMn, ... of the load adjustment element 174 are connected to the load adjustment terminal 175, and the load of the load adjustment element 174 is changed by a voltage applied to the load adjustment terminal 175.

In this embodiment, the delay time of the delay loop series 172 can be adjusted by adjusting the load of the load adjustment element 174. In addition, it can also generate any duty cycle and clock pulse of any frequency.

In this embodiment, the ratio of the number of the loop elements of the delay loop series 171 to the number of the loop elements of the delay loop series 172 is 2 to 1, but a 1 to 1 ratio or other ratio can also be applied to this embodiment.

<u style="single">Eleventh embodiment</u>

Hereinafter, an eleventh embodiment of the present invention will be described with reference to FIG. 23. Referring to FIG. 23, this embodiment is almost the same as the circuit of FIG. 18 except that the delay loop series 182 is formed by two sets of delay loop series. One of the two sets of delay loop series described above is composed of the delay loop series 181 1/3 of the number, and the other group is composed of 2/3 of the number of components of the delay loop series 181. Each group of delay loop series is connected to each 3 of the delay loop series 181 via the control loop 183. 1 output or 2 outputs every 3 outputs.

The outputs of the two delay loop series of the delay loop series 182 are used after being inverted. Among the two delay loop series of the delay loop series 182, the output of the delay loop series consisting of 1/3 of the number of components of the delay loop series 181 is connected to the delay loop 145, and the delay time of the delay loop 145 Set to (d1 + d2-tPW) / 3. The output of this delay circuit 145 is input 3-input OR circuit 187. Among the two delay loop trains in the delay loop train 182, the output of the delay loop train composed of two thirds of the number of components of the delay loop train 181 is connected to the pulse width correction circuit 185 and the pulse width correction circuit. 185 sets the pulse width to 1/3 of the output pulse width of the receiving circuit 105. The output of the pulse width correction circuit 185 is connected to the delay circuit 186. The delay time of the delay circuit 186 is set to (d1 + d2-tPW) (2 / 3), the output of the delay circuit 186 is 3-input OR circuit 187, the output of the receiving circuit 105 is connected to the pulse width correction circuit 146, and the pulse width correction circuit 146 sets the pulse width to 1/1 of the output pulse width of the receiving circuit 105 3. The output of the pulse width correction circuit 146 is an input 3-input OR circuit 187. The output of the 3-input OR circuit 187 is supplied to the internal circuit via the amplification circuit 106 as a clock pulse having a frequency of 3 times the frequency of the external clock. . In addition, the output of the delay circuit 145 and the output of the pulse width correction circuit 146 are input RS-F / F148. The output of this RS-F / F148 is a clock pulse with 33% duty cycle and is supplied to the internal circuit through the amplification circuit 149. .

In this embodiment, because the delay time ratio between the delay time of the delay loop series 181 and each of the two delay loop series in the delay loop series 182 is set to 3 to 1 and 3 to 2, the delay loop series The number of delay loops in column 182 and the number of loops in load adjustment element 184 are set to 1/3 and 2/3 of delay loop series 181, respectively, but any ratio, such as 1/5 or 3/5, can also be selected To generate clock pulses with any duty cycle or any frequency. Furthermore, by not outputting the delay loop series 182 inserted into the OR loop 187 or RS-F / F148, a clock pulse having a timing of 1/2 or 2/3 of the period of the external clock pulse can be supplied to the internal loop.

<u style="single">Twelfth embodiment</u>

A twelfth embodiment of the present invention will be described below with reference to Figs. Referring to FIG. 24, this embodiment includes a delay circuit series 191, a delay circuit series 192, a control circuit 193, and a load adjustment element 194. These circuits and components are substantially equal to the delay circuit series 101, 102, and the control circuit 103 of FIG. 5, respectively. And load adjustment element 104, this embodiment further includes an adder 195, a transmitter 196, a subtractor 197, and a delay circuit 198. The delay loop sequence 191, the delay loop sequence 192, the control loop 193, and the load adjustment element 194 are almost the same as the delay loop sequence 101, the delay loop sequence 102, the control loop 103, and the load adjustment element 104 of the first embodiment, respectively. However, the output of the last reverse-reverse switch FIz of the delay loop series 191 is input to the first NAND FN1 of the delay loop series 191, and the output of the last second reverse-reverse switch FIz-1 of the delay loop series 191 is the input control loop. The output of the last second NAND CNz-1 of 193 is the first NAND FN1 of the input delay loop series 191, and the output of the last NAND CNz of the control loop 193 is the second NAND FN2, NAND of the input delay loop series 191 FNIN is configured in FN1 instead of the lower section after the reverse circuit FI1. The output of the delay circuit 108 is input through the reverse circuit. NAND RNz, NAND RNIN is configured at the last NAND RNz of the delay loop series 192, instead of the reverse RIz. The output of the subtractor 197 is input to the NAND RNIN through the reverse gate, and the delay loop is 192. The output of the first reverse gate RI1 is input to the amplification circuit 106 via the NAND 199.

The H pulse output of the receiving circuit 105 is an input delay circuit 107, a delay circuit 198, and a subtractor 197. The output of the delay circuit 107 is input to the delay circuit series 191 via the delay circuit 108 and the reverse circuit. The H pulse entering the delay loop series 191 continues to pass through the delay loop series 191 during the next H pulse output from the receiving loop 105, and returns to the first NAND FN1 to continue when it reaches the last reversed loop FIz of the delay loop series 191 cycle.

The adder 195 counts the H pulses output from the reverse circuit FIz of the delay loop series 191 during the period from the H pulse output from the receiving circuit 105 to the next H pulse. In this embodiment, the output of the adder 195 represents the 4-bit output 1905-1, 1905-1B, 1905-2, 1905-2B, 1905-3, 1905-3B, 1905-4, and 1905-4B phases. Plus the results. When the H pulse leaves the receiving circuit 105, the output of the calculator 195 becomes a 4-bit output via the transmitter 196. 1906-1, 1906-1B, 1906-2, 1906-2B, 1906-3, 1906-3B, 1906-4 And 1906-4B to the subtractor 197. When the H pulse leaves the receiving circuit 105, the H pulse in the delay circuit series 191 is transmitted to the delay circuit series 192, and becomes an L pulse and passes through the delay circuit series 192. When the reverse pulse RI1 is reached, it is input. NAND RNz, and then pass through the delay loop series 192 again. The count sent to the subtractor 197 by the L pulse output from the reverse loop RI1 of the delay loop series 192 is subtracted. When the count becomes "0", the subtracter 197 The output 1910 is changed from L to H, and the output of the reverse circuit RNIN of the delay circuit string 192 is fixed to L. At the same time, the output of the reverse circuit RI1 in the delay circuit series 192 is input to the amplification circuit 106 via the NAND 199.

If the H pulse in the delay loop series 191 leaves the receiving loop 105 until it outputs the next H pulse and does not reach the final reversed gate FIz of the delay loop series 191, the output of the subtractor 197 remains at H, with the result from The pulse transmitted from the delay loop series 191 to the delay loop series 192 causes the output of the reverse-reverse gate RI1 of the delay loop series 192 to be input to the amplification circuit 106 via the NAND 199.

In addition, when the counter of adder 195 indicates the maximum value, that is, all 4-bit outputs 1905-1, 1905-1B, 1905-2, 1905-2B, 1905-3, 1905-3B, 1905-4, and 1905- When 4B is H output, adder 195 outputs the maximum period exceeding signal 1912. Therefore, in this embodiment, the delay loop sequence 101, the delay loop sequence 102, the control loop 103, and the load adjustment element 104 of the fifth embodiment are used instead. If there is a pulse whose period exceeds the maximum controllable period of this embodiment, When entering, the clock pulse is input to the amplification circuit 106 that has not yet passed.

Details of the configuration of the adder 195, the transmitter 196, the subtractor 197, and the delay loop 198 will be described below with reference to FIG. The adder 195 is composed of 4 sets of reversible D flip-flop circuits DF / F1 ~ 4. The NOR output of the signal derived from the reverse circuit FIz of the delay circuit series 191 via a reverse circuit signal and the signal of the delay circuit 198 is input to the C terminal of DF / F1. The output of the Q terminal of DF / F1 is 1905 input to the D terminal of DF / F1, the C terminal of DF / F2, the reverse switch IA1, 4-bit NAND ADNAND and the NAND12 of the transmitter 196. The output 1905-1B of the reverse brake IA1 is input to the NAND 11 of the transmitter 196. Q terminal output of DF / F2 1905-2 input D terminal of DF / F2, C terminal of DF / F3, reverse switch IA2, 4-input NAND ADNAND, and NAND 22 of transmitter 196. The output 1905-2B of the inverter IA2 is input to the NAND21 of the transmitter 196. The output of the Q terminal of DF / F3 1905-3 is input to the D terminal of DF / F3, the C terminal of DF / F4, and the output of reverse switch IA3 1905-3B is input to NAND 31 of the transmitter 196. Output of the Q terminal of DF / F4 1905-4 Input of the D terminal of DF / F4, and the reverse brake IA4,4-input NAND ADNAND, and NAND42 of the transmitter 196. The output 1905-4B of the reverse brake IA4 is input to the NAND 41 of the transmitter 196. The output of the receiving circuit 105 is another input terminal such as NAND 11, NAND 12, NAND 21, NAND 22, NAND 31, NAND 32, NAND 4, and NAND 42.

The reducer 197 is composed of 4 sets of reversible D forward and reverse DF / F 5-8. The NOR output of the output of the receiving loop 105 and the output of the NAND RNIN of the delay loop serial 192 is the C terminal of the input DF / F5. The output 1906-1B of NAND 11 is input to the R terminal of DF / F5, and the output 1906-1 of NAND 12 is input to the S terminal of DF / F5. The output of Q terminal of DF / F5 is input D terminal of DF / F5, C terminal of DF / F6 and 4-input NAND REDNAND. The output 1906-2B of NAND 21 is input to the R terminal of DF / F6 and the output 1906-2 of NAND 22 is input to the S terminal of DF / F6. The output of Q terminal of DF / F6 is input D terminal of DF / F6, C terminal of DF / F7, and 4-input NAND REDNAND. The output 1906-3B of NAND 31 is input to the R terminal of DF / F7 and the output 1906-3 of NAND 32 is input to the S terminal of DF / F7. The output of Q terminal of DF / F7 is input D terminal of DF / F7, C terminal of DF / F8, and 4-input NAND REDNAND. NAND 41 output 1906-4B input DF / F8 R terminal and NAND The output 1906-4 of 42 is input to the S terminal of DF / F8. The output of Q terminal of DF / F8 is input D terminal of DF / F8, and 4-input NAND REDNAND. The output of REDNAND is input to NAND 199 as the output 1910 of the subtractor 197, and is input to the NAND RNIN after being inverted.

In this embodiment, as explained above, the loop connection configuration of the delay loop series 191 and the delay loop series 192 and the setting of the counter can control the maximum delay time of the delay loop series 191 and the delay loop series 192. A clock pulse with a multiple of the period. This clock pulse can be counted by a counter. In other words, if the delay time from any NAND FNn of the delay loop series 191 to the subsequent reverse-reverse switch FIn is defined as dF, and the delay time from any NAND RNn of the delay loop series 192 to the reverse-reverse switch RIn is defined Is dR, the delay time from the delay loop serial 191st first NAND FN1 to the last reverse FIz is ZdF, from the delay loop serial 192th NAND The delay time from RNZ to the last reverse brake RI1 is ZdR. When it is necessary to eliminate the delays df and dR between the internal clock pulse and the external clock pulse, they are set to be equal, so ZdF and ZdR are also equal. At this time, if it is the situation shown in the first to seventh embodiments, that is, when the input clock pulse is shorter than ZdF + d1 + d2 (d1 + d2 is the sum of the delay time of the delay circuit 107 and the delay circuit 108), the delay is passed The clock pulses of the loop series 191 are transmitted from the delay loop series 191 to the delay loop series 192 and pass through the delay loop series 191 and the same number of NANDs in the delay loop series 192 and the reversed switching sections. If the input clock cycle is greater than ZdF + d1 + d2, the clock pulse will continue to circulate in the delay loop series 191 until the next clock pulse is input. The adder 195 counts this clock pulse through the end of the delay loop series 191 to the end. Times. When the next clock pulse enters, the clock pulse is immediately transferred from the delay loop series 191 to the delay loop series 192, and at the same time, the number of pulses counted by the adder 195 to surround the delay loop series 191 is transferred to the subtractor 197. The number of times is decremented each time the pulse passes through the reverse loop RI1 of the delay loop series 192. Because the number of times that the clock pulse surrounds the end of the delay loop series 192 is the same as the number of times that it surrounds the end of the delay loop series 191, the delay loop series 191 and the delay loop series 192. However, when the period of the input clock pulse is shorter than ZdF + d1 + d2, because the pulses pass through the same number of NANDs and reverse sections in the delay loop series 191 and the delay loop series 192, the longer the Periodic clock pulses can also achieve the same effect.

In addition, when the counter of the adder 195 indicates the maximum value, the maximum period exceeds the signal 1912 and is output from the adder 195. As a result, the delay circuit sequence 191, the delay circuit sequence 192, the control circuit 193, the load adjustment element 194, the adder 195, the transmitter 196, the subtractor 197, and the delay circuit 198 of the present embodiment are changed to the sixth embodiment. The delay loop sequence 101, the delay loop sequence 102, the control loop 103, and the load adjustment element 104. When the clock pulse input having a period exceeding the maximum controllable period of this example is input, the clock pulse is input to the amplification loop 106 that has not passed. .

At the same time, by using the delay circuit sequence 191, delay circuit sequence 192, control circuit 193, load adjustment element 194, adder 195, transmitter 196, subtractor 197, and delay circuit 198 of this embodiment, the third, The fourth and fifth embodiments of the delay circuit series 101, the delay circuit series 102, the control circuit 103, and the load adjustment element 104 can be implemented in a wide frequency range with the third, fourth, and fifth embodiments. The same effect.

In addition, by setting the delay time of the delay loop series 192 to a half of the delay time of the delay loop series 191, the same effect as that of the seventh embodiment can be obtained in a wide frequency range.

<u style="single">13th embodiment</u>

A thirteenth embodiment of the present invention will be described below with reference to Figs. Referring to FIG. 26, this embodiment replaces the delay adjustment circuit 115 of FIG. 9 with the delay adjustment circuit 201. As shown in FIG. 27, the configuration of the delay circuit 107 is particularly equal to the configuration of FIG. 10. This configuration includes eight sets of capacitive elements 1103 and transistors 1102. These components are connected to the node of the reverse gate series 1101. The transistor 1102 is inserted between the capacitor element 1103 and the node of the reverse gate series 1101. Among these transistors, one transistor 1103 is often in a conductive state, and the remaining transistors are controlled by the signal 1104. Two Controlled by signal 1105, four are controlled by signal 1106; the capacitor value connected to transistor 1102 has a level of powers of 2 and 3, that is, 8th order, and delay circuit 107 has a delay time of 8th order. However, the signals 1104, 1105, and 1106 are individually controlled by the registers 2001, 2002, and 2003 in the delay adjustment circuit 201. The output levels of register 2001, register 2002 and register 2003 are determined by external signals 2004, 2005, and 2006, and setting signal 2007 and setting release signal 2008.

In this embodiment, the delay time of the delay loop 107 can be adjusted by the external signal 2004 ~ 2006. As a result, the clock pulse timing can be set even after the delay loop device is manufactured and installed in the system. In particular, as shown in FIG. 28, a semiconductor device to which the delay loop device 202 of the present invention is applied, for example, many modules 204 can be used, and these modules 204 can use many synchronous dynamic random access memories 203; A control integrated circuit device 205 of 204. When the synchronous loop random access memory 203 data input control integrated circuit device 205 is set to the output of the delay loop device 202 in the same synchronous dynamic random access memory 203, the output 2012 can be used in the system 206. This system 206 is a signal group 2103 composed of external addresses 2004 to 2006 to receive the received signals so that the delay time difference caused by the configuration position of each group 204 can be adjusted after the system is installed. The synchronous dynamic random access memory 203 outputs data 2011.

Although the preferred embodiments of the present invention have been described with special terms, these descriptions are for description only, and it should be understood that various changes and modifications can be made without departing from the spirit and scope of the scope of patent application.