Microcontroller with analog front-end for providing intelligent battery management

Microcontroller with analog front end that provides smart battery management

The present invention relates to microcontrollers, and in particular to microcontrollers that have an analog front end for providing smart battery management.

The microcontroller consists of a microprocessor core and timer circuit, ROM and RAM memory, all of which are deeply hidden in a single semiconductor integrated circuit (IC). Microcontrollers are used in today's days with a wide variety of applications, and new applications are discovered almost every day. When holding a device, such as a tiny pocket pager, the microcontroller converts them in response to receiving letters, generates a beep to notify the user that there is an incoming message, and generates a number of messages suitable for display, such as , A liquid crystal display (LCD). The microcontroller is also used for keyboard control of personal computers, in which the microcontroller functions to offload many tasks that are officially processed by this processor. In addition, the microcontroller is also used in the modem (MODEM) for command description and data transmission, used in the printer temporary storage area, and used for printer operation at a considerably lower speed or for color Plotters are used for high-speed dumping of data when they are used to drive printers. They are used in color photocopiers, electronic typewriters, cable television terminal equipment, lawn spray control, credit card telephone equipment, and automobile applications such as engine control modules. Anti-lock brake system, car suspension control is used for the purpose of ride softness or rigidity according to the user's preference, and many other applications used daily by industrial and consumer customers.

The microcontroller can also be used to monitor and control a battery. The importance of such use has increased because many electronic tools are portable and need to use a battery as its power source. However, in order to fully monitor and control a battery, it is necessary to sense many battery parameters, such as battery voltage, current and temperature.

With reference to US Patent No. (USPN) 5,315,228 in Hess, a battery charging indicator and fuel gauge are disclosed. The device disclosed by Hess contains a microcontroller (34) in a package (B), which also contains a battery (20). It is called all the combination of monitoring the voltage, current, charging and discharging of a rechargeable battery, and calculating the charging capacity and charge level of the battery. The charging rate of the battery is controlled by hardware circuits 54 and 56 (shown in Hess in Figure 3A) and is fixed at about 5 milliamperes (mA) through the circuit 54 trickle charge (trickle charge), or fixed through the circuit 56 Fast charging at approximately 100 mA. In addition, the battery voltage and current are measured via a 4-channel analog-to-digital converter (41), which converts an analog signal into a proportional 8-bit binary number.

USPN5,345,392 discloses a battery charging display for personal computers in Mito. This display is connected to a received signal representing the battery temperature, voltage and current used to determine the state of the battery.

Both of the above-mentioned patents, however, contain circuits and techniques that are generally different from those of the present invention to monitor the voltage, current and temperature of a battery, the details of which will be described here.

Therefore, one object of the present invention is to provide a microcontroller on-chip, analogous to the front-end electrical circuit for measuring various parameters combined with the battery, such as battery voltage, current and temperature, thus providing a smart battery manage.

Reveal the use of a microcontroller for battery charging and monitoring. This microcontroller contains a microcontroller core (ie a processor) and a variety of front-end analog electrical circuits, including a ramp analog-to-digital (A/D) converter and a multiplexer to allow most analog inputs The signal is converted into a digital count indicating the signal level used to obtain the accurate voltage calculation of the selected analog input. This slope A/D converter contains an accurate comparator and a digital-to-analog converter (DAC) for charging A capacitor, a counter and a capture register. A first input of the comparator is one that is coupled to receive a selected majority of analog input signals, which is needed to obtain a measurement accordingly. A second input of the comparator is coupled to receive the voltage appearing across the capacitor, which is charged by the programmable current supplied from the DAC. In operation, a reset is performed first, whereby the voltage across the capacitor is discharged and the counter count is cleared. The capacitor then starts to charge and the counter allows counting from zero. When the voltage across the capacitor exceeds the selected analog input voltage, the comparator switches the logic state. This logic transition counts into the capture register via the counter obtained by the latch and causes a capture situation to occur. The count stored in the capture register represents the time that the capacitor is charged and exceeds the selected analog input voltage and corresponds to the selected analog input voltage measurement.

In order to make the selected analog input measurement more precise, the microcontroller uses a unique calibration procedure whereby the selected parameter/voltage subject to variation and change is measured during the test and its corresponding calibration constant is calculated from it. Then these constants are formatted and stored in the program memory and later used by the microprocessor to calculate a more precise value of analog input voltage.

The analog circuit of the microcontroller also contains two charge rate control channels for controlling the charge and/or discharge rate of an external battery. Each charge rate controller contains a digitally programmable digital-to-analog converter (DAC) used by the same comparator. This DAC provides a programmable voltage to the first input of the comparator, and the second input of the comparator receives a voltage indicating the battery current. The function of the charge rate controller is to make the voltage indicating the sensed battery current roughly equal to the programmable output voltage of the DAC, so it provides a control signal to an external power transistor that controls the charge/discharge rate of the battery.

Each charge controller can also be used as a level detector to determine when an input signal exceeds or falls below a digitally programmable threshold level. This programmable threshold level is digitally set by programming the threshold voltage required by the first input of the comparator through the DAC program. The other inputs of the comparator receive an analog input signal, such as a voltage indicating battery current. This level The function of the detector is to set a flag and provide an interrupt to the microprocessor when the analog input signal exceeds (or interactively falls below) the programmable threshold voltage. Therefore, this interrupt can be used to wake-up the microprocessor from a sleep mode (sleep mode) to provide a digitally programmable threshold for waking-up the microprocessor.

Interactively, through programming these two level detectors to detect the relative polarity, a single window detector can be provided to interrupt the microprocessor when the analog input signal exceeds the first threshold level or falls below the second threshold level It will happen when under. This will allow both the positive and negative currents of the battery to exceed a predetermined size to be detected. Therefore, when the currently unused battery is later placed in a device that draws/discharges current from the battery or in a battery charger that supplies charging current to the battery, such a window detector is useful for detecting battery applications. .

The microcontroller also contains an I²The C interface is used to support a two-way two-wire bus and a useful data transmission protocol for serial communication with other peripherals or microcontroller devices. This I²The C interface uses a comprehensive communication protocol to ensure reliable transmission and reception of data. When sending data, one device is the master and generates clock signals while other devices function as slaves. Each in I²The device of the C interface protocol has a specific address combined with it so that when a host wants to start data transfer, it first sends the address of the device it wants to connect to and if the address sent by the host matches the address of a slave device Address, the slave device is selected for data transfer. In order to complete the data transmission, the host device generates both start and stop conditions to determine the start and stop of the data transmission so that the data is transmitted between the start and stop conditions.

By using I²With C interface, the microcontroller can be programmed continuously at the end of the application circuit. Such a feature allows customers to manufacture unprogrammed circuit boards and then program the microcontroller before the product is shipped. This allows the final firmware or client firmware to be programmable.

The microcontroller 10 can be placed in a programming mode, by keeping the device's serial timing and serial data pins low, and raising the voltage programming pin to a necessary programming voltage. Once in the program mode, the user program memory and test program memory can be accessed and continuously programmed during terminal use.

The present invention will be better understood with a detailed description and accompanying drawings, in which Fig. 1 is a detailed block diagram illustrating an overview of a microcontroller system embodying the present invention; Fig. 2 is a diagram illustrating a microcontroller system Figure 3 is a detailed outline/block diagram of the slope analog-to-digital converter shown in Figure 1; Figure 4 is a diagram illustrating the location and location of calibration constants stored in the EPROM memory of Figure 1 Data format; Figure 5 is a diagram illustrating the sampling interleaving sequence of analog input for A/D conversion; Figure 6 is a flowchart illustrating the A/D data flow; Figure 7 is a detailed summary/block of the zero circuit of Figure 1 Figure; Figure 8 is a detailed block diagram illustrating the microcontroller's first charge controller/level detector; Figure 9 is a diagram illustrating the higher 5 bits of the log DAC register of the DACs in Figure 1 Course-tuned current output; Fig. 10 is a graph illustrating the lower 3-bit fine-tuned current output of the log DAC register of the DACs in Fig. 1; Fig. 11 is a The diagram illustrates the bits of the charge/level detection control (CHGCON) register; and Figure 12 is a detailed block diagram illustrating the second charge controller/level detector.

Figure 13 is a diagram illustrating an example according to I²The start and stop status of the C communication protocol; Figures 14 and 15 illustrate the use of addressing respectively I²The 7-bit and 10-bit formats of the C device; Figure 16 is a diagram illustrating the generation of an acknowledgement from a slave device; Figure 17 is a diagram illustrating an I using a 7-bit address format²Example of data transfer in C; Figure 18 is a detailed block diagram illustrating I in Figure 2²C interface; Figure 19 is a diagram illustrating an example and I used for data reception²C interface combined with the usual waveform; Figure 20 is a diagram illustrating an example of the I used for data transmission²Common waveforms of C interface combination; Figure 21 is a block diagram illustrating a common in-circuit serial programming connection of the microcontroller in Figure 1; Figure 22 is a diagram illustrating an example of serial programming Different commands are available for program operation; Figures 23 and 24 are diagrams illustrating the load data and read data commands respectively used for serial program operation; and Figure 25 is a block diagram illustrating the structure used for monitoring. Figure 1 microcontroller with external battery.

[System Overview]

Referring to Fig. 1, a detailed block diagram is shown to illustrate the microcontroller integrated circuit 10 embodying the present invention. The microcontroller 10 can take the form of an MTA 140xx/Callisto programmable control integrated circuit, which is made by Microchip Technology Corporation for applications such as battery charging and battery monitoring. The microcontroller 10 is designed for high-volume applications in portable computing, mobile phones, camcorders and other low-cost products that require battery charging and monitoring and control. However, it should be understood that the microcontroller 10 and the present invention are not limited to such applications and can be used in other applications (such as those that need to accurately estimate the input analog voltage), which will be apparent from the following.

The microcontroller 10 includes a microcontroller core 12, which can take the form of a PICI6C6X/7X microcontroller core, which is also made by Microchip Technology Corporation. The microcontroller core 12 is an 8-bit reduced instruction set (RISC) computer central processing system, which includes an 8-level deep stack and a number of internal and external interrupt sources. This microcontroller core has a Harvard architecture with separate command and data buses to allow a 14-bit wide command word and separate 8-bit wide data. Moreover, a two-stage instruction pipeline allows all instructions (a total of 35) to be executed in a single cycle, except for program branches that require two cycles.

Referring to Figure 2, a diagram is shown illustrating the timing cycle of the microprocessor core 12. Timing input, from pin OSC1 or internal oscillator 42, is internally divided into four phases (Q1, Q2, Q3 and Q4) to generate a complete processor timing cycle. Two timing loops are needed to complete any instruction so that one instruction is fetched during one timing loop and executed during the next timing loop. However, due to the two-stage pipeline, the execution of one instruction cycle is accompanied by the acquisition of the next instruction at the same time, which effectively reduces the timing cycle of each instruction to one timing cycle. If, however, an instruction causes the program counter to change, such as a GOTO instruction, two cycles are required to complete the instruction. Briefly, a fetch starts when the program counter is incremented during the Q1 part of the timing loop. The fetching instruction is to enter the instruction register, which is decoded and executed during the Q2-Q4 part of the timing loop.

The microcontroller core 12 includes a watchdog timer 14, which is implemented as a free running on-chip RC oscillator and does not require any external components. The watchdog timer usually has a nominal time-out period of 18 milliseconds. However, if a longer time-out period is required, a prescaler with a division ratio of 1:128 can be assigned to the watchdog timer under software control. Therefore, the time-out period can be implemented up to 2.3 seconds.

The microprocessor core 12 also contains a real-time clock/counter 16 and an arithmetic logic unit (ALU) 18 for performing calculations. It also contains an erasable programmable read-only memory (EPROM) 20, which contains a 64-word calibration memory space for storing various calibration constants that will be described in more detail. At the same time, the microprocessor core 12 also includes a random access memory (RAM) 22 for temporary storage, an input/output control 24 for providing general-purpose I/O, and an interrupt controller 26 for receiving and responding to interrupts.

Some analog computer peripherals form the analog front end of the microcontroller core 12. Such analog computer peripherals provide signal conditioning and analog to digital functions, which are useful for many applications such as battery charging and monitoring control. All analog functions are directly controlled by the microcontroller core to maximize flexibility and allow customization via firmware.

The front-end analog computer peripheral includes a slope A/D converter 30 and a multiplexer 32 to allow most external analog inputs to be converted into a digital count indicating its signal level. The slope A/D converter 30 is a medium-speed, high-precision converter, ideal for monitoring DC and low-frequency AC signals.

Also included in the analog front-end electrical circuit is the bandgap reference 34, which eliminates the need for an external reference voltage source. The bandgap reference block 34 also provides a voltage to the voltage distributor block 38, which generates a precise slope reference voltage for use by the slope A/D converter 30. The high slope reference is usually 1.23 volts and is used for the slope detection of A/D conversion to a higher limit. The low-slope reference voltage is usually 1/9 or about 0.14 volts of the high-slope reference voltage. Furthermore, the bandgap reference block 34 supplies a voltage to the low voltage detector 38 for detecting the occurrence of a low voltage condition.

The oscillator selection block 40 selects between an external vibration signal or an internal 4 MHz vibration signal provided by the internal oscillator 42. The selected vibration signal provides a clock signal to the slope A/D converter 30 and an external clock signal (CLKOUT).

The microcontroller 10 also includes an on-chip voltage regulator control 44 for providing an externally regulated voltage VREG, thus eliminating the need for an external voltage regulator. Voltage regulator control 44 for 3 or 5 volt operation is also optional.

Double-decimal, 8-bit digital-to-analog converters (DACs) 48 are combined with two comparators 50 and 51 to form two charge control channels. The dual DACs and comparators can be interactively configured to function as horizontal detectors, single window detectors or two separate horizontal detectors. Furthermore, these level detectors can be used to generate interrupts to the microcontroller core to provide wake-up or limit detection functions.

An on-chip temperature sensor 54 is also included for applications that require internal temperature monitoring.

The filter and zero circuit 56 is used to increase the accuracy of the low value measurement via an analog input that simulates a zero current condition. This "zero" technology can be used to enhance the accuracy of measuring low battery currents.

Also included is I²The C interface controller 58 is used to allow the microcontroller 10 to communicate with other I via its serial data pin (SDAA) and serial timing pin (SCLA).²C compatible device. Such an interface can also be used in programming microcontrollers when used in a terminal.

[Slope A/D converter]

Referring to Figure 3, a more detailed outline/block diagram of the slope A/D converter 30 is shown. The slope A/D converter 30 is the center of the analog front-end electrical circuit and is one of the most analog inputs used for conversion selection. It appears at the input of mux 32 and is a digital count value used to obtain the voltage measurement of the selected input. For example, the A/D converter 30 may be used to convert battery voltage, and current and temperature are digital count values for both battery monitoring and charging control. Most of the analog inputs selected for analog-to-digital conversion via mux 32 can include an analog input representing a battery voltage (BATV), a battery current (BATI), a battery temperature (BATT), and an external analog voltage (RA3/ AN3), the bandgap reference voltage via the bandgap reference block 34, the high and low slope reference voltages (SREFHI, SREFLO) via the voltage distributor block 38, an internal temperature voltage via the temperature sensor 54, and the dual DAC block 48 two DAC outputs (charging DAC A and charging DAC B).

The RC low-pass filter 103 is combined between the output of the analog mux 32 and the non-inverting terminal of the comparator 101. The usual time constant of an RC filter 103 is 5 microseconds.

The center of the slope A/D converter 30 is that the precision comparator 101 has a non-inverting input coupled to receive one of the selected majority analog inputs, and an inverting input is coupled to the external pin 105 (RAMP pin). The external capacitor 104 is coupled to the pin 105 to generate a ramp voltage across it.

The 4-bit programmable ramp control DAC 102 includes a majority of switchable current sources for selectively controlling the charging current to the external capacitor 104, ranging from 0 to 37.5 microamperes (uA) via 4-bit digital The control signal ADDAC is in steps of 2.5uA. The external capacitor can have a value, such as 0.1uF, and should have a low voltage coefficient for the best results.

The output of the comparator 101 is supplied to the input of a counter/capture timer 106, and its output is supplied to the input of the capture register 108.

The transistor 109 is coupled to the DAC 102 to disable all current sources if the signal ADRST is logic "1".

In operation, one of the most analog inputs is independently selected via mux 32, and each analog channel is converted into a digital count. By first resetting the counter 106 and the register 108 and simultaneously discharging the external capacitor 104 to ground for a predetermined minimum time, such as 200 microseconds, a conversion occurs. The reset is then released and the counter 106 starts counting at the same time that the capacitor 104 starts charging based on the charging current supplied via the DAC 102. It should be noted that because the low and high references (SREFLO, SREFHI) of the converter 30 are sampled and a calibration constant is calculated and stored in the meantime, as will be described below, the microcontroller 10 can correctly estimate the zero offset of the converter 30 . As a result, the capacitor 104 need not be precise, and can actually be a low-cost capacitor and still achieve precise results. In addition, the amount of time required to discharge the capacitor 104 does not have to be correct, because the cancellation of the microcontroller 10 may result in an ambiguous reset, the ability of these effects of non-zero capacitor voltage. Similarly, it is not important that the counter starts counting at the same time as the capacitor 104 starts to charge. As long as the counter starts counting and the capacitor 104 starts to charge at about the same time, any offset will be compensated by the calibration constant.

When the voltage across the external capacitor 104 exceeds the selected analog input voltage, the comparator 101 switches from a logic high to a logic low. This transition starts an interruption to the microcontroller core 12, through which the latch counter 106 counts to the capture register 108. An interrupt control signal causes a capture to occur. The count stored in the register 108 represents the time that the capacitor 104 is charged and exceeds the selected analog input voltage and corresponds to the measurement of the selected analog input voltage. This count is then used to obtain a more precise voltage measurement using the analog input selected using the unique calibration procedure and filter algorithm that will be described. In a similar method, the digital count of each analog input can be obtained. By independently selecting each analog input via mux 32, each analog input of the majority of voltages can be measured digitally.

[Calibration procedure]

In order to make the selected analog input measurement more precise, the present invention utilizes a unique calibration procedure, which will be described as follows. Generally speaking, during the test, the smallest group of parameters will need to be adjusted or "trimmed" ("trimmed") so that the calibration constants will be calculated and stored in the EPROM user space. The smallest groups of parameters that need to be trimmed include the ratio of the lower slope reference voltage of the slope A/D converter to the higher slope reference voltage, the band gap voltage, the internal temperature sensor (thermistor) voltage, and the selected oscillation Device frequency. Therefore, the present invention measures these parameters and calculates the calibration constants during the test, as mentioned below, all of which will be stored in the EPROM 20 user space for subsequent recovery and use, whereby many of these constants will be used to increase the accuracy of the A/D measurement more acurrate.

A. A/D slope reference calibration constant (Kref)

The ramp A/D converter 30 on the wafer requires a known ratio between two voltage points in order to determine the coefficient of the linear transfer function. The slope reference generator 36 (FIG. 1) generates a higher slope voltage and a lower slope voltage through a band gap voltage supplied from the band gap reference circuit 34. The ratio of the lower slope reference voltage to the higher slope reference voltage is calculated from their respective voltage measurements.

In particular, the procedure used to calculate the A/D slope reference calibration constant is as follows. The analog mux 32 is set to select a higher slope reference voltage (SREFHI), which is a voltage supplied by the slope reference generator 36. Use accurate voltage to measure electrical circuits, measure the higher slope reference voltage and record its value. This accurate voltage measurement electrical circuit is coupled to the output of mux 32 and can be located in a separate test load interface. Now, switch the analog mux 32 to select the lower slope reference voltage (SREFLO), which is the other output of the slope reference generator 36. Using this accurate voltage measurement electrical circuit, measure the lower slope reference voltage at the output of mux 32 and record its value. Now calculate the calibration constant Kref, which is equal to the ratio of SREFLO/(SREFHI-SREFLO).

B. Bandgap reference voltage calibration constant (Kbg)

The bandgap voltage provided by the bandgap reference circuit 34 should be approximately 1.23 volts. However, this voltage is usually slightly dependent on the supplied voltage (less than 1 mV) and temperature (usually less than 10 mV). Therefore, the voltage actually supplied by the bandgap reference circuit 34 should be measured and its value stored in EPROM 20.

In order to obtain the actual measurement of the voltage supplied by the bandgap reference circuit 34, the following procedure is used. First, set the analog mux 32 to select the output voltage of the bandgap reference circuit 34. Use accurate voltage measurement electrical circuits to accurately measure the bandgap voltage appearing at the output of mux 32. The measured voltage is the bandgap reference voltage calibration constant Kbg.

C. Thermistor calibration constant (Kthrm)

Although the temperature coefficient of the internal temperature sensor/thermistor 34 is quite constant with respect to temperature, the absolute magnitude of the output voltage can vary significantly with the process. Therefore, the absolute magnitude of the output voltage of the thermistor 54 should be measured at a predetermined temperature, whereby the measured value will be stored in the calibration EPROM.

The procedure for measuring the thermistor voltage is the same as the above procedure for measuring the bandgap voltage, with the exception that mux is programmed to select the output of the thermistor 54.

D. Temperature coefficient calibration constant (Ktc)

The temperature coefficient of the thermistor is assumed to be quite constant with respect to temperature. However, the temperature coefficient may depend slightly on the process. This dependence may be extrapolated by first measuring the thermistor voltage (at the output of mux 32) and then by adjusting the temperature coefficient calibration constant (Ktc) based on the measured voltage value.

The temperature coefficient calibration constant is usually obtained from the characteristic data of the thermistor's output voltage at various temperatures. One of the correlations exists between the thermistor's output voltage and its slope. Therefore, based on the output voltage at a given temperature, the temperature coefficient of the thermistor can be improved to compensate for accuracy.

Although it is not important to increase the accuracy of the A/D conversion, these next two constants are important for making accurate time-base measurements/events.

E. Internal oscillator calibration constant (Kin)

The calibration of internal timing frequency to program variation requires high accuracy. The calibration factor Fosc is calculated from the measurement of the internal timing frequency, which can be measured on the external OSC2/CLKOUT pin. In particular, the calibration factor is calculated as an integer function of [(measurement frequency -3.00 Mhz)/10 Khz]. Note that it is assumed that the measurement frequency will be greater than 3.0 MHz.

F. Watchdog timer calibration constant (Kwdt)

The watchdog timer frequency also needs to be highly accurate for the calibration of process variations. The calibration factor Kwdt is calculated from the measured frequency of the operation of the watchdog timer 14 of FIG. 1. Although the frequency of the watchdog timer is not provided by an external pin, the frequency of the watchdog timer can be measured by monitoring the logic state of a predetermined bit in a status register. The logic status bit indicates the logic level of the watchdog timer signal , The calibration factor Kwdt is equal to the integer function of [measurement frequency/1 Khz].

After obtaining each of the above-mentioned calibration constants/factors, the address location and data format of each formatted and programmed into EPROM memory 20 are as shown in Figure 4.

[A/D conversion using stored calibration constants]

The conversion of the A/D count value obtained by the A/D converter 30 into a corresponding input voltage value is implemented by the microprocessor core 12 according to the formula shown in EQN.1.

<maths><img file="TW286367B_D0001.tif" /></maths>Among them: Coffset=Creflo-Kref(Crefhi-Creflo); Vin=selected input absolute voltage value result (digital); Cin=selected input A/D count value; Creflo=A/D lower reference point A/ D count value; Crefhi=A/D count value of the higher reference point of A/D; and Cbg= A/D count value of band gap reference.

The offset term (Coffset) compensates for the startup delay or voltage offset that may occur at the beginning of the ramp voltage of the ramp A/D converter. For example, if the slash counter starts before the slash voltage starts to increase, or if the slash voltage does not start at 0 volts, there will be an offset count for each conversion. Therefore, the offset term is the count of power-on delay or offset voltage.

When performing A/D conversion on multiple analog inputs, the present invention alternately selects the analog inputs used for A/D conversion to maximize the sampling rate of high-priority signals (such as battery current), as opposed to those that change at a relatively slow speed. Low priority signals (such as temperature input) reduce the sampling rate. Referring to Figure 5, the interleaving priority scheme for sampling a variety of analog input signals is shown. Battery current is the highest priority and is sampled 8 times every 16 A/D cycles. The battery voltage is the next highest priority and is sampled twice every 16 A/D cycles. The battery temperature and internal temperature input via the external thermistor are sampled once every 16 A/D cycles. Similarly, the zero voltage of the current network, the bandgap voltage, and the lower and higher A/D reference voltages are sampled once every 16 A/D cycles.

In order to stabilize the reference value and further enhance the A/D accuracy, the raw count data of a certain analog input obtained from the A/D converter is filtered before calculating the actual voltage value of the A/D analog input. Referring to Fig. 6, a flow chart is shown to illustrate the A/D data flow including filtering algorithm 112-114 and averaging algorithm 115-116 for calculating the actual voltage value from the A/D count value. The count value of the energy band gap voltage (Cbg) is filtered by calculating the rolling average of the 16 count values recently obtained. The calculation of the filter value of the bandgap count is shown in EQN.2.

<maths><img file="TW286367B_D0002.tif" /></maths>The subscript i represents the number of staggered sequences.

The filtered value of this bandgap count is then supplied to the microprocessor core 12 and used to calculate these output voltages of block 118 as will be described later.

The count offset value (Coffset) is filtered by calculating the rolling average of the 16 most recently obtained count values, as shown in EQN.3.

<maths><img file="TW286367B_D0003.tif" /></maths>Where Coffset_i=Creflo_i-Kref(Crefhi_i-Creflo_i)

The filter value of this offset count (CfOffset) is also supplied to the microprocessor core 12 and used to calculate the A/D input voltage.

The current input zero offset count (CIzero) is filtered by calculating the rolling average of the latest 16 count values, as shown in EQN.4.

<maths><img file="TW286367B_D0004.tif" /></maths>

The filtered value of the current input zero offset count (CfIzero) is also used by the microprocessor core 12 to calculate the input voltage.

The invention also filters/averages the raw count data obtained from the battery voltage and battery current channels. The battery current count value (CIbat) is filtered by averaging 8 samples of the input channel in the interleaved sequence as shown in EQN.5.

<maths><img file="TW286367B_D0005.tif" /></maths>

This filter value of the battery current count value (CfIbat) reduces the amount of data sent to the digital integrator that tracks the battery capacity.

Similarly, the count value of the battery voltage (CbatV) is filtered by averaging 2 samples of the input channel in the interleaved sequence as shown in EQN.6.

<maths><img file="TW286367B_D0006.tif" /></maths>

The following filtered count values, together with the calibration constants stored in EPROM 20, can be used to calculate the more precise digital values of the input voltage corresponding to the battery current and battery voltage, as shown in EQNs. 7 and 8, respectively.

<maths><img file="TW286367B_D0007.tif" /></maths>

It should be noted that one item of EQN.7 (CfIzero) is a count corresponding to an input zero current condition and is used to increase the measurement accuracy of low current values, which will be explained in detail below.

In addition, the more precise digital values of the internal and external temperature and voltage are calculated as shown in EQNs. 9 and 10.

<maths><img file="TW286367B_D0008.tif" /></maths>

Therefore, the present invention includes the measurement of various calibration constants and storage in memory and various filtering algorithms for obtaining selected analog inputs (such as those representing voltage, current, and an external battery temperature) for very precise measurements.

[Zero Circuit]

When trying to measure low-level analog signals, it is indeed important to know where the zero reference point is in order to obtain accurate results. Therefore, the present invention includes a zero technique to increase the accuracy of measuring low current values. Referring to FIG. 7, a detailed outline/block diagram of the zero circuit 138 of block 56 (FIG. 1) is shown. This zero circuit contains two matched pass gates 140 and 142 for simulating a zero current condition. If the switches 140 and 142, which may be in the form of field-effect transistors, are imprecisely matched, this mismatch, if any, can be measured and stored in EPROM 20 as an additional calibration constant for improving A/ D accuracy. The switch 142 reacts to the signal ADZERO of the microcontroller core 12, and the switch 140 reacts to the inversion via the inverter 141. Also included in the zero circuit 138 are the input protection circuit 147 and the switchable current deviation source 149.

In operation, when the switch 140 is open and the switch 142 is closed, the voltage corresponding to a zero current condition is supplied to the mux 32 (with the comparator 50 or 51). Therefore, the zero current condition that occurs at pin 143 is simulated. The inclined plane A/D converter has the ability to obtain a digital count corresponding to zero current at pin 143. Therefore, when switch 140 is closed and switch 142 is open, the subsequent digital count corresponding to the subsequent analog current measurement at pin 143 is calculated in relation to this zero count. When such high accuracy is required, this zero technique provides high accuracy for low current values.

For capturing even smaller current ripples, an optional filter capacitor 152 can be coupled to the current average pin (IAVG) 154 and ground. The capacitor 152 and the internal resistor 156 form an RC network and function as a DC averaging filter so that the capacitor 152 can be adjusted to obtain a required time constant. The switch 158 is coupled between the zero circuit 138 and the IAVG pin 154 and is closed during the A/D sampling period and is automatically opened during the zero operation via the inversion of the signal ADZERO.

In the application of battery monitoring, the zero circuit 138 can be used to increase the measurement accuracy of the current supplied by the battery 146. The current is measured by connecting an external sense resistor (150) and the battery in series to the pin 143. In particular, the output of battery 146 is coupled to circuit node 148, which is coupled to pin 143 and returns to ground via inductive resistor 150. The sensing resistor 150 is usually a low-value resistor, for example, in the order of 0.05 ohm. Therefore, a low voltage is usually generated across the resistor 150. For example, for a +/-5 amp battery pack and a 0.05 ohm sense resistor, a voltage in the range -0.25 to +0.25 volts (the polarity is a function of whether the battery is charged or provides an output current) appears at the pin 143. Furthermore, in the case of low battery current, the voltage across resistor 150 is fine, for example, in the order of millivolts. Therefore, in order to obtain an accurate measurement of battery current with such a low current, it is important to know which A/D digital count corresponds to a zero current condition. For example, if a zero current condition corresponds to an A/D digital count of 100, such an offset must be considered when measuring the voltage corresponding to the battery current, especially for low currents that appear to be relatively low digital counts. As mentioned above, by simulating a zero current condition via switches 140 and 142, the zero circuit 138 provides such a zero current count.

[Charge Control/Current Flow Detector]

As discussed in the system overview, the microcontroller 10 contains double-decimal 8-bit DACs that can be combined with the comparators 50 and 51 (Figure 1) to form two charge rate control channels for controlling the charge rate of the external battery. Interactively, the dual DACs and comparators can be constructed to function as horizontal detectors, such as two separate horizontal detectors or a single window detector.

Referring to Figure 8, a detailed block diagram is shown to illustrate a dual DACs (201), which will be used with the same comparator (50) to include the first charging control channel (channel A). Briefly, DAC 201 supplies a programmable voltage at its output (the output of mux 28) and the non-inverting input of comparator 50. The other (inverting) input of the comparator 50 is coupled to receive a voltage indicating the current induced from an external battery from a zero circuit 56, for example. When operating in the charge control mode, the output of the comparator 50 is combined through the mutual exclusion or gate 212 and supplies a charge control signal. The external pin 214 and the external pin 214 will be coupled to an external power transistor for controlling the battery. recharging current.

When operating as a level detector, the circuit functions as a battery current display so that when the voltage (corresponding to the battery induced current) is lower than or interactively exceeds the output voltage of the DAC 201, the comparator 50 changes state and wakes up by setting. -up) Interrupt flag (WUIF) to cause an interrupt to the microcontroller core 12. Therefore, this interrupt can be used to wake the microprocessor from a sleep/idle mode.

Refer to DAC 201 in more detail, which includes two resistor ladders 203 and 204, current source 205 and analog multiplexers 207 and 208. The resistor ladder 203 is used for rough adjustment of the output voltage, and the resistor ladder 204 is used for the fine adjustment of the output of the first ladder. This rough resistor ladder 203 is matched to the current induced deviation resistor, so the center point of the ladder is approximately equal to the zero current flow. Therefore, this allows the DAC 201 to control or monitor both the charging and discharging current flow, that is, both the positive and negative current flow.

The resistor ladder 203 contains 32 contacts and is divided into 2 groups/regions (decades/regions). The first group is defined to control the trickle or the highest charging rate, and has a resolution of 5 millivolts and the range is +/-50 millivolts. This corresponds to a current resolution of 100 mA using an external 0.05 ohm sense resistor and the range is +/- 1 mA.

The second group is defined for fast charging applications and its resolution is 50 millivolts and the maximum range is +/-0.35 volts. This corresponds to a current resolution of 1 ampere using an external 0.05 ohm sense resistor and the range is +/- 7 amperes.

This trimming resistor ladder has 8 contacts and is used to separate the temporarily stored output voltage from the rough ladder. This output is the smallest DAC with a 0.05 ohm sense resistor, which is approximately 0.714 millivolts in voltage resolution or 14.3 milliamps in current resolution.

The voltage granularity and range of the DAC 201 depend on the value of the logic bits stored in the DAC A register (LDACA). The LDACA register is a data register used to control the output voltage of the DAC 201, where LDACA The higher five bits of the register (bits 3-7) control mux 207 to select a voltage output range via the rough ladder 203 according to the diagram shown in Figure 9. Figure 9 also shows a resistor with a 0.05 ohm resistor. The corresponding induced current range, in which the current range is displayed in the bottom half of the graph () indicates that the negative current corresponds to battery charging. Furthermore, the lower three bits (bits 0-2) of the LDACA register control mux 208 for selecting fine-tuning adjustments via the ladder 204 according to the chart shown in FIG. 10.

As an example, if a positive/discharge current of 340 mA is required, the LDACA register will be set to the binary value "00011010". The higher 5 bits ("00011") produce a rough range of 300-400 mA as shown in Figure 9, while the lower 3 bits ("010") select the fine adjustment setting to be 3/8 times the maximum number of the rough range As shown in Figure 10, or about 37.5 mA. Note that if a negative/charge current of 340 mA is required, the LDACA register will be set to the binary value "10011010".

The output of the analog mux 208, which is the analog voltage output from the DAC 201, is supplied as one of the most inputs of the A/D converter 30 and can be connected to an external filter capacitor via the external pin 210.

The output of the analog mux 208 is also coupled to the non-inverting input of the comparator 50. The inverting input of the latter is coupled to receive a current induced voltage, which corresponds to an external battery after passing through the zero circuit 56 ( BATI) an induced current.

The output of the comparator 50 is the first input that is coupled to the mutual exclusion or gate 212, the latter has a second input that is coupled to receive the charge control polarity bit, CPOLA, which is used to reverse when it is set to logic "1". The output of the phase comparator 50. Therefore, the mutual exclusion or gate 212 can be programmed to cause an interrupt via the CPOL bit in the CHGCON register, if the induced voltage exceeds or falls below the DAC voltage.

The output of the mutual exclusion or gate 212 provides a charging control signal (CCTRLA) to an external power transistor via pin 214 for controlling the charging current to the external battery. In particular, the charging control signal is provided to the base of the PNP power transistor 217 that provides the charging current to the external battery 218. The external inductor 220 and capacitor 222 are also provided to construct a charging circuit such as a usual switching buck regulator. The RC filter 215 is combined between the base of the PNP transistor 217 and the ground to filter the noise therebetween.

In an operation such as a circuit for supplying charging current to the battery 218, if the voltage representing the battery current (BATI) exceeds the digitally programmable voltage from the DAC 201, the control signal CCTRLA function is to reduce the PNP 217 transistor Average base current. This causes a corresponding decrease in the collector-emitter current of the transistor 217, that is, the charging current Ichg to the battery decreases. On the other hand, if the voltage BATI is below the digital programmable voltage from the DAC 201, the control signal CCTRLA functions to increase the average base current from the transistor 217. This causes a corresponding increase in the collector-emitter current of the transistor 217, that is, the charging current Ichg to the battery increases. Therefore, the charging control architecture of FIG. 8 provides feedback so that the voltage (corresponding to the induced current) is substantially equal to the output voltage of the DAC 201 for effectively controlling the amount of charge seen by the battery, which is based on the digital value of the DAC 201 Programmable voltage value of ground.

The combined DAC, comparator and current sensing circuit, as described above, can be used at the same time to cause a controlled battery discharge. One possible solution to complete such a discharge is, for example, to use an NPN power transistor driven by the CCTRLB output, and the logic "1" of the CCTRLB bit indicates the discharge mode. The ability of the present invention to provide both controlled charging and controlled discharging is significant because it is important to discharge the battery many times in order to have an accurate measurement, such as when the microcontroller is not synchronized with the battery and the battery capacity changes. It is unknown, and because of the previous partial discharge of the battery since the most recent complete discharge, it is also important to be able to discharge the battery to remove the memory effect, such as in the case of nickel-cadmium batteries.

In order to enable the charge control mode, a charge control function of a charge/level detection control (CHGCON) register causes the bit (CCAEN) to be set to logic "1", otherwise pins 210 and 214 will assume their normal input /The output port functions normally. The bits of these CHGCON registers are shown in detail in Figure 11. If the bit CCAEN is logic "1", the charge control circuit functions to make the current induced voltage appearing at the inverting input of the comparator 50 equal to the programmable DAC output voltage appearing at the non-inverting input of the comparator 50. Therefore, the external power transistor 217 effectively controls the amount of charging current seen by the battery. The status of the charging control of the comparator 50 (bit CCOMPA) and the charging control polarity bit A (CPOLA) can also be read through the CHGCON register. The CHGCON register also contains the corresponding comparator and polarity bit combined with channel B.

Referring to FIG. 12, a detailed block diagram is shown to illustrate the second charge control/level detector channel (channel B), which uses the second DAC represented by block 48 and comparator 51 as 201'. The charging control channel B is very similar to the charging control channel A in Fig. 8, in which the same components shown in Fig. 12 and those shown in Fig. 8 are identified by the main reference numbers. However, the input of the comparator 51 of channel B is inverted with respect to the comparator 50 of FIG. 8, whereby the inverting input of the comparator 51 is coupled to the output of the DAC 201', and the non-inverting input of the comparator 51 passes through the zero circuit Receive the voltage corresponding to the induced battery current. Note that the induced battery current in Figure 12 may be the same as the induced current in Figure 8, or when the microcontroller 10 is used to monitor and control two different batteries, it may be one Independent induction battery current. At the same time, the voltage supplied at the output of the DAC 201' is controlled by 8 bits of a B register of the DAC, which is similar to the way the LDACA register controls the current output by the DAC 201, and is based on the These charts.

As mentioned earlier, this dual charge controller/level detector can also be used to detect when an input signal exceeds or falls below a programmable threshold level. The level detector can be used even if the charging control is not implemented. In such a situation, the charge control enable bit of the CHGCON register will remain logic "0". Referring back to channel A in Figure 8, the programmable threshold level is digitally set via the LDACA register by programming the required voltage for the output program of the DAC 201. This means that a predetermined programmable threshold voltage is applied to the non-inverting input of the comparator 50 so that when the signal appearing at the inverting input of the comparator 50 exceeds the programmable threshold voltage, the comparator 50 switches the logic state . This logic change can then be used to set a flag and cause an interrupt to the microprocessor core 12 so the call for direct action will be taken. In addition, the status of the logic output of the comparator 50 can be monitored by reading the CHGCON register as described above.

[Wake-Up function with digitally programmable threshold]

The microcontroller 10 includes a sleep mode entered by the execution of a specific sleep command. In sleep mode, the oscillator on the chip is turned off but the watchdog timer continues to execute. In addition, the microcontroller 10 includes a hibernate mode, which is the same as the sleep mode except that the watchdog timer will be turned off. When these oscillators are disabled, these modes result in low power consumption and substantial power savings.

The microcontroller 10, when responding to some conditions such as an external reset input, the watchdog timer expires (such as being enabled), the I²C series start/end bit detection, or when an A/D conversion is completed, will escape from sleep mode or wake up. In addition, if the microcontroller 10 is used for battery monitoring and charging applications, the level detector can be used to detect when an induced battery current exceeds or falls below a programmable threshold level to wake up the microprocessor core 12 come over. Referring again to FIG. 8, when the induced voltage, which is a voltage representing the induced current of a battery, exceeds the programmable threshold voltage set by the DAC 201, the comparator 50 switches from logic high to logic low, so a wake-up is set Come over and interrupt the flag (WUIF) and cause an interrupt to the microcontroller core 12. Therefore, the microprocessor core can be immediately awakened from sleep mode and the increased current output from the battery can be fully monitored for accurate, accurate and timely battery level measurement.

In a similar method to the above, the level detector of channel B (Figure 12) can be used as an independent level detector to detect when another input signal exceeds or falls below a programmable threshold level. For example, when the voltage through the zero circuit exceeds the programmable threshold voltage set by the DAC 201', the comparator 51 switches from logic low to logic high, thus setting a wake-up interrupt flag (WUIF) to cause an interrupt to Microcontroller core 12.

Interactively, by programming these two DACs to detect the relative polarity, a window detector can be implemented, where the positive battery current exceeds the programmable threshold and the negative battery current falls below the programmable threshold. Either can cause an interrupt to the microprocessor core, whereby the logic bits CCOMPA and CCOMPB representing the outputs of the comparators 50 and 51 can be read to determine which of the two detectors caused the interrupt. In battery applications, when unused batteries are later placed in a device, such as a camcorder that draws/discharges current from the battery, or placed in a battery charger that supplies charging current to the battery, such a window detection The device is useful for current detection. In these two situations, it is absolutely necessary for the microprocessor core to wake up immediately to detect such a current for accurate and accurate measurement of battery power.

[Inter-Integrated Circuit Interface][Inter-Integrated Circuit(I²C)Interrace]

The microcontroller 10 supports a two-way two-wire bus and data transmission communication protocol. In particular, I²The C interface 58 is a serial interface, which is used to communicate with other peripheral or microcontroller devices, such as serial EEPROMs, shift registers, display drivers, A/D converters, and so on. And, I²The specifications of the circuit between the C interface 58 and the integrated circuit, the system management bus and the access bus are compatible.

I²The C bus is a two-wire serial interface developed by Philips/Signetics. The original specification or standard mode is designed for data transfer up to 100K bits per second (100Kbps), and its enhanced specification or fast mode supports data transfer up to 400Kbps, in which the standard and fast mode devices will interoperate if Attach to the same bus.

I²The C interface uses a comprehensive communication protocol to ensure the reliability of data transmission and reception. When transmitting data, one device is the master and generates the clock signal, while the other devices function as slaves. Each in I²The device of the C protocol interface has a specific address combined with it, so that when a host wants to start a data transfer, it first sends the address of the device that it wants to connect to, and if the address sent by the host matches the address of a slave device When the slave device is selected as the data transfer.

During the period when there is no data transfer, both the timing line (SCLA) and the data line (SDAA) are pulled to a high potential through an external pull-up resistor. To complete the data transmission, the host device generates both start and stop conditions to determine whether to start or stop the data transmission. Referring to Figure 14, when the timing line is high, the start condition is defined as a low-to-high transition on the data line, and when the timing line is high, the stop condition is defined as a low-to-high transition on the data line. Transition. Also, based on the definition of start and stop conditions, when data is being transmitted, the data line can only be changed when the timing line is low, as shown in Figure 14.

Two addressing formats exist for addressing I²C device. The first one is a 7-bit address format with a read/write bit as shown in Figure 15. Briefly, after the start bit (S), the host generates 8 bits, the first seven bits are the address of the slave device and the last bit is a read/write bit.

The second address format is a 10-bit address format with a read/write bit as shown in Figure 16. In short, after the start bit, the host must generate two bytes, and the first five bits of the first byte specify that the address is a 10-bit address. The next ten bits are the address of the slave device and the last bit is a read/write bit.

After transmitting each byte of the data, the slave/receiving device generates an acknowledgement bit. Refer to Figure 17, which is a diagram illustrating a notification generated by a slave device. In particular, the slave device informs that the last byte of the data received during the timing pulsation is used for notification by keeping its data output line low. For example, for a 7-bit address format, every ninth timing pulse corresponds to a notification timing pulse.

Referring to Figure 18, a figure illustrates an example of an I using a 7-bit address format²Example of C data transfer. Briefly, after the start bit (S), the host generates the 7-bit address of the slave device and a read/write bit. Assuming that the address is received, the slave device makes its data output low and informs the reception of the address. The host then generates a data byte that it receives as notified by the slave device. When the data transfer is completed, the host generates a stop bit (P).

Referring now to Figure 19, an I is shown²The detailed block diagram of C interface 58. I²The C interface 58 provides all the subordinate functions and provides hardware support to help the software implementation of the host function. I²The C interface provides both standard and fast mode specifications and 7-bit and 10-bit addressing.

Two wires/external pins are used for data transfer: RC6/SCLA pin, which is 1²C timing (clock), and RC7/SDAA pin, its function is like I²C data.

I²C interface 58 has 5 registers for I²Operation of C: (1) I²C control register (I²CCON), (2)I²C status register (I²CSTAT), these two are located in the file register space (file register space), (3) serial reception/transmission temporary storage area (I²CBUF) 301, (4) I2C shift register (I²CSR) 303, and (5) address register (I²CADD) 305. Also included in I²The C interface 58 is a comparator/coordination detector 307 and a start and stop bit detection electrical circuit 309.

I²CCON register control I²The operation of C allows one of the following I²C mode is selected: 1) 7-bit addressed I²C slave mode; 2) 10-bit addressed I²C slave mode; 3) 7-bit addressed I²C slave mode and host mode support; 4) 10-bit addressing I²C slave mode and host mode support; and 5) I2C master mode, the slave is idle.

I²The CSTAT register is only readable and gives the status of data transfer. This includes information such as start or stop bit detection, whether the received byte is data or address, whether the next byte is the completion of a 10-bit address, and whether this is a read or write Data transfer.

I²CBUF register is a register/temporary area for writing or reading transfer data. I²The CSR register moves data into or out of the microcontroller 10. I²The CADD register stores the subordinate address.

Referring to Figure 20, a figure illustrates the combination of I²The C interface 58 is used for data reception and has a usual waveform in a 7-bit address format. Once I²C interface 58 has been enabled (enabled), this interface is waiting for a start condition to occur. After the start condition, the 7-bit address and read/write bits are shifted into I²CSR register 303. All incoming bits are sampled on the rising edge of the serial timing line. I²The contents of the CSR register and I²The contents of the CADD register are compared at the falling edge of the eighth timing pulse. If the addresses match, I²The contents of the CSR register are loaded into I²CBUF register and I²The read/write bit of the CSTAT register is cleared (to indicate that data is being written into interface 58). At the same time a notification pulse is generated and an I after each data byte is transferred²C interrupt bit (I2CIF) is set, the interrupt bit must be cleared by software and I²The CSTAT register is used to determine the status of the byte. However, if I²The CBUF register has not been read from the previous reception, and an address byte overflow condition exists. In this case, there is no notification that the pulsation is generated and by setting one in I²The overflow bit of the CCON register represents an overflow condition.

Referring to Figure 21, a figure illustrates the combination of I²The C interface 58 is used for data transmission and has a usual waveform in a 7-bit address format. When an address match occurs and the read/write bit of the address byte is set (to indicate that data is being written to interface 58), I²The read/write bit of the CSTAT register is also set at the same time. The received address is loaded into I²CBUF register informs that the pulsation will be generated at the ninth timing pulsation. The data to be sent must be loaded I²CBUF register, which is also loaded into I²CSR register. The 8 bits of the data are shifted out at the lower edge of the serial timing line. Similar to data reception, each data byte transfer generates an I²C interrupt flag (I2CIF), where this I2CIF bit must be cleared by software and I²The CSTAT register is used to determine the status of the byte.

[Microcontroller in-circuit programming]

By using I²C interface 58, when used in the terminal application circuit, the microcontroller 10 can be programmed continuously. Such a feature allows customers to manufacture circuit boards with unprogrammed devices and then program the microcontroller before the product is shipped. This allows the final firmware or client firmware to be programmed.

By keeping the serial timing and serial data pins low, and raising the voltage programming pin to the voltage Vpp (for example, 12 volts for Vss), the microcontroller 10 can be placed in a program/verification mode. Once in the program mode, the user program memory and test program memory can be accessed in a serial or parallel manner. The initial mode of operation by program planning is serial and the memory accessed is the user program. Memory.

The present invention uses the two external pins (SCLA and SDAA pins) of the microcontroller 10 to complete serial programming in the circuit for providing timing and data to and from the microcontroller 10. In addition, when implementing program programming in the circuit, three other pins are used to provide power, ground and a program programming voltage to the microcontroller 10. Referring to FIG. 22, there is shown a general programming structure of a microcontroller 10 serially in the circuit. For demonstration purposes only, the microcontroller 10 of FIG. 21 resides in the end-circuit/battery (end-circuit/battery) 403 for controlling the charge monitoring of a battery (not shown in FIG. 22). Figure 22 illustrates the part of the microcontroller 10, which includes when the microcontroller 10 has been incorporated into the battery pack, a part of its external pins are used to couple to the external connector 401 of the battery pack 403. Program the microcontroller 10, and the external connector 401 receives external signals for supplying timing and serial data signals to the SCLA and SDAA pins of the microcontroller 10, respectively. The timing pins are used to apply a timing to the microcontroller, and the data pins are used to enter command bits and serially input and output data during serial operations. The connector 401 also receives and supplies a programming voltage, such as 12 volts, to the host clear (MCLR)/voltage programming pin of the microcontroller 10 to enable the microcontroller 10 to enter the serial programming mode. Finally, the connector 401 supplies +5 volts and ground to the external power pins Vdd and Vss of the microcontroller 10, respectively.

Referring to Figure 23, a diagram is shown to illustrate the different commands available for serial programming. The "load test" command is used to load a 14-bit word into the test program memory so that when this command is received, the program counter is set to a predetermined position in the test program memory. The "Load Data" command is used to load a 14-bit character into the user program memory. The "read data" command is used to send a 14-bit word from the user program memory. The "Increment Address" command is used to increment the program counter of the microcontroller 10 after being received. The "start program planning" command is used to test program memory or the start program planning of user program memory and a load test or load data command must be given before the start program planning command. The "enter parallel mode" command is used to program the microcontroller 10 to receive parallel mode data. Parallel mode is usually not applicable to in-circuit programming of microcontrollers because a battery pack usually only has some external connectors. Finally, the "End Program Planning" command is used to stop the program planning of the program memory.

Refer to Figures 24 and 25 respectively to illustrate the program operation of load data and read data commands for serial. In order to input an instruction, the timing pin is cycled 6 times so that each instruction bit is latched at the low edge of the timing sequence and the least significant bit (LSB) of the instruction is the first input. For the low edge of the timing, the data on the SDAA pin requires a minimum set-up (tseto, tset1) and hold time (thld0, thld1), such as 100 nanoseconds, as shown in Figures 24 and 25. Also, commands with data combination, such as read data and load data commands, are assigned a minimum delay, such as 1 millisecond, between the instruction and the data, as shown in Figures 24 and 25. After this delay, the timing pin is cycled 16 times. The first cycle is a start bit and the last cycle is a stop bit. The data is input or output in the middle of the first ground with the least significant bit. A timing cycle. In particular, during a read operation, the least significant bit will be transferred to the SDAA pin on the rising edge of the second cycle, and during a load operation, the least significant bit will be on the low edge of the second cycle Was tied up.

In this brief description, the present invention provides the programming of the microcontroller 10 serially in the circuit. This allows the use of a customer-programmable microcontroller when it has been placed in end-use applications (such as a battery pack for battery charging and battery monitoring control).

[Battery monitoring application]

Referring to FIG. 26, a block diagram is shown to illustrate the use of the microcontroller 10 architecture for monitoring the external battery 450. The voltage of the battery 450 is combined and supplied to the AN0/BATV analog input of the microcontroller 10 through the voltage distributor circuit 452. The current of the battery 450 supplies a voltage indicating the battery current to the AN1/BATI analog input of the microcontroller 10 via the sense resistor 454. The diagonal pins of the microcontroller 10 are combined through an external capacitor 456 and returned to ground for generating a programmable diagonal voltage thereon. The IAVG pin of the microcontroller 10 is selectively combined with an external capacitor 458 to return to ground for capturing small-period current pulsations as described above. The voltage regulator pin (VREG) is coupled to the gate electrode of the external N-channel FET460 to provide voltage adjustment. The row electrode of FET460 is coupled to receive the battery voltage, while the source electrode of FET460 provides a regulated voltage VDD to the microcontroller 10. Furthermore, the adjusted voltage can be measured via the external analog input AN2.

Although some preferred embodiments and methods are disclosed herein, for those skilled in the art, from the considerations described above, variations and modifications of the described embodiments and methods can be made without departing from the reality of the present invention. The spirit and scope are obvious. Therefore, the present invention is only limited to the additional requirements of the scope of the appended application and the rules and principles of applicable laws.