Device for processing digital data, and digital video system comprising the device

Device for processing digital data

The present invention relates to a digital data processing device, which includes a memory and a detection device for detecting whether there is an error in the digital data. The present invention also relates to a digital video system, which includes a video input, a video output, a video processor, a DCT circuit, a variable bit number encoder/decoder, and a modulation/demodulation Device, at least one read-write head, and also includes the above-mentioned digital data processing device.

For the same type of digital data processing device and digital video system of the present invention, please refer to European Patent Application No. 0 398 651 A2. The disclosed device can use an error correction and detection circuit after the digital data is written into the memory. Correct the erroneous data within the range, and then output a detection signal to the frame memory according to the read or unread data in the memory. The writing operation in the frame memory is interrupted when the number of error bits detected in each frame exceeds a preset value. The same data is then read again from the frame memory. The disadvantage of this type of device is that it needs to transfer data from one memory to another, so many addressing operations are required. Another disadvantage is that the memory contained in it contains many connection pins, which hinders the integration of the device on an IC. In another embodiment of the device mentioned in the above-mentioned patent application, the data is transferred to the frame memory through a converter that converts serial bits into parallel bits, so that the screen data memory The write operation performed in is interrupted when too many error bits are detected. The circuit used in the device of this embodiment is quite complicated.

Due to the above shortcomings, the purpose of the present invention is to provide a digital data processing device that does not have the above shortcomings and has a smaller volume structure. In order to achieve this goal, the device designed according to the concept of the present invention is characterized in that it also includes a read/write controller, which can be based on the error detected by the detection device at the selected address in the memory. Bits are used to write the received digital data, and reliable and correct data can be read from the memory at an address selected further. Therefore, only a single memory is sufficient. The device of the present invention only delivers data that the detected device considers to be reliable (for example, the number of bit errors is lower than a preset value or the data corrected by an error correction code).

An embodiment of the device according to the present invention is characterized in that the control device writes the received data into some addresses in the memory but does not store the last reliable data read. Therefore, a sufficient amount of reliable data will be stored in the memory at any time.

Another embodiment of the device according to the present invention is characterized in that the generated digital data includes a video signal with an error correction code; its memory includes a first sub-memory and a second sub-memory, which are respectively suitable for storing The amount of data contained in a frame in the video signal; its control device loads the bits in each frame in the received data into the sub-memory sequentially in line units, but does not read the final The bits in the fetched screen data are stored. Therefore, there will definitely be a frame data with correct bits in the memory. One thing that must be noted is that the address selection in the two sets of sub-memory can of course also be performed in a way that several rows of bit data are performed simultaneously.

Another embodiment of the device according to the present invention is characterized in that the control device outputs data in units of rows, and outputs data at the address written in the last group of absolutely correct data. The data is retrieved. This device can therefore output a video signal with no errors in every row of each data. This video signal can still produce good quality images even when the received video signal contains error bits.

Another embodiment according to the present invention is characterized in that the memory includes two sets of standard 1Mb SRAM (Static Random Access Memory) connected in parallel. This is a simple and low-cost design method.

Figure 1 shows a digital video system designed according to the concept of the present invention; Figure 2 shows a device designed according to the concept of the present invention; Figure 3 shows the operation of the device according to the present invention.

Figure 1 shows a digital video system suitable for applying the device according to the invention. This type of system generally includes a video input 1.1 for providing digital video signals to the video processor 1.5 in the video recording mode. This video data can be generated by a digital image pickup unit, such as a CCD (Charge Coupled Device) camera with 25 frames per second (50 bottom surfaces), and each frame contains approximately 420,000 pixels of video data. In the video processor 1.5, whenever two fields are sent here, they are combined into a picture, and then the bit data composing the picture is stored in a memory 1.7. The memory 1.7 can be, for example, a 5Mb DRAM (Dynamic Random Access Memory). Each pixel in the screen contains 8 bits of luminance data, so it can be used to represent 256 levels of gray. In addition, two groups of values containing 8 bits are used to determine the coarser light range (raster), for example, the chrominance (chrominance) in a picture grid composed of 2x2 pixels. The video processor 1.5 is also used to form a DCT data block composed of 8x8 bytes (1 byte is composed of 8 bits); the brightness data is called the brightness DCT data block, and The chrominance data is called the chrominance DCT data block. Four sets of brightness DCT data blocks (each block is related to the brightness data of 8x8 pixels) and its related two sets of chrominance DCT data blocks together form a set of so-called DCT data units. Each time, five sets of DCT data units generated by the homomixing performed in the video processor 1.5 constitute a data segment. The homomixing effect has the effect of averaging data, which is quite helpful for subsequent data reduction. Each DCT data block undergoes data conversion in a conventional discrete cosine conversion circuit 1.9 (this circuit also has the capability of inverse discrete cosine conversion). Then each data segment (that is, every 30 DCT data methods) is data reduced in a conventional variable-length encoder/decoder 1.10. In this encoder/decoder 1.10, 30*64*8=15,360 bits in each data segment are reduced to 3072 bits by using conventional techniques such as quantization and variable length coding. The quantification can be carried out in parallel in different methods if necessary, and the most appropriate method is selected each time.

The aforementioned system may also include an audio input 1.3 for providing digital audio data to an audio processor 1.6 in the recording mode. The audio data can be generated by one or more sets of microphones, and then sent to the audio processor 1.6 through an analog/digital (A/D) converter 1.16. This audio processor 1.6 is additionally connected to a memory 1.8. This memory 1.8 can be 256kb SRAM. Generally speaking, the number of bits of audio data is much smaller than that of video data, so the process of data reduction does not need to be used.

The audio data processed by the processor 1.6 (which also forms a data block) and the data reduced by the circuit 1.10 are sent to another device 1.11 (see Figure 2). This device 1.11 includes a memory 1.12, an encoder/decoder circuit 1.18 for error correction (hereinafter referred to as erco circuit), and a control device 1.19. In the recording mode, the data is added with the conventional error correction code in the erco circuit 1.18, such as the commonly used Reed-Solomon product code. This error correction code is described in US Patent No. 4,802,173. The series of data bits are converted into data words, and each data word is formed according to the encoding method of the error correction code and converted into a code word, and then stored in a memory in the recording mode . If these codeword groups are taken out of the memory in the regeneration mode, and some bits are different from the original codeword groups due to noise interference or other destructive factors, the error correction codes contained therein can be In the decoding process, the wrong bits are corrected. Several bytes (or data symbols of other forms) to be protected by error correction codes are arranged in a square matrix, and then the so-called parity symbols (parity symbols) are arranged in a square matrix. Symbol is applied to the data word group in each row and each column according to the coding method of the correction code used. The data block with the same symbol is called the code block. Parity symbols are additional data that can be used to correct erroneous bits in the array of bytes due to noise or memory damage during data transmission. For the generation and handling methods of these error correction codes, please refer to Richard E. Blahut's "Theory and Practice of Error Control Codes" published by Addison-Wesley Books in 1983, or refer to N. Glover and T. Dudley. The book "Practical Error Correction Design for Engineers" published by Data Systems Technology, Inc., located in Bluefield, Colorado.

The total number of brightness DCT data blocks in each grid frame is 720/8*576/8=6480, and there are 3240 chroma DCT data blocks. Therefore, each grid frame is composed of 1620 DCT data units or 324 data segments. If the conversion frequency of the electric field is 50 Hz, each grid frame is divided into 12 tracks, and if the frequency is 60 Hz, it is divided into 10 tracks. In addition to data symbols and parity symbols, each track also contains identification and synchronization data. These data symbols and parity symbols will be collectively referred to as "RS video data block" in the following description. Therefore, there are a total of 27 data segments in each RS video data box. Each RS video data block consists of 3072 bits and each data segment (-384 bytes) constitutes 3 rows of data, each row of data is composed of 128 bytes, and each row of data includes one Byte auxiliary data AUX. The auxiliary data can be, for example, the elapsed time or the status data such as the frame of the currently projected frame. An RS video data block therefore includes 81 rows of a data array composed of 128 bits, forming a data block with 81 rows and 128 vertical rows. After each RS data block enters the erco circuit 1.18, according to the Li De-Solomon product code method, the corresponding parity symbol is appended to the data symbol in it. For example, first an outer code can be added to the vertical data word group, and then an inner code is added to the parallel data word group. The standard mathematical representation of this Li De-Solomon code is RS(k+p₁,k,p+1), where k is the number of data symbols to be protected from errors, and p is the number of parity symbols added. Use primitive polynominal X⁸+X⁴+X³+X²+1 can derive that the outer code is RS(88,81,8) in the GF(256) field, and the inner code is the subprime polynomial X in the GF(256) field⁸+X⁴+X³+X²+1 derived RS (136, 128, 9). Whether encoding in the recording mode or decoding in the playback mode, it is necessary to temporarily store the digital data in the memory 1.12. Its operation is as follows. The variable-length encoding/decoding circuit 1.10 first transmits the unencoded video data to the circuit 1.11. In this process, the data is written line by line into the memory 1.12 under the control of the control device 1.19. The address used to write data into the memory is determined by the storage location of the frame whose last bit is correct. This detail will be described later. There are 81 rows and 128 rows of bytes in each RS video data box. A data string of 81 rows is formed, and each row data string is composed of 128 data words; and a data string of 128 vertical rows is composed of 81 bytes. The erco circuit 1.18 provides the corresponding parity symbols of the outer code of the data word group in the vertical row, and these parity symbols are also written into the memory along with the data word group. Then the row data block in the memory 1.12 is added with its corresponding parity symbol according to the inner code. The longitudinal parity symbols of the outer side code previously determined then also form a row of data words. The audio data is processed in a circuit with the video data in turn (for example, in a multiplexing manner), whereby the audio data can be encoded only according to the inner code. In the video mode, the codeword group encoded in this way is sent to a conventional modulation/demodulation circuit 1.13, and then sent to the two sets of read/write heads 1.14 and 1.15 after being modulated. It is therefore recorded on a data storage medium such as a magnetic tape.

When reproducing video and audio, the two sets of read/write heads 1.14 and 1.15 read out the codeword groups stored on the tape, and then send these codeword groups to the modulation/demodulation circuit 1.13. If the number of erroneous bits in the changed data is below the allowable limit, the erco circuit 1.18 can be used in circuit 1.11 to correct the erroneous bit by using the parity symbol added according to the Li De-Solomon coding method. The first decoding is to add the inner code in the horizontal video and audio containing code words, and then the corrected data is separated into the audio data and then sent to the audio processor 1.6. The remaining video data is then decoded according to the outer code, and the decoded video data is then sent to the encoding/decoding circuit 1.10. The audio processor 1.6 sends the audio data to a digital/analog (D/A) converter, and then sends it to an audio output terminal 1.4 after conversion. The variable-length encoding/decoding circuit 1.10 decodes the variable-length code, and then supplements the number of decoded bits to each data segment containing 15,360 bits. This data is then sent to the DCT circuit for inverse discrete cosine conversion. The converted data is then sent to the video processor 1.5 for proper processing of the data so that it can be output by the video output device 1.2.

When the number of error bits in the data exceeds the allowable upper limit and cannot be corrected by the error correction code in the reproduction mode, it is convenient to use the following method for concealment. For a certain amount of data (for example, one frame, one track, one data segment, or one row of data string), the erco circuit 1.18 can detect whether there is an error in this group of data bits. If there is a wrong bit, replace it with the previous reliable data. The best way to achieve this is to use, for example, a 1Mb controlled by two sets of standard models with the same address. SRAM is a group of 2M memory connected in parallel. The control device 1.19 can therefore write the received digital data in the memory at an address determined by the position of the error bit detected by the erco circuit 1.18, and by further reading from the memory Read the data to be output at the selected address to confirm that the data contained in the variable-length encoder/decoder 1.10 is deemed reliable and the last frame has been stored in the memory until There are new data that are recognized as correct by erco circuit 1.18 until they are stored, and it is confirmed that the output is only reliable and correct data. This mode of operation is shown in Figure 3. The memory 1.12 includes two sections, and each section can be used to store the amount of all data equivalent to a frame in the video signal. Depending on the data unit, each data segment or each row of data string is provided with a control bit C to memorize how the data in the above frame is absolutely correct. Two sections in the body. In recording mode, only one section of this memory can be used to temporarily store video data. In this case, the control bit C can be left unused. In the reproduction mode, all the data in a frame with an order of N-1 is in the previous frame (i.e. a screen with an order of N-2) where the data does not contain error bits exceeding the limit It is written into the left half of the memory. This data is confirmed by the erco circuit 1.18 as reliable data, and is suitable for sending to the variable-length encoding/decoding circuit 1.10 (hereinafter abbreviated as VLCD) as the output frame, such as Shown in Figure 3A. Before the data of the N-1th frame is written, the control bit C remains at 1. In order to simplify the description, a row of data string will be used as the basic data unit for storage. However, other data units are also applicable. For example, suppose that the N-1th grid frame contains error bits caused by electrical pulses. This error data can be detected by the erco circuit 1.12 but cannot be corrected. At this time, the control bit C changes its value to 0 for all reliable and error-free data strings in each row. The control bit of each row of data string containing the error bit remains at 1. The control device 1.19 reads the data from the memory and sends it to the VLCD according to the value of the control bit C in the following way: If the control bit is 0, the corresponding row of data is read from the left half of the memory. If the control bit is 1, then the corresponding row of data string will be read from the right half of the memory.

Through the above method, the damaged data in the N-1th frame can be replaced with the reliable data in the corresponding position in the N-2th frame. Then the next received Nth grid frame (see Figure 3B) is written into the memory 1.12 under the control of the control device 1.19. The memory 1.12 stored in the previous grid frame is not Data sent to the VLCD, so if the control bit value is 0, the data in the right half of the memory is considered; otherwise, if the control bit value is 1, then the data in the left half of the memory is considered material. Next, the erco circuit 1.18 is used to detect whether the data contained in the Nth grid contains incorrect data that cannot be corrected. All the control bits are inverted except for the control bits corresponding to the data string containing the error bits. The control device 1.19 then reads the data based on the value contained in the control bit and sends it to the VLCD, that is, if the control bit is 0, read the data contained in the left half of the memory; if The control bit is 1, then the data contained in the right half of the memory is read. Figure 3C shows the next step in this procedure: the frame data of the N+1 grid does not contain uncorrectable error data, so it is written in the memory at the address determined by the control device as shown in the figure. .

Therefore, the control device selects an appropriate address to write the received data according to the uncorrectable error data detected by the erco circuit in the previous frame. The control device then selects an appropriate address based on the uncorrectable error data detected by the erco circuit in the currently received frame data, and reads the data contained therein. The data read from a storage medium is first processed by a row error data decoder (inner code). Whether each row of data string has ever corrected errors is recorded in an internal RAM, and then stored in the memory 1.12 according to its corresponding control bit C. The data is then processed by the vertical error data decoder (outside code) in units of each RS video data block. Under the control of the control device, it is determined according to the corresponding control bit, and a vertical row of code words is included. Read it out. Next, the erco circuit 1.18 can determine whether the data in the RS video data box is reliable and error-free. The following situations can be distinguished based on this point. The data may be completely corrected and the values of all corresponding control bits are reversed. If the outer decoder fails to correct the wrong data, the possible reason is that the data has been smeared too much, which makes the control bit corresponding to each row data string corrected by the row decoder The value is reversed (as shown in the internal RAM). The reason may also be that the smear-type correction shows that most of the correction actions performed by the inner decoder are errors, and this wrong correction action can be detected by the vertical decoder and cannot be corrected. This makes the value of the corresponding control bit remain unchanged in the entire RS video data box (hidden the entire RS video data box).

The present invention can also provide functions for some special application modes (such as slow motion, screen search, etc.) used in the video system. In slow motion mode, an RS video data block is sent from the storage medium at a very fast speed. For example, when the slow-motion deceleration factor is 3, the data is sent in three sections, so a complete frame needs three times the time of normal playback to be combined. In this three times as long time, the reliable data in the previous frame is still continuously transmitted to the VLCD. When a complete frame data is roughly assembled in the memory (of course, it is located in the memory where there is no reliable data for the previous frame), all the corresponding control bits are once again as before Change its value in the manner described. This is not a very time-consuming process, because the decoding work performed by the erco circuit 1.18 can be performed in units of each RS video data block. Then it is recognized by the erco circuit and the reliable data displayed by the control bit C in the memory is read out in the next three frame periods, and then sent to the VLCD. A high-quality slow motion animation is thus played out. In the screen search mode, the control bit C may be set to a fixed value. This is because the outside correction cannot be performed in this case (that is, the complete RS video data block cannot be received).