Methods of operating ferroelectric memory cells, and related ferroelectric memory cells

Method of operating ferroelectric memory cell and related ferroelectric memory cell

METHODS OF OPERATING FERROELECTRIC MEMORY CELLS, AND RELATED FERROELECTRIC MEMORY CELLS

The embodiments disclosed herein are related to methods of operating ferroelectric memory cells including ferroelectric materials exhibiting asymmetric ferroelectric properties and such ferroelectric memory cells.

It has been considered to use ferroelectric random access memory (FeRAM) cells in many memory arrays. The FeRAM cell contains a ferroelectric material that has a polarization that can be switched in response to the application of an electric field (such as a bias voltage). The polarization state of the ferroelectric material in the FeRAM cell can be used to determine a logic state (for example, 1 or 0) of the FeRAM cell. After the bias voltage is removed, the polarization of the ferroelectric material can be maintained. Therefore, the FeRAM cell system is non-volatile, so there is no need to periodically renew the memory cell. The conventional FeRAM cell theoretically exhibits a square hysteresis loop 102 as shown in FIG. 1 under an applied electric field, because the atoms of the ferroelectric material transition between two equally favorable states. The FeRAM cell switches from one operating state to another by exposing the FeRAM cell to a switching bias voltage. For example, the ferroelectric material can be exposed to a positive voltage to switch the polarization of the ferroelectric material to a first direction. At a sufficiently large positive voltage (characterized as a positive switching voltage), the polarization of the ferroelectric material switches from a negative polarity to a positive polarity. To switch the FeRAM cell to another state, the ferroelectric material is exposed to a negative switching voltage to change the polarization of the ferroelectric material to a second opposite direction. Conventionally, the positive switching voltage and the negative switching voltage applied to a conventional FeRAM cell have the same magnitude (for example, have the same absolute value, which is also referred to herein as a symmetrical bias scheme). Unfortunately, many FeRAM cells need to use a high bias voltage to switch between different polarization states. Any power savings achieved by the non-volatility of the FeRAM cell relative to a DRAM cell is offset by the high bias voltage that must be applied to switch the polarization state of the ferroelectric material. Therefore, exposing the ferroelectric material to a higher voltage increases the power consumption of the FeRAM cell, increases the operating cost, and also shortens the service life of the FeRAM cell.

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<b>Priority claim</b>This application claims the name "METHODS OF OPERATING FERROELECTRIC MEMORY CELLS, "AND RELATED FERROELECTRIC MEMORY CELLS", the right of the filing date of the US Patent Application No. 14/842,124 filed on September 1, 2015. The explanatory drawings included in the present invention do not mean actual views of any specific system or semiconductor device, but are merely idealized representations for describing the embodiments herein. Common elements and features between the drawings can keep the same element signs. The following description provides specific details such as material type, material thickness, and processing conditions to provide a detailed description of the embodiments described herein. However, those of ordinary skill should understand that the embodiments disclosed herein can be practiced without using these specific details. In fact, the embodiments can be practiced in combination with conventional manufacturing techniques used in the semiconductor industry. In addition, the description provided herein does not form a complete program flow for manufacturing a ferroelectric memory cell, and the ferroelectric memory cell described below does not form a complete ferroelectric memory cell. Hereinafter, only the program actions and structures required to understand the embodiments described herein will be described in detail. The additional actions for forming a complete ferroelectric memory cell can be performed by conventional techniques. As used herein, the term "switching voltage" means and includes a bias voltage applied between a pair of electrodes (for example, a capacitor), which is sufficient to switch a pole of a ferroelectric material disposed between the pair of electrodesChemical status. The bias voltage can be a positive bias voltage, in which case the switching voltage is referred to as a "positive switching voltage"; or the bias voltage can be a negative bias voltage, in which case the switching voltage is referred to as a "negative switching voltage" Voltage". According to some embodiments, a method of operating a ferroelectric memory cell by applying an asymmetric bias scheme is disclosed. The ferroelectric memory cell can be asymmetric and can exhibit asymmetric switching characteristics. As used herein, the term "asymmetric ferroelectric memory cell" means and includes a memory cell that includes a ferroelectric material disposed between two electrodes. The asymmetric ferroelectric memory cell may include an interface material between one of the electrodes and the ferroelectric material. In some embodiments, each of the electrodes also has a different thickness or is formed by a different method. As used herein, the term "asymmetrical bias scheme" means and includes: applying a bias voltage (for example, a potential) across an electrode of a ferroelectric memory cell to form the ferroelectric material of the ferroelectric memory cell A polarization is switched from a first state to a second state, and the bias voltage is different from a bias voltage applied across electrodes for switching the polarization from the second state to the first state. In other words, applying an asymmetrical bias voltage scheme includes: applying a positive switching voltage whose magnitude is different from a negative switching voltage. For example, one polarization direction of the ferroelectric memory cell can be switched from a first direction to a second direction by applying a positive bias voltage across the ferroelectric memory cell, and the positive bias voltage is different from A negative bias voltage for switching the direction of polarization from the second direction to the first direction. Therefore, the ferroelectric memory cell can be switched from a first polarization to a second polarization at a positive bias voltage, and the positive bias voltage is different from that used for switching from the second polarization state to the One of the absolute values of the negative bias voltage of one of the first polarization states. Using an asymmetric bias scheme to operate the ferroelectric memory cell can reduce the power used to operate the ferroelectric memory cell and can increase the operating life of the ferroelectric memory cell. Using an asymmetric biasing scheme to operate the ferroelectric memory cell can also provide a more consistent switching signal strength over the life of the ferroelectric memory cell under different operating conditions (such as pulses at different frequencies). FIG. 2 shows a capacitor 200 including a ferroelectric material 206. The capacitor 200 may form a part of a ferroelectric memory cell according to an embodiment of the present invention and may include a bottom electrode 202, an interface material 204 covering the bottom electrode 202, and a ferroelectric material 206 covering the interface material 204 , And an upper electrode 208 covered on the ferroelectric material. For example, the capacitor 200 may be a metal-insulator-metal (MIM) capacitor. Although the capacitor 200 has been described and shown as being used in a ferroelectric memory cell, the capacitor 200 can also be used in dynamic random access memory (DRAM) applications. The bottom electrode 202 may include a conductive material. In some embodiments, the lower electrode 202 includes titanium, titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), platinum, combinations thereof, or other conductive materials. In some embodiments, the lower electrode 202 may be doped with carbon. The lower electrode 202 can be deposited by sputtering, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition ( LPCVD) or other suitable procedures. The interface material 204 can directly cover the bottom electrode 202 and contact the bottom electrode 202, and can be interposed between the bottom electrode 202 and the ferroelectric material 206. In some embodiments, the interface material 204 includes an oxide of the material of the bottom electrode 202. For example, when the lower electrode 202 includes titanium nitride, the interface material 204 may include titanium dioxide (TiO₂) Of titanium oxide (TiO_x). In other embodiments, the interface material 204 may include a non-conductive dielectric material such as, for example, aluminum nitride (AlN). As will be described herein, the capacitor 200 including the interface material 204 can form an asymmetric capacitor 200 exhibiting an asymmetric hysteresis loop. The ferroelectric material 206 can directly coat and contact the interface material 204. The ferroelectric material 206 may include a dielectric material that exhibits a polarization that can be switched by an applied electric field (for example, a displacement of oppositely charged ions used to generate a dipole moment). Therefore, the ferroelectric material 206 may include a material capable of exhibiting a polarization that can be switched in response to exposure to a switching voltage. In addition, the ferroelectric material 206 may include a residual polarization (P_r). Therefore, the polarization of the ferroelectric material 206 can be interpreted as the state of the associated memory cell (for example, 1 or 0). The ferroelectric material 206 may include one or more of the following: hafnium oxide (HfO_x), Zirconia (ZrO_x), lead zirconate titanate (PZT), another ferroelectric material known in the art, or a combination thereof. In some embodiments, the ferroelectric material 206 includes hafnium dioxide (HfO₂) Or zirconium dioxide (ZrO₂). The ferroelectric material 206 may include one or more dopants. For example, the ferroelectric material 206 may include one or more of the following: silicon, aluminum, zirconium, magnesium, strontium, gamma, yttrium, other rare earth elements, and combinations thereof. The upper electrode 208 can directly cover the ferroelectric material 206 and contact the ferroelectric material 206. The upper electrode 208 may include a conductive material. In some embodiments, the upper electrode 208 includes titanium, titanium nitride, titanium aluminum nitride, tantalum nitride, platinum, combinations thereof, or other conductive materials. The upper electrode 208 may be formed by sputtering, atomic layer deposition, chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or other suitable procedures. In some embodiments, the upper electrode 208 includes a different material from the lower electrode 202. In other embodiments, the upper electrode 208 may have a different thickness than the lower electrode 202. In other embodiments, the upper electrode 208 may be formed by a method different from that of the lower electrode 202 (for example, ALD). An upper electrode 208 containing a material different from the lower electrode 202, having a thickness different from the thickness of the lower electrode 202, formed by a method different from the lower electrode 202, or a combination thereof, can form an asymmetric capacitor 200. In some embodiments, the capacitor 200 includes: a bottom electrode 202 that includes titanium aluminum nitride; an interface material 204 that includes aluminum nitride; and a ferroelectric material 206 that includes one or more of hafnium oxide and zirconium oxide ; And an upper electrode 208, which includes titanium nitride. In other embodiments, the capacitor 200 includes: a bottom electrode 202 that includes titanium nitride; an interface material 204 that includes titanium oxide; a ferroelectric material 206 that includes one or more of hafnium oxide and zirconium oxide; and An upper electrode 208, which includes titanium nitride. Although FIG. 2 depicts the interface material 204 as being directly disposed between the lower electrode 202 and the ferroelectric material 206, the interface material 204 may be between the ferroelectric material 206 and the upper electrode 208. In some of these embodiments, the ferroelectric material 206 may directly cover and contact the lower electrode 202. In some embodiments, the capacitor 200 includes only one interface material 204 disposed between the lower electrode 202 and the ferroelectric material 206 or between the ferroelectric material 206 and the upper electrode 208 (That is, the interface material 204 can only be positioned on one side of the ferroelectric material 206). It is expected that in other embodiments, the capacitor 200 may include an interface material 204 between the lower electrode 202 and the ferroelectric material 206 and another interface material 204 between the upper electrode 208 and the ferroelectric material 206. In some of these embodiments, the interface material 204 between the upper electrode 208 and the ferroelectric material 206 may be formed of a material different from the interface material 204 between the lower electrode 202 and the ferroelectric material 206 or may have a material different from that of the lower electrode. A thickness of the interface material 204 between 202 and the ferroelectric material 206. Referring to FIG. 3, a ferroelectric memory cell 300 including a capacitor 200 is shown. The ferroelectric memory cell 300 includes a substrate 310 and a source region 314 and a drain region 312 formed in the substrate 310. The substrate 310 may be a semiconductor substrate, a base semiconductor material on a supporting substrate, a metal electrode, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. The substrate 310 can be a conventional silicon substrate or other bulk substrates containing semiconductor materials. As used herein, the term "bulk substrate" not only means and includes silicon wafers, but also means and includes: silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates or silicon-on-glass ("SOG") substrate; a silicon epitaxial layer on a base semiconductor base; or other semiconductor or optoelectronic materials, such as silicon-germanium (Si_1-xGe_x, Where x is (for example, one mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN) or indium phosphide (InP), etc. In addition, when referring to a "substrate" in the following description, the previous process stage can be used to form the base semiconductor structure or the material, region, or junction in the base. The ferroelectric memory cell 300 may include an access transistor, which includes a dielectric material 316 and a gate electrode 318. The capacitor 200 can be connected to the drain region 312 of the transistor through a conductive contact (such as a conductive plug) 320. The conductive contact 320 can cover the drain region 312 and can directly contact the lower electrode 202 of the capacitor 200. The conductive contact 320 may include a conductive material such as, for example, tungsten, titanium, aluminum, copper, polysilicon, or other suitable conductive materials. The gate dielectric material 316 may include a suitable dielectric material. In some embodiments, the gate dielectric material 316 includes silicon dioxide or a high-k dielectric material, such as zirconia, hafnium oxide, aluminum oxide (Al₂O₃), yttrium oxide (Y₂O₃) Or other high-k dielectrics known in the art. The source region 314 and the drain region 312 may be positioned on opposite sides of the gate dielectric material 316. The gate electrode 318 may include a conductive material such as, for example, titanium, tantalum, tungsten, ruthenium, nitride, polysilicon, or other suitable conductive gate electrode materials. Accordingly, in one embodiment, a ferroelectric memory cell includes a capacitor covering a conductive material in contact with at least one of a source region and a drain region of a semiconductor substrate, the capacitor including: A first electrode including titanium aluminum nitride; a ferroelectric material including hafnium oxide, zirconium oxide or a combination thereof; an interface material between the first electrode and the ferroelectric material; And a second electrode, which includes titanium nitride, and the second electrode is covered on the ferroelectric material. During use and operation, a bias voltage (such as a positive switching voltage or a negative switching voltage) can be applied to the ferroelectric memory cell 300 containing the ferroelectric material 206 to switch the polarization of the ferroelectric material to a first state and Between a second state. For example, a potential can be applied between the upper electrode 208 and the lower electrode 202 to generate a potential across the capacitor 200. In some embodiments, the upper electrode 208 may be exposed to a positive voltage or a negative voltage, and the lower electrode 202 may be exposed to a zero voltage. In other embodiments, a first voltage may be applied to the upper electrode 208 and a second voltage may be applied to the lower electrode 202, so that a difference between the first voltage and the second voltage is equal to the positive switching voltage or One of the negative switching voltages. Referring to FIG. 4, there is shown an asymmetric biasing scheme for changing the polarization of the ferroelectric memory cell 300. The first bias voltage (for example, a positive switching voltage) shown at 400, such as, for example, about 1.8 V, can be applied to the ferroelectric memory cell 300. In response to the first bias voltage, the ferroelectric material 206 of the capacitor 200 becomes polarized in a first direction. After a period of time, the first bias voltage 400 may be removed (for example, the ferroelectric memory cell may be exposed to a zero bias voltage), as shown at 402. In response to removing the first bias voltage 400, the ferroelectric material 206 can be restored to a remanent polarization that can correspond to a logic state of the ferroelectric memory cell 300. To switch the polarization of the ferroelectric material 206, a value such as, for example, about -1.0 A second bias voltage (for example, a negative switching voltage) 404 of V is applied to the ferroelectric material 206. Therefore, one of the absolute values of the negative switching voltage is different from one of the absolute values of the positive switching voltage. In response to exposure to the second bias voltage 404, the ferroelectric material 206 can be polarized in a second direction opposite to the first direction. After exposing the ferroelectric material 206 to the second bias voltage 404, the second bias voltage 404 can be removed, and the ferroelectric material 206 can be restored to one of another logic state corresponding to the ferroelectric memory cell 300 Residual polarization. Although FIG. 4 shows a positive bias voltage of about 1.8 V and a negative bias voltage of about -1.0 V, any one of the absolute value of the positive bias voltage different from the absolute value of the negative bias voltage can be used. Asymmetrical bias scheme. In some embodiments, the absolute value of one of the positive bias voltage and the negative bias voltage may be between about 25% and about 99% of the absolute value of the other of the positive bias voltage and the negative bias voltage. , Such as between about 25% to about 40%, about 40% to about 50%, about 50% to about 60%, about 60% to about 75%, about 75% to about 90% Time, or between about 90% to about 99%. In some embodiments, the absolute value of one of the positive bias voltage and the negative bias voltage may be less than about 2/3 of the absolute value of the other of the positive bias voltage and the negative bias voltage, such as about 2 /3 to about 1/2. The first bias voltage 400 and the second bias voltage 404 can be applied by, for example, applying a potential across the capacitor 200. For example, a first potential (eg, a positive switching voltage) can be applied between the lower electrode 202 and the upper electrode 208 to generate a potential across the capacitor 200 and induce a polarization of the ferroelectric material 206 in the capacitor 200. To induce the opposite polarization of one of the ferroelectric materials 206, a second bias voltage 404 can be applied to the bottom electrode 202 and the top electrode 208 by, for example, applying a second potential (such as a negative switching voltage) between the bottom electrode 202 and the top electrode 208 Ferroelectric material 206. Although FIG. 4 illustrates the use of a form of an asymmetric biasing scheme to induce a transition from one polarization to another, it is contemplated that other waveforms such as, for example, a square pulse or a triangular pulse may be used. Switch polarization. A ferroelectric memory cell including an asymmetric capacitor 200 (FIG. 2) is formed. The asymmetric capacitor 200 has: a lower electrode 202, which includes titanium nitride; an interface material 204, which includes titanium oxide; and a ferroelectric material 206 , Which includes one of zirconium oxide, hafnium oxide, and a combination thereof; and an upper electrode 208, which includes titanium nitride. The lower electrode 202 has a thickness of about 100 Å, the interface material 204 has a thickness of about 5 Å, the ferroelectric material 206 has a thickness of about 70 Å, and the upper electrode 208 has a thickness of about 50 Å. The performance of this ferroelectric memory cell is determined by the conventional technique shown in FIGS. 5A to 5E. FIG. 5A shows a hysteresis curve 500 of the ferroelectric memory cell to which the asymmetric bias scheme is applied. The asymmetric bias scheme may include: applying a negative switching voltage of about -1.2 V to the ferroelectric memory cell, as indicated by arrow 502A. The arrow 502 indicates that a polarization of the ferroelectric material 206 can be switched from a positive polarization to a negative polarization at a negative coercive voltage of about -0.7 V located at an inflection point of the hysteresis curve. When the ferroelectric material 206 is exposed to a negative coercive voltage of about -0.7 V (for example, during the application of a negative switching voltage), the ferroelectric material 206 can start to switch from a positive polarity to a negative polarity. After removing the negative switching voltage, the polarization of the ferroelectric material 206 can be restored to about 7 μC/cm²One negative residual polarization (e.g. -P_r). The asymmetric biasing scheme may include: applying a positive switching voltage of about 1.8 V to the ferroelectric memory cell, as indicated by arrow 504A. The arrow 504 indicates that one polarization of the ferroelectric material 206 can be switched from a negative polarization to a positive polarization at a positive coercive voltage of about 1.1 V. When the ferroelectric material 206 is exposed to a positive coercive voltage of about 1.1 V (for example, during the application of a positive switching voltage), the ferroelectric material 206 can start to switch from a negative polarity to a positive polarity. After removing the positive switching voltage, the polarization of the ferroelectric material 206 can be restored to about 5 μC/cm²One of the positive residual polarization (e.g. P_r). Accordingly, the ferroelectric material 206 can exhibit asymmetric switching properties. In other words, an absolute value of the switching voltage used to switch the polarization of the ferroelectric material 206 from a first polarization to a second polarization is not equal to the one used to switch the polarization of the ferroelectric material 206 from the second polarization Switch to an absolute value of the switching voltage of the first polarization. For example, the ferroelectric material 206 can be switched from a negative polarity to a positive polarity by applying a positive switching voltage of about 1.8 V to the ferroelectric material 206, and a negative switching voltage of about -1.2 V can be applied. The ferroelectric material 206 is switched from the positive polarization to the negative polarization. Referring to FIG. 5B, the figure shows a graph showing a difference between a positive remanent polarization and a negative polarization of a ferroelectric memory cell containing a ferroelectric material 206 in a number of cycles. Graph. Number of cycles on the x-axis and 2P on the y-axis_rThe value of is equal to a polarization difference between the positive polarization state and the negative polarization state of the ferroelectric material 206. 2P_rThe value of can be equal to a difference between the positive remanent polarization and the negative remanent polarization. In some embodiments, it can correspond to a polarization intensity of a ferroelectric memory cell containing a ferroelectric material. Within the lifetime of a ferroelectric memory cell, 2P can be expected_rThe value of is kept constant, so that one of the constant polarization signals used to read the logic state of the ferroelectric memory cell can be sensed. Continuing to refer to FIG. 5B, the upper curve shows the polarization during the operating life of the ferroelectric memory cell when a symmetrical bias scheme (for example, a positive switching voltage of about 1.8 V and a negative switching voltage of about -1.8 V) is applied strength. The lower curve shows a polarization intensity within the operating life of the same ferroelectric memory cell when an asymmetric bias scheme (for example, a positive switching voltage of about 1.8 V and a negative switching voltage of about -1.2 V) is applied. During the initial operating phase, and up to about 10⁴For each cycle, the polarization intensity using the symmetric bias scheme and the polarization intensity using the asymmetric bias scheme are substantially flat (for example, the memory cell exhibits a substantially constant polarization intensity), as shown at 506 and 510, respectively Illustrated. However, when operating using the symmetrical bias scheme, the ferroelectric memory cell exhibits an undesirable increase in signal peak as the number of cycles of the ferroelectric memory cell increases, as shown at 508. On the other hand, when operating with an asymmetric biasing scheme, the ferroelectric memory cell exhibits a reduced signal peak as the number of cycles of the ferroelectric memory cell increases, as shown at 512. Therefore, the ferroelectric memory cell can exhibit smaller signal peaks and signal strength changes during the operation of the ferroelectric memory cell when operating with the asymmetric bias scheme than when operating with the symmetric bias scheme. Even if the maximum signal strength is reduced under the asymmetric bias scheme, a more constant polarization strength can be better used to sense the operating state of the ferroelectric memory cell. It is expected that one of the positive bias voltage and the negative bias voltage can be changed during the operating life of the ferroelectric memory cell, so that the polarization intensity is maintained at a substantially constant intensity. In some embodiments, after a predetermined number of cycles, at least one of the positive bias voltage and the negative bias voltage can be adjusted to maintain a substantially flat polarization. Referring to FIG. 5C, the graph shows the frequency dependence of the ferroelectric memory cell that varies according to the number of cycles. The upper graph of Fig. 5C shows the memory cell pulses of different frequencies (for example, The delay between pulses is about 50 ns and the delay is about 10 μs). The read signal of the ferroelectric memory cell varies according to the number of cycles. The graph below shows three different ferroelectrics operating with an asymmetric bias scheme. The read signal of the ferroelectric memory cell that varies with the number of cycles of the memory cell pulse of different frequencies of the memory cell. Figure 5C shows the frequency dependence of the ferroelectric memory cell at a temperature of about 30°C. Generally speaking, as the delay time between pulses increases, the read signal decreases undesirably. At (for example) about 4×10⁷After cycles, 2P_rThe value of Norm can be defined as 2P with a long delay (e.g. 10 μs)_rDivide by 2P with a long delay (e.g. 50 ns)_rThe ratio. Generally speaking, expect 2P_rThe value of Norm is equal to about 1.0, which means that the read signal of the ferroelectric memory cell will not change with the time between cycles (ie, cycle frequency). The graph above Figure 5C shows: For the symmetrical bias scheme, 2P_rThe value of Norm is equal to approximately 0.833. The lower graph of Figure 5C shows: For the asymmetrical bias scheme, 2P_rThe value of Norm is equal to approximately 0.905. In other words, for the asymmetrical bias scheme, at about 4×10⁷After four cycles, the ferroelectric memory cell exhibits a frequency-dependent signal loss under longer pulses that is smaller than when operating with a symmetrical bias scheme. Therefore, under the asymmetric bias scheme, the ferroelectric memory cell exhibits approximately 43% less signal loss than when the symmetric bias scheme is used to operate the ferroelectric memory cell. Referring to FIG. 5D, the graph shows the frequency dependence of the ferroelectric memory cell that changes according to the number of cycles for a temperature of about 100°C. Generally speaking, the performance of ferroelectric memory cells degrades at high temperatures due to the enhanced thermal depolarization of ferroelectric materials. FIG. 5D illustrates that at 100°C, the frequency dependence of the ferroelectric memory cell when operating with an asymmetrical bias scheme is improved compared to when operating with a symmetrical bias scheme. For example, the 2P of the symmetrical bias scheme_rThe value of Norm is shown as about 0.539 and 2P of the asymmetric bias scheme_rThe value of Norm is approximately 0.678. In some embodiments, the ferroelectric memory cell can be operated at high temperature, which means that 2P can be advantageously improved at high temperature._rThe value of Norm. Referring to FIG. 5E, the figure shows the voltage of a ferroelectric memory cell operating with a symmetrical biasing scheme (for example, a positive switching voltage of about 1.8 V and a negative switching voltage of about -1.8 V) as a function of time And the current curve. Plot the number of cycles in the figure (e.g. 1×10³Cycles, 1×10⁶Cycles, 1×10⁸Cycles and 1×10¹⁰Cycles) after the ferroelectric memory cell voltage and current. Refer to the upper left graph, count in the low cycle (for example, 1×10³At 514 cycles), the current of the ferroelectric memory cell can exhibit a double peak, as indicated at 514. Refer to the upper right graph, the double peak value 514 can be about 1×10⁶The memory cell cycle is maintained afterwards. The double peak 514 can undesirably cause the ferroelectric memory cell to switch or can reduce one of the ferroelectric memory cells' sensing window at low cycle counts. As an example, the ferroelectric memory cell may have a tendency to switch at each of the peaks of the double peak 514. Refer to the graph under Figure 5E, the ferroelectric memory cell is 1×10⁸Cycles and 1×10¹⁰The double peak 514 may no longer be exhibited at each cycle. Referring to FIG. 5F, there is shown a graph of voltage and current of a ferroelectric memory cell operating with an asymmetric bias scheme as a function of time. In some embodiments, the asymmetric biasing scheme may include selecting a positive switching voltage of about 1.8 V and a negative switching voltage of about -0.8 V. With reference to different voltage and current graphs, the ferroelectric memory cell does not exhibit double peaks at low cycle counts or high cycle counts. To be precise, refer to the above graph (for example, in the 1×10³Cycles and 1×10⁶At each period), the total measurement period count only shows a single peak value, as indicated by 516. Accordingly, using an asymmetric bias scheme to operate the ferroelectric memory cell can improve the operation of the ferroelectric memory cell and reduce the undesired switching of the ferroelectric memory cell at low cycle counts. A ferroelectric memory cell including an asymmetric capacitor 200 (FIG. 2) is formed. The asymmetric capacitor 200 has: a lower electrode 202, which includes titanium aluminum nitride (TiAlN); a dielectric interface material 204, which includes nitride Aluminum (AlN); a ferroelectric material 206, which includes one of zirconium oxide, hafnium oxide, and combinations thereof; and an upper electrode 208, which includes titanium nitride. The bottom electrode 202 has a thickness of about 60 Å, the interface material 204 has a thickness of about 2 Å, the ferroelectric material 206 has a thickness of about 70 Å, and the upper electrode 208 has a thickness of about 50 Å. The performance of this ferroelectric memory cell is determined by the conventional technique shown in FIGS. 6A to 6F. FIG. 6A shows a hysteresis curve 600 of the ferroelectric memory cell to which the asymmetric bias scheme is applied. The asymmetric bias scheme may include: applying a negative switching voltage of about -1.2 V to the ferroelectric memory cell, as indicated by arrow 602A. The arrow 602 indicates that a polarization of the ferroelectric material 206 can be switched from a positive polarization to a negative polarization at a negative coercive voltage of about -0.7 V located at an inflection point of the hysteresis curve. When the ferroelectric material 206 is exposed to about -0.7 At a negative coercive voltage of V (for example, during the application of a negative switching voltage), the ferroelectric material 206 can start to switch from positive to negative. After removing the negative switching voltage, the polarization of the ferroelectric material 206 can be restored to about -10 μC/cm²One negative residual polarization (e.g. -P_r). The asymmetric bias scheme may include: applying a positive switching voltage of about 1.8 V to the ferroelectric memory cell, as indicated by arrow 604A. The arrow 604 indicates that a polarization of the ferroelectric material 206 can be switched from a negative polarization to a positive polarization at a positive coercive voltage of about 1.2 V. When the ferroelectric material 206 is exposed to a positive coercive voltage of about 1.2 V (for example, during the application of a positive switching voltage), the ferroelectric material 206 can start to switch from a negative polarity to a positive polarity. After removing the positive switching voltage, the ferroelectric material 206 can exhibit about 8 μC/cm²One is positive residual polarization. Therefore, in some embodiments, the positive remanent polarization and the negative remanent polarization may have different magnitudes (for example, an absolute value of the positive remanent polarization may not be equal to an absolute value of the negative remanent polarization). Accordingly, the ferroelectric material 206 can exhibit asymmetric switching properties. In other words, an absolute value of the switching voltage used to switch the polarization of the ferroelectric material 206 from a first polarization to a second polarization is not equal to the one used to switch the polarization of the ferroelectric material 206 from the second polarization Switch to an absolute value of the switching voltage of the first polarization. For example, the ferroelectric material 206 can be switched from a negative polarity to a positive polarity by applying a positive switching voltage of about 1.8 V to the ferroelectric material 206, and a negative switching voltage of about -1.2 V can be applied. The ferroelectric material 206 is switched from the positive polarization to the negative polarization. Referring to FIG. 6B, there is shown a graph showing the polarization intensity of one of the ferroelectric memory cells of FIG. 6A in several cycles of the ferroelectric memory cell. The upper curve shows the 2P of the ferroelectric memory cell when a symmetrical bias scheme (for example, a positive switching voltage of about 1.8 V and a negative switching voltage of about -1.8 V) is applied_rThe lower curve shows the polarization intensity of the ferroelectric memory cell when an asymmetrical bias scheme (for example, a positive switching voltage of about 1.8 V and a negative switching voltage of about -1.2 V) is applied, as above Described with reference to Figure 5B. As shown at 606 and 610, the polarization strength of the ferroelectric memory cell using the symmetric bias scheme and the polarization strength of the ferroelectric memory cell using the asymmetric bias scheme are substantially flat during the initial stage of operation of. When operating with a symmetrical bias scheme, the polarization intensity is about 10⁵It starts to increase at about 10 cycles⁸The signal peak is reached at 608 cycles, as indicated at 608. When using the asymmetric bias scheme to operate, the polarization intensity is about 10⁶It starts to increase at 10 cycles, and the signal peak appears at about 10⁸Cycles, as indicated at 612. Advantageously, the peak signal at 612 is substantially the same as the polarization intensity exhibited during the entire operating life of the ferroelectric memory cell. Accordingly, during the lifetime of the ferroelectric memory cell, the polarization intensity of the ferroelectric memory cell operated by the asymmetric bias scheme can be kept substantially constant. When using a symmetrical bias scheme to operate, the ferroelectric memory cell can be at about 10⁸Fatigue began after three cycles. For example, the read signal can be at about 10⁸Weakened after cycles, and can be at about 10¹¹Decrease to about 6 μC/cm after 3 cycles². When operating with the asymmetric bias scheme, the ferroelectric memory cell will not exhibit fatigue as early as when operating with the symmetric bias scheme. For example, ferroelectric memory cells up to about 10⁹Fatigue began to appear after three cycles. Therefore, when operating using the asymmetric biasing scheme, the ferroelectric memory cell can exhibit a lower signal peak value and will not exhibit fatigue until more operating cycles. When comparing the result of FIG. 6B with the result of FIG. 5B (which plots the polarization intensity of a ferroelectric memory cell containing a material different from that of FIG. 6B), a similar trend is observed. Continuing to refer to FIG. 6B, the ferroelectric memory cell including the titanium aluminum nitride lower electrode and the aluminum nitride interface material can exhibit better performance than the ferroelectric memory including the titanium nitride electrode with different thickness during the operation of the ferroelectric memory cell The polarization intensity of the cell changes. Referring to FIG. 6C, the graph shows the frequency dependence of the ferroelectric memory cell at a temperature of about 30°C, which changes according to the number of cycles. The graph above Figure 6C shows: For the symmetrical bias scheme, 2P_rNorm is equal to approximately 0.929. The graph below shows: For asymmetrical bias scheme, 2P_rNorm is equal to about 0.961. Therefore, when operating with the asymmetric bias scheme, the ferroelectric memory cell can exhibit a smaller frequency-dependent signal loss at longer period pulses than when operating with the symmetric bias scheme. Referring to FIG. 6D, the graph shows the frequency dependence of the ferroelectric memory cell that changes according to the number of cycles for a temperature of about 100°C. Symmetrical bias scheme 2P_rThe value of Norm is about 0.759 and 2P of the asymmetric bias scheme_rThe value of Norm is about 0.733. Therefore, when operating with a symmetrical biasing scheme, the ferroelectric memory cell can only exhibit a slightly higher 2P than when operating with an asymmetrical biasing scheme._rA value of Norm. Referring to FIG. 6E, the asymmetric biasing scheme can be adapted to achieve a desired signal strength within the operating life of the ferroelectric memory cell. FIG. 6E shows a plurality of asymmetric biasing schemes and a symmetrical biasing scheme of an asymmetric ferroelectric memory cell. When changing the positive switching voltage, each of the biasing schemes includes the same negative switching voltage (ie, -1.8 V). As shown in FIG. 6E, the positive switching voltage can affect the initial signal level of the ferroelectric memory cell. As the positive switching voltage increases, the signal level of the ferroelectric memory cell can also increase. Referring to Figure 6F, the asymmetric biasing scheme can be adapted to control the amount of signal peaks and the onset of fatigue. FIG. 6F shows the signal strength of several biasing schemes with the same positive switching voltage (ie, 1.8 V) when the negative switching voltage is changed according to the number of cycles. Generally speaking, when operating with a larger negative switching voltage (for example -2.8 V, -2.5 V, -2.2 V, etc.), the ferroelectric memory cell exhibits a larger amount of undesired signal peaks. However, when using a negative switching voltage with a lower magnitude (such as -0.8 V, -0.9 V, -1.0 V, etc.) to operate, the ferroelectric memory cell exhibits lower signal strength and is also in a lower cycle Fatigue began in several places. In conditions such as -1.2 V, -1.4 V and -1.6 At the negative switching voltage of V, the ferroelectric memory cell exhibits a substantially flat signal and does not begin to exhibit fatigue characteristics until a higher number of cycles than other biasing schemes. As an example, when operating with a bias scheme having a positive switching voltage of about 1.8 V and a negative switching voltage of about -1.2 V, the ferroelectric memory cell exhibits a substantiality during the operating life of the memory cell Up to a flat signal and even up to about 10¹⁰The fatigue-reducing characteristics are shown after three cycles. Therefore, the asymmetric bias scheme can reduce power consumption and maintain the desired performance. According to this, a strong signal can be achieved, and at the same time the fatigue properties of the ferroelectric memory cell can be reduced. Accordingly, in one embodiment, a method of operating a ferroelectric memory cell includes: applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell including a capacitor, the The capacitor includes an upper electrode, a lower electrode, a ferroelectric material between the upper electrode and the lower electrode, and an interface material between the ferroelectric material and one of the upper electrode and the lower electrode; and The other of the positive bias voltage and the negative bias voltage is applied to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from the positive bias One of the absolute values of the voltage. Accordingly, in another embodiment, a method of operating a ferroelectric memory cell includes: applying one of a positive bias voltage and a negative bias voltage to a ferroelectric capacitor, the ferroelectric capacitor including a A first electrode, an interface material between the first electrode and a ferroelectric material, and a second electrode adjacent to the ferroelectric material; and the other of the positive bias voltage and the negative bias voltage When applied to the ferroelectric capacitor, the negative bias voltage has a magnitude different from the positive bias voltage. Using an asymmetric bias scheme to operate an asymmetric ferroelectric memory cell can reduce the power consumption used during the operation of the asymmetric ferroelectric memory cell, reduce signal peaks, and reduce frequency-dependent signal loss. Under this operating scheme, the ferroelectric memory cell will not be overdriven and can be configured to operate for a longer period of time before crashing. The ferroelectric memory cell may include an upper electrode and a lower electrode, which have different thicknesses, are formed of different materials, are formed under different processing conditions, or a combination thereof. The ferroelectric material may include hafnium oxide, zirconium oxide, or a combination thereof. An interface material can be disposed between the ferroelectric material and one of the upper electrode and the lower electrode. Although certain illustrative embodiments have been described in conjunction with the drawings, those of ordinary skill will recognize and should understand that the embodiments covered by the present invention are not limited to the embodiments explicitly shown and described herein. To be precise, many additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments covered by the present invention (such as the embodiments claimed below, which include legal equivalents). In addition, the features from one disclosed embodiment can be combined with the features of another disclosed embodiment while still being encompassed within the scope of the invention anticipated by the inventor.

<p>102Hysteresis loop</p><p>200Capacitor</p><p>202Lower electrode</p><p>204Interface material</p><p>206Ferroelectric materials</p><p>208Upper electrode</p><p>300Ferroelectric memory cell</p><p>310Substrate</p><p>312Dip pole area</p><p>314Source area</p><p>316Gate Dielectric Material</p><p>318Gate electrode</p><p>320Conductive contact</p><p>400First bias voltage</p><p>402Zero bias</p><p>404Second bias voltage</p><p>500Hysteresis curve</p><p>502The polarization of ferroelectric materials switches from positive to negative at negative coercive voltage</p><p>502AApply a negative switching voltage to the ferroelectric memory cell</p><p>504The polarization of ferroelectric materials switches from negative to positive at positive coercive voltage</p><p>504AApplies a positive switching voltage to the ferroelectric memory cell</p><p>506Polarization intensity using symmetrical bias scheme</p><p>508 signal peak</p><p>510Polarization intensity using asymmetric bias scheme</p><p>512peak signal</p><p>514Double peak</p><p>516Single peak</p><p>600Hysteresis curve</p><p>602The polarization of ferroelectric materials switches from positive to negative at negative coercive voltage</p><p>602AApply a negative switching voltage to the ferroelectric memory cell</p><p>604The polarization of ferroelectric materials switches from negative to positive at positive coercive voltage</p><p>604AApply a positive switching voltage to the ferroelectric memory cell</p><p>606Polarization strength of ferroelectric memory cell using symmetrical bias scheme</p><p>608 signal peak</p><p>610Polarization strength of ferroelectric memory cell using asymmetric bias scheme</p><p>612peak signal</p>

Fig. 1 is a hysteresis curve during the use and operation of a conventional ferroelectric memory cell; Fig. 2 is a cross-sectional view of an asymmetric ferroelectric capacitor according to an embodiment of the present invention; Fig. 3 is based on the present invention A cross-sectional view of a ferroelectric memory cell including the asymmetric ferroelectric capacitor of FIG. 2 according to an embodiment of the present invention; FIG. 4 is a cross-sectional view of a ferroelectric memory cell for operating a ferroelectric memory cell according to an embodiment of the present invention A graphical representation of an asymmetric bias scheme; FIG. 5A is a hysteresis curve during the use and operation of a ferroelectric memory cell according to an embodiment of the present invention; FIG. 5B is a use according to an embodiment of the present invention A symmetrical bias scheme to operate a ferroelectric memory cell and a ferroelectric memory cell using an asymmetrical bias scheme to operate a graph of the signal strength versus the number of cycles; Figure 5C is at 30°C A graphical representation of the frequency-dependent signal loss during the cycle of a ferroelectric memory cell when a symmetrical bias scheme and an asymmetrical bias scheme are used to operate a ferroelectric memory cell; Figure 5D is used at 100°C A graphical representation of the frequency-dependent signal loss during the cycle of a ferroelectric memory cell when a symmetrical bias scheme and an asymmetrical bias scheme are used to operate a ferroelectric memory cell; Figures 5E and 5F show various cycles Figure 6A is an asymmetric ferroelectric memory cell according to an embodiment of the present invention. A hysteresis curve during use and operation; FIG. 6B is a signal strength versus cycle number of a ferroelectric memory cell using a symmetrical biasing scheme to operate a ferroelectric memory cell and an asymmetrical biasing scheme for operating a ferroelectric memory cell according to an embodiment of the present invention A graph; Fig. 6C is one of the frequency-dependent signal loss during the cycle of a ferroelectric memory cell when a symmetrical bias scheme and an asymmetrical bias scheme are used at 30°C to operate a ferroelectric memory cell Graphical representation; Figure 6D is a graphical representation of the frequency-dependent signal loss during the cycle of a ferroelectric memory cell when using a symmetrical bias scheme and an asymmetrical bias scheme at 100°C to operate a ferroelectric memory cell Fig. 6E is a graphical representation of the signal intensity of a ferroelectric memory cell operating with a constant negative bias voltage and different positive bias voltages according to the number of cycles; and Fig. 6F is a graphic representation of a constant positive bias voltage and A graphical representation of the signal strength of ferroelectric memory cells operating with different negative bias voltages according to the number of cycles.

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