Multi-processor system including memory shared by multi-processor

Multi-processor system including memory shared by multiple processors

MULTI-PROCESSOR SYSTEM INCLUDING MEMORY SHARED BY MULTI-PROCESSOR

One or more exemplary embodiments of the inventive concept relate to a system including one or more processors and a method of operating the system, and more specifically, to a system including different types of processors A multi-processor system and a method of operating the multi-processor system.

In mobile devices according to the prior art (for example, smart phones, personal computers (PC), etc.), an application processor (AP) and a connectivity processor (CP) are implemented as Different chips are connected to each other via a chip-to-chip interface. The application processor is the main chip of the mobile device and is used to drive the operating system (OS) and various application programs of the mobile device. Connectivity processors connect mobile devices to external devices and can also be referred to as communication chips.

Therefore, in the prior art, the connectivity processor and the application processor operate separately as independent systems and exchange data with each other through the chip-to-chip interface.

Recently, a method in which the application processor and the connectivity processor are combined together as a system-on-chip (SoC) has been introduced

According to at least some example embodiments, a multi-processor system includes a first processor; a second processor; and a shared memory for storing data generated by the first processor and used by the second processor Generated data; and a memory interface circuit for interfacing between the shared memory and the first processor and the second processor, and the first processor is used for The received signal is demodulated and decoded, and the decoded data is stored in the shared memory through the memory interface circuit, and the memory interface circuit is used for processing the data stored in the shared memory The decoded data is read and decrypted, and the decrypted data is stored in the shared memory.

According to at least some exemplary embodiments of the inventive concept, a multi-processor system includes a first processor; a second processor; and a shared memory for storing data generated by the first processor and Data generated by the second processor; and a memory interface circuit for interfacing between the shared memory and the first processor and the second processor, and the second processor is used to generate The uplink data is used for wireless communication and the uplink data is stored in the shared memory through the memory interface circuit, and the memory interface circuit is further used to compare the data stored in the shared memory. The upstream data is read and encrypted, and the encrypted data is stored in the shared memory.

The shared memory may include a first processor allocation area and a second processor allocation area, the memory interface circuit may be used to store the uplink data in the second processor allocation area, and the memory The body interface circuit can be used to store the encrypted data in the first processor allocation area.

FIG. 1 is a schematic block diagram of a multi-processor system 10 according to at least one exemplary embodiment of the inventive concept. 1, the multi-processor system 10 includes a system-on-chip (SoC) 100 and a shared memory 300.

The system chip 100 includes a first processor 110, a second processor 130, and a shared memory interface circuit 200.

Each of the first processor 110 and the second processor 130 can access the shared memory 300 through the shared memory interface circuit 200. That is, the shared memory interface circuit 200 can interface between the shared memory 300 and the first processor 110 and the second processor 130. Each of the first processor 110 and the second processor 130 may include at least one processing unit.

The shared memory 300 is a main memory shared by the first processor 110 and the second processor 130. The shared memory 300 may be, for example, a dynamic random-access memory (DRAM), but it is not limited to this. For example, the shared memory 300 can be implemented as a non-volatile memory.

The first processor 110 or the second processor 130 can transmit a memory access request, also a data storage (write) request or a data read request, to the shared memory interface circuit 200. For example, the first processor 110 or the second processor 130 can exchange data with the shared memory interface circuit 200 through its direct memory access (DMA) unit 116 or direct memory access unit 134 .

The first bus 140 located between the first processor 110 and the shared memory interface circuit 200 can support data exchange between the first processor 110 and the shared memory interface circuit 200.

The second bus 150 located between the second processor 130 and the shared memory interface circuit 200 can support data exchange between the second processor 130 and the shared memory interface circuit 200.

In one embodiment, each of the first bus 140 and the second bus 150 may be based on the Advanced Microcontroller Bus architecture (AMBA) specification or the Advanced eXtensible Interface (Advanced eXtensible Interface) specification. , AXI) standard bus. However, the first bus bar 140 and the second bus bar 150 are not limited to the above-mentioned specification and may be a bus bar according to another interconnection specification.

The first processor 110 can demodulate and decode signals received through wireless communication to obtain decoded data, and store the decoded data in the shared memory 300 via the shared memory interface circuit 200. The decoded data may be encrypted (ciphered or encrypted) data. In one embodiment, the first processor 110 may generate packet data that has a predetermined or (alternatively) required format and includes the decoded data (for example, Internet Protocol (Internet Protocol)). protocol, IP) packet data). In this case, the packet data including the decoded data can be stored in the shared memory 300.

The shared memory interface circuit 200 reads and decrypts the decoded data stored in the shared memory 300, and stores the decrypted data in the shared memory 300.

To this end, the shared memory interface circuit 200 includes an encryption/decryption module 240 to decrypt the decoded data. The encryption/decryption module 240 can be implemented by a circuit included in the shared memory interface circuit 200.

After storing the decrypted data in the shared memory 300 through the shared memory interface circuit 200, the second processor 130 reads the decrypted data from the shared memory 300 and processes the decrypted data.

FIG. 2 is a diagram illustrating a shared memory 300a (for example, the shared memory shown in FIG. 1) according to at least one exemplary embodiment of the inventive concept. 1 and 2, the shared memory 300a may be divided into a plurality of areas, for example, two or more areas. In one embodiment, the shared memory 300a can be divided into a first processor allocation area 310, a second processor allocation area 320, and a reserved area 330.

The first processor allocation area 310 may include a firmware area 311, an address descriptor area 313, and a packet data area 315.

The firmware area 311 is an area for storing the firmware of the first processor 110. The address descriptor area 313 may be an area for storing address descriptors generated by the first processor 110. The address descriptor generated by the first processor 110 may include address information that specifies the location where the data to be used (stored or read) by the first processor 110 will be stored.

The packet data area 315 is an area for storing data for the first processor 110. For example, the packet data generated by the first processor 110 or to be read by the first processor 110 may be stored in the packet data area 315.

The data decoded by the first processor 110 can be stored in the packet data area 315 according to the address descriptor stored in the address descriptor area 313.

The second processor allocation area 320 may include a Transmission Control Protocol/Internet Protocol (TCP/IP) data area 321 and an address descriptor area 325.

The transmission control protocol/Internet protocol data area 321 is an area for storing data for the second processor 130. For example, the packet data generated by the second processor 130 or read by the second processor 130 may be stored in the transmission control protocol/Internet protocol data area 321.

The transmission control protocol/Internet protocol data area 321 may include a socket buffer 323.

The address descriptor area 325 may be an area for storing address descriptors generated by the second processor 130. The address descriptor generated by the second processor 130 may include address information that specifies the location where the data to be used (stored or read) by the second processor 130 will be stored.

The data decrypted by the shared memory interface circuit 200 can be stored in the socket buffer 323 according to the address descriptor stored in the address descriptor area 325.

FIG. 3 is a diagram illustrating in more detail a multi-processor system 10a according to at least one exemplary embodiment of the inventive concept. 3, the multi-processor system 10a includes a system-on-chip (SoC) 100a and a shared memory 300.

The system chip 100a includes a connectivity processor (CP) system chip 101, an application processor (AP) system chip 103, and a shared memory interface circuit 200.

The connectivity processor system chip 101 may include a modem processor 110 a, a central processing unit (CPU) 122, a digital signal processor (DSP) 124, and a first bus 140.

The central processing unit 122 controls the overall operation of the connectivity processor system chip 101.

The modem processor 110a may include a modulator/demodulator (modem Rx/Tx) 112, an encoder/decoder 114, and a first direct memory access unit 116. The modem processor 110a may correspond to the first processor 110 shown in FIG. 1. As shown in FIG. 3, the modem processor 110a can be implemented as a system chip (ie, the connectivity processor system chip 101) together with another processor and/or device, but is not limited to this example. According to at least some embodiments of the inventive concept, the term "direct memory access unit" used in the present invention may refer to, for example, a direct memory access controller.

The modulator/demodulator (modem Rx/Tx) 112 can demodulate the data received by wireless communication (for example, downlink data), and perform the demodulation of the data to be transmitted by wireless communication (for example, uplink data). Data) for modulation.

Here, the downlink data can be comprehensively understood as the data to be processed by being transmitted from the mobile communication base station to the mobile device, and the uplink data can be comprehensively understood as being generated by the mobile device and transmitted to the mobile communication base station. data of.

The multi-processor systems 10, 10a, and 10b according to at least some exemplary embodiments of the inventive concept are suitable for mobile devices for mobile communication. The modulation/demodulation method to be implemented by the modulator/demodulator (modem Rx/Tx) 112 can be changed according to the wireless communication protocol.

In the case of downlink data, the encoder/decoder 114 can receive and decode the data modulated by the modulator/demodulator (modem Rx/Tx) 112. In the case of uplink data, the encoder/decoder 114 may encode the data and transmit the encoded data to the modulator/demodulator (modem Rx/Tx) 112. In this case, the modulator/demodulator (modem Rx/Tx) 112 can modulate the encoded data into wireless data to be transmitted through wireless communication.

In one embodiment, the encoded data may be cyphered data by the shared memory interface circuit 200a. Therefore, the modem processor 110a can convert the encrypted data into wireless data to be transmitted through wireless communication.

The digital signal processor 124 can perform various processing operations on the digital signal.

For example, the digital signal processor 124 can process image data received from an image sensor (not shown in the figure).

The first bus 140 supports the communication between the components included in the connectivity processor system chip 101 and the communication between the connectivity processor system chip 101 and external devices.

The shared memory interface circuit 200a may include a regional bus 210a and a memory controller 220a.

The area bus 210 a can be connected to the first bus 140 and the second bus 150.

For example, the regional bus 210a can support data exchange between the first processor 110 and the memory controller 220a together with the first bus 140, and support the second processor 130 and memory together with the second bus 150 Data exchange between the controllers 220a. As discussed in more detail below, the central processing unit 130a shown in FIG. 3 may be an example of the second processor 130 shown in FIG.

The memory controller 220a may include a regional direct memory access unit 230a, an encryption/decryption module 240a, a read buffer 251, and a write buffer 253.

The memory controller 220a can receive the decoded data from the first direct memory access unit 116 via the first bus 140 and the regional bus 210a and temporarily store the decoded data in the write buffer 253. The memory controller 220a can store the decoded data stored in the write buffer 253 in the shared memory 300.

For example, the memory controller 220a may store the decoded data in the packet data area 315 of the first processor allocation area 310 of the shared memory 300.

The write buffer 253 is a buffer used to temporarily store data to be stored in the shared memory 300.

The encryption/decryption module 240a can request the regional direct memory access unit 230a to read the decoded data stored in the shared memory 300. The regional direct memory access unit 230a reads the decoded data from the shared memory 300 according to the request and provides the read data to the encryption/decryption module 240a. In one embodiment, the regional direct memory access unit 230a can detect the address information of the decoded data by referring to the first address descriptor, and read the decoded data according to the address information .

The information for referring to the first address descriptor may be included in the command issued from the first processor 110. For example, the first processor 110 may issue a command including information for referring to the first address descriptor to the regional direct memory access unit 230a. In addition, the first processor 110 may set the information for the reference first address descriptor in a register (for example, a special function register) included in the regional direct memory access unit 230a (not shown in the figure) from.

The decoded data read from the shared memory 300 can be temporarily stored in the read buffer 251.

The read buffer 253 is a buffer used to temporarily store data read from the shared memory 300.

The encryption/decryption module 240a generates decrypted data by decrypting the decoded data received via the regional direct memory access unit 230a. In one embodiment, the encryption/decryption module 240a may include an encryption/decryption accelerator 241 and an encryption/decryption buffer 243. The encryption/decryption accelerator 241 may be implemented as one or more circuits for encrypting unencrypted data and decrypting encrypted data (eg, decoded data). Alternatively, the encryption/decryption accelerator 241 may be implemented as a processor that executes a program that, when executed by the processor, causes the processor to encrypt unencrypted data and to encrypt data (eg, decoded Data) instructions for decryption. The encryption/decryption buffer 243 can temporarily store the input data and/or output data of the encryption/decryption accelerator 241.

The encryption/decryption module 240a may request the area direct memory access unit 230a to store the decrypted data. According to the request, the regional direct memory access unit 230a receives the decrypted data from the encryption/decryption module 240a and stores the decrypted data in the shared memory 300 via the write buffer 253.

In one embodiment, the regional direct memory access unit 230a can detect the information about the address of the decrypted data to be stored by referring to the second address descriptor, and based on the information about the bit The information of the address stores the decrypted data in the shared memory 300.

For example, the local direct memory access unit 230a can store the decrypted data in the socket buffer 323 of the transmission control protocol/Internet protocol data area 321 of the second processor allocation area 320.

The information for referring to the second address descriptor may be included in the command sent from the second processor 130 to the regional direct memory access unit 230a. For example, the second processor 130 may send the information for the reference second address descriptor to the regional direct memory access unit 230a. Alternatively, the second processor 130 may set the information for the reference second address descriptor in a register (not shown in the figure) included in the regional direct memory access unit 230a.

The application processor system chip 103 may include a central processing unit 130a, a graphics processing unit (GPU) 132, a second direct memory access unit 134, and a second bus 150.

The central processing unit 130a controls the overall operation of the application processor system chip 103.

The central processing unit 130a may be implemented as a multi-core processor, for example. The multi-core processor may be a computing component with two or more independent and substantial processing units (referred to as "cores"). Each of the cores can read and execute program instructions.

The central processing unit 130a may correspond to the second processor 130 shown in FIG. 1. As shown in FIG. 3, the central processing unit 130a can be implemented as a system chip (ie, the application processor system chip 103) together with another processor and/or device, but it is not limited to this.

The central processing unit 130a can read and process the decrypted data stored in the shared memory 300. In addition, the central processing unit 130a can generate data to be transmitted through wireless communication (for example, packet data), and store the generated data in the shared memory 300.

The graphics processing unit 132 can read and execute program instructions related to graphics processing. For example, the graphics processing unit 132 can perform graphics-related processing and the like at a high speed.

The second direct memory access unit 134 can store data in shared memory or self-shared memory according to a request from the central processing unit 130a, graphics processing unit 132, or other bus master 136 Read the data.

For example, the second direct memory access unit 134 can read the decrypted data stored in the shared memory 300 or store the packet data generated by the central processing unit 130a in the shared memory according to a request from the central processing unit 130abody300middle.

FIG. 4 is a diagram specifically illustrating a multi-processor system 10b according to at least another exemplary embodiment of the inventive concept. The multi-processor system 10b shown in FIG. 4 is substantially the same as the multi-processor system 10a shown in FIG. 3 in terms of its structure and operation. Differences between processor systems 10a.

3 and 4, the multi-processor system 10b includes a system chip 100b and a shared memory 300.

The system chip 100b includes a connectivity processor system chip 101, an application processor system chip 103, and a shared memory interface circuit 200b.

The shared memory interface circuit 200b may include a regional bus 210b, a memory controller 220b, a regional direct memory access unit 230b, and an encryption/decryption module 240b.

In the embodiment shown in FIG. 3, the regional direct memory access unit 230a and the encryption/decryption module 240a are located in the memory controller 220a at the rear end of the regional bus 210a. However, in the embodiment shown in FIG. 4 Among them, the regional direct memory access unit 230b and the encryption/decryption module 240b are located at the front end of the regional bus 210b.

The area bus 210 b can be connected to the first bus 140 and the second bus 150.

For example, the regional bus 210b and the first bus 140 can support data exchange between the first processor 110 (for example, the modem processor 110a) and the memory controller 220b together with the second bus 150. Together, it supports data exchange between the second processor 130 (for example, the central processing unit 130a) and the memory controller 220b.

The memory controller 220b may include a read buffer 251 and a write buffer 253.

The memory controller 220b can receive the decoded data from the first direct memory access unit 116 via the first bus 140 and the regional bus 210b, and temporarily store the decoded data in the write buffer 253. The memory controller 220b can store the decoded data stored in the write buffer 253 in the shared memory 300.

The encryption/decryption module 240b can request the regional direct memory access unit 230b to read the decoded data stored in the shared memory 300. The regional direct memory access unit 230b reads the decoded data from the shared memory 300 according to the request and provides the decoded data to the encryption/decryption module 240b.

In this embodiment, the decoded data read from the shared memory 300 can be temporarily stored in the read buffer 251, and stored in the direct memory included in the direct memory access unit 230b via the regional bus 210b. The memory access buffer 231 is transmitted and stored in the encryption/decryption buffer 243 included in the encryption/decryption module 240b.

The encryption/decryption accelerator 241 generates decrypted data by decrypting the decoded data stored in the encryption/decryption buffer 243 included in the encryption/decryption module 240b.

The encryption/decryption module 240b may request the regional direct memory access unit 230b to store the decrypted data. The regional direct memory access unit 230b receives the decrypted data from the encryption/decryption module 240b according to the request and stores the decrypted data in the shared memory 300.

In at least one exemplary embodiment, the encryption/decryption accelerator 241 may store the decrypted data in the encryption/decryption buffer 243 included in the encryption/decryption module 240b. The decrypted data can be sent from the encryption/decryption buffer 243 to the direct memory access buffer 231 of the regional direct memory access unit 230b, stored in the direct memory access buffer 231, and passed through the regional bus 210b It is temporarily stored in the write buffer 253 of the memory controller 220b, and then stored in the shared memory 300.

As described above, the path to read the decoded data or the path to store the decrypted data can be directly based on the area included in the shared memory interface circuit 200a, the memory access unit 230a and the encryption/decryption module 240a or the shared memory interface. The regions included in the circuit directly change the positioning of the memory access unit 230b and the encryption/decryption module 240b. However, the functional and operational nature of reading decoded data from the shared memory 300 through the shared memory interface circuit 200a, decrypting the decoded data, and storing the decrypted data in the shared memory 300 The above is the same as the functions and operations of reading decoded data from the shared memory 300 by using the shared memory interface circuit 200b, decrypting the decoded data, and storing the decrypted data in the shared memory 300 .

As described above, according to at least one exemplary embodiment of the inventive concept, the regional direct memory access unit 230a or 230b and the encryption/decryption module 240a or 240b are included in the shared memory interface circuit 200a or 200b. Therefore, when data is transferred from the first processor allocation area 310 of the shared memory 300 to the second processor allocation area 320 of the shared memory 300 or from the second processor allocation area 320 to the first processor allocation area 310 The data is only internally transmitted through the shared memory interface circuit 200 without passing through the bus 140 of the first processor 110 and the bus 150 of the second processor 130. Therefore, when data is exchanged between the first processor 110 and the second processor 130, the number of times the shared memory 300 is accessed can be reduced.

Therefore, the performance (for example, computing speed, etc.) of the multi-processor system can be improved and the power consumption of the multi-processor system can be reduced.

FIG. 5 is a block diagram of a shared memory interface circuit 200c as a modified example of the shared memory interface circuit 200a shown in FIG. 3. 3 and 5, the structure and operation of the shared memory interface circuit 200c are substantially the same as the shared memory interface circuit 200a shown in FIG. The difference between the interface circuit 200c and the shared memory interface circuit 200a.

Compared with the shared memory interface circuit 200 a shown in FIG. 3, the shared memory interface circuit 200 c further includes a system cache 260.

The system cache 260 can store some of the data stored in the shared memory 300. Before reading data from the shared memory 300, the shared memory interface circuit 200c can check whether the data has been stored in the system cache 260.

For example, in order to read decoded data from the shared memory 300 according to a request from the encryption/decryption module 240a, the area direct memory access unit 230a of the shared memory interface circuit 200c may first request the system cache 260 to provide Decoded data. In FIG. 5, reference numeral 215 represents a block including the area direct memory access unit 230a and the encryption/decryption module 240a.

The scenario in which the required data (for example, decoded data) has been stored in the system cache 260 is called a "cache-hit". When a cache hit occurs, the regional direct memory access unit 230a can read the decoded data from the system cache 260 and provide the decoded data to the encryption/decryption module 240a.

The scenario in which the required data (for example, decoded data) is not stored in the system cache 260 is referred to as a "cache-miss". When a cache miss occurs, the regional direct memory access unit 230a can read the decoded data from the shared memory 300 via the memory controller 220c and provide the decoded data to the encryption/decryption module 240a. In this case, the decoded data read from the shared memory 300 can be stored in the system cache 260.

FIG. 6 is a block diagram of a shared memory interface circuit 200d as a modified example of the shared memory interface circuit 200b shown in FIG. 4. 4 and 6, the structure and operation of the shared memory interface circuit 200d are substantially the same as the shared memory interface circuit 200b shown in FIG. The difference between the interface circuit 200d and the shared memory interface circuit 200b.

Compared with the shared memory interface circuit 200b shown in FIG. 4, the shared memory interface circuit 200d further includes a system cache 260.

The system cache 260 is the same as described above with reference to FIG. 5, and therefore it will not be repeated here.

FIG. 7 is a flowchart of a method of operating a multi-processor system according to at least one exemplary embodiment of the inventive concept. FIG. 8 is a diagram illustrating a method of operating a multi-processor system according to at least one exemplary embodiment of the inventive concept. Specifically, FIG. 7 and FIG. 8 illustrate an example of a method for processing downlink data by a multi-processor system according to at least some exemplary embodiments of the inventive concept. The method shown in FIGS. 7 and 8 can be implemented by the multi-processor system 10 shown in FIG. 1, the multi-processor system 10a shown in FIG. 3, or the multi-processor system 10b shown in FIG. 4 .

First, the connection processor (connectivity processor 101) can generate a first address descriptor indicating the location where the downstream data is to be stored (operation S110) and store the first address descriptor in the shared memory interface circuit 200 In the shared memory 300 (operations S115, S120). The connectivity processor 101 may correspond to the first processor 110 shown in FIG. 1 and/or the connectivity processor system chip 101 shown in FIG. 3 or FIG. 4. The first address descriptor may include address information indicating the location in the shared memory 300 where downstream data (for example, decoded data) is to be stored.

For example, the connectivity processor 101 may generate a first address descriptor (operation S110) and request the shared memory interface circuit 200 to store the first address descriptor (operation S115). The shared memory interface circuit 200 may store the first address descriptor in the shared memory 300 according to the request (operation S120).

In one embodiment, as shown in FIG. 8, the first address descriptor may be stored in the address descriptor area 313 of the first processor allocation area 310 of the shared memory 300 (the operation shown in FIG. 8 S13).

Similarly, the application processor (application processor 103) can generate a second address descriptor indicating the location to store the downstream data (operation S125) and store the second address descriptor in the shared memory interface circuit 200 In the shared memory 300 (operations S130 and S135). The application processor 103 may correspond to the second processor 130 shown in FIG. 1 and/or the application processor system chip 103 shown in FIG. 3 or FIG. 4.

The second address descriptor may include address information indicating a location in the shared memory 300 where downstream data (for example, decrypted data) is to be stored.

For example, the application processor 103 may generate a second address descriptor (operation S125) and request the shared memory interface circuit 200 to store the second address descriptor (operation S130). The shared memory interface circuit 200 may store the second address descriptor in the shared memory 300 according to the request (operation S135).

In one embodiment, as shown in FIG. 8, the second address descriptor may be stored in the address descriptor area 325 of the second processor allocation area 320 of the shared memory 300 (the operation shown in FIG. 8 S11).

The connectivity processor 101 receives wireless data through wireless communication, and generates decoded data by modulating and decoding the received wireless data (operation S140). In addition, the connectivity processor 101 can generate packet data (for example, Internet Protocol (IP) packet data) in a predetermined or (alternatively) required format from the decoded data.

The connectivity processor 101 may request the shared memory interface circuit 200 to store the decoded data by transmitting the decoded data to the shared memory interface circuit 200 (operation S145).

For example, the connectivity processor 101 may request the shared memory interface circuit 200 to store the decoded data (operation S145), and the shared memory interface circuit 200 may store the decoded data in response to the request In the shared memory 300 (operation S150).

In one embodiment, as shown in FIG. 8, the connectivity processor 101 may generate Internet Protocol packet data including the decoded data and store the Internet Protocol packet data in the first part of the shared memory 300. In the packet data area 315 of the processor allocation area 310 (operation S14 shown in FIG. 8).

The shared memory interface circuit 200 reads the Internet protocol packet data including the decoded data from the first processor allocation area 310 of the shared memory 300 (operation S155), and performs processing on the Internet protocol packet data Decryption (operation S160). In addition, the shared memory interface circuit 200 stores the decrypted data in the second processor allocation area 320 of the shared memory 300 (operation S165).

For example, as shown in FIG. 8, the shared memory interface circuit 200 may refer to the second address descriptor stored in the address descriptor area 325 of the second processor allocation area 320 to transfer the memory The decrypted data is stored in the socket buffer 323 of the second processor allocation area 320 (operation S15 shown in FIG. 8).

When storing the decrypted data in the socket buffer 323 of the second processor allocation area 320, the application processor 103 may request the shared memory interface circuit 200 to read the decrypted data (operation S170), And the shared memory interface circuit 200 can read the decrypted data from the shared memory 300 in response to the request (operation S175) and provide the decrypted data to the application processor 103 (operation S180). The application processor 103 may process the decrypted data and provide the decrypted data to the user (operation S185).

In one embodiment, before operation S15, the application processor 103 may generate a socket buffer structure for storing the unsealed packet data, and store the socket buffer structure in the second processor allocation area 320 in the transmission control protocol/Internet protocol data area 321.

In one embodiment, when the unsealed packet data is stored in the socket buffer 323 of the second processor allocation area 320, the "end" signal may be stored in the mailbox 350 shown in FIG. 8. In this case, the mailbox 350 can generate an interrupt signal to the application processor 103 (operation S16 shown in FIG. 8). The mailbox 350 may be, for example, a circuit included in a shared memory interface circuit (for example, the shared memory interface circuit 200 and/or 200a-200d).

Then, the application processor 103 can read the decrypted data from the shared memory 300 and process the decrypted data in response to the interrupt signal (operation S17 shown in FIG. 8).

In one embodiment, the operations included in the method of operating a multiprocessor system shown in FIG. 7 and/or FIG. 8 may be performed in an order different from the above-mentioned sequence, and the operations of the method may be performed in parallel At least one of them.

FIG. 9 is a flowchart of a method of operating a multi-processor system according to at least another exemplary embodiment of the inventive concept. FIG. 10 is a diagram illustrating a method of operating a multi-processor system according to at least another exemplary embodiment of the inventive concept. Specifically, FIG. 9 and FIG. 10 illustrate an example of a method for processing uplink data by a multi-processor system according to at least some exemplary embodiments of the inventive concept. The methods shown in FIGS. 9 and 10 can be implemented by the multi-processor system 10 shown in FIG. 1, the multi-processor system 10 a shown in FIG. 3, or the multi-processor system 10 b shown in FIG. 4.

First, the application processor (application processor 103) can generate a third address descriptor indicating the location where the uplink data is to be stored (operation S210), and store the third address descriptor in the shared memory interface circuit 200 via the shared memory interface circuit 200. In the memory 300 (operations S215 and S220). The application processor 103 may correspond to the second processor 130 shown in FIG. 1 or the application processor system chip 103 shown in FIG. 3 or FIG. 4. The third address descriptor may include address information indicating a location in the shared memory 300 where uplink data (for example, packet data generated by the application processor 103) is to be stored.

For example, the application processor 103 may generate a third address descriptor (operation S210) and request the shared memory interface circuit 200 to store the third address descriptor (operation S215), and the shared memory interface circuit 200 may respond to According to the request, the third address descriptor is stored in the shared memory 300 (operation S220).

In one embodiment, as shown in FIG. 10, the third address descriptor may be stored in the address descriptor area 325 of the second processor allocation area 320 of the shared memory 300 (the operation shown in FIG. 10 S21).

Similarly, the connection processor (connectivity processor 101) can generate a fourth address descriptor indicating the location where the uplink data is to be stored (operation S225) and store the fourth address descriptor via the shared memory interface circuit 200 In the shared memory 300 (operations S230 and S235). The connectivity processor 101 may correspond to the first processor 110 shown in FIG. 1 or the connectivity processor system chip 101 shown in FIG. 3 or FIG. 4.

The fourth address descriptor may include address information indicating the location in the shared memory 300 where the upstream data is to be stored.

For example, the connectivity processor 101 may generate a fourth address descriptor (operation S225) and request the shared memory interface circuit 200 to store the fourth address descriptor (operation S230), and the shared memory interface circuit 200 may respond In response to the request, the fourth address descriptor is stored in the shared memory 300 (operation S235).

In one embodiment, as shown in FIG. 10, the fourth address descriptor may be stored in the address descriptor area 313 of the first processor allocation area 310 of the shared memory 300 (the operation shown in FIG. 10 S23).

The application processor 103 generates uplink data to be transmitted through wireless communication (operation S240). In addition, the application processor 103 may generate packet data (for example, Internet Protocol packet data) in a predetermined or (alternatively) required format and including uplink data.

The application processor 103 may request the shared memory interface circuit 200 to store the upstream data by sending the upstream data to the shared memory interface circuit 200 (operation S245).

For example, the application processor 103 may request the shared memory interface circuit 200 to store uplink data (operation S245), and the shared memory interface circuit 200 may store the uplink data in the shared memory 300 in response to the request (operation S245). S250).

In one embodiment, as shown in FIG. 10, the application processor 103 may generate Internet Protocol packet data including uplink data and store the Internet Protocol packet data in the second processor of the shared memory 300 In the socket buffer 323 of the transmission control protocol/Internet protocol data area 321 of the allocation area 320 (operation S22 shown in FIG. 10).

In one embodiment, before operation S22, the application processor 103 may generate a socket buffer structure for storing uplink packet data, and store the socket buffer structure in the second processor allocation area 320 The transmission control protocol/Internet protocol data area 321.

The shared memory interface circuit 200 reads upstream data from the socket buffer 323 of the second processor allocation area 320 of the shared memory 300 (operation S255), and encrypts the upstream data (operation S260).

In addition, the shared memory interface circuit 200 stores the encrypted data in the first processor allocation area 310 of the shared memory 300 (operation S265).

For example, as shown in FIG. 10, the shared memory interface circuit 200 can store the encrypted uplink data in the packet data area 315 of the first processor allocation area 310 by referring to the fourth address descriptor The fourth address descriptor is stored in the address descriptor area 313 of the first processor allocation area 310 (operation S25 shown in FIG. 10).

When storing the encrypted uplink data in the packet data area 315 of the first processor allocation area 310, the connectivity processor 101 may request the shared memory interface circuit 200 to read the encrypted uplink data (operation S270) , And the shared memory interface circuit 200 can read the encrypted uplink data from the shared memory 300 in response to the request (operation S275) and provide the encrypted uplink data to the connectivity processor 101 (operation S280) ). The connectivity processor 101 can convert the encrypted uplink data into wireless data to be transmitted through wireless communication by encoding and modulating the encrypted uplink data (operation S285).

In one embodiment, when the encrypted uplink data is stored in the packet data area 315 of the first processor allocation area 310, the "end" signal may be stored in the mailbox 350 shown in FIG. 10. In this case, the mailbox 350 can generate an interrupt signal to the connectivity processor 101 (operation S26 shown in FIG. 10).

Then, the connectivity processor 101 can read the encrypted uplink data from the shared memory 300 in response to the interrupt signal and convert the encrypted uplink data into wireless data (operation S27 shown in FIG. 10).

FIG. 11 is a block diagram of an electronic system 400 according to at least one exemplary embodiment of the inventive concept.

11, the electronic system 400 may be implemented as a personal computer (PC), a data server, a laptop computer, or a portable device. The portable device may be a mobile phone, a smart phone, a tablet personal computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera (digital still camera), and a digital camera. Video camera (digital video camera), portable multimedia player (PMP), personal navigation device or portable navigation device (PDN), handheld game console, or e-book ).

The electronic system 400 includes a system chip 100, a power supply 410, a storage device 420, a memory 300, an input/output (I/O) port 440, an expansion card 450, a network device 460, and a display 470. In one embodiment, the electronic system 400 may further include a camera module 480.

The system chip 100 can control the operation of at least one of the components 410 to 480. The system chip 100 corresponds to the system chip 100 shown in FIG. 1, the system chip 100a shown in FIG. 3, or the system chip 100b shown in FIG.

The power supply 410 can supply an operating voltage to at least one of the elements 100 and 420-480.

The storage device 420 may be implemented as a hard disk drive or a solid state drive (SSD).

The memory 300 can be implemented as a volatile memory or a non-volatile memory.

The input/output port 440 is a port used to transmit data to the electronic system 400 or transmit data output from the electronic system 400 to an external device. For example, the input/output port 440 may include a port for connecting a pointing device such as a computer mouse to the electronic device 400, a port for connecting a printer to the electronic device 400, and a port for connecting a universal serial bus A universal serial bus (USB) driver is connected to the port of the electronic device 400, etc.

The expansion card 450 may be implemented as a secure digital (SD) card or a multimedia card (MMC). In one embodiment, the expansion card 450 may be a subscriber identity module (SIM) card or a universal subscriber identity module (USIM) card.

The network device 460 is a device used to connect the electronic system 400 to a wired network or a wireless network.

The display 470 can display data output from the storage device 420, the memory 300, the input/output port 440, the expansion card 450, or the network device 460.

The camera module 480 is a module for converting optical images into electrical images (for example, a module that may include at least one lens and at least one image sensor). Therefore, the electrical image output from the camera module 480 can be stored in the storage device 420, the memory 300, or the expansion card 450. In addition, the electrical image output from the camera module 480 can be displayed on the display 420.

FIG. 12 is a schematic diagram illustrating a mobile device 500 according to at least one exemplary embodiment of the inventive concept. Referring to FIG. 12, the mobile device 500 may include the multi-processor system 10 shown in FIG. 1.

The mobile device 500 can be implemented as, but not limited to, a smart phone, a tablet personal computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a mobile internet device (MID), etc.

According to at least one exemplary embodiment of the inventive concept, in a system in which two or more processors share a memory, the memory interface circuit includes a regional direct memory access unit and an encryption and decryption module . Therefore, when data is transmitted from one processor to another processor, the data can only be transmitted internally through the memory interface circuit without passing through the bus of the processor. Therefore, when data is exchanged between processors, the number of times to access the shared memory can be reduced. Therefore, the performance (for example, computing speed, etc.) of the multi-processor system can be improved and the power consumption of the multi-processor system can be reduced.

Since the exemplary embodiments of the inventive concept have been explained, it will be apparent that the exemplary embodiments of the inventive concept can be varied in many ways. Such changes should not be regarded as deviating from the expected spirit and scope of the exemplary embodiments of the concept of the present invention, and as will be obvious to those skilled in the art, all such modifications are intended to be included in the scope of the following patent applications Within range.

<p>10, 10a, 10bMulti-processor system</p><p>100System chip</p><p>100a, 100bsystem chip</p><p>101Connectivity Processor/Connectivity Processor System Chip</p><p>103Application Processor/Application Processor System Chip</p><p>110First processor</p><p>110aModem processor</p><p>112Modulator/demodulator</p><p>114Encoder/Decoder</p><p>116First Direct Memory Access Unit</p><p>122, 130aCentral Processing Unit</p><p>124Digital Signal Processor</p><p>130Second processor</p><p>132Graphics Processing Unit</p><p>134Second Direct Memory Access Unit</p><p>136Bus main controller</p><p>140First bus</p><p>150Second bus</p><p>200, 200a, 200b, 200c, 200dShared memory interface circuit</p><p>210a, 210barea bus</p><p>Block 215</p><p>220a, 220b, 220c, 220dMemory Controller</p><p>230a, 230bRegional Direct Memory Access Unit</p><p>231Direct memory access buffer</p><p>240, 240a, 240bEncryption/Decryption Module</p><p>241Encryption/Decryption Accelerator</p><p>243Encryption/Decryption Buffer</p><p>251Read buffer</p><p>253Write buffer</p><p>260System cache</p><p>300, 300aShared memory</p><p>310First processor allocation area</p><p>311Firmware Zone</p><p>313, 325Address Descriptor Area</p><p>315Packet data area</p><p>320Second processor allocation area</p><p>321Transmission Control Protocol/Internet Protocol Data Area</p><p>323Socket buffer</p><p>330Reserved Area</p><p>350Mailbox</p><p>400Electronic system/electronic device</p><p>410Power</p><p>420Storage device</p><p>440Input/Output Port</p><p>450Expansion card</p><p>460Network Device</p><p>470Display</p><p>480Camera Module</p><p>500Mobile device</p><p>S11, S13, S14, S15, S16, S17, S21, S22, S23, S25, S26, S27, S110, S115, S120, S125, S130, S135, S140, S145, S150, S155, S160, S165, S170, S175, S180, S185, S210, S215, S220, S225, S230, S235, S240, S245, S250, S255, S260, S265, S270, S275, S280, S285Operation</p>

The above and other features and advantages of the exemplary embodiments of the inventive concept will become more apparent by explaining the exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings. The drawings are intended to illustrate exemplary embodiments of the inventive concept and should not be construed as limiting the desired scope of the patent application. Unless clearly noted, the drawings described should not be considered to be drawn to scale.

FIG. 1 is a schematic block diagram of a multi-processor system according to at least one exemplary embodiment of the inventive concept. FIG. 2 is a diagram illustrating the structure of the shared memory shown in FIG. 1 according to at least one exemplary embodiment of the inventive concept. FIG. 3 is a diagram illustrating in detail a multi-processor system according to at least one exemplary embodiment of the inventive concept. FIG. 4 is a diagram illustrating in detail a multi-processor system according to at least another exemplary embodiment of the inventive concept. FIG. 5 is a block diagram of a modified example of the memory interface circuit shown in FIG. 3. FIG. 6 is a block diagram of a modified example of the memory interface circuit shown in FIG. 4. FIG. FIG. 7 is a flowchart of a method of operating a multi-processor system according to at least one exemplary embodiment of the inventive concept. FIG. 8 is a diagram illustrating a method of operating a multi-processor system according to at least one exemplary embodiment of the inventive concept. FIG. 9 is a flowchart of a method of operating a multi-processor system according to at least another exemplary embodiment of the inventive concept. FIG. 10 is a diagram illustrating a method of operating a multi-processor system according to at least another exemplary embodiment of the inventive concept. FIG. 11 is a block diagram of an electronic system according to at least one exemplary embodiment of the inventive concept. FIG. 12 is a schematic diagram illustrating a mobile device according to at least one exemplary embodiment of the inventive concept.

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