Half bridge power conversion circuits using GaN devices

Half-bridge power conversion circuit using gallium nitride device

HALF BRIDGE POWER CONVERSION CIRCUITS USING GaN DEVICES

<b>Cross reference of related applications</b>

This application claims the priority of the following patent applications: U.S. Utility Patent Application No. 14/667,319 regarding "HYBRID HALF-BRIDGE POWER CONVERSION CIRCUITS USING GAN DEVICES" filed on March 24, 2015, and March 2015 U.S. Provisional Patent Application No. 62/127,725 filed on "HALF BRIDGE POWER CONVERSION CIRCUITS USING GAN AND SILICON DEVICES" filed on 3rd, and "HYBRID HALF-BRIDGE DRIVER USING GAN AND" filed on September 16, 2014. SILICON DEVICES" US Provisional Patent Application No. 62/051,160, which is hereby incorporated by reference in its entirety for all purposes.

The present invention relates generally to power conversion circuits and, in particular, to power conversion circuits using one or more GaN-based semiconductor devices.

Electronic devices (such as computers, servers, televisions, and other devices) use one or more power conversion circuits to convert one form of electrical energy into another form of electrical energy. Some power conversion circuits use a circuit topology called a half-bridge converter to convert a high DC voltage to a lower DC voltage. Since many electronic devices are sensitive to the size and efficiency of the power conversion circuit, new half-bridge converter circuits and components may be required to meet the requirements of new electronic devices. Set the demand.

In some embodiments, a half-bridge circuit including a low-side circuit arranged on a first GaN device and a high-side circuit arranged on a second GaN device is disclosed. The low-side circuit includes a low-side switch having a low-side switch control gate and a low-side switch driver having an output connected to the low-side switch control gate. The high-side circuit includes a high-side switch with a high-side control gate and a high-side switch driver with an output connected to the high-side switch control gate.

In some embodiments, the half-bridge circuit may further include a low-side control circuit coupled to the high-side switch driver and the low-side switch driver. In still other embodiments, the level shifter can be configured to couple one or more signals from the low-side control circuit to the high-side switch driver. In other embodiments, the high-side circuit includes a level shift receiver coupled to the level shifter, and the level shift receiver includes a signal modulator coupled to the high-side switch driver .

In some embodiments, the half-bridge circuit includes a level shifter with an inverter. The inverter includes a resistor pull-up transistor and a pull-down transistor. In other embodiments, the half-bridge circuit includes one or more pulse generators and a shoot through protection circuit configured to prevent simultaneous conduction of the high-side and low-side switches. In still other embodiments, at least one of the low-side switch driver and the high-side switch driver has at least one delay circuit. In still other embodiments, the low-side circuit includes a synchronous circuit. In some embodiments, the high-side circuit includes a high-side controller coupled to the high-side switch driver, and the low-side circuit includes a low-side control coupled to the low-side switch driver and the high-side controller Device. In other embodiments, at least one of the low-side circuit and the high-side circuit has an ESD clamp circuit.

In some embodiments, an electronic power conversion component includes a package base, a first die fixed to the package base and including a low-side circuit, fixed to a package base and It includes a second die of a high-side circuit, at least a part of a top surface of the package base encapsulating, and an electrically insulating molding compound of the first die and the second die. In still other embodiments, the low-side circuit may include a low-side switch having a low-side switch control gate and a low-side switch driver having an output connected to the low-side switch control gate. In still other embodiments, the high-side circuit may include a high-side switch having a high-side control gate and a high-side switch driver having an output connected to the high-side switch control gate.

In some embodiments, the package base includes a lead frame. In other embodiments, the assembly may include an insulator mounted to the lead frame, wherein the first die is mounted to the lead frame and the second die is mounted to the insulator. In other embodiments, the package base includes a printed circuit board. In still other embodiments, at least one of the first crystal grain and the second crystal grain includes GaN. In still other embodiments, the component may have at least one electrical connection from the first die to the second die formed in the component.

In some embodiments, a method of operating a half-bridge power conversion circuit includes using a low-side driver to operate a low-side switch, wherein the low-side switch and the low-side driver are disposed on a first GaN device. The method may further include: using a high-side driver to operate a high-side switch, wherein the high-side switch and the high-side driver are disposed on a second GaN device. In still other embodiments, the method may include: controlling the low-side driver and the high-side driver with a control circuit, the control circuit transmitting on and off signals to the low-side driver and the high-side driver. In some embodiments, the method may include: transmitting a control signal from a low-side control circuit to the high-side switch driver through a level shifter. In still other embodiments, the control signals may be received by a level shift receiver, which modulates the control signals and transmits them to the high-side switch driver.

In some embodiments, a level shift circuit including a first GaN-based inverter circuit is disclosed. The inverter circuit may include a first input terminal and a first output terminal And a first inverter circuit coupled between the first input terminal and the first output terminal. The inverter circuit can be configured to receive a first input logic signal at the first input terminal and provide a first inverted output logic signal at the first output terminal in response. In other embodiments, the first input logic signal and the first inverted output logic signal can be referenced to different voltage levels.

In some embodiments, the first inverting circuit is configured to operate with the first inverted output logic signal, the first inverted output logic signal is referenced to a reference voltage higher than the first input logic signal One voltage above 20 volts. In other embodiments, the first inverter circuit includes a first GaN-based enhancement mode transistor, and the first GaN-based enhancement mode transistor has a gate coupled to the first input terminal and coupled to the A drain of the first output terminal and a source coupled to a ground. In still other embodiments, the first inverter circuit further includes a current sink device coupled between the source and the ground.

In some embodiments, the first inverter circuit further includes a pull-up device coupled between the drain and a floating power supply. In other embodiments, the first input logic signal controls the on and off transition of a high-side gate. In one embodiment, there is at least one logic gate configured to prevent simultaneous conduction of the high-side transistor and the low-side transistor. In other embodiments, the first inverted output logic signal at the first output terminal is transmitted to a receiver circuit including a driver circuit configured to deliver more than one of a floating power supply Voltage.

In some embodiments, the level shifting circuit includes an active pull-up device configured to shorten the first input logic signal when the first input logic signal changes from a high state to a low state. It takes a time for an inverted output logic signal to reset to a positive state. In some embodiments, there may be a first capacitor between the first output terminal and a floating voltage and a second capacitor between the first output terminal and ground, wherein the first capacitor Greater than the second capacitance. In other embodiments, a clamp is used to prevent an overvoltage condition on the first output terminal. In one embodiment, measuring a floating supply Voltage signal, and in response, generate a supply voltage logic signal and combine it with the first inverted output logic signal. In other embodiments, the supply voltage logic signal is coupled with a hysteresis inverter.

In some embodiments, the level shift circuit further includes a second GaN-based inverter circuit having a second input terminal and a second output terminal. A second inverter circuit can be coupled between the second input terminal and the second output terminal and is configured to receive a second input logic signal at the second input terminal, and in response, at the second input terminal A second inverted output logic signal is provided at the output terminal. In still other embodiments, the second inverter circuit includes a second GaN-based enhancement mode transistor, the second GaN-based enhancement mode transistor having a gate coupled to the second input terminal, coupled to A drain of the second output terminal and a source coupled to the ground. In still other embodiments, the first input logic signal is received from a level shift driver and the second input logic signal is received from a pulse generator. In one embodiment, the second inverted output logic signal is transmitted to a circuit that is configured to prevent one of the first inverted output logic signals from changing.

In some embodiments, an electronic power conversion device including a package base and one or more GaN-based dies fixed to the package base is disclosed. The one or more GaN-based dies may include a first GaN-based inverter circuit including a first input terminal and a first output terminal. A first inverter circuit can be coupled between the first input terminal and the first output terminal and is configured to receive a first input logic signal at the first input terminal and in response, at the first output A first inverted output logic signal is provided at the terminal. In still other embodiments, the first input and the first inverted output logic signal can be referenced to different voltage levels.

In some embodiments, the first inverting circuit is configured to operate with the first inverted output logic signal, the first inverted output logic signal is referenced to a reference voltage higher than the first input logic signal One voltage above 20 volts. In other embodiments, the first inverter circuit includes a first GaN-based enhancement mode transistor, and the first GaN-based enhancement transistor The strong transistor has a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground.

In some embodiments, a method of operating a GaN-based level shift circuit is disclosed. The method may include: transmitting a first input logic signal to a first input terminal and in response, a first inverter circuit provides an inverted first output logic signal on a first output terminal to control a power circuit One of the gates of the crystal. In one embodiment, the first input logic signal and the inverted first output logic signals are referenced to different voltages.

In some embodiments, a level shift circuit including a first inverter circuit and a second inverter circuit is disclosed. The first inverter circuit may include a first input terminal, a first output terminal, and a first GaN-based enhancement mode transistor. The first GaN-based enhancement mode transistor has a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground. The second inverter circuit may have a second input terminal, a second output terminal, and a second GaN-based enhancement mode transistor. The second GaN-based enhancement mode transistor has a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground.

In some embodiments, the first input terminal and the second input terminal are referenced to a first voltage that is grounded, and the first output terminal and the second output terminal are referenced to a potential that is different from ground. A second voltage. In one embodiment, the first inverter circuit further includes a pull-up device coupled between the drain and a floating power supply. In other embodiments, a first capacitor is coupled between the first output terminal and a floating voltage and a second capacitor is coupled between the first output terminal and ground, wherein the first capacitor is larger than the second capacitor .

In some embodiments, a clamp is used to prevent an overvoltage condition on the first output terminal. In still other embodiments, the first inverter circuit input terminal is configured to receive a first pulse input signal from a first pulse generator and the second inverter circuit input terminal is configured to receive a first pulse input signal from a first pulse generator. The second pulse generator receives a second pulse input signal. In a In one embodiment, at least one of the first pulse generator and the second pulse generator is configured to receive input pulses in a range of 2 nanoseconds to 20 microseconds and transmit substantially within the range A pulse of constant duration on the upper limit. In still other embodiments, at least one of the first pulse generator and the second pulse generator includes at least one combinational logic function.

In some embodiments, the input signals from the first pulse generator and the second pulse generator correspond to the pulse width modulation (PWM) signal for controlling one of the gates of a high-side transistor Switch on and off. In still other embodiments, the level shift circuit further includes a latch memory logic circuit configured to change in response to a first pulse input signal from the first pulse generator The state changes in response to a second pulse input signal from the second pulse generator. In one embodiment, the first pulse input signal and the second pulse input signal from the first pulse generator and the second pulse generator respectively correspond to the on and off transitions of a PWM signal to control The gate of a high-side transistor. In still other embodiments, at least one of the first pulse generator and the second pulse generator is coupled with one or more logic gates. In other embodiments, the level shift circuit is further configured to generate a logical combination of at least one PWM signal and at least one pulse generator output signal, wherein the logical combination is used to prevent a high-side switch and a low-side switch The switches are turned on at the same time.

In some embodiments, an on-level shift pulse is shortened by an off input pulse to achieve an on-time of less than 50 nanoseconds on a high-side switch. In one embodiment, a turn-off level shift pulse can be shortened by a turn-on input pulse to achieve a turn-off time of less than 50 nanometers on a high-side switch. In other embodiments, the first output terminal is coupled to a circuit configured to charge a state storage capacitor that is referenced to the second voltage. In still other embodiments, the second output terminal is coupled to a circuit configured to discharge a state storage capacitor that is referenced to the second voltage. In still other embodiments, an output signal from one of the first output terminal or the second output terminal prevents a signal from one of the other output terminals One of dv/dt induces changes.

In some embodiments, an electronic power conversion device includes a package base and one or more GaN-based dies fixed to the package base. The one or more GaN-based dies include a first inverter circuit including a first input terminal and a first output terminal. A first GaN-based enhancement mode transistor has a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground. The one or more GaN-based dies include a second inverter circuit including a second input terminal and a second output terminal. A second GaN-based enhancement mode transistor has a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground.

In some embodiments, a method of operating a GaN-based level shift circuit is disclosed. The method includes generating a first pulse with a first pulse generator, the first pulse operation being configured to change a state of a state storage device, a first inverter circuit. The method further includes generating a second pulse with a second pulse generator, the second pulse operation being configured to change a state of a second inverter circuit of the state storage device.

In certain embodiments, a charging circuit including a GaN-based semiconductor circuit is disclosed that is configured to allow unidirectional current flow from a ground-referenced power supply to a floating power supply terminal . In one embodiment, the semiconductor circuit is configured to operate with the floating power supply terminal at a voltage that is 20 volts or greater than a voltage of the ground-referenced power supply. In still other embodiments, the semiconductor circuit includes at least one of the following: a Schottky diode, an enhanced transistor, or a depleted transistor. In still other embodiments, the semiconductor circuit includes an enhanced transistor including a gate and a source connected to a common voltage potential.

In some embodiments, the drain of the enhanced transistor is connected to the floating power supply terminal. In one embodiment, the semiconductor circuit includes an enhanced transistor, and the enhanced transistor The strong electric crystal includes a gate controlled by a gate drive circuit. In other embodiments, the drain of the enhanced transistor is connected to the floating power supply terminal. In still other embodiments, the enhanced transistor includes a source and a drain connected to a depletion type transistor and a drain of the depletion type transistor is connected to the floating power supply terminal. In still other embodiments, a gate of the depletion transistor is connected to the ground-referenced power supply.

In some embodiments, one of the depletion transistors is connected to ground. In one embodiment, the semiconductor circuit is used in conjunction with a half-bridge circuit. The half-bridge circuit includes: a low-side GaN-based transistor having a low-side GaN-based transistor configured to receive a ground-referenced gate drive circuit The gate signal is a low-side transistor that controls the gate; a high-side GaN-based transistor that has a high-side transistor that controls the gate is configured to self-reference to a gate of a second floating power supply terminal The pole drive circuit receives a high-side gate signal. In still other embodiments, the second floating power supply terminal is a switching node of the half-bridge circuit. In still other embodiments, a capacitor is connected between the floating power supply terminal and the second floating power supply terminal.

In some embodiments, the semiconductor circuit includes an enhanced transistor including a gate controlled by a gate drive circuit and the gate drive circuit is configured so that it provides one of the same phases as the low-side gate signal The output voltage. In still other embodiments, a delay circuit is configured to turn on the enhancement mode transistor after the low-side GaN-based transistor is turned on. In still other embodiments, a delay circuit is configured to turn off the enhancement mode transistor before the low-side GaN-based transistor turns off.

In some embodiments, an electronic power conversion device includes a package base and one or more GaN-based dies fixed to the package base including a charging circuit. In still other embodiments, the charging circuit includes a GaN-based semiconductor circuit configured to allow unidirectional current flow from a ground-referenced power supply to a floating power supply terminal. In some embodiments, the semiconductor circuit includes at least one of the following: a Schottky diode, an enhanced transistor, and a depleted transistor. In some other embodiments Wherein, the semiconductor circuit includes an enhanced transistor having a source and a drain connected to a depletion type transistor, wherein a drain of the depletion type transistor is connected to the floating power supply terminal.

In some embodiments, a method of operating a GaN-based charging circuit is disclosed. The method includes: supplying power to a first terminal of a GaN-based semiconductor circuit by means of a ground-referenced power supply. Current is allowed to flow through the GaN-based semiconductor circuit only in one direction from the first terminal to a second terminal, and the second terminal is a floating power supply.

In some embodiments, a power supply circuit is disclosed that includes a GaN-based depletion transistor used as one of a voltage-limited voltage source or a voltage-limited current source. In one embodiment, the depletion transistor is used in a reference circuit to set a reference voltage and includes a first drain coupled to a power source and a first source coupled to a first node. In another embodiment, a first gate of the depletion transistor is connected to ground. In another embodiment, a first gate of the depletion type transistor is formed by a metal layer disposed above a passivation layer. In still other embodiments, the depletion transistor is mounted on a GaN-based power integrated circuit device.

In some embodiments, the power supply circuit further includes a plurality of series-connected circuit elements coupled between the first node and the second node, and one of the plurality of series-connected circuit elements is arranged in each of the plurality of series-connected circuit elements. One or more intermediate nodes between. In one embodiment, the power supply circuit further includes a GaN-based reference voltage transistor having one of the second gates connected to one of the one or more intermediate nodes, and is configured to transfer the power Delivered to a second source of a circuit and connected to a second drain of a power source. In still other embodiments, the GaN-based reference voltage transistor includes one or more diodes arranged between the second gate and the second source and configured as a gate overvoltage protection device. The diode is connected to the transistor.

In some embodiments, the power supply circuit further includes configuration to prevent second The source delivers power to a deactivated circuit of a circuit. In one embodiment, the reference voltage transistor system is an enhancement mode transistor based on GaN. In another embodiment, the power supply circuit is configured as a ground-referenced power supply in a half-bridge circuit. In still other embodiments, the second node is connected to ground. In another embodiment, a capacitor is connected between the first node and the second node. In still other embodiments, at least one of the first node and the second node is connected to a capacitor. In other embodiments, a diode or a diode-connected transistor is coupled between the first node and a circuit configured to deliver the circuit.

In some embodiments, the power supply includes a floating voltage. In another embodiment, the reference circuit is configured to only supply power when the power source is within a predetermined range. In still other embodiments, the power supply has a constantly changing voltage. In still other embodiments, the power source is an AC line voltage. In other embodiments, the power supply circuit further includes: a third enhanced transistor having a third gate, a third source, and a third drain; and a fourth enhanced transistor, It has a fourth gate, a fourth source and a fourth drain. The third source and the fourth source are coupled to a third node, the third gate and the fourth gate are coupled together, the third drain is coupled to the second node, and the fourth drain is coupled To a reference current tank terminal. In some embodiments, the power supply circuit further includes a comparator circuit coupled to a ground reference power supply and the reference current sink terminal.

In some embodiments, an electronic power conversion component is disclosed that includes a package base having one or more GaN-based dies fixed to the package base and including a power supply circuit. In one embodiment, a GaN-based depletion transistor is used as one of a voltage-limited voltage source or a voltage-limited current source.

In some embodiments, a method of operating a GaN-based power supply circuit is disclosed. The method includes: supplying power to a drain terminal of a GaN-based depletion type device, the GaN-based depletion type device having a first gate connected to ground and connected to one or more series-connected circuit elements A first source, the one or more circuits connected in series The element includes one or more intermediate nodes between each of the plurality of serially connected circuit elements. The method further includes: delivering power from a second source of a GaN-based enhancement mode device to one or more circuits, the GaN-based enhancement mode device having a device coupled to one of the one or more intermediate nodes A second gate and a second drain connected to a power source.

In some embodiments, a semiconductor device including a level shift transistor is disclosed. The level shift transistor has a ratio of output saturation current (Idsat) to output capacitor charge (Qoss) greater than 1A/nc . In one embodiment, the level shift transistor is based on GaN. In another embodiment, the level shift transistor has an output charge (Qoss) less than 25 pC. In still other embodiments, the level shifting transistor system operates with a pulse input signal. In still other embodiments, one of the pulse input signals has a duration of less than 100 ns. In some embodiments, a channel width of the level shift transistor is less than 100 microns. In still other embodiments, a drain structure of the level shift transistor is placed less than 100 microns from a bonding pad.

In some embodiments, the level shift transistor includes a source ohmic contact region connected to a source terminal, and the source terminal is connected to a metal pad that is immediately adjacent to the source terminal and It is more than 100 times that of the source ohmic contact area. In other embodiments, the level shift transistor includes a drain ohmic contact region connected to a drain terminal and the drain terminal is connected to a metal pad that is immediately adjacent to the drain terminal and is The drain ohmic contact area is more than 100 times. In still other embodiments, the level shift transistor includes a source region and a drain region, and the source region does not surround the drain region. In still other embodiments, the level shift transistor includes an active region having a source region at a first end and a drain region at an opposite end.

In some embodiments, a level shift circuit including an input referenced to ground and an output referenced to a floating voltage is disclosed. The circuit is configured to be integrated on at least one GaN device. In some embodiments, the level shift circuit includes a level greater than The ratio of 1A/nc is one of Idsat to Qoss. In other embodiments, the level shift circuit includes a first capacitor between the output and the floating voltage, wherein the first capacitor is configured to prevent the floating voltage from changing the voltage potential from ground to One of the output states changes at a maximum allowable voltage. In other embodiments, the level shift circuit includes a conductive circuit element coupled between a source of the level shift transistor and the base.

In some embodiments, the level shift circuit includes a conductive circuit element coupled between a drain of the level shift transistor and a reference of a power source to a positive side of the floating voltage. In still other embodiments, the level shift circuit includes a first circuit part disposed on a first GaN device and a second circuit part disposed on a second GaN device. In some embodiments, the first circuit part includes the output and the second circuit part includes a receiver circuit, and a bonding wire forms an electrical connection between the output and the receiver circuit.

In some embodiments, the level shift circuit includes at least one output terminal bonding pad, and the at least one output terminal bonding pad has a conductive shield underneath that is referenced to the floating voltage. In other embodiments, at least one level shift transistor and all ground reference circuit components are arranged on the first GaN device. In one embodiment, the level shift circuit includes a low-side power switch disposed on the first GaN device. In still other embodiments, the second circuit part includes a conductive circuit element coupled between a drain of a level shift transistor and a reference of a power source to a positive side of the floating voltage. In still other embodiments, the level shift circuit includes a high-side power switch integrated on the same device.

In some embodiments, a circuit including overvoltage protection is disclosed. The circuit includes a first pin and a second pin, and an overvoltage protection circuit includes a first pin that is arranged on a GaN-based substrate and coupled between the first pin and the second pin. Enhanced transistor. In some embodiments, the overvoltage protection circuit does not contain a depletion transistor. In still other embodiments, the over-voltage protection circuit includes The strong transistor has a gate, a source, and a second enhanced transistor, and a conductive element coupled to an electrical path between the source and the second pin. The conductive element includes one of a resistor, a depletion transistor, a reference current tank or a reference current source.

In some embodiments, the overvoltage protection circuit includes a second enhanced transistor having a gate and a source coupled to a third enhanced transistor. A conductive element is coupled in an electrical path between the source electrode and the gate electrode. The conductive element includes one of a resistor, a depletion transistor, a reference current tank or a reference current source. In still other embodiments, the first pin is the gate of a power transistor and the second pin is the source of the power transistor. In one embodiment, the overvoltage protection circuit is coupled between a power supply terminal and ground.

In some embodiments, the over-voltage protection circuit is configured to remain in an off state until the voltage potential across one of the first pin and the second pin exceeds a predetermined voltage level. In still other embodiments, the first enhanced transistor has a first source coupled to the first pin and a first drain coupled to the second pin. The first enhanced transistor is configured to provide overvoltage protection between the first pin and the second pin. In one embodiment, a first gate of the first enhancement mode transistor is coupled to the first source and the first enhancement mode transistor is configured to remain in an off state until it undergoes a Until the voltage pulse. In some embodiments, one or more diodes or diode-connected transistors are connected in series and coupled to a gate of the first enhancement mode transistor, configured to drive the first enhancement mode transistor.

In some embodiments, the first enhanced transistor is configured to conduct a current greater than 500 mA when exposed to an overvoltage pulse. In one embodiment, the over-voltage protection circuit includes second and third enhanced transistors. A third source of the third enhancement mode transistor is connected to a second gate of the second enhancement mode transistor, and a second source of the second enhancement mode transistor is connected to the first enhancement mode The first gate of one of the transistors. In still other embodiments, a disabling circuit is configured to target less than 1V/ns at the first pin or the A predetermined dv/dt value occurring at the second pin prevents current flow between the first pin and the second pin. In still other embodiments, the disabling circuit includes a dv/dt detection filter coupled to the first gate of the first enhancement mode transistor.

In some embodiments, the dv/dt detection filter includes at least one GaN-based logic circuit. In one embodiment, the first enhancement mode transistor is connected in series with a source of a depletion mode transistor. A drain of the depletion transistor is connected to the first pin, and the first source is connected to the second pin. In other embodiments, the overvoltage protection circuit includes a second enhanced transistor connected in parallel with the first enhanced transistor. The overvoltage protection circuit is configured to provide symmetrical overvoltage protection for the circuit when exposed to positive or negative overvoltage conditions. In still other embodiments, the overvoltage protection circuit includes a second enhanced transistor connected in series with the first enhanced transistor, and the overvoltage protection circuit is configured to be exposed to positive or negative overvoltage conditions. Provide symmetrical over-voltage protection for the circuit.

In some embodiments, an ESD protection circuit including a GaN-based circuit with one of two pins is disclosed. A first enhanced transistor is coupled between the two pins and has a first gate. A dv/dt detection filter is coupled to the gate and configured to realize the two pins when one of the dv/dt on at least one of the two pins is greater than a value of 1V/ns The current flows between. In some embodiments, the ESD protection circuit further includes an overvoltage protection circuit that includes a voltage coupled between the two pins and configured to be between the two pins An enhanced transistor that temporarily conducts current between the two pins when the potential exceeds a predetermined level.

In some embodiments, an electronic power conversion device including a package base and one or more GaN-based dies fixed to the package base is disclosed. The one or more GaN-based dies include a first circuit including at least one enhanced transistor and an overvoltage protection circuit coupled to the first circuit.

In some embodiments, one method of operating a GaN-based circuit is disclosed. The method includes: receiving a voltage potential exceeding a predetermined value across two pins of a circuit, and connecting A GaN-based enhancement mode transistor is connected between the two pins. The enhanced transistor temporarily conducts current between the two pins when the voltage potential is higher than the predetermined value. In some embodiments, the method further includes: receiving a dv/dt signal greater than 1V/ns on at least one of the two pins, and in response, turning on a second GaN-based enhancement mode Transistor, so that current can flow between the two pins.

In some embodiments, an electronic circuit including a substrate is disclosed, the substrate including GaN. A power switch is formed on the substrate and includes a first control gate and a first source. A driving circuit is formed on the substrate and includes an output coupled to the first gate. A power supply has a maximum voltage and is coupled to the driving circuit, wherein the output can be driven to the maximum voltage. In still other embodiments, the driving circuit is coupled to at least one power supply and an input, and the at least one power supply and the input are all referenced to the first source. In some embodiments, the driver circuit is coupled to exactly one PWM input. In other embodiments, the driving circuit includes at least one enhanced transistor, at least one current conducting element, and does not include any depleted transistor.

In some embodiments, the driving circuit includes an inverter including a first enhancement mode transistor, the first enhancement mode transistor having a second gate connected to a first input signal, connected to the The first source is a second source and a second drain. A second enhanced transistor has a third drain connected to the power supply, a third source connected to the second drain, and a third gate connected to a circuit. The circuit is assembled State to generate a voltage higher than the power supply. In one embodiment, the voltage of a capacitive element moves up and down synchronously with the third source and supplies power to the third gate. In some embodiments, a rectifying element is configured to supply power to the capacitive element and prevent the capacitive element from discharging when a terminal of the capacitive element rises above a voltage on the power supply.

In some embodiments, the second enhanced transistor can be turned on in less than 100 nanoseconds. In one embodiment, a third enhanced transistor has a fourth gate connected to the first input signal, a fourth drain connected to the third gate, and a fourth drain connected to the first source One of the fourth source. In other embodiments, a current limiting element is arranged in a current conduction path from the power supply to the first source. The current conduction path includes a rectifying element, a current limiting element, and one of the third enhanced transistors connected in series. In still other embodiments, a resistor is placed between the first input signal and the control gate. In still other embodiments, the driving circuit includes two inverters connected in series to form a non-inverting buffer circuit. In one embodiment, the driving circuit includes at least one buffer circuit. In other embodiments, the driving circuit is coupled with a gate of a fourth enhanced transistor, and the fourth enhanced transistor has a fifth drain connected to the control gate and a fifth drain connected to the first source One of the fifth source. Further embodiments include an electrostatic discharge protection circuit.

In some embodiments, an electronic component is disclosed that includes a package base having at least one GaN-based die fixed to the package base and including an electronic circuit. A power switch is formed on the at least one GaN-based die and includes a first control gate and a first source. A driving circuit is formed on the at least one GaN-based die and includes an output coupled to the control gate. A power supply with a maximum voltage is coupled to the driving circuit, wherein the output can be driven to the maximum voltage. In one embodiment, the driving circuit is coupled to at least one power supply and an input, and the at least one power supply and the input are referenced to the first source. In another embodiment, the drive circuit is coupled to exactly one PWM input.

In some embodiments, the driving circuit further includes at least one enhanced transistor, at least one current conducting element, and does not include any depleted transistor.

In some embodiments, a method of operating a GaN-based circuit is disclosed. The method includes: receiving a signal with a driving circuit and processing the signal with the driving circuit. A signal is transmitted to a control gate of a switch and the driving circuit and the switch are arranged on a single GaN substrate. The driving circuit includes at least one enhanced transistor, at least one current conducting element, and does not include any depleted transistor.

<p>100Circuit/Integrated Half-Bridge Power Conversion Circuit</p><p>103Low-side GaN device/Low-side device</p><p>104GaN-based low-side circuit/low-side circuit</p><p>105High-side GaN device/High-side device</p><p>106GaN-based high-side circuit/high-side circuit</p><p>107Load</p><p>110Bootstrap capacitor</p><p>115Low-Side Power Transistor/Low-Side Transistor</p><p>117Low-side transistor control gate</p><p>120Integrated low-side transistor driver</p><p>123output</p><p>125High-Side Power Transistor/High-Side Transistor</p><p>127High-side control gate</p><p>130Integrated high-side transistor driver</p><p>133output</p><p>135Voltage source</p><p>137Dip pole</p><p>140Source</p><p>143Dip pole</p><p>145Switch Node</p><p>147Source</p><p>150Level shift circuit/low-side control circuit</p><p>153Control circuit</p><p>155Starting circuit</p><p>157Bootstrap capacitor charging circuit</p><p>160Shielding capacitor</p><p>161Clamper circuit</p><p>203The first level shift transistor</p><p>205The second level shift transistor</p><p>207First level shift resistor</p><p>210Source</p><p>213Gate</p><p>215Dip pole</p><p>217Level shift driver circuit</p><p>223Blanking Pulse Generator</p><p>225Bootstrap transistor drive circuit</p><p>227Undervoltage lockout circuit</p><p>303Pull-up resistor</p><p>305First level shift node/first output terminal/output terminal</p><p>505First-stage inverter</p><p>510RC Pulse Generator</p><p>515Capacitor</p><p>520Resistor</p><p>525Second inverter</p><p>530Third inverter</p><p>535Buffer</p><p>600Waveform</p><p>605Trace</p><p>610Trace</p><p>615trace</p><p>620trace</p><p>705series delay resistor</p><p>730Inverter</p><p>735First buffer</p><p>805First inverter</p><p>810Buffer</p><p>815Second inverter</p><p>820Second buffer</p><p>825Third buffer/final buffer stage</p><p>830Delay resistor</p><p>840Resistive divider</p><p>850Transistor pull-down</p><p>905Depleted Transistor</p><p>906Gate</p><p>907Source</p><p>909Dip pole</p><p>910Enhanced Low Voltage Transistor</p><p>911First node</p><p>912Second Node/Second Junction</p><p>913Intermediate node</p><p>915Current Mirror</p><p>920First current mirror transistor</p><p>925Second current mirror transistor</p><p>930Starting Transistor</p><p>935Disable Transistor/Disable Pull-down Transistor</p><p>940Pull-down resistor</p><p>945Diode clamp</p><p>955Reference Voltage Transistor</p><p>1050Enhanced transistor based on GaN</p><p>1105Differential comparator</p><p>1110Down level shifter</p><p>1115Inverter</p><p>1120Voltage (VA)</p><p>1125Voltage (VB)</p><p>1205High voltage diode connection enhanced transistor/high voltage bootstrap diode/bootstrap diode</p><p>1210High Voltage Bootstrap Transistor/Transistor/Bootstrap Transistor</p><p>1300Bootstrap diode and transistor circuit</p><p>1305Depleted device</p><p>1310Enhanced device</p><p>1410The first level shift receiver</p><p>1415High-side undervoltage lockout circuit</p><p>1420The second level shift receiver</p><p>1425Pull-up trigger circuit</p><p>1430Pull-up resistor</p><p>1435Pull-up Transistor</p><p>1440Blanking Transistor</p><p>1505Enhanced Transistor</p><p>1510Enhanced Transistor</p><p>1515Enhanced Transistor/Transistor/Source Follower Transistor</p><p>1520Triode connected to transistor clamp/clamp</p><p>1605Down level shift circuit</p><p>1610Inverter circuit</p><p>1615Enhanced Transistor</p><p>1620Diode connected to transistor clamp/clamp</p><p>1705First inverter</p><p>1710Second inverter</p><p>1715RC Pulse Generator</p><p>1720Gate-to-source clamp</p><p>1805Down Level Shifter</p><p>1810Resistor pull-up inverter/inverter</p><p>1815Gate-to-source clamp</p><p>1905First inverter stage</p><p>1910High-side driver stage</p><p>2000Reference voltage generating circuit/circuit</p><p>2005Depleted Transistor</p><p>2010Source Follower Capacitor</p><p>2011The first node</p><p>2012Second node</p><p>2015Reference Voltage Capacitor</p><p>2020Enhanced Low Voltage Transistor</p><p>2025High voltage diode connected to transistor</p><p>2055Reference Voltage Transistor</p><p>2100Half-bridge circuit/circuit/integrated half-bridge power conversion circuit</p><p>2103Low-side GaN device/Low-side device</p><p>2105High-side GaN device/High-side device</p><p>2107Load</p><p>2110Bootstrap capacitor</p><p>2115Low-side transistor</p><p>2117Low-side control gate/low-side transistor control gate</p><p>2120Integrated low-side transistor driver</p><p>2123output</p><p>2125High-Side Transistor</p><p>2127High-side control gate/High-side transistor control gate</p><p>2130Integrated high-side transistor driver</p><p>2133Output</p><p>2135Voltage source</p><p>2137Dip pole</p><p>2140Source</p><p>2143Dip pole</p><p>2145Switch Node</p><p>2147Source</p><p>2150Level shift circuit/low-side control circuit</p><p>2153Control circuit</p><p>2155Starting circuit</p><p>2157Bootstrap capacitor charging circuit</p><p>2160shielded capacitor</p><p>2203The first level shift transistor</p><p>2207First resistor</p><p>2208Second resistor</p><p>2215The second level shift transistor</p><p>2220Low-side drive circuit/low-side transistor drive circuit</p><p>2223Blanking Pulse Generator</p><p>2225High-Side Transistor/Bootstrap Transistor Drive Circuit</p><p>2227Undervoltage lockout circuit</p><p>2250Inverter/Buffer/Inverter/Buffer Circuit</p><p>2260Turn on the pulse generator</p><p>2270Turn off the pulse generator</p><p>2275Inverter</p><p>2303Pull-up resistor</p><p>2305First output terminal</p><p>2405First inverter stage</p><p>2410First buffer stage</p><p>2505First inverter stage</p><p>2510First buffer stage</p><p>2515RC pulse generator</p><p>2520Second inverter stage</p><p>2525Third inverter stage</p><p>2530Third buffer stage</p><p>2603RC Pulse Generator</p><p>2605First inverter stage</p><p>2610Second inverter stage</p><p>2615First buffer stage</p><p>2805First inverter stage</p><p>2810First buffer stage</p><p>2815Second inverter stage</p><p>2820Second buffer stage</p><p>2825Third buffer stage</p><p>2910Level Shift 1 Receiver Circuit/Level Shift 1 Receiver</p><p>2915High-side undervoltage lockout circuit</p><p>2920Level Shift 2 Receiver Circuit</p><p>2940Blanking Transistor</p><p>2955State storage capacitor</p><p>2960Pull-up Transistor</p><p>2965Pull-down transistor</p><p>2970First shielding capacitor</p><p>2975Second Shielding Capacitor</p><p>3005Down level shifter</p><p>3010First inverter</p><p>3015Second inverter</p><p>3020First buffer</p><p>3025Third inverter</p><p>3030Second buffer</p><p>3105Blanking Pulse Generator</p><p>3110Down Level Shifter</p><p>3115First inverter</p><p>3120Second inverter</p><p>3120First buffer</p><p>3130Third inverter</p><p>3135Third buffer</p><p>3140Third buffer</p><p>3205Down Level Shifter</p><p>3210Resistor pull-up inverter stage</p><p>3305First inverter</p><p>3310First buffer</p><p>3315Second inverter</p><p>3320Second buffer</p><p>3325Third buffer</p><p>3400Electrostatic discharge clamp circuit</p><p>3405Source Follower Stage</p><p>3406Gate</p><p>3407Source</p><p>3408Dip pole</p><p>3410Final resistor</p><p>3415Electrostatic Discharge Transistor</p><p>3420Source</p><p>3425Dip pole</p><p>3430Gate</p><p>3500Electrostatic discharge clamp circuit</p><p>3505Source Follower Stage</p><p>3506Gate</p><p>3507Source</p><p>3508Dip pole</p><p>3510Resistor</p><p>3515Electrostatic Discharge Transistor</p><p>3520Source</p><p>3525Dip pole</p><p>3600Electronic Packaging</p><p>3610Package base</p><p>3615Die Mat/First Die Mat</p><p>3620Terminal/First device</p><p>3625Second device</p><p>3627Second die pad/die pad</p><p>3630Wire Bonding</p><p>3635Device bonding pad</p><p>3640Terminal</p><p>3705Non-conductive material</p><p>B_PULSEBlanking pulse signal/Blanking pulse input</p><p>BLANK_FETsignal</p><p>BOOTFET_DRGate drive signal/signal</p><p>HS_GATE signal</p><p>HS_UVLO</p><p>IrefReference Current/Reference Current Tank</p><p>INVSignal</p><p>L1_DRHigh gate signal/signal</p><p>L2_DR signal</p><p>LS_GATEGate signal/signal</p><p>LS_HSGsignal</p><p>LS_NODEFirst output terminal</p><p>LS_UVLOLow-side undervoltage lockout signal/signal</p><p>L_SHIFT1Signal/node voltage</p><p>L_SHIFT2Signal/node voltage</p><p>PD_FETsignal</p><p>PU_FET signal</p><p>PULLUP_FETsignal</p><p>PULSE_OFFInput signal/Turn off pulse signal</p><p>PULSE_ONInput signal</p><p>PWM_LSsignal/low signal</p><p>PWM_HSHigh-side signal/high signal/signal via pulse width modulation</p><p>S_CAP signal</p><p>START_VccInternal voltage</p><p>STP_LS Breakdown protection signal/signal</p><p>STP_LS1 signal</p><p>STP_LS2 signal</p><p>STP_HS signal</p><p>UV_LS2signal</p><p>VbootSignal/Maximum voltage</p><p>VccVoltage</p><p>Vdd_hssource voltage</p><p>Vdd_LsLow-side voltage</p><p>VrefReference voltage</p><p>VswSwitching node voltage</p><p>V+Main Line Voltage</p>

Fig. 1 is a simplified schematic diagram of a half-bridge power conversion circuit according to an embodiment of the present invention; Fig. 2 is a simplified schematic diagram of a circuit in the low-side control circuit illustrated in Fig. 1; Fig. 3 is a simplified schematic diagram of the circuit in the low-side control circuit illustrated in Fig. 1 A schematic diagram of the first level shift transistor illustrated; Fig. 4 is a schematic diagram of the level shift driver circuit illustrated in Fig. 1; Fig. 5 is a blanking pulse generator illustrated in Fig. 1 A schematic diagram of the circuit; Fig. 6 is an example of the waveform in the blanking pulse generator illustrated in Fig. 5; Fig. 7 is a schematic diagram of the bootstrap transistor drive circuit illustrated in Fig. 1; Fig. 8 is a schematic diagram of the bootstrap transistor drive circuit illustrated in Fig. 1 A block diagram of the low-side transistor driving circuit illustrated in Fig. 1; Fig. 9 is a schematic diagram of the starting circuit illustrated in Fig. 1; Fig. 10 can be used as a diode in the schematic diagram of Fig. 9 The series diodes of the clamp are connected to an enhanced transistor based on GaN; Figure 11 is a schematic diagram of the UVLO circuit illustrated in Figure 1; Figure 12 is one of the bootstrap capacitor charging circuits illustrated in Figure 1 Schematic diagram; Figure 13 is a schematic diagram of an alternative bootstrap capacitor charging circuit compared with the circuit illustrated in Figure 12; Figure 14 is a schematic diagram of the high-side logic and control circuit illustrated in Figure 1; Figure 15 It is a schematic diagram of the first level shift receiver circuit illustrated in FIG. 14; FIG. 16 is a schematic diagram of the second level shift receiver circuit illustrated in FIG. 14; FIG. 17 is a schematic diagram of the second level shift receiver circuit illustrated in FIG. A schematic diagram of the illustrated pull-up trigger circuit; FIG. 18 is a schematic diagram of the high-side UVLO circuit illustrated in FIG. 14; FIG. 19 is a schematic diagram of the high-side transistor driver circuit illustrated in FIG. 14 20 is a schematic diagram of a high-side reference voltage generating circuit illustrated in FIG. 14; FIG. 21 is a simplified schematic diagram of a half-bridge power conversion circuit according to another embodiment of the present invention; FIG. 22 is FIG. 21 A simplified schematic diagram of one of the circuits in the low-side control circuit illustrated in Fig. 23; Fig. 23 is a schematic diagram of the first level shift transistor illustrated in Fig. 22; Fig. 24 is the reverse of that illustrated in Fig. 22 A schematic diagram of a phaser/buffer circuit; FIG. 25 is a schematic diagram of the on-pulse generator circuit illustrated in FIG. 22; FIG. 26 is a schematic diagram of the off-pulse generator circuit illustrated in FIG. 22; Fig. 27 is a schematic diagram of the blanking pulse generator circuit illustrated in Fig. 22; Fig. 28 is a schematic diagram of the low-side transistor drive circuit illustrated in Fig. 22; Fig. 29 is a schematic diagram of the low-side transistor drive circuit illustrated in Fig. 21 A simplified schematic diagram of one of the circuits in the high-side control circuit; Fig. 30 is a schematic diagram of the level shift 1 receiver circuit illustrated in Fig. 29; Fig. 31 is the level shift 2 receiver illustrated in Fig. 29 Fig. 32 is a schematic diagram of the high-side UVLO circuit illustrated in Fig. 29; Fig. 33 is a schematic diagram of the high-side transistor driver circuit illustrated in Fig. 29; Fig. 34 is according to the present invention A schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the invention; FIG. 35 is a schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the present invention; FIG. 36 is a schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the present invention An illustration of a part of an electronic package in an embodiment; and FIG. 37 is a diagrammatic illustration of one of the electronic packages of FIG. 36. FIG.

Certain embodiments of the present invention relate to half-bridge power conversion circuits using one or more gallium nitride (GaN) devices. Although the present invention can be used in a wide variety of half-bridge circuits, some embodiments of the present invention are designed to be compatible with integrated driver circuits, integrated level shift circuits, integrated bootstrap capacitor charging circuits, integrated start circuits, and A half-bridge circuit that uses only a hybrid solution of GaN and silicon devices together to operate at high frequency and/or high efficiency is particularly useful, as explained in more detail below.

<b>Half bridge circuit #1</b>

Referring now to FIG. 1, in some embodiments, the circuit 100 may include a pair of complementary power transistors (also referred to herein as switches) that are configured to adjust the power delivered to a load. Controlled by one or more control circuits. In some embodiments, a high-side power transistor and a portion of the control circuit are placed on a high-side device and a low-side power transistor and a portion of the control circuit are placed on a low-side device, as described below Elaborate in detail.

The integrated half-bridge power conversion circuit 100 illustrated in FIG. 1 includes a low-side GaN device 103, a high-side GaN device 105, a load 107, a bootstrap capacitor 110, and other circuit elements, as illustrated in more detail below Description and discussion. Some embodiments may also have an external controller (not shown in FIG. 1) that provides one or more inputs to the circuit 100 to regulate the operation of the circuit. The circuit 100 is for illustration purposes only and other variations and configurations are within the scope of the present invention.

In one embodiment, the low-side GaN device 103 may have a GaN-based low-side circuit 104 including a low-side power transistor 115 with a low-side control gate 117. The low-side circuit 104 may further include an integrated low-side transistor driver 120 having an output 123 connected to the low-side transistor control gate 117. In another embodiment, the high-side GaN device 105 may have a high-side power transistor 125 including a high-side control gate 127 A high-side circuit 106 based on GaN. The high-side circuit 106 may further include an integrated high-side transistor driver 130 having an output 133 connected to the high-side transistor control gate 127.

A voltage source 135 (also referred to as a rail voltage) can be connected to a drain 137 of the high-side transistor 125, and the high-side transistor can be used to control the power input to the power conversion circuit 100. The high-side transistor 125 may further have a source 140 coupled to a drain 143 of the low-side transistor 115 to form a switching node 145. The low-side transistor 115 may have a source 147 connected to ground. In one embodiment, the low-side transistor 115 and the high-side transistor 125 may be GaN-based enhancement mode field effect transistors. In other embodiments, the low-side transistor 115 and the high-side transistor 125 can be any other types of devices, including but not limited to GaN-based depleted transistors, GaN-based depleted transistors, and silicon-based enhanced transistors. The field effect transistors are connected in series, so that the gate of the depletion transistor is connected to the source of the silicon-based enhanced field-effect transistor, the silicon carbide-based transistor, or the silicon-based transistor.

In some embodiments, the high-side device 105 and the low-side device 103 may be made of a GaN-based material. In one embodiment, the GaN-based material may include a GaN layer on a silicon layer. In still other embodiments, the GaN-based material may include, but is not limited to, a GaN layer on a silicon carbide layer, a sapphire layer, or an aluminum nitride layer. In one embodiment, the GaN-based layer may include, but is not limited to, a composite stack of other Group III nitrides (such as aluminum nitride and indium nitride) and Group III nitride alloys (such as AlGaN and InGaN). In still other embodiments, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may be placed on a monolithic GaN-based device. In other embodiments, the GaN-based low-side circuit 104 can be placed on a first GaN-based device and the GaN-based high-side circuit 106 can be placed on a second GaN-based device. In still other embodiments, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may be placed on more than two GaN-based devices. In one embodiment, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 104 The circuit 106 can contain any number of active or passive circuit elements in any configuration.

<b>Low-side device</b>

The low-side device 103 may include numerous circuits for controlling and operating the low-side device and the high-side device 105. In some embodiments, the low-side device 103 may include a logic, control, and level shift circuit (low-side control circuit) 150 that controls the switching of the low-side transistor 115 and the high-side transistor 125 as well as other functions, as follows Discuss in more detail. The low-side device 103 may also include an active circuit 155, a bootstrap capacitor charging circuit 157, and a shielding capacitor 160, which are also discussed in more detail below.

Referring now to FIG. 2, the circuits within the low-side control circuit 150 are functionally illustrated. Each circuit within the low-side control circuit 150 is discussed below, and in some cases is shown in more detail in FIGS. 3-14. In one embodiment, the main function of the low-side control circuit 150 may be to receive one or more input signals (such as a PWM signal) from a controller, and to control the operation of the low-side transistor 115 and the high-side transistor 125 .

In one embodiment, the first level shifting transistor 203 and the second level shifting transistor 205 can be respectively used to communicate with the high-side logic and control circuit 153 (see FIG. 1). In some embodiments, the first level shift transistor 203 may be a high voltage enhancement mode GaN transistor. In still other embodiments, the first level shift transistor 203 can be similar to the low-side transistor 115 (see FIG. 1) and the high-side transistor 125, except that it can be much smaller in size (for example, the first A level shift transistor can be several tens of microns in gate width and has a minimum channel length).

In other embodiments, the first level shift transistor 203 can experience high voltage and high current at the same time (that is, the device can be operated at the high-power portion of the safe operating area of the device), as long as the high-side transistor 125 (see Figure 1) Turn on. These conditions can lead to relatively high power consumption, so certain embodiments can involve design and device reliability considerations in the design of the first level shift transistor 203, as discussed in more detail below. In still other embodiments, a first level shift resistor connected in series with a source 210 of the first level shift transistor 203 can be added 207 to limit the voltage from the gate 213 to the source 210 and therefore limit the maximum current passing through the first level shift transistor. Other methods can be used to limit the current through the first level shift transistor 203 and are within the scope of the present invention. The drain 215 of the first level shift transistor 203 can be coupled to the high-side logic AND control circuit 153 (see FIG. 1), as discussed in more detail below.

In one embodiment, the first level shifting transistor 203 may form part of an inverter circuit having a first input and a first output and configured to be at the first input The terminal receives a first input logic signal and in response provides a first inverted output logic signal at the first output terminal, as discussed in more detail below. In still other embodiments, the first input and the first inverted output logic signal can be referenced to different voltage levels. In some embodiments, the first level shift resistor 207 may be capable of operating with a first inverted output logic signal, the first inverted output logic signal is referenced to a reference voltage 13 volts higher than the first input logic signal One of the above voltages. In other embodiments, it may be able to operate with a first inverted output logic signal, the first inverted output logic signal is referenced to a voltage higher than a reference voltage of the first input logic signal by 20 volts, and in other In an embodiment, it can be higher between 80 volts and 400 volts.

In other embodiments, the first level shift resistor 207 can be replaced by one of the current tanks in any form. For example, in one embodiment, the source 210 of the first level shift transistor 203 may be connected to a gate-to-source short-circuit depletion type device. In yet another embodiment, the depletion type device can be fabricated by replacing the enhanced gate stack with a high-voltage electric field metal plate superimposed on top of the electric field dielectric layer. The thickness of the electric field dielectric and the work function of the metal can be used to determine the pinch-off voltage of the stack.

In other embodiments, the first level shift resistor 207 can be replaced by a current sink. The current sink can use a reference current (Iref) that can be generated by the starting circuit 155 (illustrated in FIG. 1 and discussed in more detail below). Compared with the resistor embodiment, both the depletion transistor and the current sink embodiment can lead to a significant device area reduction (that is, this is due to a phase It will be sufficient for a small depleted transistor and Iref has been obtained from the starting circuit 155. ).

The second level shift transistor 205 may be designed similar to the first level shift transistor 203 (for example, in terms of voltage capability, current handling capability, thermal resistance, etc.). Similar to the first level shifting transistor 203, the second level shifting transistor 205 can also be constructed with an active current sink or a resistor. In one embodiment, the main difference from the second level shift transistor 205 may be its operation. In some embodiments, the main purpose of the second level shift transistor 205 can be to prevent false triggering of the high-side transistor 125 (see FIG. 1) when the low-side transistor 115 is turned off.

In one embodiment, for example, when the low-side transistor 115 is turned off, the load current flows through the high-side transistor 125 and the third quadrant of the transistor in which its gate is shorted to its source In the middle (ie, in the synchronous rectification mode) operation, a false trigger occurs in a boost operation. This condition can cause a dv/dt condition at the switching node (Vsw) 145 because the switching node is at a voltage close to ground when the low-side transistor 115 is turned on and then transitions in a relatively short period of time To mains voltage 135. The resulting parasitic C*dv/dt current (ie, where C=Coss of the first level shift transistor 203 plus any other capacitance to ground) can cause the first level shift node 305 (see Figure 3) to be pulled If low, this will then turn on the high-side transistor 125. In some embodiments, this situation may be undesirable because there may be no dead time control, and breakdown can occur from both the high-side transistor 125 and the low-side transistor 115 that are in a conducting state at the same time.

FIG. 3 illustrates an embodiment showing how the first level shift transistor 203 can be electrically coupled to the high-side device 105. The first level shift transistor 203 positioned on the low-side device 103 is illustrated together with a pull-up resistor 303 that can be positioned on the high-side device 105 (see FIG. 1). In some embodiments, the first level shift transistor 203 can be operated as a pull-down transistor in a resistor pull-up inverter.

In still other embodiments, when the level shift driver circuit 217 (see FIG. 2) supplies a high gate signal (L1_DR) to the first level shift transistor 203, a first level shift The bit node 305 is pulled low, which is inverted by the high-side logic AND control circuit 153 (see FIG. 1). The inverted signal appears as a high-state signal that turns on the high-side transistor 137 (see FIG. 1), which then pulls the voltage at the switching node (Vsw) 145 close to the mains voltage 135.

Conversely, when the level shift driver circuit 217 (see FIG. 2) supplies a low gate signal to the first level shift transistor 203, a first level shift node 305 is pulled to a high logic level. State, this is inverted by the high-side logic AND control circuit 153 (see FIG. 1). The inverted signal appears as a low logic state signal that turns off the high-side transistor 125. This solution can result in an uninverted gate signal to the high-side transistor 125. In still other embodiments, the first level shift transistor 203 may be designed to be large enough to pull up and down the first level shift node 305, but not so large that it drains to the source and drain. The capacitance to the substrate (ie, the semiconductor substrate) causes false triggering of the high-side logic and control circuit 153.

In some embodiments, the pull-up resistor 303 can be replaced by an enhanced transistor, a depleted transistor, or a reference current source element. In still other embodiments, the pull-up resistor 303 may be coupled between the drain and the positive terminal of a floating power source (eg, a bootstrap capacitor, discussed in more detail below) referenced to a voltage rail other than ground. In still other embodiments, there may be a first capacitor between the first output terminal (LS_NODE) 305 and the switching node (Vsw) 145 (see FIG. 1) and a capacitor between the first output terminal and ground. A second capacitor, wherein the first capacitor is greater than the second capacitor. The first capacitor can be designed to respond to a high dv/dt signal at the switching node (Vsw) 145 (see FIG. 1), allowing most of the C*dv/dt current to pass through the first capacitor, thereby ensuring The voltage at the first output terminal 305 tracks the voltage at the switching node (Vsw). In certain embodiments, the shielding capacitor 160 (see FIG. 1) may be designed to act as the first capacitor, as explained above. In still other embodiments, the shielding capacitor 160 (see FIG. 1) may be used to form a capacitance between the first output terminal 305 and the switching node (Vsw) 145 (see FIG. 1) in the half-bridge power conversion circuit 100. In still other embodiments, the shielding capacitor 160 (see FIG. 1) can also be used to make the first output A capacitance between the output terminal 305 and the substrate (ie, the semiconductor substrate) is minimized. More specifically, in some embodiments, the shielding capacitor 160 may be formed by adding a conductive shielding layer to the device and coupling the layer to the switching node (Vsw) 145. This structure can effectively form two capacitors. One capacitor is coupled between the output terminal 305 and the switching node (Vsw) 145, and the other capacitor is coupled between the switching node and the substrate. This effectively eliminates the capacitance between the output terminal 305 and the substrate. In still other embodiments, the shielding capacitor 160 (see FIG. 1) may be constructed on the low-side wafer 103.

The logic, control, and level shift circuit 150 (see FIG. 2) may have other functions and circuits, such as but not limited to a level shift driver circuit 217, a low-side transistor drive circuit 120, and a blanking pulse generator 223. A bootstrap transistor drive circuit 225 and an undervoltage lockout (UVLO) circuit 227, as explained in more detail in separate figures below.

Referring now to FIG. 4, the level shift driver circuit 217 is shown in more detail. In one embodiment, the level shift driver circuit 217 may include a first inverter 405 and a second inverter 410 in a continuous chain. In still other embodiments, since the level shift driver circuit 217 can drive the first level shift transistor 203 with a small gate width, a buffer stage may not be required.

In one embodiment, the level shift driver circuit 217 is directly driven by a pulse width modulated high-side signal (PWM_HS) from a controller (not shown). In some embodiments, the (PWM_HS) signal can be supplied by an external control circuit. In one embodiment, the external control circuit may be an external controller, which is in the same package as the high-side device 105, the low-side device 103, and the two devices or is independently packaged. In still other embodiments, the level shift driver circuit 217 may also include logic to control when the level shift driver circuit is connected to the first level shift transistor 203 (see FIG. 3). In one embodiment, an optional low-side undervoltage lockout signal (LS_UVLO) can be generated by an undervoltage lockout circuit in the level shift driver circuit 217. The low-side undervoltage lockout circuit can be used to turn off when the (Vcc) or (Vdd) of the low-side (Vdd_LS) drops below a specific reference voltage or a fraction of the reference voltage Level shift driver circuit 217.

In still other embodiments, the level shift driver circuit 217 may generate a breakdown protection signal for the low-side transistor (STP_LS). The breakdown protection signal is used to prevent the low-side transistor 115 and the high-side transistor Breakdown caused by overlapping gate signals on crystal 125. The function of the (STP_LS) signal can be to ensure that the low-side driver circuit 120 (see FIG. 2) only communicates with the gate terminal of the low-side transistor 115 when the gate signal of the high-side transistor 125 is low. In other embodiments, the output of the first inverter 405 can be used to generate a breakdown protection signal (STP_LS) for the low-side transistor 115.

In still other embodiments, the logic for UVLO and breakdown protection can be implemented by adding a multi-input "inverting" gate to the first inverter 405, where the input to the "inverting" gate is ( PWM_HS), (LS_UVLO) and (STP_HS) signals. In still other embodiments, the first inverter 405 may only respond to the (PWM_HS) signal when both the (STP_HS) signal and the (LS_UVLO) signal are high. In still other embodiments, the STP_HS signal can be generated from the low-side gate driver block 120, as explained in more detail in a separate figure.

Referring now to FIG. 5, the blanking pulse generator 223 can be used to generate a pulse signal corresponding to the turn-off transient of the low-side transistor 115. This pulse signal can then turn on the second level shift transistor 205 for the pulse duration, which triggers a control circuit on the high-side device 105 (see FIG. 1) to prevent an error in the voltage of the first level shift node 305 drop down.

FIG. 5 illustrates a schematic diagram of an embodiment of the blanking pulse generator 223. In some embodiments, a low-side transistor 115 gate signal (LS_GATE) is fed to the blanking pulse generator 223 as an input. The (LS_GATE) signal is inverted by a first-stage inverter 505, and then sent through an RC pulse generator 510 to generate a positive pulse. In some embodiments, an inverted signal may be required because the pulse corresponds to the falling edge of the (LS_GATE) signal. One of the capacitors 515 in the RC pulse generator 510 circuit can be used as a high-pass filter that allows dv/dt across the resistor 520 to appear at its input. Once the dv/dt is in the RC pulse The input of the impulse generator 510 disappears, the capacitor 515 can be slowly charged through the resistor 520, and a slowly decayed voltage waveform is generated across the resistor. The pulse can then be sent through a second inverter 525, a third inverter 530, and a buffer 535 to generate a square wave pulse for the blanking pulse (B_PULSE) signal. The duration of the pulse can be determined by the values of the capacitor 515 and the resistor 520 in the RC pulse generator 510. In some embodiments, a drain-to-source short-circuit enhanced GaN transistor can be used to construct the capacitor 515.

Referring now to FIG. 6, for one embodiment, an example waveform 600 in the blanking pulse generator 223 is illustrated. Trace 605 shows one of the falling edges of the low-side gate pulse (LS_GATE). Trace 610 shows the rising edge of the first stage inverter 505 output. Trace 615 shows the output of RC pulse generator 510 and trace 620 shows the resulting blanking pulse (B_PULSE) signal output by one of the blanking pulse generators 223.

Referring now to FIG. 7, the bootstrap transistor driving circuit 225 is illustrated in more detail. The bootstrap transistor driving circuit 225 includes an inverter 730, a first buffer 735, and a second buffer 745. The bootstrap transistor drive circuit 225 can receive the (BOOTFET_DR_IN) signal from the low-side driver circuit 120. The (BOOTFET_DR_IN) signal can be inverted with respect to the LS_GATE signal. The bootstrap transistor drive circuit 225 may be configured to provide a gate drive signal called (BOOTFET_DR) to one of the bootstrap transistors in the bootstrap charging circuit 157 (see FIG. 1), as discussed in more detail below. The (BOOTFET_DR) gate drive signal can be timed to turn on the bootstrap transistor when the low-side transistor 115 is turned on. In addition, since the bootstrap transistor drive circuit 225 is driven by (Vcc), the output of this circuit can have a voltage ranging from 0V in the low state to (Vcc)+6V in the high state. In one embodiment, the bootstrap transistor is turned on after the low-side transistor 115 is turned on, and the bootstrap transistor is turned off before the low-side transistor is turned off.

In some embodiments, the ON transient of the (BOOTFET_DR) signal can be achieved by introducing a series delay resistor 705 to the second buffer 745 (which can be a gate of a transistor in a final buffer stage). (Polar) input and delay. In still other embodiments, the low-side transistor The turn-off transient of 115 (see FIG. 1) can be delayed by adding a series resistor to one of the low-side drive circuits 120 to finally pull down one of the gates of the transistor. In one embodiment, one or more capacitors can be used in the bootstrap transistor drive circuit 225 and support a voltage of approximately (Vcc) (for example, it can be 20 volts), depending on the end user requirements and Circuit design. In some embodiments, one or more capacitors can be made of an electric field dielectric to GaN capacitor instead of a drain-to-source short-circuit enhanced transistor.

Referring now to FIG. 8, a block diagram of the low-side transistor driving circuit 120 is illustrated. The low-side transistor driving circuit 120 may have a first inverter 805, a buffer 810, a second inverter 815, a second buffer 820, and a third buffer 825. The third buffer 825 can provide the (LS_GATE) signal to the low-side transistor 115 (see FIG. 1). In some embodiments, two inverter/buffer stages can be used, because the input to the gate of the low-side transistor 115 (see FIG. 1) can be synchronized with (Vin). Therefore, (Vin) in a high state can correspond to (Vgate) in the low-side transistor 115 in a high state and vice versa.

In still other embodiments, certain parts of the low-side drive circuit 120 may have an asymmetrical hysteresis. Some embodiments may include asymmetrical hysteresis using a resistor divider 840 and a transistor pull-down 850.

A further embodiment may have multiple input "inverse and" gates for the (STP_LS) signal (breakdown protection on the low-side transistor 115). In one embodiment, the low-side driver circuit 120 may receive the breakdown protection signal (STP_LS) from the level shift driver circuit 217. The purpose of the (STP_LS) signal can be similar to the previously described (STP_HS) signal. The (STP_LS) signal can ensure that the low-side transistor drive circuit 120 does not communicate with the gate 117 (see FIG. 1) of the low-side transistor 115 when the output of the level shift driver circuit 217 is in a high state. In other embodiments, the output of the first inverter stage 805 can be used as the (STP_HS) signal of the level shift drive circuit 217 and the (BOOTFET_DR_IN) signal of the bootstrap transistor drive circuit 225.

In some embodiments, the low-side transistor drive circuit 120 can connect multiple inputs "inverted" The "and" gate is used for the (LS_UVLO) signal received from the UVLO circuit 227 (see FIG. 2). A further embodiment may adopt a turn-off delay resistor 830 which can be connected in series with a gate of one of the final pull-down transistors in the final buffer stage 825. In some embodiments, the delay resistor 830 can be used to ensure that the bootstrap transistor is turned off before the low-side transistor 115 is turned off.

Referring now to FIG. 9, the starting circuit 155 is illustrated in more detail. The starting circuit 155 can be designed to have numerous functionalities as discussed in more detail below. First, the starting circuit 155 can be used to provide an internal voltage (START_Vcc in this case) and provide enough current to support the circuit driven by (Vcc). This voltage can be kept on to support the circuit until the (Vcc) is externally charged from the mains voltage 135 (V+) to the required voltage. The starting circuit 155 can also provide a reference voltage (Vref) and a reference current tank (Iref) which can be independent of the starting voltage.

In one embodiment, a depletion transistor 905 can act as the main current source in the circuit. In still other embodiments, the depletion transistor 905 may be formed by a metal layer disposed above a passivation layer. In some embodiments, the depletion transistor 905 can use a high voltage field plate (usually inherent to any high voltage GaN technology) as the gate metal. In still other embodiments, an electric field dielectric can act as a gate insulator. The resulting gated transistor can be a depleted device with a high channel pinch-off voltage (Vpinch) (that is, the pinch-off voltage is proportional to the thickness of the electric field dielectric). The depletion transistor 905 can be designed to block the relatively high voltage between its drain (connected to V+) and its source. This connection can be referred to as a source follower connection. The depletion transistor 905 may have a gate 906 coupled to the ground, a source 907 coupled to a first node 911, and a drain 909 coupled to the voltage source 135.

In still other embodiments, a series of identical diode-connected enhanced low voltage transistors 910 may be connected in series with depleted transistors 905. The series of the same diode-connected enhanced low-voltage transistor 910 can be connected in series between a first node 911 and a second node 912. One or more intermediate nodes 913 may be placed between each of the series of identical diode-connected enhanced low-voltage transistors 910. The aspect ratio of the transistor can be set from the current drawn from (V+) and the voltage across each diode. In order to remove the threshold voltage and deal with the change sensitivity, the series phase The enhanced low-voltage transistor 910 connected to the same diode can be designed as a large channel length device. In some embodiments, one or more high-value resistors can be used to replace the series of identical diode-connected enhanced low-voltage transistors 910.

In still other embodiments, at the bottom end of the series of identical diodes connected to the enhanced low voltage transistor 910, a current mirror 915 can be constructed from two enhanced low voltage transistors and used to generate a reference current tank (Iref ). The first current mirror transistor 920 may be a diode connection and the second current mirror transistor 925 may have one of the gates connected to the first current mirror transistor. The sources of the first current mirror transistor 920 and the second current mirror transistor 925 can be coupled and tied to ground, respectively. A drain terminal of the first current mirror transistor 920 can be coupled to the second junction 912 and a source terminal of the second current mirror transistor 925 can be used as a current sink terminal. The current mirror 915 is stacked and a series of identical diodes connected to the enhanced low voltage transistor 910 can form a "source follower load" called a depletion transistor 905.

In other embodiments, when the gate 906 of the depletion transistor 905 is tied to ground, the source 907 of the depletion transistor can be close to (Vpinch) when supplying current to the "source follower load". ) One voltage. At the same time, the voltage drop across the diode connected to the transistor 920 in the current mirror 915 can be close to the threshold voltage of the transistor (Vth). This situation means that the voltage drop across each of the series of identical diodes connected to each of the enhanced low voltage transistors 910 can be equal to (Vpinch-Vth)/n, where "n" is the current mirror 915 and the depleted transistor 905 The number of diodes connected between enhanced transistors.

For example, if the gate of a moving transistor 930 is connected from the bottom to the third same diode connected to an enhanced low-voltage transistor, the gate voltage of the starting transistor can be 3*(Vpinch-Vth)/n +Vth. Therefore, the starting voltage can be 3*(Vpinch-Vth)/n+Vth-Vth=3*(Vpinch-Vth)/n. As a more specific example, in one embodiment, in the case of (Vpinch)=40 volts, (Vth)=2 volts, where n=6 and (Vstartup)=19 volts.

In other embodiments, the starting circuit 155 can generate a reference voltage signal (Vref). In one embodiment, the circuit for generating (Vref) may be similar to the starting voltage generating circuit discussed above. A reference voltage transistor 955 can be connected between two transistors in the series of the same diode-connected enhanced low voltage transistor 910. In one embodiment, (Vref)=(Vpinch-Vth)/n.

In still other embodiments, a deactivated pull-down transistor 935 can span the gate-to-source connection of the start transistor 930. When the deactivation signal is high, the starting transistor 930 will be deactivated. A pull-down resistor 940 can be connected to the gate of the disabled transistor 935 to prevent the disabled transistor from being turned on by mistake. In other embodiments, a diode clamp 945 can be connected between the gate and source terminals of the starting transistor 930 to ensure circuit operation (that is, configured as a gate overvoltage protection device) During the period, the gate-to-source voltage capability of the transistor is not violated. In some embodiments, the diode clamp 945 may be made of a series of diodes connected to a GaN-based enhancement mode transistor 1050, as illustrated in FIG. 10.

Referring now to FIG. 11, the UVLO circuit 227 is illustrated in more detail. In some embodiments, the UVLO circuit 227 may have a differential comparator 1105, a downward level shifter 1110, and an inverter 1115. In still other embodiments, the UVLO circuit 227 can use the (Vref) and (Iref) generated by the starter circuit 155 (see FIG. 9) in a differential comparator/down-level shifter circuit to generate feed-to-bits. The (LS_UVLO) signal in the quasi-shift driver circuit 217 (see FIG. 2) and the low-side transistor driver circuit 120. In some embodiments, the UVLO circuit 227 can also be designed to have asymmetrical hysteresis. In still other embodiments, the output of the UVLO circuit 227 may be independent of the threshold voltage. The above situation can be accomplished by choosing a differential comparator with a relatively high gain. In one embodiment, the gain can be increased by increasing the value of the current source and the pull-up resistor in the differential comparator. In some embodiments, the current and resistor limits can be set by (Vref).

In other embodiments, voltage (VA) 1120 and voltage (VB) 1125 may be proportional to (Vcc) or (Vdd_LS) and (Vref), respectively (as specified by the resistance divider ratio on each input). When (VA)1120&gt;(VB)1125, the input of the inverting terminal changes to a low state. In a specific embodiment, the low state=(Vth), because the current source forms a source follower configuration. Similarly, when (VA)1120&lt;(VB)1125, the output changes to a high state (Vref). In some embodiments, a down-level shifter 1110 may be needed, because the low voltage needs to be shifted down by a threshold voltage to ensure that the low input to the next stage is lower than (Vth). The shift-down output can be inverted by a simple resistor pull-up inverter 1115. The output of the inverter 1115 is the (LS_UVLO) signal.

Referring now to FIG. 12, the bootstrap capacitor charging circuit 157 is illustrated in more detail. In one embodiment, the bootstrap diode and transistor circuit 157 may include a high-voltage diode-connected enhanced transistor 1205 and a high-voltage bootstrap transistor 1210 connected in parallel. In still other embodiments, the high voltage diode connection enhanced transistor 1205 and the high voltage bootstrap transistor 1210 can be designed to share the same drain finger. In some embodiments, the (BOOTFET_DR) signal can be derived from the bootstrap transistor drive circuit 225 (see FIG. 2). As discussed above, the high-voltage bootstrap transistor 1210 can be turned on in unison with the turn-on of the low-side transistor 115 (see FIG. 1).

Referring now to FIG. 13, an alternative bootstrap diode and transistor circuit 1300 can be used to replace the bootstrap diode and transistor circuit 157 discussed in FIG. 12 above. In the embodiment illustrated in FIG. 13, a depletion mode device 1305 stacked by an enhancement mode low voltage GaN device 1310 can be connected as illustrated in a schematic diagram 1300. In another embodiment, a gate of the depleted device 1305 can be connected to ground to reduce the voltage stress on the stacked enhanced device 1310, which depends on the pinch-off voltage of the depleted device.

<b>High side device</b>

Referring now to FIG. 14, the high-side logic AND control circuit 153 is illustrated in more detail. In one embodiment, the high-side driver 130 receives inputs from the first level shift receiver 1410 and the high-side UVLO circuit 1415 and sends a (HS_GATE) signal to the high-side transistor 125 (see FIG. 1). In still other embodiments, a pull-up trigger circuit 1425 is configured to receive the (LSHIFT_1) signal and control the pull-up transistor 1435. In some embodiments, the second The quasi-shift receiver circuit 1420 is configured to control the blanking transistor 1440. Both the pull-up transistor 1435 and the blanking transistor 1440 may be connected in parallel with the pull-up resistor 1430. Each circuit within the high-side logic AND control circuit 153 is discussed below, and in some cases is shown in more detail in FIGS. 16-20.

Referring now to FIG. 15, the first level shift receiver 1410 is illustrated in more detail. In some embodiments, the first level shift receiver 1410 can convert the (L_SHIFT1) signal into a (LS_HSG) signal, and the (LS_HSG) signal can be processed by the high-side transistor driver 130 (see FIG. 14) to drive the high-side Transistor 125 (see Figure 1). In still other embodiments, the first level shift receiver 1410 may have three enhanced transistors 1505, 1510, 1515 used in the level down shifter and act as a diode clamp The plurality of diodes are connected to the transistor 1520, as discussed in more detail below.

In one embodiment, the first level shift receiver 1410 can shift the (L_SHIFT1) signal down by 3*Vth (for example, each enhanced transistor 1505, 1510, 1515 can have a value close to Vth). Gate to source voltage). In some embodiments, the last source follower transistor (eg, transistor 1515 in this case) may have a triode connected transistor clamp 1520 spanning its gate to source. In still other embodiments, this configuration can be used because its source voltage can only be as high as (Vdd_HS) (that is, because its drain is connected to Vdd_HS), and its gate voltage can be as high as V(L_SHIFT1 )-2*Vth. Therefore, in some embodiments, the maximum gate-to-source voltage on the final source follower transistor 1515 may be greater than the maximum rated gate-to-source voltage of the device technology. Finally, the output of the source follower transistor 1515 is the input of the high-side transistor driver 130 (see FIG. 1), (that is, the output is the LS_HSG signal). In still other embodiments, fewer or more than three source follower transistors may be used. In still other embodiments, fewer or more than three diode-connected transistors can be used in the clamp 1520.

Referring now to FIG. 16, the second level shift receiver 1420 is illustrated in more detail. In one embodiment, the second level shift receiver 1420 may have a downward level shift circuit Road 1605 and an inverter circuit 1610. In some embodiments, the second level shift receiver 1420 may be constructed in a manner similar to the first level shift receiver 1410 (see FIG. 15), except that the second level shift receiver may have There is only one downward level shift circuit (for example, enhanced transistor 1615) and one continuous inverter circuit 1610. In one embodiment, the downward level shift circuit 1605 can receive the (L_SHIFT2) signal from the second level shift transistor 205 (see FIG. 2). In one embodiment, the inverter circuit 1610 can be driven by the (Vboot) signal, and the gate voltage of the pull-up transistor above the inverter can be used to drive the (BLANK_FET) of the blanking transistor 1440 (see FIG. 14) Signal. In some embodiments, the voltage can rise from 0 volts in a low state to (Vboot+0.5*(Vboot-Vth)) in a high state. Similar to the first level shift receiver 1410, the second level shift receiver 1420 can span the gate of the source follower transistor 1615 to the source and has a diode connected to the transistor clamp 1620 . In other embodiments, the clamp 1620 may include less or more than three diode-connected transistors.

Referring now to FIG. 17, the pull-up trigger circuit 1425 is illustrated in more detail. In one embodiment, the pull-up trigger circuit 1425 may have a first inverter 1705, a second inverter 1710, an RC pulse generator 1715, and a gate-to-source clamp 1720. In some embodiments, the pull-up trigger circuit 1425 can receive the (L_SHIFT1) signal as an input, and in response, the (L_SHIFT1) voltage transitions to approximately the input threshold of the first inverter 1705 to generate a pulse. The generated pulse can be used as the (PULLUP_FET) signal to drive the pull-up transistor 1435 (see FIG. 14). The second inverter 1710 can be driven by (Vboot) instead of (Vdd_HS), because the gate voltage of the pull-up transistor 1435 may be greater than the (L_SHIFT1) signal voltage.

Referring now to FIG. 18, the high-side UVLO circuit 1415 is illustrated in more detail. In one embodiment, the high-side UVLO circuit 1415 may have a downward level shifter 1805, a resistor pull-up inverter 1810 with asymmetric hysteresis, and a gate-to-source clamp 1815. In still other embodiments, the (HS_UVLO) signal generated by the high-side UVLO circuit 1415 can be supplemented by This helps prevent circuit failure by turning off the (HS_GATE) signal generated by the high-side drive circuit 130 (see FIG. 14) when the voltage of the bootstrap capacitor 110 becomes lower than a certain threshold. In some embodiments, the voltage of the bootstrap capacitor 110 (Vboot) (ie, the voltage of a floating power supply) is measured, and in response, a logic signal is generated and compared with the voltage from the first level shift receiver 1410 The output signal (LS_HSG) combination, which is then used as the input to the high-side gate drive circuit 130. More specifically, in this embodiment, for example, the UVLO circuit is designed to engage when (Vboot) is reduced to exceed the switching node (Vsw) 145 and the voltage is less than 4*Vth. In other embodiments, a different threshold level may be used.

In still other embodiments, the high-side UVLO circuit 1415 can shift (Vboot) downward in the downward level shifter 1805 and transmit the signal to the inverter 1810 with asymmetrical hysteresis. The output of the inverter 1810 with asymmetrical hysteresis can generate a (HS_UVLO) signal, which is logically combined with the output from the first level shift receiver 1410 to turn off the high-side transistor 125 (see figure 1). In some embodiments, hysteresis can be used to reduce the number of self-triggered turn-on and turn-off events of the high-side transistor 125 (see FIG. 1) that are detrimental to the overall performance of the half-bridge circuit 100.

Referring now to FIG. 19, the high-side transistor driver 130 is illustrated in more detail. The high-side transistor driver 130 may have a first inverter stage 1905 followed by a high-side driver stage 1910. The first inverter stage 1905 can invert the downward shift (LS_HSG) signal received from the level shift 1 receiver 1410 (see FIG. 15). The shift down signal can then be sent through the high-side driver stage 1910. The high-side driver stage 1910 can generate a (HS_GATE) signal to drive the high-side transistor 125 (see FIG. 1). In still other embodiments, the first inverter stage 1905 may include a dual-input "inverted-OR" gate that ensures that the high-side transistor 125 (see Figure 1) is turned off when the (HS_UVLO) signal is in a high state. .

Referring now to FIG. 20, a reference voltage generating circuit 2000 can be used to generate a high-side reference voltage from a supply rail. This circuit can be placed on the high-side GaN device 105 to generate an internal power supply referenced to the switching node voltage 145. In some embodiments, the electrical The circuit 2000 can be similar to the starting circuit 155 in FIG. 9. One difference in the circuit 2000 may be the addition of a source follower capacitor 2010 connected between the first node 2011 and the second node 2012. In some embodiments, the source follower capacitor 2010 may be required to ensure that the formation between the first node 2011 and the second node 2012 does not follow the dv/dt fluctuations present at the switching node (Vsw) 145 and is well regulated. Voltage. In other embodiments, a reference voltage capacitor 2015 may be connected between a source of the reference voltage transistor 2055 and the second node 2012. In some embodiments, the drain of the reference voltage transistor 2055 can be connected to the (Vboot) node. In some embodiments, the reference voltage capacitor 2015 may be required to ensure that (Vref) is well regulated and does not respond to high dv/dt conditions at the switching node (Vsw) 145 (see FIG. 1). In still other embodiments, another difference in the circuit 2000 may be that the second node 2012 may be coupled to a constantly changing voltage (such as the switching node (Vsw) 145 (see FIG. 1)) instead of passing through a current sink circuit 915 (See Figure 9) One of the ground connections. In still other embodiments, (Vref) can be used as (Vdd_HS) in the half-bridge circuit 100.

Another difference in the circuit 2000 can be the addition of a high-voltage diode-connected transistor 2025 (that is, a high-voltage diode-connected transistor 2025 (that is, The gate is coupled to the source of the transistor). More specifically, the high-voltage diode-connected transistor 2025 may have a source coupled to the source of the depletion transistor 2005, a drain coupled to the first node 2011, and a source coupled to the first node One of the gates. The high-voltage diode-connected transistor 2025 can be used to ensure that the source follower capacitor does not discharge when the voltage at the top plate of the source follower capacitor 2010 rises above (V+). In still other embodiments, the source follower capacitor 2010 can be relatively small and can be integrated on a semiconductor substrate or in an electronic package. FIG. 21 also shows a bootstrap capacitor 110 that can be externally added to the half-bridge circuit.

In some embodiments, the shielding capacitor 160 (see FIG. 1) can be connected to the switching node 145 from the first level shift node 305 (see FIG. 3) and the second level shift node (not shown) to assist in reducing The false trigger discussed above. In some embodiments, the shielding capacitor 160 The larger the value, the more immune the circuit will be to false trigger effects caused by parasitic capacitance to ground. However, during the off period of the high-side transistor 125, the shielding capacitor 160 can be discharged through the pull-up resistor 303 (see FIG. 3) connected to the first level shift node 305. This can significantly slow down the turn-off procedure of the high-side transistor 125. In some embodiments, this consideration can be used to set an upper limit of the value of the shielding capacitor 160. In still other embodiments, an overvoltage condition on the first level shift node 305 (see FIG. 3) can be achieved by using a clamp circuit 161 between the first level shift node and the switching node 145. (See Figure 1) to prevent. In some embodiments, the clamp circuit 161 may be composed of a diode connected to a transistor, wherein a drain of the transistor is connected to the first level shift node 305 (see FIG. 3) and a gate and a The source is connected to the switching node (Vsw) 145 (see Figure 1). In still other embodiments, a second shielding capacitor and a second clamp circuit may be placed between the second level shift node and the switching node (Vsw) 145 (see FIG. 1).

<b>Half-bridge circuit #1 operation</b>

The following sequence of operations of the half-bridge circuit 100 is only an example and other sequences may be used without departing from the invention. Reference will now be made to FIG. 1, FIG. 2 and FIG. 14 at the same time.

In one embodiment, when the (PWM_LS) signal from the controller is high, the low-side logic, control, and level shift circuit 150 sends a high signal to the low-side transistor driver 120. The low-side transistor driver 120 then connects to the low-side transistor 115 through the (LS_GATE) signal to turn it on. This will set the switching node voltage (Vsw) 145 to be close to 0 volts. When the low-side transistor 115 is turned on, it provides a path for the bootstrap capacitor 110 to be charged through the bootstrap charging circuit 157 that can be connected between (Vcc) and (Vboot). The charging path has a high-voltage bootstrap diode 1205 (see FIG. 12) and one of the transistors 1210 combined in parallel. The (BOOTFET_DR) signal provides a driving signal to the bootstrap transistor 1210 (see FIG. 12), which provides a low resistance path for charging the bootstrap capacitor 110.

The bootstrap diode 1205 (see Figure 12) can be used to ensure that there is a charge for the bootstrap capacitor 110 when the low-side transistor 115 gate drive signal (LS_GATE) is not present during startup. One path. During this time, the (PWM_HS) signal should be low. If the (PWM_HS) signal is inadvertently turned on (ie, in a high state) during this time, the (STP_HS) signal generated from the low-side transistor driver 120 will prevent the high-side transistor 125 from turning on. If the (PWM_LS) signal is turned on when the (PWM_HS) signal is turned on, the (STP_LS) signal generated by the level shift driver circuit 217 will prevent the low-side transistor 115 from turning on. In addition, in some embodiments, the (LS_UVLO) signal can prevent the low-side transistor 115 and the high-side transistor 125 from turning on when (Vcc) or (Vdd_LS) becomes lower than a preset threshold voltage level.

In still other embodiments, when the (PWM_LS) signal is low, the low-side gate signal (LS_GATE) to the low-side transistor 115 is also low. During the dead time between (PWM_LS) signal low state to (PWM_HS) high state transition, an inductive load will force high-side transistor 125 or low-side transistor 115 to turn on in synchronous rectifier mode, depending on the power The direction of the flow. If the high-side transistor 125 is turned on during the dead time (for example, during the boost mode operation), the voltage of the switching node (Vsw) 145 can rise close to (V+) 135 (mains voltage).

In some embodiments, a dv/dt condition on the switching node 145 (Vsw) may often pull the first level shift node (LSHIFT_1) 305 (see FIG. 3) relative to the switching node (Vsw) 145 to a level Low state, this is due to capacitive coupling to ground. This can turn on the high-side gate drive circuit 130, thereby causing the high-side transistor 125 to be triggered unexpectedly. In one embodiment, this may result in no dead time, which may harm the half-bridge circuit 100 in the case of a breakdown condition. In still other embodiments, to prevent this situation from occurring, the blanking pulse generator 223 can sense the turn-off transient of the low-side transistor 115 and send a pulse to turn on the second level shift transistor 205. The above situation can pull the (L_SHIFT2) signal voltage to a low state, which then communicates with the second level shift receiver 1420 to generate a blanking pulse signal (B_PULSE) to drive the blanking transistor 1440. The blanking transistor 1440 can then act as a pull-up to prevent the first level shift node (LSHIFT_1) 305 (see FIG. 3) from changing to a low state relative to the switching node (Vsw) 145.

In still other embodiments, after the dead time, when the (PWM_HS) signal changes to a high state, the level shift driver circuit 217 may send a high signal to the gate of the first level shift transistor 203 (Via the L1_DR signal from the level shift driver circuit 217). The high signal will pull the first level shift node (LSHIFT_1) 305 (see Figure 3) low with respect to the switch node (Vsw) 145, which will cause a high signal at the input of the high-side transistor 125 to connect Pass the high-side transistor 125. The switching node voltage (Vsw) 145 will remain close to (V+) 135. In one embodiment, during this time, the bootstrap capacitor 110 can be discharged through the first level shift transistor 203 (it is in an on state during this time).

If the high-side transistor 125 remains on for a relatively long time (ie, a large duty cycle), the voltage of the bootstrap capacitor 110 will drop to a sufficiently low voltage so that it will prevent the high-side transistor 125 from being in (PWM_HS) Turns on when the signal goes low. In some embodiments, the above situation may occur because the maximum voltage (Vboot) that the (L_SHIFT1) signal can reach may be too low to turn off the high-side transistor 125. In some embodiments, this situation can be prevented by the high-side UVLO circuit 1415, which sends a high input to the high-side gate drive circuit 130 when (Vboot) becomes lower than a certain level. To forcibly turn off the high-side transistor 125.

In still other embodiments, when the (PWM_HS) signal goes low, the first level shift transistor 203 will also be turned off (via the L1_DR signal from the level shift driver circuit 217). This will pull the first level shift node (LSHIFT_1) 305 (see FIG. 3) to a high state. However, in some embodiments, this procedure can be relatively slow, because the high value pull-up resistor 303 (see FIG. 3) (in some embodiments, to reduce power consumption) needs to be attached to All capacitances of the first level shift node (L_SHIFT1) 305 (see FIG. 3) (including the output capacitance (Coss) of the first level shift transistor 213 and the shielding capacitor 160) are charged. This can increase the turn-off delay of the high-side transistor 125. In order to reduce the turn-off delay of the high-side transistor 125, the pull-up trigger circuit 1425 can be used to sense the time when the first level shift node (L_SHIFT1) 305 (see FIG. 3) becomes over (Vth). This condition can be applied to one of the pull-up transistors 1435 (PULLUP_FET) signal, the pull-up transistor, acting in parallel with the pull-up resistor 1430, can significantly accelerate the first level shift node (L_SHIFT1) 305 (see Figure 3) voltage pull-up, thereby speeding up the shutdown procedure .

<b>Half bridge circuit #2</b>

Referring now to FIG. 21, a second embodiment of a half-bridge circuit 2100 is disclosed. The half-bridge circuit 2100 may have the same block diagram as the circuit 100 illustrated in FIG. 1, however, the level shift transistor in the circuit 2100 may operate with a pulse input instead of a continuous signal, as described in more detail below Elaboration. In some embodiments, pulse input can result in lower power dissipation, reduced stress on the level shift transistor, and reduced switching time, as discussed in more detail below.

21, an embodiment includes an integrated half-bridge power conversion circuit 2100, which uses a low-side GaN device 2103, a high-side GaN device 2105, a load 2107, a bootstrap capacitor 2110 and other circuit elements, As discussed in more detail below. Some embodiments may also have an external controller (not shown in FIG. 21) that provides one or more inputs to the circuit 2100 to regulate the operation of the circuit. The circuit 2100 is for illustration purposes only and other variations and configurations are within the scope of the present invention.

As further illustrated in FIG. 21, in one embodiment, the integrated half-bridge power conversion circuit 2100 may include a low-side circuit disposed on the low-side GaN device 2103, and the low-side GaN device 2103 includes a low-side control circuit. Gate 2117 is a low-side transistor 2115. The low-side circuit may further include an integrated low-side transistor driver 2120 having an output 2123 connected to a low-side transistor control gate 2117. In another embodiment, there may be a high-side circuit disposed on the high-side GaN device 2105, and the high-side GaN device 2105 includes a high-side transistor 2125 with a high-side control gate 2127. The high-side circuit may further include an integrated high-side transistor driver 2130 having an output 2133 connected to the high-side transistor control gate 2127.

The high-side transistor 2125 can be used to control the power input to the power conversion circuit 2100 and There is a voltage source (V+) 2135 (sometimes referred to as a mains voltage) connected to a drain 2137 of the high-side transistor. The high-side transistor 2125 may further have a source 2140 coupled to a drain 2143 of the low-side transistor 2115, thereby forming a switching node (Vsw) 2145. The low-side transistor 2115 may have a source 2147 connected to the ground. In one embodiment, the low-side transistor 2115 and the high-side transistor 2125 may be enhanced field effect transistors. In other embodiments, the low-side transistor 2115 and the high-side transistor 2125 can be any other types of devices, including but not limited to GaN-based depleted transistors, GaN-based depleted transistors, and silicon-based enhanced transistors. The field-effect transistors are connected in series, so that the gate of the depletion-type transistor is connected to the source of the silicon-based enhanced field-effect transistor, silicon carbide-based transistor, or silicon-based transistor.

In some embodiments, the high-side device 2105 and the low-side device 2103 may be made of a GaN-based material. In one embodiment, the GaN-based material may include a GaN layer on a silicon layer. In still other embodiments, the GaN-based material may include, but is not limited to, a GaN layer on a silicon carbide layer, a sapphire layer, or an aluminum nitride layer. In one embodiment, the GaN-based layer may include, but is not limited to, a composite stack of other Group III nitrides (such as aluminum nitride and indium nitride) and Group III nitride alloys (such as AlGaN and InGaN).

<b>Low-side device</b>

The low-side device 2103 may have numerous circuits for controlling and operating the low-side device and the high-side device 2105. In some embodiments, the low-side device 2103 may include a low-side logic, control, and level shift circuit (low-side control circuit) 2150 that controls the switching of the low-side transistor 2115 and the high-side transistor 2125 as well as other functions. , Discussed in more detail below. The low-side device 2103 may also include an active circuit 2155, a bootstrap capacitor charging circuit 2157, and a shielding capacitor 2160, as discussed in more detail below.

Referring now to FIG. 22, the circuits within the low-side control circuit 2150 are functionally illustrated. Each circuit within the low-side control circuit 2150 is discussed below, and in some cases is shown in more detail in FIGS. 23-28. In one embodiment, the low-side control circuit 2150 Its main function can be to receive one or more input signals (such as a PWM signal) from a controller, and to control the operation of the low-side transistor 2115 and the high-side transistor 2125.

The first level shift transistor 2203 can be an "on" pulse level shift transistor, and the second level shift transistor 2215 can be an "off" pulse level shift transistor. In one embodiment, a pulse width modulated high side (PWM_HS) signal from a controller (not shown) can be processed by the inverter/buffer 2250 and sent to an on pulse generator 2260 and a turn off Pulse generator 2270. The turn-on pulse generator 2260 can generate a pulse corresponding to a low state to a high state transient state of the (PWM_HS) signal, so that the first level shift transistor 2203 is turned on during the duration of the pulse. The turn-off pulse generator 2270 can similarly generate a pulse corresponding to the high-state to low-state transition of the (PWM_HS) signal, so the second level shift transistor 2205 is turned on for the duration of the turn-off pulse.

The first level shift transistor 2203 and the second level shift transistor 2205 can be operated as pull-down transistors in the resistor pull-up inverter circuit, respectively. More specifically, turning on may mean that the voltage of the respective level shift node is pulled low relative to the voltage of the switching node (Vsw) 2145, and turning off may cause the respective level shift node to exhibit (Vboot) voltage. Since the first level shifting transistor 2203 and the second level shifting transistor 2215 are only "on" for the duration of the pulse, respectively, the power dissipation and stress levels on these two devices can be less than those shown in Figure 1. The half-bridge circuit 100 illustrated in.

A first resistor 2207 and a second resistor 2208 connected in series with the sources of the first level shift transistor 2203 and the second level shift transistor 2215 can be added to limit the gate-to-source voltage and Therefore, the maximum current passing through the transistor. The first resistor 2207 and the second resistor 2208 can be smaller than the source follower resistor of the half-bridge circuit 100 illustrated in FIG. 1, respectively, which can shift the first level of the transistor 2203 and the second level The pull-down action of the quasi-shift transistor 2215 is faster, and the propagation delay to the high-side transistor 2125 is reduced.

In still other embodiments, the first resistor 2207 and the second resistor 2208 can be replaced with any type of current sink, respectively. An embodiment can shift the first level transistor The sources of 2203 and the second level shift transistor 2205 are respectively connected to a gate of a source short-circuit depletion type device. One embodiment of forming a depletion transistor with a high voltage GaN technology can replace the enhanced gate stack with one of the high voltage field plate metals superimposed on top of the electric field dielectric layer. The thickness of the electric field dielectric and the work function of the metal can control the pinch-off voltage of the stack.

In still other embodiments, the first resistor 2207 and the second resistor 2208 can be replaced with a current sink, respectively. In one embodiment, a reference current (Iref) generated by the starting circuit 2155 (see FIG. 21) can be used. Compared with the resistor option, both the depleted transistor and current sink embodiments can result in a significant die area reduction (ie, this is because a small depleted transistor will be sufficient and Iref is already available).

The bootstrap transistor drive circuit 2225 may be similar to the crystal drive circuit 225 illustrated in FIG. 2 above. The bootstrap transistor drive circuit 2225 can receive input from the low-side drive circuit 2220 (see Figure 22) and provide a gate drive signal called (BOOTFET_DR) to the bootstrap capacitor charging circuit 2157 (see Figure 21) Transistor, as discussed in more detail above.

Referring now to FIG. 23, the first level shift transistor 2203 is illustrated along with a pull-up resistor 2303 that can be located in the high-side device 2105. In some embodiments, the first level shift transistor 2203 can be similar to the first level shift transistor 203 illustrated in FIG. 3 as a pull-down transistor in a resistor pull-up inverter operate. As discussed above, the pull-up resistor 2303 may be placed in the high-side device 2105 (see FIG. 21). The second level shift transistor 2215 may have a similar configuration. In some embodiments, there may be a first capacitor between the first output terminal (LS_NODE) 2305 and the switching node (Vsw) 2145 (see FIG. 21), and there may be a capacitor between the first output terminal 2305 and ground. The second capacitance, wherein the first capacitance is greater than the second capacitance. The first capacitor can be designed to respond to a high dv/dt signal at the switching node (Vsw) 2145 (see FIG. 21), allowing most of the C*dv/dt current to pass through the first capacitor, ensuring the first Voltage tracking switching node at output terminal 2305 The voltage at (Vsw). A shielding capacitor 2160 (see FIG. 21) can be configured to act as the first capacitor, as explained above. In still other embodiments, the shielding capacitor 2160 (see FIG. 21) may be used to form a capacitance between the first output terminal 2305 in the half-bridge power conversion circuit 2100 and the switching node (Vsw) 2145 (see FIG. 21). The shielding capacitor 2160 can also be used to minimize the capacitance between the first output terminal 2305 and a substrate of the semiconductor device. In still other embodiments, the shielding capacitor 2160 may be constructed on the low-side GaN device 2103. In some embodiments, a diode 2161 can be connected in parallel with the shielding capacitor 2160.

Referring now to FIG. 24, the inverter/buffer circuit 2250 is explained in more detail. In one embodiment, the inverter/buffer circuit 2250 may have a first inverter stage 2405 and a first buffer stage 2410. In still other embodiments, the inverter/buffer circuit 2250 can be directly driven by a (PWM_HS) signal from a controller (not shown). The output of the first inverter stage 2405 can be an input signal (PULSE_ON) to the turn-on pulse generator 2260 (see FIG. 22) and the output of the first buffer stage 2410 can be an input signal of the turn-off pulse generator 2270 (PULSE_OFF).

In some embodiments, an optional (LS_UVLO) signal can be achieved by sending a signal generated by the UVLO circuit 2227 (see FIG. 22) to an "inverse and" gate disposed in the first inverter stage 2405 To produce. If (Vcc) or (Vdd_LS) becomes lower than a specific reference voltage (or reference voltage fraction), this circuit can be used to turn off the level shift operation. In still other embodiments, the inverter/buffer circuit 2250 can also generate a breakdown protection signal (STP_LS1) that can be applied to the low-side transistor 2115 (see FIG. 21) of the low-side transistor gate drive circuit 2120. . This can turn off the low-side transistor gate drive circuit 2120 (see Figure 21) when the (PWM_HS) signal is high to prevent breakdown.

Referring now to FIG. 25, the turn-on pulse generator 2260 is illustrated in more detail. In one embodiment, the turn-on pulse generator 2260 may have a first inverter stage 2505, a first buffer stage 2510, an RC pulse generator 2515, a second inverter stage 2520, and a second inverter stage 2520. Three inverter stages 2525 and a third buffer stage 2530. In still other embodiments, from The (PULSE_ON) signal input of the inverter/buffer circuit 2250 (see FIG. 22) can be inverted first and then converted into an on pulse by the RC pulse generator 2515 and the square wave generator. The result of this operation is transmitted to the gate drive signal (LI_DR) of the first level shift transistor 2203 (see FIG. 22).

In still other embodiments, the turn-on pulse generator 2260 may include one or more logic functions, such as, for example, a binary or combination function. In one embodiment, the turn-on pulse generator 2260 may have a multi-input "inverted OR" gate for the (STP_HS) signal. The (STP_HS) signal can have the same polarity as the (LS_GATE) signal. Therefore, if the (STP_HS) signal is high (corresponding to the LS_GATE signal being high), the on pulse may not be generated. This is because the first inverter circuit 2505 in FIG. 25 is pulled low, which will cancel the start pulse Producer 2515.

In still other embodiments, the RC pulse generator 2515 may include a clamp diode (not shown). A clamp diode can be added to ensure that the RC pulse generator 2515 works very small duty cycle for the (PWM_LS) signal. In some embodiments, the turn-on pulse generator 2260 can be configured to receive input pulses in the range of 2 nanoseconds to 20 microseconds and transmit pulses of substantially constant duration in the range. In one embodiment, if the voltage across the clamp diode becomes greater than (Vth), the clamp diode can turn on one of the resistors in the RC pulse generator 2515 and short-circuit it (provide A very small capacitor discharge time). This can significantly improve the maximum duty cycle of the operation of the pulse generator circuit 2260 (relative to the PWM_HS signal).

Referring now to FIG. 26, the turn-off pulse generator 2270 is illustrated in more detail. In one embodiment, the turn-off pulse generator 2270 may have an RC pulse generator 2603, a first inverter stage 2605, a second inverter stage 2610, and a first buffer stage 2615. In still other embodiments, the turn-off pulse generator 2270 can receive an input signal (PULSE_OFF) from the inverter/buffer circuit 2250 (see FIG. 22) which can then be connected to the RC pulse generator 2603.

In still other embodiments, the pulse from the RC pulse generator 2603 is sent through the first inverter stage 2605, the second inverter stage 2610, and the buffer stage 2615. The pulse can be connected as a (L2_DR) signal and sent to the second level shift transistor 2215 (see FIG. 22). A clamp diode can also be included in the turn-off pulse generator 2270. In some embodiments, the operating principle may be similar to the operating principle described above with regard to turning on the pulse generator 2260 (see FIG. 25). These operating principles can ensure that the turn-off pulse generator 2270 operates up to the extremely low on-time of the high-side transistor 2125 (see FIG. 21) (that is, the circuit will operate for a relatively small duty cycle). In some embodiments, the turn-off pulse generator 2270 can be configured to receive input pulses in the range of 2 nanoseconds to 20 microseconds and transmit pulses of substantially constant duration in the range. In still other embodiments, a turn-off level shift pulse is shortened by a turn-on input pulse to achieve a turn-off time of less than 50 nanoseconds on the high-side transistor 2125.

In some embodiments, the RC pulse generator 2603 may include a capacitor connected to a resistor divider network. The output from the resistor may be a signal (INV) sent to an inverter 2275 (see FIG. 22), which generates a breakdown protection signal (STP_LS2) transmitted to the low-side driver circuit 2220. In still other embodiments, the turn-off pulse generator 2270 may include one or more logic functions, such as, for example, a binary or combination function. In one embodiment, similar to the (STP_LS1) signal, the (STP_LS2) signal is sent to a "inverse" logic circuit in the low-side driver circuit 2220. In some embodiments, these signals can be used to ensure that during the duration of the off pulse signal (PULSE_OFF), the low-side transistor 2115 (see FIG. 21) is not turned on (that is, because the high-side transistor 2125 is off) Turn off during the off pulse). In some embodiments, this method can be useful for compensating for a turn-off propagation delay (that is, the PULSE_OFF signal can achieve breakdown protection), thereby ensuring that the low-side transistor 2115 will only be completely turned off at the high-side transistor 2125 gate. Turn on after turning off.

In still other embodiments, the second level shift transistor 2215 can be used to shift a blanking pulse level to the high-side device 2105. To accomplish the above situation, a blanking pulse can be sent to one of the "inverse OR" inputs of the first inverter stage 2605. Blanking pulse can be used Suppresses false triggers due to high dv/dt conditions at the switching node Vsw 2145 (see Figure 20). In some embodiments, no blanking pulses can be used to filter dv/dt induced or other unwanted level shift output pulses.

Referring now to FIG. 27, the blanking pulse generator 2223 is illustrated in more detail. In one embodiment, the blanking pulse generator 2223 can be a simpler design than the design used in the half-bridge circuit 100 illustrated in FIG. 1, because the square wave pulse generator is turned off Part of the pulse generator 2270. In one embodiment, the (LS_GATE) signal is fed to the blanking pulse generator 2223 from the low-side gate drive circuit 2220 (see FIG. 22) as an input. This signal can be inverted and then sent through an RC pulse generator to generate a forward pulse. In some embodiments, an inverted signal can be used because the pulse needs to correspond to the falling edge of the (LS_GATE) signal. The output of the above situation can be used as the blanking pulse input (B_PULSE) to turn off the pulse generator 2270.

Referring now to FIG. 28, the low-side transistor driving circuit 2220 is illustrated in more detail. In one embodiment, the low-side transistor drive circuit 2220 may have a first inverter stage 2805, a first buffer stage 2810, a second inverter stage 2815, a second buffer stage 2820, and A third buffer stage 2825. In some embodiments, two inverter/buffer stages can be used because the input to the gate of the low-side transistor 2115 is synchronized with the (PWM_LS) signal. Therefore, in some embodiments, a (PWM_LS) high state may correspond to a (LS_GATE) high state and vice versa.

In still other embodiments, similar to the solution described in 120 (see FIG. 8), the low-side transistor drive circuit 2220 may also include an asymmetrical hysteresis using a resistor divider with a transistor pull-down. In one embodiment, the low-side transistor drive circuit 2220 includes multiple input "inverse and" gates for (STP_LS1) and (STP_LS2) (breakdown prevention on the low-side transistor 2115) signals. The (STP_LS1) and (STP_LS2) signals can ensure that when the high-side transistor 2125 is turned on, the low-side transistor drive circuit 2220 (see FIG. 22) is not connected to the low-side transistor 2115 (see FIG. 21). This technique can be used to avoid the possibility of breakdown. Other embodiments can include Contains the "inverse and" gate for the (LS_UVLO) signal (similar to the "inverse and" gate used in Figure 28 above). An embodiment may include a turn-off delay resistor in series with the gate of the final pull-down transistor. The above situation can be used to ensure that the bootstrap transistor is turned off before the low-side transistor 2115 is turned off.

In still other embodiments, the low-side device 2103 (see FIG. 21) may also include a starting circuit similar to the starting circuit 155, the bootstrap capacitor charging circuit 157, the shielding capacitor 160, and the UVLO circuit 227 as discussed above. 2155. Bootstrap capacitor charging circuit 2157, a shielding capacitor 2160, and a UVLO circuit 2227.

<b>High side device</b>

Referring now to FIG. 29, the high-side logic and control circuit 2153 and how it interacts with the high-side transistor driver 2130 are explained in more detail. In some embodiments, the high-side logic AND control circuit 2153 can operate in a manner similar to the high-side logic AND control circuit 153 discussed in FIG. 15 above. In still other embodiments, the high-side logic AND control circuit 2153 may operate in different ways, as discussed in more detail below.

In one embodiment, the level shift 1 receiver circuit 2910 receives a (L_SHIFT1) signal from the first level shift transistor 2203 (see FIG. 22), and the first level shift transistor is in (PWM_HS) ) Receive a turn-on pulse when the signal transitions from a low state to a high state, as discussed above. In response, the level shift 1 receiver circuit 2910 drives a gate of the pull-up transistor 2960 (e.g., in some embodiments, a low-voltage enhancement mode GaN transistor). In still other embodiments, the pull-up transistor 2960 can then pull up the voltage of a state storage capacitor 2955 relative to the voltage of the switching node (Vsw) 2145 to a value close to (Vdd_HS). The voltage on a state storage capacitor 2955 can then be transferred to the high-side transistor driver 2130 and to the gate of the high-side transistor gate 2127 (see FIG. 21) to turn on the high-side transistor 2125. In some embodiments, the state storage capacitor 2955 may be a latch storage logic circuit configured to change state in response to a first pulse input signal and change state in response to a second pulse input signal. In still other embodiments, either type of lock may be used A storage circuit such as, but not limited to, an RS flip-flop replaces the state storage capacitor 2955.

In still other embodiments, during this time, the level shift 2 receiver circuit 2920 can maintain the pull-down transistor 2965 (e.g., in some embodiments, a low-voltage enhancement mode GaN transistor) in an off state. Status. In the above situation, any discharge path of the state storage capacitor 2955 can be turned off. Therefore, in some embodiments, the state storage capacitor 2955 may have a relatively small charging time constant and a relatively large discharging time constant.

Similarly, the level shift 2 receiver 2920 can receive a (L_SHIFT2) signal from the second level shift transistor 2215 (see FIG. 22). The second level shift transistor is at the high of the (PWM_HS) signal. When the state transitions to the low state, a turn-off pulse is received, as discussed above. In response, the level shift 2 receiver circuit 2920 drives a gate of the pull-down transistor 2965 (e.g., in some embodiments, a low-voltage enhancement mode GaN transistor). In still other embodiments, the pull-down transistor 2965 can then pull down (ie, discharge) the voltage of the state storage capacitor 2955 to a value close to the switching node (Vsw) 2145, which can be turned off by the high-side transistor driver 2130. Turn off the high-side transistor 2125.

Continuing to refer to FIG. 29, the first shielding capacitor 2970 and the second shielding capacitor 2975 can be connected from the (L_SHIFT1) node and (L_SHIFT2) node respectively to help the high dv/dt condition at the switching node (Vsw) 2145 (see FIG. 21) Prevent false triggering during the period. In still other embodiments, a clamp diode may also exist between the (L_SHIFT1) and (L_SHIFT2) nodes and the switching node (Vsw) 2145 (see FIG. 21). This can ensure that the potential difference between the switching node (Vsw) 2145 (see FIG. 21) and the (L_SHIFT1) and (L_SHIFT2) nodes never exceeds (Vth). This can be used to form a relatively fast turn-on and turn-off of one of the high-side transistors 2125 (see FIG. 21).

Referring now to FIG. 30, the level shift 1 receiver 2910 is illustrated in more detail. In one embodiment, the level shift 1 receiver 2910 may include a down level shifter 3005, a first inverter 3010, a second inverter 3015, a first buffer 3020, and a first Three inverters 3025, a second buffer 3030 and a third buffer 3135. In some embodiments In, the level shift 1 receiver 2910 shifts the (L_SHIFT1) signal downward (that is, modulates) a voltage of 3*Vth (for example, using three enhanced transistors, each of which can have A gate-to-source voltage close to Vth). In other embodiments, one less or more downward shifting transistors can be used.

In still other embodiments, the last source follower transistor can span its gate to its source with a triode connected transistor clamp. In some embodiments, this configuration can be used because its source voltage can only be as high as (Vdd_HS) (that is, because its drain is connected to Vdd_HS), and its gate voltage can be as high as V( L_SHIFT1)-2*Vth. Therefore, in some embodiments, the final maximum gate-to-source voltage on the source follower transistor can be greater than the maximum rated gate-to-source voltage in the technology.

In still other embodiments, the first inverter 3010 may also have an "inverted OR" gate for high-side lock-off using the (UV_LS1) signal generated by the high-side UVLO circuit 2915. In one embodiment, one output of the level shift 1 receiver 2910 (see FIG. 29) may be a signal transmitted to one of the gates (PU_FET) of the pull-up transistor 2960 (see FIG. 29). This signal can have a voltage that changes from 0 volts in a low state to (Vdd_HS)+(Vdd_HS-Vth) in a high state. This voltage can be kept on for the duration of the on pulse.

Referring now to FIG. 31, the level shift 2 receiver 2920 is illustrated in more detail. In one embodiment, the level shift 2 receiver 2920 may be similar to the level shift 1 receiver 2910 discussed above. In still other embodiments, the level shift 2 receiver 2920 may include a blanking pulse generator 3105, a downward level shifter 3110, a first inverter 3115, a second inverter 3120, a A first buffer 3125, a third inverter 3130, a second buffer 3135, and a third buffer 3140. In one embodiment, in addition to a 3*Vth down-level shifter 3110 and multiple inverter/buffer stages, a blanking pulse generator 3105 can also be used.

In other embodiments, different configurations can be used. In some embodiments, this particular The configuration can be useful when the level shift 2 receiver 2920 doubles as a high-side transistor 2125 (see Figure 21) to turn off and a blanking transistor 2940 (see Figure 29) to drive to achieve the best dv/dt immunity. In some embodiments, the blanking pulse generator 3105 may be the same as the level shift 2 receiver 1520 illustrated in FIG. 17. In one embodiment, the level shift 2 receiver 2920 (see FIG. 29) can receive (L_SHIFT2) and (UV_LS2) signals and transmit a (PD_FET) signal to the pull-down transistor 2965 in response. In still other embodiments, the first inverter 3115 may have a dual input "inverted" gate for one of the (UV_LS2) signals from the high-side UVLO circuit 2915 (see FIG. 29).

Referring now to FIG. 32, the high-side UVLO circuit 2915 is illustrated in more detail. In one embodiment, the high-side UVLO circuit 2915 may include a down-level shifter 3205 and a resistor pull-up inverter stage 3210. In some embodiments, the high-side UVLO circuit 2915 can be configured to turn off the (HS_GATE ) Signal to prevent circuit failure. In an exemplary embodiment, the high-side UVLO circuit 2915 is designed to engage when (Vboot) decreases below the switching node (Vsw) 2145 voltage less than a value of 4*Vth. In another embodiment, the output of the lower level shifter 3205 may be a signal (UV_LS2) transmitted to the second level shift receiver 2920 and the output of the resistor pull-up inverter stage 3210 may be a transmission To the first level shift receiver 2910 (UV_LS1) signal.

As discussed below, in certain embodiments, the high-side UVLO circuit 2915 may be different from the high-side UVLO circuit 1415 of the half-bridge circuit 100 discussed above in FIGS. 14 and 18, respectively. In one embodiment, the (Vboot) signal can be shifted down by 3*Vth and sent to the resistor pull-up inverter stage 3210. In still other embodiments, the level shift 2 receiver circuit 2920 (see FIG. 29) controls the shutdown procedure based on the high-side transistor 2125 (see FIG. 21), thereby shifting a 3*Vth down to output The "reverse and" gate directly applied to the input of the level shift 2 receiver circuit 2920 will engage the undervoltage lockout.

However, in some embodiments, since the bootstrap voltage may be too low, this can also be maintained The pull-up transistor 2960 (see Figure 29) is turned on. In some embodiments, the above situation may lead to a conflict. When the level shift 2 receiver circuit 2920 (see FIG. 29) attempts to keep the high-side transistor 2125 (see FIG. 21) off, the level shift 1 receiver circuit 2910 may try to turn on the high-side transistor. To avoid this scenario, some embodiments may invert the output of the 3*Vth down shift signal from the high-side UVLO circuit 2915 (see FIG. 29) and send it to the level shift 1 receiver circuit 2910 One of the "reverse or" input. This ensures that the level shift 1 receiver circuit 2910 does not interfere with the UVLO induced shutdown procedure.

Referring now to FIG. 33, the high-side transistor driver 2130 is illustrated in more detail. In one embodiment, the high-side transistor driver 2130 may include a first inverter 3305, a first buffer 3310, a second inverter 3315, a second buffer 3320, and a third buffer 3325. In some embodiments, the high-side transistor driver 2130 may be a more basic design than the high-side transistor driver 130 used in the half-bridge circuit 100 illustrated in FIG. 1. In one embodiment, the high-side transistor driver 2130 receives a (S_CAP) signal from the state storage capacitor 2955 (see FIG. 29) and delivers a corresponding drive (HS_GATE) signal to the high-side transistor 2125 (see FIG. 21). More specifically, when the (S_CAP) signal is in a high state, the (HS_GATE) signal is in a high state and vice versa.

<b>Half bridge circuit #2 operation</b>

The following sequence of operations of the half-bridge circuit 2100 (see FIG. 21) is only an example and other sequences may be used without departing from the present invention. Reference will now be made to FIG. 21, FIG. 22, and FIG. 29 at the same time.

In one embodiment, when the (PWM_LS) signal is in a high state, the low-side logic, control, and level shift circuit 2150 can send a high signal to the low-side transistor driver 2120, and then the low-side transistor driver Pass that signal to the low-side transistor 2115 to turn it on. This can set the voltage of the switching node (Vsw) 2145 to be close to 0 volts. In still other embodiments, when the low-side transistor 2115 is turned on, it can provide a path for charging the bootstrap capacitor 2110. The charging path may have a parallel combination of a high-voltage bootstrap diode and one of the transistors.

In some embodiments, the bootstrap transistor drive circuit 2225 can provide a drive signal (BOOTFET_DR) to the bootstrap transistor, which provides a low resistance path for charging the bootstrap capacitor 2110. In one embodiment, the bootstrap diode can ensure that there is a path for charging the bootstrap capacitor 2110 when there is no low-side gate drive signal (LS_GATE) during startup. During this time, the (PWM_HS) signal should be in a low state. If the (PWM_HS) signal is unintentionally turned on during this time, the (STP_HS) signal generated from the low-side driver circuit 2220 will prevent the high-side transistor 2125 from turning on. If the (PWM_LS) signal is turned on when the (PWM_HS) signal is turned on, the (STP_LS1) and (STP_LS2) signals generated from the inverter/buffer 2250 and inverter 2275 respectively will prevent the low-side transistor 2115 from being connected. Pass. In addition, in some embodiments, the (LS_UVLO) signal can prevent the low-side gate 2117 and the high-side gate 2127 from turning on when (Vcc) or (Vdd_LS) becomes lower than a predetermined voltage level.

Conversely, in some embodiments, when the (PWM_LS) signal is in a low state, the (LS_GATE) signal to the low-side transistor 2115 can also be in a low state. During the dead time between (PWM_LS) low signal and (PWM_HS) high signal transition, an inductive load will force high-side transistor 2125 or low-side transistor 2115 to turn on in synchronous rectifier mode, depending on the power flow The direction. If the high-side transistor 2125 is turned on during the dead time (for example, in a boost mode), the voltage of the switching node (Vsw) 2145 can rise close to (V+) 2135 (mains voltage). This dv/dt condition on the switching node (Vsw) 2145 can often pull the (L_SHIFT1) node relative to the switching node to a low state (that is, due to capacitive coupling to ground), which can turn on the high-side transistor driver 2130, resulting in the unscheduled conduction of the high-side transistor 2125. This condition can invalidate the dead time and cause breakdown.

In some embodiments, this situation can be prevented by using the blanking pulse generator 2223 to sense the turn-off transient of the low-side transistor 2115 and send a pulse to turn on the second level shift transistor 2205. . The above situation can pull the (L_SHIFT2) signal to a low state, which can Then it communicates with the level shift 2 receiver 2920 to generate a blanking pulse to drive the blanking transistor 2940. In one embodiment, the blanking transistor 2940 can act as a pull-up to prevent the (LSHIFT_1) signal from changing to a low state relative to the switching node (Vsw) 2145.

In still other embodiments, when the (PWM_HS) signal transitions from a low state to a high state after the dead time, a turn-on pulse can be generated by the turn-on pulse generator 2260. This can pull the (L_SHIFT1) node voltage low for a short period of time. In still other embodiments, this signal can be inverted by the level shift 1 receiver circuit 2910 and a brief high signal will be sent to the pull-up transistor 2960, which will charge the state storage capacitor 2955 to a high state. The above situation can result in a corresponding high signal at the input of the high-side transistor driver 2130 that will turn on the high-side transistor 2125. The voltage of the switching node (Vsw) 2145 can be kept close to (V+) 2135 (ie, the mains voltage). The voltage of the state storage capacitor 2955 can remain in a high state during this time because there is no discharge path.

In other embodiments, the bootstrap capacitor 2110 can be discharged through the first level shift transistor 2203 during the turn-on pulse. However, because the time period is relatively short, the bootstrap capacitor 2110 may not be as good as it is when the first level shift transistor 2203 is turned on during the entire duration of the (PWM_HS) signal (as shown in the half bridge in Figure 1). In the case of the circuit 100, it is discharged like a discharge. More specifically, in some embodiments, the above-mentioned situation may cause the switching frequency of the UVLO junction to be relatively lower than one of the values of the half-bridge circuit 100 in FIG. 1.

In some embodiments, when the (PWM_HS) signal transitions from a high state to a low state, a turn-off pulse can be generated by the turn-off pulse generator 2270. This can pull the (L_SHIFT2) node voltage low for a short period of time. This signal can be inverted by the level shift 2 receiver circuit 2920 and a brief high signal will be sent to the pull-down transistor 2965, which will discharge the state storage capacitor 2955 to a low state. The above situation will result in a low signal at the input of the high-side transistor driver 2130 that will turn off the high-side transistor 2125. In still other embodiments, the voltage of the state storage capacitor 2955 can be maintained at a level during this period of time. Low state, this is because it does not have a discharge path.

In one embodiment, since the turn-off procedure in the circuit 2100 does not involve charging the level shift node capacitor through a high-value pull-up resistor, the turn-off time can be relatively shorter than that of the half-bridge circuit 100 in FIG. 1 . In still other embodiments, the turn-on and turn-off procedures of the high-side transistor 2125 can be controlled by turning on substantially similar level shift transistors 2203, 2205, so the turn-on and turn-off propagation delays can be substantially similar. . This may result in the need for a pull-up trigger circuit and/or a pull-up transistor (such as both used in the half-bridge circuit 100 of FIG. 1).

<b>ESD circuit</b>

Referring now to FIG. 34, in some embodiments, one or more pins (ie, the connection from a semiconductor device in an electronic package to an external terminal on the electronic package) may use an electrostatic discharge (ESD) Clamper circuit to protect the circuit. The following embodiments illustrate an ESD clamp circuit on one or more pins that can be used in one or more of the embodiments disclosed herein and other embodiments that may require ESD protection. In still other embodiments, the ESD clamp circuits disclosed herein can be used on GaN-based devices.

An embodiment of an electrostatic discharge (ESD) clamp circuit 3400 is illustrated. The ESD clamp circuit 3400 may have a configuration using one or more source follower stages 3405 made of enhanced transistors. Each source follower stage 3405 may have a gate 3407 connected to a source 3406 of an adjacent source follower stage. In the embodiment illustrated in FIG. 34, four source follower stages 3405 are used, however, in other embodiments, fewer or more may be used. The resistor 3410 is coupled to the source 3407 of the source follower stage 3405.

An ESD transistor 3415 is coupled to one or more source follower stages 3405 and can be configured to conduct a current greater than 500 mA when exposed to an overvoltage pulse, as discussed below. The resistor 3410 is placed between the source 3420 of the ESD transistor 3415 and each source 3407 of the source follower stage 3405. The drain 3408 of the source follower stage 3405 is connected to the drain 3425 of the ESD transistor 3415. Finally, the source 3407 of the source follower stage is coupled to the gate 3430 of the ESD transistor 3415.

In one embodiment, one of the turn-on voltages of the ESD clamp circuit 3400 can be set by the total number of source follower stages 3405. However, since the final source follower stage has a specific drain 3408 to source 3407 voltage and gate 3406 to source voltage a transistor, the current through the final resistor 3410 can be relatively large And can cause a larger gate 3430 to source 3420 voltage across the ESD transistor 3415. Compared with other ESD circuit configurations, this condition can result in a relatively large ESD current capability and in some embodiments an improved leakage performance.

In still other embodiments, the ESD clamp circuit 3400 may have multiple degrees of freedom with respect to the size and resistance of the transistor. In some embodiments, the ESD clamp circuit 3400 may be able to become smaller than other ESD circuit configurations. In other embodiments, the performance of the ESD clamp circuit 3400 can be improved by incrementally increasing the size of the source follower 3405 as it becomes closer to the ESD transistor 3415. In still other embodiments, the resistor 3410 may be replaced with a depletion transistor, a reference current sink, or a reference current source, for example.

Referring now to FIG. 35, an embodiment similar to the ESD clamp circuit 3400 in FIG. 34 is illustrated, however, the ESD clamp circuit 3500 may have resistors in a different configuration, as discussed in more detail below. The ESD clamp circuit 3500 may have a configuration using one or more source follower stages 3505 made of one or more enhanced transistors. Each source follower stage 3505 may have a gate 3506 connected to a source 3507 of an adjacent source follower stage. In the embodiment illustrated in FIG. 35, four source follower stages 3505 are used, however, in other embodiments, fewer or more may be used. The resistor 3510 is coupled between the source 3507 adjacent to the source follower stage 3505. An ESD transistor 3515 is coupled to the source follower stage 3505, wherein the resistor 3510 is placed between the source 3520 of the ESD transistor 3515 and the source 3507 of a source follower stage 3505. The drain 3508 of the source follower stage 3505 can be coupled together and coupled to the drain 3525 of the ESD transistor 3515.

<b>Electronic packaging</b>

Referring now to FIGS. 36 and 37, in some embodiments, one or more semiconductor devices Can be placed in one or more electronic packages. Countless package configurations and types of electronic packages are available and are within the scope of the present invention. Figure 36 illustrates an example of what is referred to as a four-sided flat no-lead electronic package with one of two semiconductor devices in it.

The electronic package 3600 may have a package base 3610 with one or more die pads 3615 surrounded by one or more terminals 3620. In some embodiments, the package base 3610 may include a lead frame while in other embodiments it may include an organic printed circuit board, a ceramic circuit, or another material.

In the embodiment depicted in FIG. 36, a first device 3620 is mounted to a first die pad 3615 and a second device 3625 is mounted to a second die pad 3627. In another embodiment, one or more of the first device 3620 and the second device 3625 may be mounted on an insulator (not shown) mounted to the package base 3610, respectively. In one embodiment, the insulator may be a ceramic or other non-conductive material. The first device 3620 and the second device 3625 are respectively electrically coupled to the terminal 3640 via wire bonds 3630 or any other type of electrical interconnect (such as, for example, flip chip bumps or pillars that can be used in a flip chip application). Wire bonds 3630 can extend between device bond pads 3635 to terminals 3640, and in some cases to die pads 3615, 3627 and in other cases to device bond pads 3635 on an adjacent device.

Referring now to FIG. 37, an isometric view of an electronic package 3600 is shown. The terminals 3640 and die attach pads 3615 and 3627 may be disposed on an external surface and configured to attach to a printed circuit board or other device. In still other embodiments, the terminals 3640 and die attach pads 3615 and 3627 may only be connected inside the electronic package 3600 and other connections may be placed on the outside of the electronic peak. More specifically, certain embodiments may have internal electrical wiring and there must be no one-to-one correlation between internal and external connections.

In still other embodiments, the first device 3620 and the second device 3625 (see FIG. 36) and a top surface of the package base 3610, respectively, may be encapsulated by a non-conductive material 3705 (such as, for example, a molding compound). Countless other electronic packages can be used, such as but not limited to SOIC, DIPS, MCM, and others. In addition, in some embodiments, each device can be In a single electronic package, other embodiments may have two or more electronic devices in a single package. Other embodiments may have one or more passive devices in one or more electronic packages.

In the foregoing specification, the embodiments of the present invention have been described with reference to numerous specific details due to different implementations. Therefore, the description and drawings should be regarded as illustrative rather than restrictive. The unique and exclusive indicator of the scope of the present invention and the content determined by the applicant to be the scope of the invention are the literal and equivalent categories of the set of claims issued by this application, in the specific form of these claims, including Any subsequent corrections.