Semiconductor device and method for manufacturing semiconductor device

Semiconductor device and semiconductor device manufacturing method

Semiconductor device and method for manufacturing semiconductor device

The invention disclosed in this specification and the like relates to a semiconductor device and a method of manufacturing the semiconductor device.

Note that in this specification and the like, semiconductor devices refer to all devices that can operate by utilizing the characteristics of semiconductors. Therefore, electro-optical devices, image display devices, semiconductor circuits, and electronic devices are all semiconductor devices.

The technique of using a semiconductor thin film formed on a substrate with an insulating surface to construct a transistor is attracting attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and video display devices (simply described as display devices). As semiconductor thin films that can be applied to transistors, silicon-based semiconductor materials are widely known. However, as other materials, oxide semiconductors are attracting attention.

For example, a technique for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Document 1).

[Patent Document 1] Japanese Patent Application Publication No. 2006-165528

In addition, for example, when manufacturing a semiconductor device (for example, a liquid crystal panel, etc.) using a transistor using an oxide semiconductor, it is necessary to provide an interlayer insulating film on the transistor using an oxide semiconductor.

The interlayer insulating film not only insulates between the transistor and the wiring and between the wiring in the integrated circuit, but also is an important factor in stabilizing the characteristics of the transistor.

Therefore, one of the problems of the present invention is to suppress variations in electrical characteristics of a semiconductor device having an interlayer insulating film on a transistor using an oxide semiconductor.

One aspect of the present invention adopts the following structure: the step region generated by the source electrode and the drain electrode on the semiconductor film has a void portion, and includes a first insulating film containing silicon oxide as a component, and to block the first insulating film The void portion is provided in contact with the first insulating film and contains a second insulating film composed of silicon nitride as a component. By adopting this structure, it is possible to prevent the void portion generated in the first insulating film from further expanding to the outside. More specifically, for example, the following structure can be adopted.

One aspect of the present invention is a semiconductor device including: a semiconductor film in which at least a part overlaps with a gate electrode via a gate insulating film; and a source electrode and a drain electrode having a region in contact with a part of the top surface of the semiconductor film ; Cover the source electrode, the drain electrode and the semiconductor film, and there is a gap in the step area caused by the source electrode and the drain electrode on the semiconductor film A first insulating film containing silicon oxide as a component; and a second insulating film that is provided in contact with the first insulating film so as to block the void portion of the first insulating film and contains silicon nitride as a component.

Another aspect of the present invention is a semiconductor device including: a semiconductor film; a source electrode and a drain electrode having a region in contact with a part of the top surface of the semiconductor film; covering the source electrode, the drain electrode, and the semiconductor film, and The step region generated by the source electrode and the drain electrode on the semiconductor film has a void portion, and a first insulating film containing silicon oxide as a component; A second insulating film provided in contact and containing silicon nitride as a component; and a gate electrode overlapping the semiconductor film via the second insulating film.

Another aspect of the present invention is a semiconductor device having the above structure, wherein the source electrode and the drain electrode have a stacked structure including a first conductive film in contact with the semiconductor film and a second conductive film on the first conductive film, And the side end surface of the second conductive film is on the top surface of the first conductive film.

Another aspect of the present invention is a semiconductor device having the above structure, wherein the film density of the first insulating film is preferably 2.26 g/cm³Above and 2.50g/cm³the following.

Another aspect of the present invention is a semiconductor device having the above structure, wherein the first insulating film is preferably a silicon oxynitride film, and the second insulating film is preferably a silicon nitride film.

Another aspect of the present invention is a semiconductor device having the above structure, wherein the thickness of the first insulating film is greater than the thickness of the second insulating film.

Another aspect of the present invention is a semiconductor device having the above structure Wherein, the semiconductor film is preferably an oxide semiconductor film.

Another aspect of the present invention is a method of manufacturing a semiconductor device, including the steps of: forming a semiconductor film in which at least a portion overlaps with a gate electrode via a gate insulating film; and forming a region having contact with a portion of the top surface of the semiconductor film The source electrode and the drain electrode; forming a first insulating film, the first insulating film covers the source electrode, the drain electrode and the semiconductor film, in the step area generated by the source electrode and the drain electrode on the semiconductor film Having voids and containing silicon oxide as a component; and forming a second insulating film that is provided in contact with the first insulating film so as to block the voids of the first insulating film and containing silicon nitride as a component .

Another aspect of the present invention is a method of manufacturing a semiconductor device, including: forming a semiconductor film; forming a source electrode and a drain electrode having a region in contact with a part of the top surface of the semiconductor film; forming a first insulating film, the second An insulating film covers the source electrode, the drain electrode, and the semiconductor film, and the step area generated by the source electrode and the drain electrode on the semiconductor film has voids, and contains silicon oxide as a component; forming a second insulating film, The second insulating film is provided in contact with the first insulating film so as to block the voids of the first insulating film and contains silicon nitride as a component; and a gate electrode overlapping the semiconductor film is formed on the second insulating film.

Another aspect of the present invention is a method of manufacturing a semiconductor device, wherein the source electrode and the drain electrode have a stacked structure including a first conductive film in contact with the semiconductor film and a second conductive film on the first conductive film, and The first conductive film and the second conductive film are etched, and the side end surface of the second conductive film is on the top surface of the first conductive film by the etching process.

Another aspect of the present invention is a method of manufacturing a semiconductor device having the above structure, wherein the film density of the first insulating film is preferably 2.26 g/cm³Above and 2.50g/cm³the following.

Another aspect of the present invention is a method of manufacturing a semiconductor device having the above structure, wherein the first insulating film is preferably a silicon oxynitride film, and the second insulating film is preferably a silicon nitride film.

Another aspect of the present invention is a method of manufacturing a semiconductor device having the above-mentioned structure, wherein the thickness of the first insulating film is greater than the thickness of the second insulating film.

Another aspect of the present invention is a method of manufacturing a semiconductor device having the above-mentioned structure, wherein the semiconductor film is preferably an oxide semiconductor film.

According to one aspect of the present invention, it is possible to provide a semiconductor device with high reliability with suppressed variation in electrical characteristics.

<p>11Silicon chip</p><p>12Silicon Nitride Film</p><p>21Glass substrate</p><p>22Gate insulation film</p><p>23Oxide semiconductor film</p><p>24electrode</p><p>25Oxide insulating film</p><p>25aThe first silicon oxynitride film</p><p>25bSecond silicon oxynitride film</p><p>26Nitride insulating film</p><p>27Insulation film</p><p>31Oxide semiconductor film</p><p>32Oxide insulating film</p><p>32aOxide insulating film</p><p>32bOxide insulating film</p><p>400Substrate</p><p>401Base insulating film</p><p>402Gate electrode</p><p>404Gate insulation film</p><p>404aGate insulating film</p><p>404bGate insulating film</p><p>406Semiconductor film</p><p>407aConductive film</p><p>407bConductive film</p><p>407cConductive film</p><p>408aSource electrode</p><p>408bDrain electrode</p><p>410Oxide insulating film</p><p>410aOxide insulating film</p><p>410bOxide insulating film</p><p>410cOxide insulating film</p><p>410dOxide insulating film</p><p>410eOxide insulating film</p><p>411Nitride insulating film</p><p>412Insulation film</p><p>413Space</p><p>414Interlayer insulation film</p><p>416electrode</p><p>450Transistor</p><p>510Oxide insulating film</p><p>510aOxide insulating film</p><p>510bOxide insulating film</p><p>511Nitride insulating film</p><p>512Gate insulation film</p><p>530Insulation film</p><p>550Transistor</p><p>552Gate electrode</p><p>560Transistor</p><p>570Transistor</p><p>580Transistor</p><p>601Substrate</p><p>602Photodiode</p><p>606aSemiconductor film</p><p>606bSemiconductor film</p><p>606cSemiconductor film</p><p>608Adhesive layer</p><p>613Substrate</p><p>632Insulation film</p><p>633Planarization film</p><p>634Planarization film</p><p>640Transistor</p><p>641aelectrode</p><p>641belectrode</p><p>642electrode</p><p>643Conductive film</p><p>645Conductive film</p><p>656Transistor</p><p>658Photoelectric diode reset signal line</p><p>659Gate signal line</p><p>671Photoelectric sensor output signal line</p><p>672Photoelectric sensor reference signal line</p><p>901Substrate</p><p>902Pixel</p><p>903Signal line drive circuit</p><p>904Scan line drive circuit</p><p>905Sealing material</p><p>906Substrate</p><p>908Liquid crystal layer</p><p>910Transistor</p><p>911Transistor</p><p>913Liquid crystal element</p><p>915Connecting terminal electrode</p><p>915aConnecting terminal electrode</p><p>915bConnect terminal electrode</p><p>916Terminal electrode</p><p>917Conductive film</p><p>918FPC</p><p>918aFPC</p><p>918bFPC</p><p>919Anisotropic conductive agent</p><p>921Interlayer insulation film</p><p>922Gate Insulation Film</p><p>923Insulation film</p><p>924Insulation film</p><p>925Sealing material</p><p>930electrode</p><p>931electrode</p><p>932Insulation film</p><p>933Insulation film</p><p>935Spacer</p><p>936Sealing material</p><p>941electrode</p><p>943Liquid crystal element</p><p>944Insulation film</p><p>950Silicon Nitride Film</p><p>951electrode</p><p>955Connect terminal electrode</p><p>960Separating Wall</p><p>963Light-emitting element</p><p>964filling material</p><p>971Source electrode</p><p>973Drain electrode</p><p>975Common potential line</p><p>977Common electrode</p><p>985Common potential line</p><p>987Common electrode</p><p>9000table</p><p>9001Shell</p><p>9002Legs</p><p>9003Display</p><p>9004Display button</p><p>9005Power supply line</p><p>9033 clip</p><p>9034switch</p><p>9035Power switch</p><p>9036Switch</p><p>9038Operation switch</p><p>9100TV</p><p>9101Shell</p><p>9103Display</p><p>9105Support</p><p>9107Display</p><p>9109Operation keys</p><p>9110Remote control</p><p>9201Main body</p><p>9202Shell</p><p>9203Display</p><p>9204Keyboard</p><p>9205External port</p><p>9206Pointing device</p><p>9630Shell</p><p>9631Display</p><p>9631aDisplay</p><p>9631bDisplay</p><p>9632aarea</p><p>9632b area</p><p>9633Solar cell</p><p>9634Charge and discharge control circuit</p><p>9635Battery</p><p>9636DCDC converter</p><p>9637Converter</p><p>9638Operation keys</p><p>9639Button</p>

In the drawings: FIGS. 1A and 1B are plan views and cross-sectional views showing one mode of a semiconductor device; FIGS. 2A to 2C are diagrams showing an example of a method of manufacturing a semiconductor device; FIGS. 3A to 3C are diagrams showing a semiconductor device Figures of an example of the manufacturing method; Figures 4A and 4B are plan views and cross-sectional views showing one mode of a semiconductor device; 5A to 5C are diagrams showing an example of a method of manufacturing a semiconductor device; FIGS. 6A to 6D are diagrams showing an example of a method of manufacturing a semiconductor device; Figures 8A to 8C are cross-sectional views showing the process of generating the void portion; Figures 9A to 9C are cross-sectional views illustrating one mode of the display device; Figures 10A and 10B are cross-sectional views illustrating one mode of the display device; 11 is a cross-sectional view illustrating one mode of the display device; FIGS. 12A to 12C are diagrams illustrating one mode of the display device; FIGS. 13A and 13B are diagrams illustrating one mode of a semiconductor device; FIGS. 14A to 14C are diagrams illustrating an electronic device 15A to 15C are diagrams illustrating electronic devices; FIGS. 16A and 16B are diagrams showing STEM images of example examples in the embodiment; FIGS. 17A and 17B are diagrams showing STEM images of example examples in the embodiment Figures; Figures 18A and 18B are diagrams showing STEM images of example samples in the embodiment; Figures 19A and 19B are diagrams showing the electrical characteristics of the example samples in the embodiment; Figures 20A1 to 20A3 and 20B1 to 20B3 Is shown in the embodiment Figure 21 is a diagram illustrating the electrical characteristics of the sample in the embodiment; Figures 22A and 22B are diagrams illustrating the SIMS data of the sample in the embodiment; Figures 23A and 23B are diagrams illustrating Figs. 24A and 24B are diagrams showing SIMS data of the embodiment samples in the embodiment; Figs. 25A to 25D are diagrams illustrating the nitrogen, Model diagrams of the movement of hydrogen and water; FIGS. 26A to 26E are model diagrams illustrating the movement of nitrogen, hydrogen, and water of the oxide semiconductor film in the heat treatment; FIGS. 27A to 27C are diagrams illustrating the oxide semiconductor film in the heat treatment A model diagram of the changes in oxygen deficiencies.

Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description. Those of ordinary skill in the art can easily understand the fact that the method and details of the present invention can be changed into various forms without departing from the spirit and scope of the present invention. Various forms. Therefore, the present invention should not be interpreted as being limited to the content described in the embodiments shown below.

Note that the functions of "source" and "drain" are sometimes interchanged when transistors with different polarities are used, or when the current direction of circuit operation changes. Therefore, in this specification, "source" and "drain" Can be exchanged with each other.

"Electrical connection" includes the connection by "components with a certain electrical function". Here, the "component with a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between connection targets.

For ease of description, the positions, sizes, and ranges of each structure shown in the drawings and the like sometimes do not indicate the actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

Ordinal numbers such as "first", "second", and "third" are appended to avoid confusion of constituent elements.

Note that in this specification, "parallel" means that the angle formed by two straight lines is -10° or more and 10° or less, and therefore also includes the case where the angle is -5° or more and 5° or less. In addition, "perpendicular" means that the angle formed by two straight lines is 80° or more and 100° or less, and therefore also includes the case where the angle is 85° or more and 95° or less.

In this specification, the hexagonal crystal system includes the trigonal crystal system and the rhombohedral crystal system.

[Embodiment 1]

In this embodiment, a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. 1A and 1B show a plan view and a cross-sectional view of a transistor 450 of a semiconductor device according to an embodiment of the present invention. FIG. 1A shows a top view of the transistor 450, and FIG. 1B shows a cross-sectional view along the chain line AB shown in FIG. 1A.

The transistor 450 shown in FIGS. 1A and 1B includes The gate electrode 402 on the surface of the substrate 400, the gate insulating film 404 provided on the gate electrode 402, the semiconductor film 406 provided on the gate insulating film 404 and overlapping the gate electrode 402, and the semiconductor film 406 provided on the The source electrode 408a and the drain electrode 408b on the upper side. In addition, the transistor 450 may further include an insulating film 412 that covers the source electrode 408a and the drain electrode 408b and is in contact with the semiconductor film 406. Furthermore, an interlayer insulating film 414 covering the insulating film 412 and an electrode 416 on the interlayer insulating film 414 that are electrically connected to the drain electrode 408b through openings provided in the insulating film 412 and the interlayer insulating film 414 are provided. In addition, although the electrode 416 is electrically connected to the drain electrode 408b in this embodiment, it is not limited to this, and the electrode 416 may also be electrically connected to the source electrode 408a.

In this embodiment, the gate insulating film 404 has a stacked structure of a gate insulating film 404a in contact with the gate electrode 402 and a gate insulating film 404b in contact with the gate insulating film 404a and the semiconductor film 406. In addition, the insulating film 412 has an oxide insulating film 410 as a first insulating film in contact with the semiconductor film 406, a source electrode 408a, and a drain electrode 408b, and a second insulating film serving as a protective film on the oxide insulating film 410. A stacked structure of the nitride insulating film 411. In addition, the oxide insulating film 410 has an oxide insulating film 410a with high coverage and an oxide on the oxide insulating film 410a formed in contact with the semiconductor film 406, the source electrode 408a, and the drain electrode 408b and formed under low power conditions. The laminated structure of the insulating film 410b.

In addition, due to the step of the side end surfaces of the source electrode 408a and the drain electrode 408b, a void 413 is generated in the oxide insulating film 410 covering the step. The void portion 413 is formed due to the ratio of the dielectric constant of the void portion 413 The film is low, so it is possible to reduce the capacitance between wirings accompanying the miniaturization of semiconductor devices, and to achieve high-speed operation while maintaining high integration. In addition, moisture invades into the semiconductor film 406 from the portion of the gap 413 and adversely affects the characteristics of the transistor 450. However, by providing the nitride insulating film 411 on the oxide insulating film 410, it is possible to cover the oxide The void portion of the object insulating film 410.

Furthermore, by blocking the void portion 413 by the nitride insulating film 411, the void portion 413 can be prevented from expanding to the outside of the oxide insulating film 410. In addition, the void portion 413 may be buried by the nitride insulating film 411. In addition, the nitride insulating film 411 functions as a barrier film that suppresses the intrusion of hydrogen or a hydrogen-containing compound (water or the like) into the semiconductor film 406 from the outside or an interlayer insulating film 414 formed later.

Next, a method of manufacturing the transistor 450 will be described with reference to FIGS. 2A to 2C and FIGS. 3A to 3C.

First, a gate electrode 402 (including wiring formed of the same layer as it) is formed on a substrate 400 having an insulating surface.

Although there is no major limitation on the substrate that can be used as the substrate 400 having an insulating surface, it is required to have at least a degree of heat resistance that can withstand the subsequent heat treatment. For example, as the substrate 400, a glass substrate such as barium borosilicate glass or aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, as the substrate 400, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, etc., a compound semiconductor substrate made of silicon germanium, etc., or an SOI substrate, etc., can also be used on these substrates. A substrate provided with a semiconductor element.

The gate electrode 402 may be formed of metal materials such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or alloy materials containing them as main components. In addition, as the gate electrode 402, it is also possible to use a semiconductor film such as a polysilicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide.

In addition, as the material of the gate electrode 402, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin oxide containing titanium oxide can also be used. , Indium oxide zinc oxide, indium tin oxide added with silicon oxide and other conductive materials.

Alternatively, as the material of the gate electrode 402, In-Ga-Zn-based oxide containing nitrogen, In-Sn-based oxide containing nitrogen, In-Ga-based oxide containing nitrogen, and In-Zn containing nitrogen can also be used. Type oxide, Sn type oxide containing nitrogen, In type oxide containing nitrogen, metal nitride film (indium nitride film, zinc nitride film, tantalum nitride film, tungsten nitride film, etc.). Since the above-mentioned material has a work function of 5 electron volts or more, by using the above-mentioned material to form the gate electrode 402, the threshold voltage in the electrical characteristics of the transistor can be made a positive value, thereby achieving a normally-off (normally-off) Switching transistors. In addition, the gate electrode 402 may have a single-layer structure or a laminated structure in which copper is formed on tantalum nitride, for example. The gate electrode 402 may have a tapered shape. For example, the tapered angle may be set to 15° or more and 70° or less. Here, the taper angle refers to the angle formed by the side end surface of the layer having a tapered shape and the bottom surface of the layer.

Next, a gate insulating film 404 is formed on the gate electrode 402 so as to cover the gate electrode 402 (refer to FIG. 2A). As a gate insulating film 404. Form a silicon oxide film, a silicon oxynitride film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, and a zirconium oxide film by a plasma CVD method, a sputtering method, etc. , Gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film, a single layer or a stack of one or more insulating films. In addition, it is preferable to perform a microwave plasma treatment for repairing oxygen defects after forming the gate insulating film 404, and then perform a radical oxidation treatment.

Note that in this specification and the like, "oxynitride" such as silicon oxynitride refers to a substance whose composition contains more oxygen than nitrogen.

In addition, in this specification and the like, "oxynitride" such as silicon oxynitride or the like refers to a substance having a nitrogen content greater than an oxygen content in its composition.

In addition, in the gate insulating film 404, the region in contact with the semiconductor film 406 formed later (the gate insulating film 404b in this embodiment) is preferably an oxide insulating film.

Next, a semiconductor film 406 is formed on the gate insulating film 404 (refer to FIG. 2B).

As the semiconductor film 406, an amorphous semiconductor film, a polycrystalline semiconductor film, or a microcrystalline semiconductor film can be used. In addition, as the material of the amorphous semiconductor film, silicon, silicon germanium (SiGe) alloy, or the like can be used. In addition, an oxide semiconductor film can also be used.

Next, a conductive film is formed on the semiconductor film 406, and the conductive film is processed into a source electrode 408a and a drain electrode 408b (including wiring formed in the same layer) by etching (see FIG. 2C).

As the source electrode 408a and the drain electrode 408b, for example, you can use A conductive film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. containing the above elements as components . In addition, high melting point conductive films of Ti, Mo, W, etc. or their metal nitride films (titanium nitride film, nitrogen Molybdenum film, tungsten nitride film). In addition, the source electrode 408a and the drain electrode 408b may also be formed using conductive metal oxide. As the conductive metal oxide, for example, indium oxide (In₂O₃), tin oxide (SnO₂), zinc oxide (ZnO), indium oxide tin oxide (In₂O₃-SnO₂), indium oxide zinc oxide (In₂O₃-ZnO) or materials containing silicon oxide in these metal oxide materials.

In addition, as the source electrode 408a and the drain electrode 408b, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen, and an In-Ga-Zn-O film containing nitrogen can be used as the source electrode 408a and the drain electrode 408b. -Metal nitride films such as Zn-O film, Sn-O film containing nitrogen, In-O film containing nitrogen. In addition, the ends of the source electrode 408a and the drain electrode 408b are preferably tapered. By adopting the above steps, the coverage of the insulating film can be improved and disconnection can be prevented. Here, the taper angle is set to 30° or more and 70° or less, preferably 30° or more and 60° or less.

In addition, when due to the interface characteristics of the film adhesion and conductivity, as shown in FIG. 8A, the source electrode 408a and the drain electrode 408b form a laminated structure of a conductive film 407a, a conductive film 407b, and a conductive film 407c. At this time, in the case of processing a stack of conductive films by etching treatment, the etching rate differs depending on the type of conductive film. Therefore, as shown in FIG. 8B, the side end surface of the conductive film 407c is in contact with the top surface of the conductive film 407b, and the conductive film 407b The side end surface of the electrode is in contact with the top surface of the conductive film 407a, thereby generating steps on the side end surfaces of the source electrode 408a and the drain electrode 408b.

Due to this step, a void portion as shown in FIG. 8C is generated in the oxide insulating film 410 to be formed later. In addition, although the present embodiment is described with reference to the laminated structure of the conductive film having distinct steps on the side end surfaces of the source electrode 408a and the drain electrode 408b, it is not limited to this, and the single layer structure of the conductive film Also, voids are generated in the oxide insulating film 410 to be formed later due to the corners of the side end surfaces. The void portion in the oxide insulating film 410 will be described later.

Next, an oxide insulating film 410 which is a part of the insulating film 412 is formed so as to cover the gate insulating film 404, the semiconductor film 406, the source electrode 408a, and the drain electrode 408b (see FIG. 3A).

The oxide insulating film 410 is a laminated film of the oxide insulating film 410a and the oxide insulating film 410b. It can be formed by a plasma CVD method or a sputtering method, and since it is in contact with the semiconductor film 406, it is preferably as As the oxide insulating film 410, a film capable of supplying oxygen to the semiconductor film 406 is used. In addition, as the oxide insulating film 410, a single layer or a stacked layer of a silicon oxide film, a silicon oxynitride film, or the like can be used. In addition, as the oxide insulating film 410, a gallium oxide film, an aluminum oxide film, an aluminum oxynitride film, or the like can also be used.

The silicon oxide film or silicon oxynitride film can be formed as the oxide insulating film 410a under the following conditions: the substrate mounted in the vacuum-evacuated processing chamber of the plasma CVD equipment is maintained at 300°C or higher and 400°C or lower , It is more preferable to keep the temperature at 320°C or higher and 370°C or lower, introduce the raw material gas into the processing chamber, and set the pressure in the processing chamber to 100Pa or higher and 250 Pa or less, and high-frequency power is supplied to the electrodes provided in the processing chamber.

Under these film forming conditions, by setting the substrate temperature to the above-mentioned temperature, the bonding force between silicon and oxygen becomes stronger. As a result, an oxygen-permeable, dense and hard oxide insulating film can be formed as the oxide insulating film 410a. Typically, the etching rate for 0.5 weight% hydrofluoric acid at 25° C. is 10 nm/min or less, preferably It is a silicon oxide film or silicon oxynitride film of 8nm/min or less.

Here, as the oxide insulating film 410a, a plasma CVD method is performed to form a silicon oxynitride film with a thickness of 50 nm under the following conditions: silane with a flow rate of 30 sccm and nitrous oxide with a flow rate of 4000 sccm are used as source gases, The pressure in the processing chamber is 200 Pa, the substrate temperature is 220°C, and a 27.12 MHz high-frequency power supply is used to supply 150 W of high-frequency power to the parallel plate electrodes. Under these conditions, a silicon oxynitride film permeable to oxygen can be formed.

As the oxide insulating film 410b, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate mounted in the evacuated processing chamber of the plasma CVD equipment is maintained at 180°C or higher and 260°C or lower , It is more preferable to maintain the temperature of 200°C or higher and 240°C or lower, introduce the raw material gas into the processing chamber, and set the pressure in the processing chamber to 100Pa or higher and 250Pa or lower, more preferably 100Pa or higher and 200Pa or lower, and The electrode set in the processing chamber supplies high-frequency power, that is, 0.17W/cm²Above and 0.5W/cm²Below, preferably 0.25W/cm²Above and 0.35W/cm²the following.

As the source gas of the oxide insulating film 410b, it is preferable to use a package Deposition gas and oxidizing gas containing silicon. As typical examples of the deposition gas containing silicon, there are silane, ethyl silane, propyl silane, fluorinated silane, and the like. As the oxidizing gas, there are oxygen, ozone, nitrous oxide, nitrogen dioxide, and the like.

As the film forming condition of the oxide insulating film 410b, the high-frequency power with the above-mentioned power density is supplied in the above-mentioned pressure processing chamber, so the decomposition efficiency of the raw material gas in the plasma increases, the oxygen radicals increase, and the raw material gas The oxidation progresses, so the oxygen content in the oxide insulating film 410b exceeds the stoichiometric composition. However, when the substrate temperature is the above-mentioned temperature, since the bonding force between silicon and oxygen is low, part of the oxygen is released due to heating. As a result, it is possible to form an oxide insulating film that contains more oxygen than the oxygen that satisfies the stoichiometric composition and part of the oxygen is released by heating. In addition, an oxide insulating film 410a is provided on the semiconductor film 406. Therefore, in the formation process of the oxide insulating film 410b, the oxide insulating film 410a becomes a protective film of the semiconductor film 406. As a result, the oxide insulating film 410b can be formed using high-frequency power with high power density while reducing damage to the semiconductor film 406.

In this way, the oxide insulating film 410 is preferably an oxide insulating film 410a and an oxide insulating film 410a that are in contact with the semiconductor film 406, the source electrode 408a, and the drain electrode 408b, and are formed under low power conditions and have high coverage. The stacked structure of the oxide insulating film 410b on the upper surface.

In addition, when the side end surfaces of the source electrode 408a and the drain electrode 408b are stepped, a void 413 as shown in FIG. 8C is generated when the oxide insulating film 410 is formed. By using STEM (Scanning Transmission Electron Microscopy: Scanning Transmission Electron Microscopy) Observing the cross-sectional shape of the insulating film 412 with a mirror) method, such a void 413 can be confirmed. Since the dielectric constant of the void portion 413 is lower than that of the film forming the void portion 413, it is possible to reduce the capacitance between the wirings caused by the miniaturization of the semiconductor device, and to perform high-speed operation while maintaining a high degree of integration.

In addition, the oxide insulating film 410 is a low-density film having voids in the film. The oxide insulating film 410 has a feature that the film density of the entire film is low due to void portions (low-density regions).

The film density of the entire insulating film 412 measured by X-ray reflectometry (XRR: X-ray Reflectometry) is preferably 2.26 g/cm³Above and 2.50g/cm³the following.

The heat treatment may be performed after the oxide insulating film 410 is formed. The temperature of this heat treatment is typically 150°C or higher and lower than the strain point of the substrate, preferably 200°C or higher and 450°C or lower, and more preferably 300°C or higher and 450°C or lower.

Next, a nitride insulating film 411 is formed to cover the oxide insulating film 410 (see FIG. 3B).

The nitride insulating film 411 can be formed by a plasma CVD method or a sputtering method using a single layer or a stacked layer of silicon nitride, silicon oxynitride, or the like. In addition, as the nitride insulating film 411, aluminum nitride, aluminum oxynitride, or the like can also be used. In addition, when a high-coverage film is used as the nitride insulating film 411, the steps of the side end surfaces of the source electrode 408a and the drain electrode 408b are smaller (the step is partially flattened), so it is not easy to generate Therefore, it is preferable. In addition, aluminum oxide may be used instead of the nitride insulating film 411.

The nitride insulating film 411 has a function of covering the voids generated in the oxide insulating film 410 due to the step of the side end surfaces of the source electrode 408a and the drain electrode 408b. Furthermore, by blocking the void portion by the nitride insulating film 411, the void portion can be prevented from expanding to the outside of the oxide insulating film 410. In addition, the void portion may be buried in the nitride insulating film 411. In addition, since the nitride insulating film 411 serves as a barrier film that suppresses the intrusion of hydrogen or hydrogen-containing compounds (water, etc.) into the semiconductor film 406 from the outside or the interlayer insulating film 414 formed later, the reliability of the transistor can be improved. .

Through the above steps, the transistor 450 of this embodiment can be formed.

Next, an interlayer insulating film 414 is formed on the transistor 450.

The interlayer insulating film 414 can use organic materials such as acrylic resin, epoxy resin, benzocyclobutene-based resin, polyimide, and polyamide. Furthermore, in addition to the above-mentioned organic materials, silicone resins and the like can also be used. In addition, a plurality of insulating films formed of the above-mentioned materials may be stacked to form the interlayer insulating film 414.

Next, an opening is provided in the insulating film 412 and the interlayer insulating film 414, and an electrode 416 electrically connected to the drain electrode 408b through the opening is formed on the interlayer insulating film 414 (see FIG. 3C).

For the electrode 416, the material represented as the source electrode 408a and the drain electrode 408b can be appropriately used. In addition, the electrode 416 may use a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide. Oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

As a result, the dielectric constant of the void portion of the oxide insulating film 410 is lower than that of the film forming the void portion. Therefore, it is possible to reduce the capacitance between wirings due to the miniaturization of the semiconductor device, and maintain a high degree of integration. Realize high-speed work. By blocking the void portion by the nitride insulating film 411, the void portion can be prevented from expanding to the outside of the oxide insulating film 410. In addition, the void portion may be buried in the nitride insulating film 411. In addition, since the nitride insulating film 411 serves as a barrier film for suppressing the intrusion of hydrogen or hydrogen-containing compounds (water, etc.) into the semiconductor film 406 from the outside or the interlayer insulating film 414 formed later, the reliability of the transistor 450 can be improved. sex.

As described above, the structure, method, etc. shown in this embodiment can be implemented in appropriate combination with the structure, method, etc. shown in other embodiments.

[Embodiment 2]

In this embodiment mode, a semiconductor device different from Embodiment Mode 1 will be described with reference to the drawings. 4A and 4B show a plan view and a cross-sectional view of a transistor 550 of a semiconductor device according to an embodiment of the present invention. FIG. 4A shows a top view of the transistor 550, and FIG. 4B is a cross-sectional view along the chain line CD shown in FIG. 4A. The transistor 550 shown in this embodiment is different from the transistor 450 shown in Embodiment 1 in that the transistor 550 has a top gate structure.

The transistor 550 shown in FIGS. 4A and 4B includes: a base insulating film 401 disposed on a substrate 400 having an insulating surface; a semiconductor film 406 disposed on the base insulating film 401; and a semiconductor film 406 disposed on the base insulating film 401 and the semiconductor film 406 The source electrode 408a and the drain electrode 408b; the gate covering the source electrode 408a and the drain electrode 408b and in contact with the semiconductor film 406 An insulating film 512; and a gate electrode 402 provided on the gate insulating film 512 and overlapping the semiconductor film 406. In addition, an interlayer insulating film 414 covering the transistor 550 and an electrode 416 on the interlayer insulating film 414 that are electrically connected to the drain electrode 408b through openings provided in the insulating film 412 and the interlayer insulating film 414 are also provided. In addition, although the electrode 416 is electrically connected to the drain electrode 408b in this embodiment, it is not limited to this and the electrode 416 may be electrically connected to the source electrode 408a.

In this embodiment, the gate insulating film 512 uses the oxide insulating film 510 of the first insulating film in contact with the semiconductor film 406, the source electrode 408a, and the drain electrode 408b, and the oxide insulating film 510 as a protective film. The second insulating film is a laminated structure of the nitride insulating film 511. In addition, the oxide insulating film 510 has an oxide insulating film 510a and an oxide on the oxide insulating film 510a that are in contact with the semiconductor film 406, the source electrode 408a, and the drain electrode 408b, and are formed under low power conditions and have high coverage. The laminated structure of the insulating film 510b.

In addition, due to the step of the side end surfaces of the source electrode 408a and the drain electrode 408b, a void 413 is generated in the oxide insulating film 510 covering the step. Since the dielectric constant of the void portion 413 is lower than that of the film forming the void portion 413, it is possible to reduce the capacitance between wirings caused by the miniaturization of the semiconductor device, and to achieve high-speed operation while maintaining a high integration. In addition, moisture invades into the semiconductor film 406 from the portion of the gap 413 and may adversely affect the characteristics of the transistor 550. However, by providing the nitride insulating film 511 on the oxide insulating film 510, it can cover the semiconductor film 406. The void portion of the oxide insulating film 510.

Furthermore, by blocking the void 413 by the nitride insulating film 511, the void 413 can be prevented from expanding to the outside of the oxide insulating film 510. In addition, the void portion 413 may be buried in the nitride insulating film 511 in some cases. In addition, the nitride insulating film 511 functions as a barrier film that suppresses the intrusion of hydrogen or a hydrogen-containing compound (water or the like) into the semiconductor film 406 from the outside or an interlayer insulating film 414 formed later.

Next, a method of manufacturing the transistor 550 will be described with reference to FIGS. 5A to 5C and FIGS. 6A to 6D.

First, a base insulating film 401 is formed on a substrate 400 having an insulating surface. Regarding the materials and manufacturing methods of the substrate 400 and the base insulating film 401, refer to the description of the substrate 400 and the gate insulating film 404 in the first embodiment.

Next, a semiconductor film 406 is formed on the base insulating film 401 (see FIG. 5A). For the material and manufacturing method of the semiconductor film 406, refer to the description of the semiconductor film 406 in the first embodiment.

Next, a conductive film is formed on the semiconductor film 406, and the conductive film is processed into a source electrode 408a and a drain electrode 408b (including wiring formed in the same layer) by etching (see FIG. 5B). For the material and manufacturing method of the source electrode 408a and the drain electrode 408b, reference can be made to the description of the source electrode 408a and the drain electrode 408b in the first embodiment.

In addition, as shown in the first embodiment, a step is generated on the side end surfaces of the source electrode 408a and the drain electrode 408b, and a void portion is generated in the gate insulating film 512 to be formed later due to the step. The gate insulating film will be explained later 512 in the gap.

Next, an oxide insulating film 510 which is a part of the gate insulating film 512 is formed so as to cover the base insulating film 401, the semiconductor film 406, the source electrode 408a, and the drain electrode 408b (see FIG. 5C).

In addition, it is preferable that the oxide insulating film 510 is in contact with the base insulating film 401, the semiconductor film 406, the source electrode 408a and the drain electrode 408b, and is formed under low power conditions and has high coverage. The laminated structure of the oxide insulating film 510b on the object insulating film 510a. For the material and manufacturing method of the oxide insulating film 510, refer to the description of the oxide insulating film 410 in the first embodiment.

In addition, when steps are generated on the side end surfaces of the source electrode 408a and the drain electrode 408b, when the oxide insulating film 510 is formed, a void 413 as shown in the first embodiment is generated. Since the dielectric constant of the void portion 413 is lower than that of the film forming the void portion 413, it is possible to reduce the capacitance between wirings caused by the miniaturization of the semiconductor device, and to achieve high-speed operation while maintaining a high integration.

In addition, the oxide insulating film 510b is a low-density film having voids 413 in the film. The oxide insulating film 510b has a feature that the film density of the entire film is low due to the low-density region.

The film density of the entire gate insulating film 512 measured by X-ray reflectometry (XRR: X-ray Reflectometry) is preferably 2.26 g/cm³Above and 2.50g/cm³the following.

Next, a nitride insulating film 511 is formed so as to cover the oxide insulating film 510 (see FIG. 6A). About the material and manufacture of the nitride insulating film 511 For the method and the like, reference can be made to the nitride insulating film 411 in Embodiment Mode 1.

The nitride insulating film 511 has a function of covering the voids generated in the oxide insulating film 510 due to the step of the side end surfaces of the source electrode 408a and the drain electrode 408b. Furthermore, by blocking the void portion by the nitride insulating film 511, it is possible to prevent the void portion from expanding to the outside of the oxide insulating film 510. In addition, the void portion may be buried in the nitride insulating film 511. In addition, since the nitride insulating film 511 serves as a barrier film for suppressing the intrusion of hydrogen or hydrogen-containing compounds (water, etc.) into the semiconductor film 406 from the outside or the interlayer insulating film 414 formed later, the reliability of the transistor can be improved. .

Next, a gate electrode 402 is formed on the gate insulating film 512 overlapping the semiconductor film 406 (see FIG. 6B). For the material and manufacturing method of the gate electrode 402, reference can be made to the description of the gate electrode 402 in the first embodiment.

Through the above steps, the transistor 550 of this embodiment can be formed.

Next, an interlayer insulating film 414 is formed on the transistor 550, an opening is provided in the insulating film 412 and the interlayer insulating film 414, and an electrode 416 electrically connected to the drain electrode 408b through the opening is formed on the interlayer insulating film 414. (Refer to Figure 6C). For the material and manufacturing method of the interlayer insulating film 414 and the electrode 416, refer to the interlayer insulating film 414 and the electrode 416 in the first embodiment.

In addition, as shown in FIG. 6D, an insulating film 530 composed of an oxide insulating film and a nitride insulating film may be provided on the gate electrode 402. By forming a nitride insulating film covering the oxide insulating film, voids are generated in the insulating film 530 due to the corners of the side end surfaces of the gate electrode 402. However, borrow The gap portion is blocked by the nitride insulating film, and the gap portion can be prevented from expanding to the outside of the oxide insulating film. In addition, the insulating film 530 may have a structure in which a nitride insulating film covers the oxide insulating film instead of the gate insulating film 512 having this structure.

As a result, the dielectric constant of the void portion of the oxide insulating film 510 is lower than that of the film forming the void portion. Therefore, it is possible to reduce the capacitance between wirings due to the miniaturization of the semiconductor device, and maintain a high degree of integration. Realize high-speed work. In addition, by blocking the void portion by the nitride insulating film 511, the void portion can be prevented from expanding to the outside of the oxide insulating film 510. In addition, the void portion may be buried in the nitride insulating film 511. In addition, since the nitride insulating film 511 serves as a barrier film for suppressing the penetration of hydrogen or hydrogen-containing compounds (water, etc.) into the semiconductor film 406 from the outside or the interlayer insulating film 414 formed later, the reliability of the transistor 550 can be improved. sex.

As described above, the structure, method, etc. shown in this embodiment can be implemented in appropriate combination with the structure, method, etc. shown in other embodiments.

[Embodiment 3]

In this embodiment mode, a semiconductor device different from Embodiment Mode 1 and Embodiment Mode 2 will be described with reference to FIGS. 7A to 7C.

The transistor 560 shown in FIG. 7A includes a plurality of gate electrodes opposed to each other with a semiconductor film 406 interposed therebetween. The transistor 560 includes: a gate electrode 552 and a base insulating film 401 provided on the gate electrode 552; a semiconductor film 406 provided on the base insulating film 401; and a base insulating film 401 provided on the base insulating film 401 And the source electrode on the semiconductor film 406 A gate electrode 408a and a drain electrode 408b; a gate insulating film 512 covering the source electrode 408a and the drain electrode 408b and in contact with the semiconductor film 406; and a gate electrode provided on the gate insulating film 512 and overlapping the semiconductor film 406 402. In addition, an interlayer insulating film 414 covering the transistor 560 and an electrode 416 on the interlayer insulating film 414 that are electrically connected to the drain electrode 408b through openings provided in the insulating film 412 and the interlayer insulating film 414 are also provided.

For the material and manufacturing method of the gate electrode 552, refer to the description of the gate electrode 402 in the first embodiment.

The transistor 560 shown in this embodiment includes a gate electrode 552 and a gate electrode 402 that face each other with a semiconductor film 406 therebetween. By applying different potentials to the gate electrode 552 and the gate electrode 402, the threshold voltage of the transistor 560 can be controlled. Alternatively, by applying the same potential to the gate electrode 552 and the gate electrode 402, the on-state current of the transistor 560 can be increased.

In addition, the oxide insulating film 410 does not necessarily need to adopt a two-layer structure. For example, the transistor 570 shown in FIG. 7B has a structure in which an oxide insulating film 410c is further provided on the oxide insulating film 410b of the oxide insulating film 410 of the transistor 450 of Embodiment 1. In addition, the transistor 580 shown in FIG. 7C has a structure in which a stacked layer of an oxide insulating film 410d and an oxide insulating film 410e is further provided on the oxide insulating film 410c. In addition, the oxide insulating film 410c and the oxide insulating film 410e may be the same as the oxide insulating film 410a, and the oxide insulating film 410d may be the same as the oxide insulating film 410b.

In addition, the oxide insulating film 410a formed with a lower power than the oxide insulating film 410b is a low-density film. The coverage is high, so the steps can be reduced by stacking in the above-mentioned method.

Moreover, by forming the oxide insulating film 410b denser than the oxide insulating film 410a on the oxide insulating film 410a, the effect of the oxide insulating film 410a (the step portion is flattened due to the high coverage of the step) On the other hand, voids due to steps are not easily generated in the oxide insulating film 410b.

In addition, in the semiconductor film 406, the thickness of the region in contact with the oxide insulating film 410a is smaller than the thickness of the region in contact with the source electrode 408a and the drain electrode 408b. In the semiconductor film 406, a part of the conductive film that becomes the source electrode 408a and the drain electrode 408b is etched when the source electrode 408a and the drain electrode 408b are processed, or by forming the source electrode 408a and the drain electrode 408b after the semiconductor film 406 is formed The exposed area is etched to form an area with a small thickness. This region is a region used as a channel formation region for transistor 570 and transistor 580.

In the semiconductor film 406, by reducing the thickness of the channel formation region, the resistance of the region in contact with the source electrode 408a and the drain electrode 408b can be lower than that of the channel formation region. Therefore, the contact resistance between the semiconductor film 406 and the source electrode 408a and the drain electrode 408b can be reduced.

As described above, the structure, method, etc. shown in this embodiment can be implemented in appropriate combination with the structure, method, etc. shown in other embodiments.

[Embodiment 4]

In this embodiment mode, a case where an oxide semiconductor film is used for the semiconductor film 406 in the above embodiment mode will be described.

Since the transistor using the oxide semiconductor film can suppress the current value in the off state (off-state current value) to be low, and can obtain a higher field-effect mobility, it can be driven at a high speed. In addition, in the above-mentioned embodiment, by forming the oxide insulating film under the nitride insulating film as a film capable of supplying oxygen, oxygen is released from the void part of the closed space due to the nitride insulating film during heating, and the The oxide semiconductor film supplies oxygen, so that the above-mentioned effects are more pronounced. The method of forming the oxide semiconductor film will be described below.

As the method of forming the oxide semiconductor film, sputtering method, MBE (Molecular Beam Epitaxy) method, CVD (Chemical Vapor Deposition) method, pulsed laser deposition (Pulsed Laser Deposition) method can be suitably used. : PLD) method, ALD (Atomic Layer Deposition) method, etc.

In addition, when the oxide semiconductor film contains a large amount of hydrogen, a part of the hydrogen becomes a donor due to the combination of hydrogen and the oxide semiconductor, and electrons as carriers are generated. Therefore, the threshold voltage of the transistor drifts to the negative direction. Therefore, in the oxide semiconductor film, the hydrogen concentration is less than 5×10¹⁸atoms/cm³, Preferably 1×10¹⁸atoms/cm³Below, more preferably 5×10¹⁷atoms/cm³Below, further preferably 1×10¹⁶atoms/cm³the following. In addition, the hydrogen concentration in the oxide semiconductor film was measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

For the above reasons, the gas used when forming the oxide semiconductor film preferably does not contain impurities such as water, hydrogen, hydroxyl groups, or hydrides. In other words, it is preferable to use a gas with a purity of 6N or more, preferably 7N or more (that is, the impurity concentration in the gas is 1 ppm or less, preferably 0.1 ppm or less).

In addition, when forming an oxide semiconductor film, in order to remove moisture (including water, water vapor, hydrogen, hydroxyl, or hydride) during film formation, it is preferable to use an adsorption-type vacuum pump, such as cryopump, ion pump, titanium sublimation Pump. In addition, a turbomolecular pump equipped with a cold trap can also be used as the exhaust unit. Because in the film forming chamber that uses cryopumps for exhaust, for example, hydrogen atoms, water (H₂O) and other compounds containing hydrogen atoms are exhausted (preferably, compounds containing carbon atoms are also exhausted), so it is possible to reduce the hydrogen, The concentration of impurities such as moisture.

Note that the relative density of the target used in the sputtering device is 90% or more and 100% or less, preferably 95% or more and 100% or less. By using a relatively high-density target material, the formed oxide semiconductor film becomes a dense film.

As the material of the oxide semiconductor film, for example, an In-M-Zn-O-based material can be used. Here, the metal element M is an element whose binding energy with oxygen is higher than that of In and Zn, or an element that has a function of suppressing the deintercalation of oxygen from the In-M-Zn-O-based material. Due to the action of the metal element M, the generation of oxygen vacancies in the oxide semiconductor film is suppressed. As a result, variations in the electrical characteristics of the transistor due to oxygen defects can be reduced, and a highly reliable transistor can be obtained. body.

Specifically, as the metal element M, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga, Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta or W, preferably Al, Ti, Ga, Y, Zr, Ce or Hf is used. As the metal element M, one or two or more of the above-mentioned elements can be selected. Alternatively, Ge may be used instead of the metal element M.

Here, in an oxide semiconductor expressed as an In-M-Zn-O-based material, the higher the In concentration, the higher the carrier mobility and carrier density. As a result, in this oxide semiconductor, the higher the In concentration, the higher the conductivity.

The structure of the oxide semiconductor film is explained below.

The oxide semiconductor film is roughly classified into a single crystal oxide semiconductor film and a non-single crystal oxide semiconductor film. Non-single crystal oxide semiconductor films include amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, polycrystalline oxide semiconductor films, and CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) films Wait.

The amorphous oxide semiconductor film has a disordered atomic arrangement and does not have a crystalline component. A typical example of this is an oxide semiconductor film that does not have crystal portions in a minute region, and the entire film has a complete amorphous structure.

The microcrystalline oxide semiconductor film includes, for example, microcrystals (also referred to as nanocrystals) having a size of 1 nm or more and less than 10 nm. Therefore, microcrystalline oxide semiconducting ordered arrangement of atoms film is higher than that of the amorphous oxide semiconductor film. Therefore, the defect state density of the microcrystalline oxide semiconductor film is lower than that of the amorphous oxide semiconductor film. Conductor film.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts have a size that can be accommodated in a cube whose one side is shorter than 100 nm. Therefore, the size of the crystal part included in the CAAC-OS film may be a size that can be accommodated in a cube whose one side is shorter than 10 nm, shorter than 5 nm, or shorter than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film. Hereinafter, the CAAC-OS film will be described in detail.

In the transmission electron microscope (TEM: Transmission Electron Microscope) image of the CAAC-OS film, no clear boundary between the crystal part and the crystal part, that is, the grain boundary, is not observed. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries does not easily occur.

According to the TEM image (cross-sectional TEM image) of the CAAC-OS film observed from a direction substantially parallel to the sample surface, it can be seen that the metal atoms are arranged in layers in the crystal portion. Each metal atomic layer has a shape that reflects the surface on which the CAAC-OS film is formed (also referred to as the formed surface) or the convex and concave shapes of the top surface of the CAAC-OS film and is parallel to the formed surface or top surface of the CAAC-OS film arrangement.

On the other hand, from the TEM image (planar TEM image) of the CAAC-OS film observed from a direction substantially perpendicular to the sample surface, it can be seen that the metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal portion. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

It can be seen from the cross-sectional TEM image and the plane TEM image that CAAC-OS The crystalline part of the film has orientation.

X-ray diffraction (XRD: X-Ray Diffraction) device was used to analyze the structure of the CAAC-OS film. For example, when using out-of-plane analysis including InGaZnO₄In the case of a crystalline CAAC-OS film, a peak often appears around a diffraction angle (2θ) of 31°. Since the peak is derived from InGaZnO₄The (009) plane of the crystal shows that the crystal in the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or top surface of the CAAC-OS film.

On the other hand, when the CAAC-OS film is analyzed by the in-plane method in which X-rays are incident on the sample from a direction substantially perpendicular to the c-axis, a peak often appears around 56° in 2θ. This peak comes from InGaZnO₄Crystalline (110) plane. Here, 2θ is fixed at around 56° and the normal vector of the sample surface is taken as the axis (<img file="TW201409708A_D0001.tif" wi="46" he="64" img-format="tif" img-content="character" orientation="portrait" inline="no" />Axis) Analyze under the condition of rotating the sample (<img file="TW201409708A_D0002.tif" wi="44" he="66" img-format="tif" img-content="character" orientation="portrait" inline="no" />scanning). When the sample is InGaZnO₄The single crystal oxide semiconductor film has six peaks. The six peaks are derived from crystal planes equal to the (110) plane. On the other hand, when the sample is a CAAC-OS film, even when 2θ is fixed to around 56°<img file="TW201409708A_D0003.tif" wi="49" he="64" img-format="tif" img-content="character" orientation="portrait" inline="no" />Scanning also cannot observe clear peaks.

From the above results, it can be seen that in the CAAC-OS film with c-axis alignment, although the directions of the a-axis and the b-axis are different between the crystal parts, the c-axis is oriented parallel to the normal vector of the surface to be formed or the top surface. direction. Therefore, each metal atom layer arranged in a layered shape observed in the cross-sectional TEM image corresponds to a plane parallel to the ab plane of the crystal.

Note that the crystal portion is formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As mentioned above, the orientation of the c-axis of the crystal is parallel to The direction of the normal vector of the formed surface or top surface of the CAAC-OS film. Thus, for example, when the shape of the CAAC-OS film is changed due to etching or the like, the c-axis of the crystal is not necessarily parallel to the normal vector of the formed surface or the top surface of the CAAC-OS film.

In addition, the degree of crystallization in the CAAC-OS film is not necessarily uniform. For example, when the crystal portion of the CAAC-OS film is formed by crystal growth near the top surface of the CAAC-OS film, the degree of crystallinity near the top surface may be higher than the degree of crystallinity near the surface to be formed. In addition, when impurities are added to the CAAC-OS film, the degree of crystallinity of the region to which the impurities are added changes, so the degree of crystallinity in the CAAC-OS film may vary depending on the region.

Note that when using out-of-plane analysis including InGaZnO₄In the case of a crystalline CAAC-OS film, in addition to a peak at 2θ around 31°, a peak at 2θ around 36° may be observed. The 2θ peak at around 36° means that a part of the CAAC-OS film contains crystals that do not have c-axis alignment. Preferably, in the CAAC-OS film, a peak appears when 2θ is around 31° and does not appear when 2θ is around 36°.

In the transistor using the CAAC-OS film, the change in electrical characteristics due to irradiation of visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Note that the oxide semiconductor film may be, for example, a stacked film including two or more types of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

The CAAC-OS film uses, for example, a polycrystalline oxide semiconductor sputtering target and is formed by a sputtering method. When ions collide with the sputtering target, The crystalline region contained in the sputtering target material may split along the ab plane, that is, the flat or granular sputtering particles having a plane parallel to the ab plane may peel off. At this time, by allowing the flat sputtered particles to reach the substrate while maintaining the crystalline state, the CAAC-OS film can be formed.

In addition, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

By reducing the mixing of impurities during film formation, it is possible to suppress damage to the crystalline state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) existing in the film forming chamber may be reduced. In addition, it is only necessary to reduce the impurity concentration in the film forming gas. Specifically, a film-forming gas having a dew point of -80°C or lower, preferably -100°C or lower, and more preferably -120°C or lower is used.

In addition, by increasing the substrate heating temperature during film formation, migration of the sputtered particles occurs after the sputtered particles reach the substrate. Specifically, the film formation is performed in a state where the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate heating temperature during film formation, when the flat sputtered particles reach the substrate, they migrate on the substrate, and the flat surface of the sputtered particles adhere to the substrate.

In addition, it is preferable to reduce the plasma damage during the film formation by increasing the oxygen ratio in the film forming gas and optimizing the power. The oxygen ratio in the film-forming gas is set to 30 vol% or more, preferably 100 vol%.

Hereinafter, an In-Ga-Zn-based oxide target is shown as an example of a sputtering target.

InO_XPowder, GaO_YPowder and ZnO_ZPowder in prescribed moles The numbers are mixed, pressure treatment is performed, and then heat treatment is performed at a temperature of 1000° C. or higher and 1500° C. or lower, thereby obtaining a polycrystalline In-Ga-Zn-based oxide target material. In addition, X, Y, and Z are arbitrary positive numbers. Here, InO_XPowder, GaO_YPowder and ZnO_ZThe predetermined molar ratio of the powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. In addition, the type of powder and the molar ratio at the time of mixing the powder can be appropriately changed according to the sputtering target to be manufactured.

In addition, immediately after the film is formed, the oxide semiconductor film is preferably in a supersaturated state containing more than the stoichiometric composition of oxygen. For example, when forming an oxide semiconductor film by a sputtering method, it is preferable to form the film under the condition that the proportion of oxygen in the film-forming gas is high, and in particular, it is preferable to perform the film formation in an oxygen atmosphere (oxygen gas is 100%). ) Under the film formation. When the film is formed under conditions where the proportion of oxygen in the film-forming gas is high, especially in an atmosphere where the oxygen gas is 100%, even if the film-forming temperature is set to 300°C or higher, the release from the film can be suppressed. Zn.

In addition, the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. For example, a stack of a first oxide semiconductor film and a second oxide semiconductor film may be used as the oxide semiconductor film, and metal oxides of different compositions may be used for the first oxide semiconductor film and the second oxide semiconductor film. . For example, an oxide containing three metal elements may be used as the first oxide semiconductor film, and an oxide containing two metal elements may be used as the second oxide semiconductor film. In addition, for example, an oxide containing three metal elements may be used as both the first oxide semiconductor film and the second oxide semiconductor film.

In addition, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and the composition of the two may be different. For example, the atomic ratio of the first oxide semiconductor film may be set to In:Ga:Zn=1:1:1, and the atomic ratio of the second oxide semiconductor film may be set to In:Ga:Zn=3: 1:2. In addition, the atomic ratio of the first oxide semiconductor film may be set to In:Ga:Zn=1:3:2, and the atomic ratio of the second oxide semiconductor film may be set to In:Ga:Zn=2: 1:3.

At this time, it is preferable to set the In and Ga content ratios of the oxide semiconductor film on the side closer to the gate electrode of the first oxide semiconductor film and the second oxide semiconductor film to In&gt;Ga. In addition, it is preferable to set the In and Ga content ratios of the oxide semiconductor film on the far side from the gate electrode to In<img file="TW201409708A_D0004.tif" wi="49" he="64" img-format="tif" img-content="character" orientation="portrait" inline="no" />Ga.

In oxide semiconductors, the s-orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the content rate of In, the overlap rate of the s-orbitals tends to increase, and thus the mobility of oxides with the composition of In&gt;Ga Than having In<img file="TW201409708A_D0005.tif" wi="56" he="54" img-format="tif" img-content="character" orientation="portrait" inline="no" />The composition of Ga has a high oxide. In addition, the formation energy of oxygen vacancies in Ga is larger than that in In, and Ga is less prone to oxygen vacancies, so it has In<img file="TW201409708A_D0006.tif" wi="59" he="59" img-format="tif" img-content="character" orientation="portrait" inline="no" />The oxide of the composition of Ga has stable characteristics compared with the oxide of the composition of In&gt;Ga.

By using an oxide semiconductor with the composition of In&gt;Ga on the channel side and the back channel side (the opposite side of the channel) with In<img file="TW201409708A_D0007.tif" wi="61" he="61" img-format="tif" img-content="character" orientation="portrait" inline="no" />An oxide semiconductor composed of Ga can further improve the mobility and reliability of the transistor.

In addition, it can also be used as a first oxide semiconductor film and a second oxide As the semiconductor film, oxide semiconductors with different crystallinities are used. That is, it is also possible to adopt a structure in which a single crystal oxide semiconductor film, a polycrystalline oxide semiconductor film, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CAAC-OS film is appropriately combined. In addition, when an amorphous oxide semiconductor is used as at least one of the first oxide semiconductor film and the second oxide semiconductor film, the internal stress or external stress of the oxide semiconductor film can be alleviated, and the characteristic unevenness of the transistor can be reduced. And further improve the reliability of the transistor.

On the other hand, an amorphous oxide semiconductor easily absorbs impurities that become a donor, such as hydrogen, and is prone to oxygen vacancies, making it easy to become n-type. Therefore, it is preferable to use a crystalline oxide semiconductor such as a CAAC-OS film for the oxide semiconductor film on the channel side.

In addition, as the oxide semiconductor film, a stacked structure of three or more layers may be adopted, in which an amorphous semiconductor film is sandwiched between a plurality of crystalline semiconductor films. In addition, a structure in which a crystalline semiconductor film and an amorphous semiconductor film are alternately laminated may also be adopted.

In addition, when a stacked structure of a plurality of layers is adopted as the oxide semiconductor film, the above-mentioned structures can be appropriately combined and used.

In addition, a stacked structure of a plurality of layers may be adopted as the oxide semiconductor film, and oxygen may be added every time after each oxide semiconductor film is formed. As a method of adding oxygen, heat treatment in an oxygen atmosphere, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment in an atmosphere containing oxygen, and the like can be used.

By adding oxygen each time each oxide semiconductor film is formed, it is possible to improve Highly effective in reducing oxygen defects in oxide semiconductors.

In addition, as the insulating film in contact with the oxide semiconductor film, the film density of the entire film measured by X-ray reflectivity (XRR: X-ray Reflectometry) is preferably 2.26 g/cm³Above and 2.50g/cm³the following. An insulating film having a film density in this range can have a high oxygen release amount.

Before the insulating film is formed, after the active species of the raw material gas is adsorbed on the surface to be formed (here, the top surface of the source electrode and the drain electrode), the active species swims on the surface to be formed. The insulating film is a film capable of supplying oxygen, and the dangling bonds of the active species of the raw material gas are blocked and stabilized by excess oxygen in the insulating film, and the movement amount of the active species of the raw material gas migrating on the surface to be formed is reduced. Corresponding to this, since there are portions where film formation is not easy due to the step portion or the like, void portions are likely to be generated. In addition, the active species of the raw material gas of the film to be formed later do not easily penetrate into the void portion, and the void portion further expands.

In addition, since the void portion can be formed as a closed space by forming the nitride insulating film, and the void portion that becomes the closed space can extract a large amount of oxygen, the amount of oxygen released from the oxide insulating film can be increased when heating is performed. Therefore, oxygen vacancies in the oxide semiconductor film can be filled with oxygen from the oxide insulating film, so that the reliability of the transistor can be improved.

In addition, when the oxide insulating film is laminated as shown in FIGS. 7B and 7C of Embodiment 3, since the oxide insulating film 410b supplies oxygen to the oxide semiconductor film, nitrogen is formed in contact with the oxide insulating film 410b with high applied power. When the oxide insulating film 411 is formed, excess oxygen contained in the oxide insulating film 410b is released, which may cause a decrease in oxygen supply capability.

Therefore, by providing the oxide insulating film 410c and the oxide insulating film 410e directly under the nitride insulating film 411, the oxide insulating film 410b or the oxide insulating film 410d caused by the formation of the nitride insulating film 411 can be suppressed. The reduction of oxygen supply capacity.

Next, a model in which nitrogen, hydrogen, and water in the oxide semiconductor film 31 and the oxide insulating film 32 capable of supplying oxygen move by heat treatment will be described with reference to FIGS. 25A to 27C. In addition, in FIGS. 25A to 27C, the dashed cut-out heads indicate the movement of various atoms by heating, and the solid arrows indicate changes during or before and after the heating treatment. In addition, as the oxide insulating film 32, an oxide insulating film containing more oxygen than the oxygen satisfying the stoichiometric composition is used for description.

25A to 25C show models that can be mainly produced by heating in the oxide insulating film 32.

FIG. 25A shows the behavior of the nitrogen atom by the heat treatment. FIG. 25A shows that the nitrogen atoms N (here, two nitrogen atoms) contained in the oxide insulating film 32 are combined in the oxide insulating film 32 or on the surface thereof by a heat treatment, and become nitrogen molecules, which are removed from the oxide insulating film 32 De-embedded model.

FIG. 25B is a model showing the behavior of oxygen atoms by heat treatment. Oxygen atoms (exO, here, two oxygen atoms) contained in the oxide insulating film 32 more than oxygen satisfying the stoichiometric composition are combined in the oxide insulating film 32 or on the surface thereof to become oxygen molecules by heat treatment. However, it is released from the oxide insulating film 32.

FIG. 25C is a model showing the behavior of hydrogen atoms and oxygen atoms by heat treatment. The hydrogen atoms H contained in the oxide insulating film 32 (here, two One hydrogen atom) and oxygen atoms exO that are more than oxygen that satisfies the stoichiometric composition are combined in the oxide insulating film 32 or on the surface thereof by heat treatment, and become water molecules, which are released from the oxide insulating film 32.

FIG. 25D is a model showing the behavior of water molecules treated by heat. The water molecules contained in the oxide insulating film 32 are released from the oxide insulating film 32 by heat treatment.

As shown in the above model, one or more of nitrogen, hydrogen, and water are deintercalated from the oxide insulating film 32 by heat treatment, so that the content of nitrogen, hydrogen, and water in the film can be reduced.

Next, a model that may be generated when the oxide semiconductor film 31 is heated will be described with reference to FIGS. 26A to 26E.

FIG. 26A is a model showing the behavior of nitrogen atoms by heat treatment. The nitrogen atoms N (here, two nitrogen atoms) contained in the oxide semiconductor film 31 are heated in the oxide semiconductor film 31, the interface between the oxide semiconductor film 31 and the oxide insulating film 32, and the oxide The insulating film 32 is bonded to or on the surface thereof, becomes nitrogen molecules, and is released from the oxide semiconductor film 31.

FIG. 26B is a model showing the behavior of hydrogen atoms and oxygen atoms by heat treatment. After the hydrogen atoms H (here, two hydrogen atoms) contained in the oxide semiconductor film 31 are transferred to the oxide insulating film 32 by the heat treatment, the hydrogen atoms H in the oxide insulating film 32 or on the surface thereof are compared with Oxygen atoms exO with a large amount of oxygen satisfying the stoichiometric composition combine to form water molecules and are released from the oxide insulating film 32.

FIG. 26C is another diagram showing hydrogen atoms and oxygen atoms treated by heat A model of action. The hydrogen atoms H contained in the oxide semiconductor film 31 are heated in the oxide semiconductor film 31 or the interface between the oxide semiconductor film 31 and the oxide insulating film 32 and oxygen atoms that are more than the oxygen that satisfies the stoichiometric composition. exO binds to become water molecules, and is released from the oxide insulating film 32.

26D and 26E are models showing another behavior of hydrogen atoms and oxygen atoms by heat treatment. The hydrogen atoms H and oxygen atoms O contained in the oxide semiconductor film 31 are processed by heating in the oxide semiconductor film 31, the interface between the oxide semiconductor film 31 and the oxide insulating film 32, the oxide insulating film 32, or The surface is bonded and becomes water molecules, which are released from the oxide insulating film 32. At this time, in the oxide semiconductor film 31, as shown in FIG. 26E, the position where the oxygen atoms are deintercalated becomes the oxygen defect Vo, but the oxide insulating film 32 contains more oxygen atoms exO than the oxygen that satisfies the stoichiometric composition. It moves to the position of the oxygen defect Vo, fills the oxygen defect Vo, and becomes an oxygen atom O.

As a result, one or more of nitrogen, hydrogen, and water are released from the oxide semiconductor film 31 by the heat treatment, so that the content of nitrogen, hydrogen, and water in the film can be reduced.

Next, a model of the oxygen defect change of the oxide semiconductor film 31 by the heat treatment will be described with reference to FIGS. 27A to 27C.

When oxygen more than the oxygen satisfying the stoichiometric composition moves to the oxide semiconductor film 31, the oxygen more than the oxygen satisfying the stoichiometric composition pushes out the first oxygen atom from the position of the first oxygen atom. In addition, the pushed out first oxygen atom moves to the position of the second oxygen atom and pushes out the second oxygen atom. picture In this way, when more oxygen than the oxygen that satisfies the stoichiometric composition moves to the oxide semiconductor film 31, the ejection of the oxygen atoms is sequentially repeated among the plurality of oxygen atoms. In FIGS. 27A to 27C, the introduction of oxygen atoms among a plurality of oxygen atoms is omitted, and the three oxygen vacancies (Vo_1 to Vo_3) included in the oxide semiconductor film 31 and the oxide insulating film 32 capable of supplying oxygen are used. The oxygen contained, specifically, more oxygen atoms (exO_1 to exO_3) than oxygen that satisfies the stoichiometric composition is a model for explaining changes in oxygen defects. Note that the oxide insulating film 32 is a laminated film of an oxide insulating film 32a that is formed under low power conditions and has high coverage and an oxide insulating film 32b capable of supplying oxygen.

27A to 27C show the three oxygen vacancies (Vo_1 to Vo_3) contained in the oxide semiconductor film 31 and the oxygen contained in the oxide insulating film 32b capable of supplying oxygen. Specifically, the oxygen contained in the oxide insulating film 32b is higher than the oxygen that satisfies the stoichiometric composition. More oxygen atoms (exO_1 to exO_3).

FIG. 27A shows the reaction of the oxygen defect Vo_1 and the oxygen atom exO_1 by the heat treatment. The oxygen atoms exO_1 having more oxygen than the oxygen satisfying the stoichiometric composition move to the position of the oxygen defect Vo_1 included in the oxide semiconductor film 31 by the heat treatment, fill the oxygen defect Vo_1, and become the oxygen atom O_1.

Next, as shown in FIG. 27B, when oxygen atoms exO_2 having more oxygen than satisfying the stoichiometric composition are closer to the position of the oxygen atom O_1 contained in the oxide semiconductor film 31, the oxygen atom O is deintercalated from the position of the oxygen atom O_1. The released oxygen atom O moves to the position of the oxygen defect Vo_2, fills the oxygen defect Vo_2, and becomes the oxygen atom O_2. On the other hand, although the oxygen atoms are de-intercalated The position of the oxygen atom O_1 becomes an oxygen defect, but the oxygen atom exO_2 moves to the position of the oxygen defect and becomes an oxygen atom O_1a.

Next, as shown in FIG. 27C, when oxygen atoms exO_3 having more oxygen than satisfying the stoichiometric composition are closer to the position of the oxygen atom O_1a contained in the oxide semiconductor film 31, the oxygen atom O is deintercalated from the position of the oxygen atom O_1a. The deintercalated oxygen atom O moves to the position of the oxygen atom O_2. The oxygen atom O is deintercalated from the oxygen atom O_2. The released oxygen atom O fills the oxygen defect Vo_3 and becomes the oxygen atom O_3. On the other hand, although the position of the oxygen atom O_1a from which the oxygen atom is released becomes an oxygen defect, the oxygen atom exO_3 moves to the position of the oxygen defect and becomes an oxygen atom O_1b. In addition, although the position of the oxygen atom O_2 from which the oxygen atom is desorbed also becomes an oxygen defect, the oxygen desorbed from the oxygen atom O_1a moves to the position of the oxygen defect and becomes the oxygen atom O_2a.

Through the above process, the oxygen contained in the oxide insulating film 32b capable of supplying oxygen can fill the oxygen defects contained in the oxide semiconductor film 31. In addition, the heat treatment not only fills the oxygen vacancies on the surface of the oxide semiconductor film 31 but also fills the oxygen vacancies in the film. Thus, by forming the oxide insulating film 32b capable of supplying oxygen while heating, or performing heat treatment after providing the oxide insulating film 32b capable of supplying oxygen, the amount of oxygen defects contained in the oxide semiconductor film 31 can be reduced. .

In addition, by providing an oxygen-permeable oxide insulating film as an oxide insulating film 32a in the back channel of the oxide semiconductor film 31, an oxide insulating film 32b containing more oxygen than oxygen that satisfies the stoichiometric composition can be provided. Move oxygen to the back channel side of the oxide semiconductor film 31 and reduce the

Oxygen defects on one side of the back channel.

As described above, the structure, method, etc. shown in this embodiment can be implemented in appropriate combination with the structure, method, etc. shown in other embodiments.

[Embodiment 5]

A semiconductor device with a display function (also referred to as a display device) can be manufactured by using the transistor shown as an example in the above embodiment. In addition, a system-on-panel can be formed by integrally forming a part or the entire part of the driving circuit including the transistor and the pixel portion on the same substrate. In this embodiment, an example of a display device using the transistor shown as an example in the above embodiment will be described with reference to FIGS. 9A to 12C. Note that FIGS. 10A, 10B, and 11 are cross-sectional views showing the cross-sectional structure along the chain line MN in FIG. 9B.

In FIG. 9A, a sealing material 905 is provided so as to surround the pixel portion 902 provided on the first substrate 901, and the second substrate 906 is used for sealing. In FIG. 9A, a signal line driver circuit 903 and a scanning line formed on a separately prepared substrate using a single crystal semiconductor or a polycrystalline semiconductor are mounted on the first substrate 901 in a region different from the region surrounded by the sealing material 905. Drive circuit 904. In addition, various signals and potentials supplied to the signal line driving circuit 903, the scanning line driving circuit 904, or the pixel portion 902 are supplied from FPC (Flexible printed circuit) 918a and FPC 918b.

In FIGS. 9B and 9C, the The pixel portion 902 and the scanning line drive circuit 904 are provided with a sealing material 905. In addition, a second substrate 906 is provided on the pixel portion 902 and the scanning line driving circuit 904. Therefore, the pixel portion 902, the scanning line driving circuit 904, and the display element are sealed by the first substrate 901, the sealing material 905, and the second substrate 906. In FIGS. 9B and 9C, a signal line driver circuit 903 formed on a separately prepared substrate using a single crystal semiconductor or a polycrystalline semiconductor is mounted on the first substrate 901 in a region different from the region surrounded by the sealing material 905. In FIGS. 9B and 9C, various signals and potentials supplied to the signal line driving circuit 903, the scanning line driving circuit 904, or the pixel portion 902 are supplied from the FPC918.

In addition, FIGS. 9B and 9C show an example in which the signal line driver circuit 903 is separately formed and mounted on the first substrate 901, but it is not limited to this structure. The scanning line driver circuit may be separately formed and mounted, or only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed and mounted.

In addition, there are no particular restrictions on the connection method of the separately formed drive circuit, and COG (Chip On Glass) method, wire bonding method, TAB (Tape Automated Bonding) method, etc. can be used. . FIG. 9A is an example of installing the signal line driving circuit 903 and the scanning line driving circuit 904 by the COG method, FIG. 9B is an example of installing the signal line driving circuit 903 by the COG method, and FIG. 9C is an example of installing the signal line driver by the TAB method Example of circuit 903.

In addition, the display device includes a panel in which a display element is sealed and a module in which an IC including a controller and the like are mounted.

Note that the display device in this specification refers to an image display device, a display device, or a light source (including lighting equipment). In addition, the display device also includes: a module installed with connectors such as FPC, TAB tape or TCP; a module with a printed circuit board installed on the end of the TAB tape or TCP; IC (integrated circuit ) Module directly mounted to the display component.

In addition, the pixel portion and the scan line driving circuit provided on the first substrate include a plurality of transistors, and the transistors described in the above embodiments can be applied.

As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) and a light emitting element (also referred to as a light emitting display element) can be used. Light-emitting elements include elements whose brightness is controlled by current or voltage, and specifically include inorganic EL (Electro Luminescence) elements, organic EL elements, and the like. In addition, electronic ink and other display media whose contrast changes due to electrical action can also be used.

The display device shown in FIG. 10A includes a connection terminal electrode 915 and a terminal electrode 916, and the connection terminal electrode 915 and the terminal electrode 916 are electrically connected to the terminals included in the FPC 918 by an anisotropic conductive agent 919.

The connection terminal electrode 915 is formed of the same conductive film as the first electrode 930, and the terminal electrode 916 is formed of the same source electrode and drain electrode (hereinafter, also referred to as a pair of electrodes) of the transistor 910 and the transistor 911. The conductive film is formed.

The display device shown in FIG. 10B includes a connection terminal electrode 915a, a connection terminal electrode 915b, and a terminal electrode 916, and the connection terminal electrode 915a, the connection terminal electrode 915b, and the terminal electrode 916 are electrically connected to the terminals included in the FPC 918 by an anisotropic conductive agent 919.

The connection terminal electrode 915a is formed of the same conductive film as the first electrode 930, the connection terminal electrode 915b is formed of the same conductive film as the third electrode 941, and the terminal electrode 916 is formed of the same pair of electrodes as the transistor 910 and the transistor 911. The conductive film is formed.

In addition, as shown in FIG. 11, the semiconductor device includes a connection terminal electrode 955 and a terminal electrode 916, and the connection terminal electrode 955 and the terminal electrode 916 are electrically connected to the terminals included in the FPC 918 by the anisotropic dielectric 919.

The connection terminal electrode 955 is formed of the same conductive film as the second electrode 931, and the terminal electrode 916 is formed of the same conductive film as the pair of electrodes of the transistor 910 and the transistor 911.

In addition, the pixel portion 902 and the scan line driving circuit 904 provided on the first substrate 901 include a plurality of transistors. FIGS. 10A and 10B and FIG. 11 illustrate the transistor 910 included in the pixel portion 902 and the transistor 911 included in the scan line driving circuit 904. In FIGS. 10A and 10B, the transistor 910 and the transistor 911 are provided with an insulating film 924 corresponding to the insulating film 412 shown in Embodiment Mode 1, and an interlayer insulating film 921 serving as a planarizing film is also provided on the insulating film 924. . In addition, the insulating film 923 is an insulating film used as a base film.

In the embodiment, as the transistor 910 and the transistor 911, the transistor shown in the above embodiment can be used.

In addition, FIG. 11 shows the power consumption of the driving circuit on the insulating film 924 An example in which the conductive film 917 is provided at the position where the channel formation region of the semiconductor film of the crystal 911 overlaps. In addition, an oxide semiconductor film is used as the semiconductor film. By disposing the conductive film 917 at a position overlapping with the channel formation region of the oxide semiconductor film, the variation of the threshold voltage of the transistor 911 before and after the BT stress test can be further reduced. In addition, the potential of the conductive film 917 may be the same as or different from the potential of the gate electrode of the transistor 911, and the conductive film may also be used as the second gate electrode. In addition, the potential of the conductive film 917 may also be GND, 0V, or a floating state.

In addition, the conductive film 917 also has a function of shielding an external electric field. In other words, the conductive film 917 also has a function of preventing an external electric field from acting on the inside (a circuit part including a transistor) (especially, a static electricity shielding function against static electricity). The shielding function of the conductive film 917 can be used to prevent the electrical characteristics of the transistor from changing due to the influence of an external electric field such as static electricity. The conductive film 917 can be used for any of the transistors shown in the above embodiments.

The transistor 910 provided in the pixel portion 902 is electrically connected to the display element to constitute a display panel. As long as the display can be performed, there is no particular limitation on the display element, and various display elements can be used.

Regarding the first electrode and the second electrode (also called pixel electrode, common electrode, counter electrode, etc.) that apply voltage to the display element, the light transmittance or the pattern structure of the electrode can be selected according to the direction of light extraction, the place where the electrode is provided, and the pattern structure of the electrode. Reflective.

As the first electrode 930, the second electrode 931, and the third electrode 941, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide can be used. Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and the like.

In addition, the first electrode 930, the second electrode 931, and the third electrode 941 may use tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum ( Metals such as Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc., alloys of the above metals And one or more of the metal nitrides of the above-mentioned metals.

In addition, the first electrode 930, the second electrode 931, and the third electrode 941 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer or a derivative thereof composed of two or more of aniline, pyrrole, and thiophene, or the like can be cited.

10A and 10B show an example of a liquid crystal display device using a liquid crystal element as a display element. Fig. 10A is an example of using a vertical electric field method.

In FIG. 10A, the liquid crystal element 913 of the display element includes a first electrode 930, a second electrode 931, and a liquid crystal layer 908. Note that an insulating film 932 and an insulating film 933 serving as alignment films are provided so as to sandwich the liquid crystal layer 908. In addition, the second electrode 931 is provided on the second substrate 906 side, and the first electrode 930 and the second electrode 931 overlap with the liquid crystal layer 908 interposed therebetween.

In FIG. 10B, the liquid crystal element 943 of the display element includes a first electrode 930, a third electrode 941, and a liquid crystal layer formed on an interlayer insulating film 921. 908. The third electrode 941 serves as a common electrode. An insulating film 944 is provided between the first electrode 930 and the third electrode 941. The insulating film 944 is formed using a silicon nitride film. In addition, an insulating film 932 and an insulating film 933 serving as alignment films are provided so as to sandwich the liquid crystal layer 908.

In addition, the spacer 935 is a columnar spacer obtained by selectively etching the insulating film, and it is provided for controlling the interval (cell gap) between the first electrode 930 and the second electrode 931. Note that spherical spacers can also be used.

When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit a cholesterol phase, a smectic phase, a cubic phase, a hand-nematic phase, and an isotropy equal according to the conditions.

In addition, a liquid crystal exhibiting a blue phase that does not use an alignment film can also be used. The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric phase liquid crystal is increased, it appears just before the cholesteric phase is transformed into an isotropic phase. Since the blue phase only appears in a narrow temperature range, a liquid crystal composition mixed with a chiral agent is used for the liquid crystal layer in order to improve the temperature range. Since the response speed of the liquid crystal composition including the liquid crystal exhibiting a blue phase and the chiral agent is short, that is, 1 msec or less, and because it is optically isotropic, alignment processing is not required and viewing angle dependence is low. In addition, since there is no need to provide an alignment film and no rubbing treatment is required, electrostatic damage caused by rubbing treatment can be prevented, and the failure and breakage of the liquid crystal display device in the manufacturing process can be reduced. Thus, the productivity of the liquid crystal display device can be improved.

The first substrate 901 and the second substrate 906 are fixed by a sealing material 925. As the sealing material 925, organic resins such as thermosetting resins and photocurable resins can be used.

In addition, in the liquid crystal display device shown in FIG. 10A, the sealing material 925 is in contact with the gate insulating film 922, and the interlayer insulating film 921 is provided inside the sealing material 925. In addition, a silicon nitride film and a silicon oxynitride film are stacked to form a gate insulating film 922. In addition, it is preferable that when the insulating film 924 is selectively etched, the silicon oxynitride film on the upper layer of the gate insulating film 922 is etched to expose the silicon nitride film. As a result, the sealing material 925 is in contact with the silicon nitride film formed on the gate insulating film 922, so that water from the outside can be prevented from entering the sealing material 925.

Furthermore, in the liquid crystal display device shown in FIG. 10B, the sealing material 925 is in contact with the insulating film 924. Since the interlayer insulating film 921 is provided inside the sealing material 925, and the sealing material 925 is in contact with the silicon nitride film on the surface of the insulating film 924, it is possible to suppress water from the outside from entering the inside of the sealing material 925.

The size of the storage capacitor provided in the liquid crystal display device is set in consideration of the leakage current of the transistor arranged in the pixel portion and the like so that the charge can be retained during a predetermined period. Since it is sufficient to use a transistor with a high-purity oxide semiconductor film, it is sufficient to provide a storage capacitor having a capacitance of 1/3 or less of the liquid crystal capacitance in each pixel, preferably 1/5 or less. The aperture ratio in the pixel.

In addition, in the display device, optical members (optical substrates) such as a black matrix (light-shielding film), a polarizing member, a phase difference member, an anti-reflection member, and the like are appropriately provided. For example, it is also possible to use polarized substrates and phase The circular polarization of the differential substrate. In addition, as a light source, a backlight, a side light, etc. may also be used.

In addition, as a display method in the pixel portion, a progressive scan method, an interlace scan method, or the like can be adopted. In addition, the color elements controlled in the pixels when performing color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white) or adding one or more colors of yellow, cyan, and magenta to RGB may be used. In addition, the size of the display area of the dots of each color element may be different. Note that the present invention is not limited to display devices for color display, but can also be applied to display devices for monochrome display.

12A to 12C show an example in which a common connection portion (pad portion) electrically connected to the second electrode 931 provided on the substrate 906 is formed on the substrate 901 in the display device shown in FIG. 10A.

The common connection part is arranged at a position overlapping with the sealing material used to bond the substrate 901 and the substrate 906, and is electrically connected to the second electrode 931 by conductive particles contained in the sealing material. Alternatively, a common connection part may be provided at a position that does not overlap with the sealing material (note, except for the pixel part), and a paste containing conductive particles and the sealing material may be separately provided so as to overlap the common connection part, and the second electrode 931 Electric connection.

FIG. 12A is a cross-sectional view of the common connection part, and corresponds to the IJ line of the top view shown in FIG. 12B.

The common potential line 975 is provided on the gate insulating film 922, and uses the source electrode 971 or the drain electrode of the transistor 910 shown in FIGS. 10A and 10B. The electrode 973 is manufactured with the same material and manufacturing process.

In addition, the common potential line 975 is covered by the insulating film 924 and the interlayer insulating film 921, and the insulating film 924 and the interlayer insulating film 921 include a plurality of openings at positions overlapping the common potential line 975. The opening is manufactured by the same process as connecting one of the source electrode 971 and the drain electrode 973 of the transistor 910 and the contact hole of the first electrode 930.

In addition, the common potential line 975 and the common electrode 977 are connected at the opening. The common electrode 977 is disposed on the interlayer insulating film 921, and is manufactured using the same material and process as the connection terminal electrode 915 and the first electrode 930 of the pixel portion.

In this way, the common connection part can be manufactured together with the manufacturing process of the switching element of the pixel part 902.

The common electrode 977 is an electrode that is in contact with the conductive particles contained in the sealing material, and is electrically connected to the second electrode 931 of the substrate 906.

In addition, as shown in FIG. 12C, the same material and process as the gate electrode of the transistor 910 can also be used to manufacture the common potential line 985.

In the common connection portion shown in FIG. 12C, the common potential line 985 is provided in the lower layer of the gate insulating film 922, the insulating film 924, and the interlayer insulating film 921, and the gate insulating film 922, the insulating film 924, and the interlayer insulating film 921 The position overlapping with the common potential line 985 includes a plurality of openings. The opening is etched after the insulating film 924 and the interlayer insulating film 921 are etched by the same process as connecting one of the source electrode 971 and the drain electrode 973 of the transistor 910 and the contact hole of the first electrode 930. The polar insulating film 922 is selectively etched and formed.

In addition, the common potential line 985 and the common electrode 987 are connected at the opening. The common electrode 987 is disposed on the interlayer insulating film 921 and is manufactured using the same material and process as the connection terminal electrode 915 and the first electrode 930 of the pixel portion.

In addition, in the FFS mode liquid crystal display device shown in FIG. 10B, the common electrodes 977 and 987 are connected to the third electrode 941, respectively.

Next, as a display element included in the display device, a light-emitting element utilizing electroluminescence can be applied. Light-emitting elements using electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In an organic EL element, by applying a voltage to a light-emitting element, electrons and holes are respectively injected from a pair of electrodes into a layer including a light-emitting organic compound, and current flows. In addition, by the recombination of these carriers (electrons and holes), the light-emitting organic compound forms an excited state, and emits light when returning from the excited state to the ground state. Due to this mechanism, such light-emitting elements are called current-excited light-emitting elements.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to their element structure. The dispersion type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination light emission using donor energy levels and acceptor energy levels. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and the dielectric layer is sandwiched by electrodes. ). Here, an organic EL element is used as a light-emitting element for description.

In order to extract light, at least one of the pair of electrodes of the light-emitting element may be made transparent. In addition, a transistor and a light-emitting element are formed on the substrate. As the light-emitting element, there are: a light-emitting element with a top emission structure that emits light from the surface on the opposite side of the substrate; a light-emitting device with a bottom emission structure that emits light from the surface of the substrate. Element; and a light-emitting element of a double-emission structure that emits light from the substrate side and the surface on the opposite side of the substrate, and any light-emitting element of the above-mentioned emission structure can be applied.

FIG. 11 shows an example of a light-emitting device using a light-emitting element as a display element. The light-emitting element 963 as a display element is electrically connected to the transistor 910 provided in the pixel portion 902. In addition, although the structure of the light-emitting element 963 is a stacked structure of the first electrode 930, the light-emitting layer 951, and the second electrode 931, it is not limited to the illustrated structure. The structure of the light-emitting element 963 can be appropriately changed according to the direction of light taken out from the light-emitting element 963 and the like.

A silicon nitride film 950 is included between the interlayer insulating film 921 and the first electrode 930. The silicon nitride film 950 is in contact with the side surfaces of the interlayer insulating film 921 and the insulating film 924. The silicon nitride film 950 and the ends of the first electrode 930 include a partition wall 960. The partition wall 960 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material, to form an opening in the first electrode 930, and to form the side wall of the opening into an inclined surface having a continuous curvature.

The light-emitting layer 951 may be composed of a single layer, or may be composed of a stacked layer of a plurality of layers.

In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from intruding into the light-emitting element 963, protection may also be formed on the second electrode 931 and the partition wall 960 Floor. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC film, etc. can be formed. In addition, a filling material 964 is provided and sealed in the space sealed by the first substrate 901, the second substrate 906, and the sealing material 936. In this way, in order not to be exposed to external air, it is preferable to use a protective film (adhesive film, ultraviolet curable resin film, etc.) and a covering material with high airtightness and little outgassing for encapsulation (enclosure).

As the sealing material 936, an organic resin such as a thermosetting resin or a photocurable resin, or glass frit including low-melting glass, or the like can be used. The glass powder has high barrier properties to impurities such as water and oxygen, so it is preferable. In addition, when glass powder is used as the sealing material 936, as shown in FIG. 11, by disposing the glass powder on the silicon nitride film 950, it is possible to improve the adhesion between the silicon nitride film 950 and the glass powder and prevent intrusion from the outside. Water in the sealing material 936.

As the filler 964, in addition to inert gases such as nitrogen or argon, ultraviolet curable resins or thermosetting resins can also be used. For example, PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, etc. can be used. PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate). For example, nitrogen may be used as the filling material.

In addition, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a phase difference plate (λ/4 plate, λ/2 plate), and a color filter can also be appropriately provided on the emission surface of the light-emitting element. And other optical films. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. For example, anti-glare treatment may be performed, which is a treatment that can reduce glare by diffusing reflected light by using irregularities on the surface.

In addition, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably constructed using a non-linear element.

As described above, by applying the transistor described in the above-mentioned embodiments, it is possible to provide a highly reliable semiconductor device having a display function.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

[Embodiment 6]

The transistor of the above-mentioned embodiment can be used to manufacture a semiconductor device having an image sensor function that reads information of a target object.

FIG. 13A shows an example of a semiconductor device having an image sensor function. FIG. 13A is an equivalent circuit of the photoelectric sensor, and FIG. 13B is a cross-sectional view showing a part of the photoelectric sensor.

One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658, and the other electrode of the photodiode 602 is electrically connected to the gate of the transistor 640. One of the source and drain of the transistor 640 is electrically connected to the photoelectric sensor reference signal line 672, and the other of the source and drain of the transistor 640 is electrically connected to the source and the drain of the transistor 656 one of the. The gate of the transistor 656 is electrically connected to the gate signal line 659, and the other of the source and drain of the transistor 656 is electrically connected to the photoelectric sensor output signal line 671.

Note that in the circuit diagrams in this specification, in order to make the transistor using the oxide semiconductor film clear at a glance, the transistor using the oxide semiconductor film will be used. The symbol of the body is represented as "OS". In FIG. 13A, the transistor 640 and the transistor 656 can be the transistors shown in the above-mentioned embodiments, and they are transistors using an oxide semiconductor film. This embodiment mode shows an example in which a transistor having the same structure as the transistor 450 shown in Embodiment Mode 1 is applied.

13B is a cross-sectional view showing a photodiode 602 and a transistor 640 in a photoelectric sensor, in which a photodiode 602 and a transistor 602 serving as a sensor are provided on a substrate 601 (element substrate) having an insulating surface Transistor 640. By using the adhesive layer 608, a substrate 613 is provided on the photodiode 602 and the transistor 640.

An insulating film 632, a planarizing film 633, and a planarizing film 634 are provided on the transistor 640. The photodiode 602 has: an electrode 641b formed on the planarization film 633; a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c stacked on the electrode 641b in this order; and is provided on the planarization film 634 The electrode 642 electrically connected to the electrode 641b through the first semiconductor film to the third semiconductor film; and the electrode 641a electrically connected to the electrode 642 provided in the same layer as the electrode 641b.

The electrode 641b is electrically connected to the conductive film 643 formed in the planarization film 634, and the electrode 642 is electrically connected to the conductive film 645 through the electrode 641a. The conductive film 645 is electrically connected to the gate electrode of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a pin-type photodiode is illustrated in which a semiconductor film having p-type conductivity used as a first semiconductor film 606a and a high-resistance semiconductor film (i-type semiconductor film) used as a second semiconductor film 606b are stacked. ), a semiconductor with n-type conductivity used as the third semiconductor film 606c Body membrane.

The first semiconductor film 606a is a p-type semiconductor film, and may be formed of an amorphous silicon film containing an impurity element imparting p-type. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing an impurity element (for example, boron (B)) belonging to Group 13 in the periodic table. As the semiconductor material gas, silane (SiH₄). In addition, Si can be used₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄, SiF₄Wait. In addition, it is also possible to use a method in which after an amorphous silicon film containing no impurity elements is formed, the impurity elements are introduced into the amorphous silicon film using a diffusion method or an ion implantation method. It is preferable to perform heating or the like to diffuse the impurity element after introducing the impurity element using an ion implantation method or the like. In this case, as a method of forming an amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like can be used. It is preferable to set the thickness of the first semiconductor film 606a to 10 nm or more and 50 nm or less.

The second semiconductor film 606b is an i-type semiconductor film (essential semiconductor film) and is formed of an amorphous silicon film. In order to form the second semiconductor film 606b, an amorphous silicon film is formed by a plasma CVD method using a semiconductor material gas. As the semiconductor material gas, silane (SiH₄). Alternatively, Si can also be used₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄Or SiF₄Wait. The second semiconductor film 606b can also be formed by an LPCVD method, a vapor phase growth method, a sputtering method, or the like. It is preferable to set the thickness of the second semiconductor film 606b to be 200 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film, and is formed of an amorphous silicon film containing an impurity element imparting n-type. Use includes belonging to the periodic table A semiconductor material gas of an impurity element of Group 15 (for example, phosphorus (P)) is formed into the third semiconductor film 606c by a plasma CVD method. As the semiconductor material gas, silane (SiH₄). Alternatively, Si can also be used₂H₆, SiH₂Cl₂, SiHCl₃, SiCl₄Or SiF₄Wait. In addition, it is also possible to use a method in which after an amorphous silicon film containing no impurity elements is formed, the impurity elements are introduced into the amorphous silicon film using a diffusion method or an ion implantation method. It is preferable to perform heating or the like to diffuse the impurity element after introducing the impurity element using an ion implantation method or the like. In this case, as a method of forming the amorphous silicon film, an LPCVD method, a vapor deposition method, a sputtering method, or the like can be used. It is preferable to set the thickness of the third semiconductor film 606c to be 20 nm or more and 200 nm or less.

In addition, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using polycrystalline semiconductors or microcrystalline semiconductors (Semi Amorphous Semiconductor: SAS) instead of amorphous semiconductors.

In addition, since the mobility of holes generated by the photoelectric effect is lower than that of electrons, when the surface on one side of the p-type semiconductor film is used as the light-receiving surface, the pin-type photodiode has better characteristics . Here, an example of converting the light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed into an electric signal is shown. In addition, light from the side of the semiconductor film whose conductivity type is opposite to the side of the semiconductor film serving as the light-receiving surface is interference light. Therefore, it is preferable to use a conductive film having light-shielding properties for the electrode. In addition, the surface on the side of the n-type semiconductor film may also be used as the light receiving surface.

By using insulating materials and using sputtering method, plasma The insulating film 632, the planarizing film 633, and the planarizing film 634 can be formed by a CVD method, a spin coating method, a dipping method, a spray method, a droplet ejection method (an inkjet method, etc.), screen printing, offset printing, or the like. In addition, as the insulating film 632, the same insulating film as the insulating film 412 of the first embodiment can be used.

As the planarization film 633 and the planarization film 634, for example, a heat-resistant organic insulating material such as polyimide resin, acrylic resin, benzocyclobutene-based resin, polyamide resin, and epoxy resin can be used. In addition, in addition to the above-mentioned organic insulating materials, a single layer or stack of low dielectric constant materials (low-k materials), silicone resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Floor.

By detecting the light incident on the photodiode 602, the information of the detection target can be read. In addition, when reading the information of the detection target, a light source such as a backlight can be used.

The structure, method, etc. shown in this embodiment can be implemented in appropriate combination with the structure, method, etc. shown in other embodiments.

[Embodiment 7]

The semiconductor device disclosed in this specification can be applied to various electronic devices (including game consoles). Examples of electronic devices include televisions (also called televisions or television receivers), monitors used in computers, etc., digital cameras, digital cameras, digital photo frames, mobile phones, portable game consoles, and portable information terminals. , Audio reproduction device, game machine (pachinko machine or slot machine, etc.), shell game machine. 14A to 14C show specific examples of the above-mentioned electronic device.

Fig. 14A shows a table 9000 having a display unit. In the table 9000, a display portion 9003 is incorporated in the housing 9001, and the display portion 9003 can display images. In addition, a structure in which the housing 9001 is supported by the four legs 9002 is shown. In addition, the housing 9001 has a power supply line 9005 for supplying electric power.

The transistor shown in any of the above-mentioned embodiments can be used in the display portion 9003, thereby providing high reliability to the electronic device.

The display portion 9003 has a touch input function, and by touching the display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, screen operations or information input can be performed, and the display portion 9003 can also be used as the following control device, That is, by enabling it to have the function of communicating with other household electrical appliances or the function of controlling other household electrical appliances, and controlling other household electrical appliances through screen operation. For example, by using the semiconductor device having an image sensor function described in Embodiment 6, the display portion 9003 can be provided with a touch input function.

In addition, the screen of the display portion 9003 can also be erected perpendicular to the floor by the hinge provided in the housing 9001, so that the table 9000 can also be used as a television. Although installing a large-screen TV in a small room will reduce the free space, if the table is equipped with a display unit, the room space can be effectively used.

FIG. 14B shows a television 9100. In the television 9100, a display portion 9103 is incorporated in the housing 9101, and the display portion 9103 can display images. Note that the structure in which the housing 9101 is supported by the bracket 9105 is shown here.

The television 9100 can be operated by using the operation switch provided in the housing 9101 and the remote control 9110 provided separately. By using the operation keys 9109 of the remote control 9110, the channel and volume can be adjusted, and the image displayed on the display portion 9103 can be operated. In addition, a configuration in which the remote controller 9110 is provided with a display unit 9107 that displays information output from the remote controller 9110 may also be adopted.

The television 9100 shown in FIG. 14B includes a receiver, a modem, and the like. The television 9100 can receive general television broadcasts by using a receiver. Furthermore, by connecting a modem to a wired or wireless communication network, one-way (from sender to receiver) or two-way (between sender and receiver or between receivers, etc.) information can also be carried out. Communication.

The transistor shown in any of the above-mentioned embodiments can be used for the display portion 9103 and the display portion 9107, thereby providing high reliability to the television and the remote control.

14C shows a computer, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

The transistor shown in any of the above-mentioned embodiments can be used for the display portion 9203, thereby providing high reliability to the computer.

15A and 15B show a tablet terminal that can be folded. 15A is an open state, and the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switch 9034, a power switch 9035, a power saving mode switch 9036, a clip 9033, and an operation switch 9038.

The transistor shown in any of the above embodiments can be used for the display portion 9631a and the display portion 9631b, thereby making it possible to manufacture a highly reliable tablet terminal.

In the display portion 9631a, a part of it can be used as an area 9632a of the touch screen, and data can be input by touching the displayed operation key 9638. In addition, in the display portion 9631a, as an example, half of the area has only a display function and the other half has the function of a touch screen, but it is not limited to this structure. It is also possible to adopt a structure in which the entire area of the display portion 9631a has the function of a touch screen. For example, it is possible to display keyboard buttons on the entire surface of the display portion 9631a to use it as a touch screen, and use the display portion 9631b as a display screen surface.

In addition, a part of the display portion 9631b can also be used as an area 9632b of the touch screen similarly to the display portion 9631a. In addition, by touching the position of the display keyboard display switching button 9639 on the touch screen with a finger, a stylus, or the like, the keyboard buttons can be displayed on the display portion 9631b.

In addition, it is also possible to simultaneously perform touch input on the area 9632a of the touch screen and the area 9632b of the touch screen.

In addition, the display mode switching switch 9034 can switch the display directions of portrait display and landscape display, and select switching between black and white display or color display, and the like. The power saving mode switch 9036 can set the brightness of the display to the most suitable brightness according to the amount of external light during use detected by the light sensor built into the tablet terminal. In addition to the light sensor, the tablet terminal may also have built-in other detection devices such as sensors that detect inclination, such as a gyroscope and an acceleration sensor.

In addition, FIG. 15A shows an example in which the display area of the display portion 9631b is the same as the display area of the display portion 9631a, but it is not limited to this. It is possible to make the size of one side different from the size of the other side and also make their display quality different. . For example, one of the display portion 9631a and the display portion 9631b can perform a higher-definition display than the other.

15B is a closed state, and the tablet terminal includes a housing 9630, a solar battery 9633, and a charge and discharge control circuit 9634. In addition, in FIG. 15B, as an example of the charge and discharge control circuit 9634, a structure having a battery 9635 and a DCDC converter 9636 is shown.

In addition, the tablet terminal can be folded, so the housing 9630 can be closed when not in use. Therefore, the display portion 9631a and the display portion 9631b can be protected, and a tablet terminal having good durability and good reliability from the viewpoint of long-term use can be provided.

In addition, the tablet terminal shown in FIGS. 15A and 15B may also have the following functions: display various information (still images, moving images, text images, etc.); display calendar, date, or time on the display; The information on the display is operated or edited by touch input; processing is controlled by various software (programs), etc.

By using the solar battery 9633 installed on the surface of the tablet terminal, power can be supplied to the touch screen, the display unit, or the image signal processing unit, etc. In addition, the solar battery 9633 can be disposed on one side or both sides of the housing 9630, and a structure for efficiently charging the battery 9635 can be adopted. In addition, when a lithium ion battery is used as the battery 9635, there are advantages such as miniaturization.

In addition, the structure and operation of the charge and discharge control circuit 9634 shown in FIG. 15B will be described with reference to the block diagram shown in FIG. 15C. 15C shows a solar battery 9633, a battery 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display portion 9631, a battery 9635, a DCDC converter 9636, a converter 9637, and switches SW1 to SW3 correspond to FIG. 15B The charge and discharge control circuit 9634 shown.

First, an example of the operation when the solar cell 9633 is used to generate electricity using external light will be described. The DCDC converter 9636 is used to step up or step down the power generated by the solar cell so that it becomes the voltage used to charge the battery 9635. Then, when the display unit 9631 is operated by the power from the solar battery 9633, the switch SW1 is turned on, and the converter 9637 is used to boost or step down the power to the voltage required by the display unit 9631. In addition, when the display on the display portion 9631 is not performed, a structure in which SW1 is turned off and SW2 is turned on to charge the battery 9635 may be adopted.

Note that the solar cell 9633 is shown as an example of the power generation unit, but it is not limited to this, and other power generation units such as piezoelectric elements or thermoelectric conversion elements (Peltier elements) can also be used for the battery. 9635 charging. For example, it is also possible to use a wireless power transmission module that can transmit and receive power in a wireless (non-contact) manner for charging, or to combine other charging methods for charging.

The structure, method, etc. shown in this embodiment can be implemented in appropriate combination with the structure, method, etc. shown in other embodiments.

[Example 1]

In this embodiment, a cross-sectional observation result of the stepped portion of the source electrode and the drain electrode of the transistor in the semiconductor device according to the disclosed invention is described.

First, the manufacturing method of the transistor of the example sample is explained.

First, a gate electrode is formed on a glass substrate. A 100nm thick tungsten film is formed by a sputtering method, a mask is formed on the tungsten film by a photolithography process, and a part of the tungsten film is etched using the mask to form a gate electrode.

Next, a gate insulating film is formed on the gate electrode. As the gate insulating film, a silicon nitride film with a thickness of 50 nm and a silicon oxynitride film with a thickness of 200 nm are laminated. Supply 50sccm of silane and 5000sccm of nitrogen into the processing chamber of the plasma CVD equipment, control the pressure in the processing chamber to 60Pa and use a 27.12MHz high-frequency power supply to supply 150W of power to form a silicon nitride film. Supply 20sccm of silane and 3000sccm of nitrous oxide to the processing chamber of the plasma CVD equipment, control the pressure in the processing chamber to 40Pa and use a 27.12MHz high-frequency power supply to supply 100W of power to form silicon oxynitride membrane. In addition, the silicon nitride film and the silicon oxynitride film were formed under the condition that the substrate temperature was set to 350°C.

Next, an oxide semiconductor film overlapping with the gate electrode is formed via the gate insulating film. Here, an IGZO film of a CAAC-OS film is formed on the gate insulating film by sputtering, a mask is formed on the IGZO film by a photolithography process, and a part of the IGZO film is processed using the mask eclipse carve. Then, the etched IGZO film is heated to form an oxide semiconductor film. Note that a 35 nm thick IGZO film is formed in this embodiment.

As the sputtering target, a target of In:Ga:Zn=1:1:1 (atomic ratio) was used, and 50sccm of argon and 50sccm of oxygen used as the sputtering gas were supplied to the processing chamber of the sputtering device. The pressure in the processing chamber is controlled to 0.6 Pa, and 5 kW of DC power is supplied to form an IGZO film. Note that the substrate temperature when forming the IGZO film is 170°C.

Next, heat treatment is performed to deintercalate water, hydrogen, etc. contained in the oxide semiconductor film. Here, after the heat treatment is performed at 450° C. for 1 hour in a nitrogen atmosphere, the heat treatment is performed at 450° C. for 1 hour in a nitrogen and oxygen atmosphere.

Next, a conductive film is formed on the gate insulating film and the oxide semiconductor film, a mask is formed on the conductive film by a photolithography process, and a part of the conductive film is etched using the mask to form a source Electrode and drain electrode. Note that, as the conductive film that becomes the source electrode and the drain electrode, a 400-nm-thick aluminum film is formed on a 50-nm-thick tungsten film, and a 100-nm-thick titanium film is formed on the aluminum film.

Next, after the substrate was moved to a decompressed processing chamber and heated at 220° C., the substrate was moved to a processing chamber filled with nitrous oxide. Next, the oxide semiconductor film was exposed to oxygen plasma generated by using a 27.12 MHz high-frequency power supply to supply 150 W of high-frequency power to the upper electrode provided in the processing chamber.

Then, after the above plasma treatment, in a manner not exposed to the atmosphere An insulating film is continuously formed on the oxide semiconductor film, the source electrode, and the drain electrode. The insulating film was formed under four conditions, namely, condition A1 to condition A4, and samples formed under various conditions were sample A1 to sample A4. Note that in sample A1 to sample A4, the thickness of the insulating film is 400 nm.

In Condition 1, a silicon oxynitride film is used as the insulating film. The plasma CVD method is used to form a silicon oxynitride film under the following conditions: silane with a flow rate of 30 sccm and nitrous oxide with a flow rate of 4000 sccm are used as raw materials, the pressure of the processing chamber is set to 40 Pa, and the substrate temperature is set to 220°C, 150W of high frequency power is supplied to the parallel plate electrodes. Note that the film density of the whole film measured by XRR is 2.26g/cm³。

In Condition 2, a silicon oxynitride film is used as the insulating film. The plasma CVD method is performed to form a silicon oxynitride film under the following conditions: silane with a flow rate of 160 sccm and nitrous oxide with a flow rate of 4000 sccm are used as raw materials, the pressure of the processing chamber is set to 200 Pa, and the substrate temperature is set to At 220°C, 1500W of high-frequency power is supplied to the parallel plate electrodes. Note that the film density of the whole film measured by XRR is 2.31g/cm³。

In condition 3, a silicon oxynitride film is used as the insulating film. The plasma CVD method is used to form a silicon nitride film under the following conditions: silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm are used as raw materials, the pressure of the processing chamber is set to 200 Pa, and the substrate temperature It was set to 220°C, and 1000W of high-frequency power was supplied to the parallel plate electrodes. Note that the film density of the whole film measured by XRR is 2.50g/cm³。

In condition 4, a silicon oxynitride film is used as the insulating film. In the following article Plasma CVD method is performed to form silicon nitride film under the workpiece: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm are used as raw material gases, the pressure of the processing chamber is 200 Pa, and the substrate temperature is set to 3³At 50°C, 2000W high-frequency power is supplied to the parallel plate electrodes. Note that the film density of the whole film measured by XRR is 2.72g/cm³。

The cross-sections of the sample A1 to the sample A4 were respectively observed using a cross-sectional scanning transmission electron microscope (STEM: Scanning Transmission Electron Microscopy). FIG. 16A shows the STEM image of sample A1, FIG. 16B shows the STEM image of sample A2, FIG. 17A shows the STEM image of sample A3, and FIG. 17B shows the STEM image of sample A4.

As shown in FIGS. 16A, 16B, and 17A, it was confirmed that a void portion was generated in a portion surrounded by a dotted line in the insulating film covering the source electrode and the drain electrode. On the other hand, in FIG. 17B, it was not confirmed that the voids were generated in the insulating film covering the source electrode and the drain electrode.

It can be seen that in samples A1 to A4, when the film density of the insulating film covering the source electrode and the drain electrode is 2.26 g/cm³Above and 2.50g/cm³In the following cases, voids are generated in the insulating film.

[Example 2]

In this embodiment, a measurement result of the characteristics of a transistor in which a nitride insulating film is formed on an oxide insulating film will be described.

First, the manufacturing method of the transistor of the example sample is explained.

As in Example 1, a gate electrode and a gate electrode were formed on the glass substrate The insulating film and the oxide semiconductor film are subjected to heat treatment to deintercalate water, hydrogen, etc. contained in the oxide semiconductor film. Here, after the heat treatment is performed at 450° C. for 1 hour in a nitrogen atmosphere, the heat treatment is performed at 450° C. for 1 hour in a nitrogen and oxygen atmosphere.

Next, a conductive film is formed on the gate insulating film and the oxide semiconductor film, a mask is formed on the conductive film by a photolithography process, and a part of the conductive film is etched using the mask to form a source Electrode and drain electrode.

Next, after the substrate was moved to a decompressed processing chamber and heated at 220° C., the substrate was moved to a processing chamber filled with nitrous oxide. Next, the oxide semiconductor film was exposed to oxygen plasma generated by using a 27.12 MHz high-frequency power supply to supply 150 W of high-frequency power to the upper electrode provided in the processing chamber.

For the steps so far, refer to Embodiment 1.

Next, after the above-mentioned plasma treatment, an insulating film is continuously formed on the oxide semiconductor film, the source electrode, and the drain electrode without being exposed to the atmosphere. The insulating film has a stacked structure in which a nitride insulating film is formed on an oxide insulating film. A first silicon oxynitride film with a thickness of 50 nm and a second silicon oxynitride film with a thickness of 400 nm are stacked to form an oxide insulating film.

The plasma CVD method is performed to form the first silicon oxynitride film under the following conditions: silane with a flow rate of 30 sccm and nitrous oxide with a flow rate of 4000 sccm are used as source gases, the pressure of the processing chamber is set to 40 Pa, and the substrate temperature Set to 220°C, and supply high-frequency power of 150W to the parallel plate electrodes.

The plasma CVD method is performed to form the second silicon oxynitride film under the following conditions: silane with a flow rate of 160 sccm and nitrous oxide with a flow rate of 4000 sccm are used as raw materials, the pressure of the processing chamber is set to 200 Pa, and the substrate temperature Set to 220°C, and supply 1500W of high-frequency power to the parallel plate electrodes. Under these conditions, a silicon oxynitride film containing more oxygen than oxygen satisfying the stoichiometric composition and part of the oxygen released by heating can be formed.

Next, heat treatment is performed to release water, hydrogen, etc. from the oxide insulating film. Here, heat treatment was performed at 350°C for 1 hour in a nitrogen and oxygen atmosphere.

Next, a nitride insulating film is formed on the oxide insulating film. As the nitride insulating film, a silicon nitride film with a thickness of 50 nm is formed. The plasma CVD method is performed to form a silicon nitride film under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia with a flow rate of 100 sccm are used as raw materials, the pressure of the processing chamber is set to 100 Pa, and the substrate temperature Set to 350°C, and supply high-frequency power of 2000W to the parallel plate electrodes.

Next, a part of the insulating film (the oxide insulating film and the nitride insulating film) is etched to form an opening that exposes a part of the source electrode and the drain electrode.

Next, an interlayer insulating film is formed on the insulating film (nitride insulating film). Here, the composition is applied on the nitride insulating film, and then exposure and development are performed to form an interlayer insulating film having an opening through which a part of the source electrode or the drain electrode is exposed. In addition, an acrylic resin having a thickness of 1.5 μm was formed as an interlayer insulating film. Then, heat treatment is performed. This heat treatment was performed at 250°C for 1 hour in an atmosphere containing nitrogen.

Next, a conductor connected to a part of the source electrode or the drain electrode is formed Electric film. Here, ITO containing silicon oxide is formed to a thickness of 100 nm by a sputtering method.

The transistors of the embodiment samples were manufactured by the above-mentioned process.

In addition, as a comparative example, a transistor of a comparative example sample was manufactured in which only an oxide insulating film was formed as the insulating film of the example sample, and no nitride insulating film was formed.

The cross-sections of the samples of the above examples and the samples of the comparative examples were observed using a cross-sectional scanning transmission electron microscope (STEM: Scanning Transmission Electron Microscopy). FIG. 18A shows the STEM image of the sample of the example, and FIG. 18B shows the STEM image of the sample of the comparative example.

As shown in FIGS. 18A and 18B, it was confirmed that a void portion was generated in the portion surrounded by the dotted line in the first silicon oxynitride film and the second silicon oxynitride film covering the source electrode and the drain electrode. In addition, as shown in FIG. 18A, no void is generated in the silicon nitride film on the second silicon oxynitride film. It can be confirmed that the void is blocked by the silicon nitride film.

Next, the Vg-Id characteristics of the transistors of the samples of the above examples and the samples of the comparative examples were measured.

As an accelerated life test for evaluating moisture resistance, a pressure cooker test (PCT: Pressure Cooker Test) was performed. In the PCT of this embodiment, the sample of the embodiment and the sample of the comparative example were maintained for 1 hour under the conditions of a temperature of 130° C., a humidity of 85%, and a pressure of 0.23 MPa.

GBT (gate bias temperature: gate bias temperature) pressure test was performed on the sample of the embodiment and the sample of the comparative example. In this embodiment, the GBT pressure test is performed under the following conditions: In a dark environment, Vg=-30V, Vd=0V, Vs=0V, pressure temperature is 60°C, light irradiation is not performed, and pressure application time is 1 hour. In addition, the actual measured values are as follows: the channel length (L) is 6 μm, the channel width (W) is 50 μm, and the oxide film (gate insulating film) thickness (Tox) is 280 nm.

FIG. 19A shows the result of the GBT pressure test of the sample of the example, and FIG. 19B shows the result of the GBT pressure test of the sample of the comparative example. In addition, the dotted line in the drawing shows the measurement result before PCT is performed, and the solid line in the drawing shows the measurement result after PCT is performed. In addition, FIGS. 19A and 19B show the measurement results when the drain voltage (Vd: [V]) is 1V and 10V, and the horizontal axis shows the gate voltage (Vg: [V]), and the vertical axis shows the drain current. (Id: [A]). Note that "drain voltage (Vd: [V])" refers to the potential difference between the drain and source based on the source, and "gate voltage (Vg: [V])" refers to the source based The potential difference between the gate and the source.

As shown in FIG. 19A, it was confirmed that the transistor of the example sample did not change before and after PCT. On the other hand, as shown in FIG. 19B, it was confirmed that the transistor of the comparative example sample greatly changed before and after the PCT, and the critical value drifted to the negative value side after the PCT.

The difference between the sample of the example and the sample of the comparative example is whether there is a silicon nitride film on the second silicon oxynitride film. Therefore, after PCT, the effect of the silicon nitride film is used to suppress the variation in characteristics.

Thus, by blocking the voids in the silicon oxynitride film by the silicon nitride film, it is possible to provide a semiconductor device using an oxide semiconductor with stable electrical characteristics and achieve high reliability.

[Example 3]

In this embodiment, the measurement results of transistor characteristics with different film forming temperatures of the nitride insulating film on the oxide insulating film will be described.

First, the manufacturing method of the transistor of the example sample is explained.

Regarding the example samples, the sample in which the film formation temperature of the silicon nitride film of the example sample of Example 2 was set to 220°C was sample B1, and the same sample as the example sample of Example 2 (silicon nitride film The film forming temperature is 350°C) for sample B2.

The plasma CVD method was performed to form the silicon nitride film of sample B1 under the following conditions: silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm were used as source gases, and the pressure of the processing chamber was set to 200 Pa. The substrate temperature was set to 220°C, and high-frequency power of 1000 W was supplied to the parallel plate electrodes. The method of forming the silicon nitride film of sample B2 was the same as that of sample B1 except that the substrate temperature of the silicon nitride film of sample B1 was set to 350°C.

Next, the Vg-Id characteristics of the transistors of the above-mentioned sample B1 and sample B2 were measured.

As an accelerated life test for evaluating moisture resistance, a pressure cooker test (PCT) is performed. In the PCT of this embodiment, the sample B1 and the sample B2 were maintained for 1 hour under the conditions of a temperature of 130° C., a humidity of 85%, and a pressure of 0.20 MPa.

Perform GBT pressure test on sample B1 and sample B2. In this embodiment, the GBT pressure test is performed under the following conditions: In a dark environment, Vg=-30V to 30V, Vd=0V, Vs=0V, pressure temperature is 60°C, light irradiation is not performed, and pressure application time is 1 hour. In addition, the actual measured values are as follows: the channel length (L) is 6 μm, the channel width (W) is 50 μm, and the thickness (Tox) of the oxide film (gate insulating film) is 280 nm.

FIG. 20A1 shows the result of the GBT pressure test before the PCT of the sample B1, and FIG. 20A2 shows the result of the GBT pressure test after the PCT of the sample B1. FIG. 20B1 shows the result of the GBT pressure test before the PCT of the sample B2, and FIG. 20B2 shows the result of the GBT pressure test after the PCT of the sample B2. 20A1, 20A2, 20B1, and 20B2 show the measurement results when the drain voltage (Vd: [V]) is 1V and 10V, and the horizontal axis shows the gate voltage (Vg: [V]), and the vertical axis Shows the drain current (Id: [A]) and the field effect mobility (μFE: [cm²/Vs]). In addition, FIGS. 20A3 and 20B3 show the change amount (ΔVth) of the critical value and the change amount (ΔShift) of the drift value before and after the PCT of the sample B1 and the sample B2.

In addition, in this specification, the threshold voltage (Vth) is defined as follows: the horizontal axis represents the gate voltage (Vg: [V]) and the vertical axis represents the square root of the drain current (Id^(1/2): In the curve of [A]), when the Id of the maximum slope is extrapolated^(1/2)When the wiring is connected to the Vg axis (ie, Id^(1/2)It is the gate voltage at the point where 0A) crosses. Note that in this specification, the threshold voltage is calculated when the drain voltage Vd is 10V.

In addition, in this specification, the shift value (Shift) is defined as follows: the horizontal axis represents the gate voltage (Vg: [V]) and the vertical axis represents the logarithm of the drain current (Id: [A]) In the curve, when extrapolating the connection of the Id with the maximum inclination, the connection and the straight line Id=1.0×10^-12[A] The gate of the crossing point Voltage. Note that in this specification, the drift value is calculated when the drain voltage Vd is 10V.

As shown in FIGS. 20A3 and 20B3, it can be observed that the transistors of sample B1 and sample B2 have slight changes in threshold voltage and drift before and after PCT, and the transistors of sample B1 and sample B2 have deteriorated. In addition, compared with the transistor of sample B1 (silicon nitride film formation temperature is 220°C), the threshold voltage and drift value of the transistor of sample B2 (silicon nitride film formation temperature is 350°C) change The amount is less.

[Example 4]

In this embodiment, the analysis results of the silicon nitride film using RBS (Rutherford Backscattering Spectrometry) and the use of secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) of the silicon nitride film as a part of the insulating film will be described. The results of the evaluation.

First, the sample to be analyzed is explained.

The sample was manufactured by forming a silicon nitride film 12 on the silicon wafer 11 by the plasma CVD method (refer to FIG. 21). The silicon nitride film 12 was formed under two conditions, namely condition C1 and condition C2, and the samples formed under each condition were sample C1 and sample C2.

In condition C1, the plasma CVD method is performed to form a 100nm thick silicon nitride film 12 under the following conditions: maintaining the temperature of the silicon wafer 11 at 220°C, adding silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and a flow rate of 100 sccm The ammonia is used as the raw material gas, the pressure of the processing chamber is set to 200Pa, and the high-frequency power of 1000W is supplied to the parallel plate electricity pole.

In condition C2, a plasma CVD method was performed to form a silicon nitride film 12 with a thickness of 300 nm under the following conditions: maintaining the temperature of the silicon wafer 11 at 350°C, adding silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and a flow rate of 100 sccm The ammonia is used as the raw material gas, the pressure of the processing chamber is set to 200 Pa, and the high frequency power of 2000 W is supplied to the parallel plate electrodes.

Next, the sample C1 and the sample C2 were evaluated. Table 1 shows the RBS results.

<tables><img he="676" wi="1310" file="tw201409708a_d0008.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

It is confirmed from Table 1 that sample C1 contains 26.5 atomic% silicon, 45.5 atomic% nitrogen, and 28.1 atomic% hydrogen. It is confirmed from Table 1 that sample C2 contains 40.0 atomic% silicon, 49.2 atomic% nitrogen, and 10.8 atomic% hydrogen. Therefore, the proportion of hydrogen in the composition of sample C2 is reduced compared to sample C1.

Next, Figures 22A and 22B show the results of the SIMS analysis.

Figure 22A shows the concentration profile of hydrogen, oxygen, fluorine and carbon of sample C1 obtained by SIMS, and Figure 22B shows the sample obtained by SIMS Concentration profile of hydrogen, oxygen, fluorine and carbon of C2.

In addition, Table 2 shows the details of the SIMS analysis results of FIGS. 22A and 22B.

<tables><img he="744" wi="1433" file="tw201409708a_d0009.tif" img-content="drawing" img-format="tif" orientation="portrait" inline="no" /></tables>

It is confirmed from Table 2 that sample C1 contains 2.8×10²²atoms/cm³Hydrogen, 1.0×10¹⁹atoms/cm³Oxygen, 2.3×10¹⁹atoms/cm³Fluorine and 5.5×10¹⁸atoms/cm³Of carbon. It is also confirmed from Table 2 that sample C2 contains 1.6×10²²atoms/cm³Hydrogen, 6.8×10¹⁷atoms/cm³Oxygen, 7.4×10¹⁸atoms/cm³Fluorine and 7.4×10¹⁷atoms/cm³Of carbon. Therefore, it was confirmed that the hydrogen ratio in the composition of the sample C2 was reduced in comparison with the sample C1 in the same manner as the result of the RBS. In addition, the concentration of impurities such as hydrogen, oxygen, fluorine, and carbon in sample C2 is lower than that in sample C1.

[Example 5]

In this embodiment, it is verified whether the voids generated in the insulating film become an intrusion path of water, hydrogen, or the like. SIMS is used as an evaluation method for verification.

First, a sample will be described with reference to FIGS. 23A and 23B. As a sample, quasi Two types of samples are prepared, namely the sample D1 shown in FIG. 23A in which the void is formed by providing an electrode on the oxide semiconductor film and the sample D1 shown in FIG. 23B where the electrode is not formed on the oxide semiconductor film and the void is not formed. Sample D2.

A gate insulating film 22 and an oxide semiconductor film 23 are formed on the glass substrate 21, and water, hydrogen, etc. contained in the oxide semiconductor film 23 are deintercalated by heat treatment. Here, heat treatment is performed at 450°C for 1 hour in a nitrogen atmosphere, and then heat treatment is performed at 450°C for 1 hour in a nitrogen and oxygen atmosphere.

Next, a conductive film is formed on the gate insulating film 22 and the oxide semiconductor film 23, a mask is formed on the conductive film by a photolithography process, and a part of the conductive film is etched using the mask to form Electrode 24.

Next, after the substrate was moved to a decompressed processing chamber and heated at 220° C., the substrate was moved to a processing chamber filled with nitrous oxide. Next, the oxide semiconductor film was exposed to oxygen plasma generated by using a 27.12 MHz high-frequency power supply to supply 150 W of high-frequency power to the upper electrode provided in the processing chamber.

For the steps so far, refer to Embodiment 1.

Next, after the above-mentioned plasma treatment, the insulating film 27 is continuously formed on the oxide semiconductor film 23 and the electrode 24 so as not to be exposed to the atmosphere. The insulating film 27 has a stacked structure in which a nitride insulating film 26 is formed on the oxide insulating film 25. A first silicon oxynitride film 25a having a thickness of 50 nm and a second silicon oxynitride film 25b having a thickness of 400 nm are stacked to form an oxide insulating film 25.

The plasma CVD method is performed to form the first silicon oxynitride film 25a under the following conditions: silane with a flow rate of 30 sccm and monooxygen with a flow rate of 4000 sccm Dinitrogen was used as the raw material gas, the pressure of the processing chamber was set to 40 Pa, the substrate temperature was set to 220° C., and high frequency power of 150 W was supplied to the parallel plate electrodes.

The plasma CVD method is performed to form the second silicon oxynitride film 25b under the following conditions: silane with a flow rate of 160 sccm and nitrous oxide with a flow rate of 4000 sccm are used as source gases, the pressure of the processing chamber is set to 200 Pa, and the substrate The temperature is set to 220°C, and high-frequency power of 1500W is supplied to the parallel plate electrodes. According to the above conditions, it is possible to form a silicon oxynitride film that contains more oxygen than oxygen that satisfies the stoichiometric composition, and a part of the oxygen is released by heat treatment.

Next, heat treatment is performed to release water, hydrogen, etc. from the oxide insulating film. Here, heat treatment was performed at 350°C for 1 hour in a nitrogen and oxygen atmosphere.

Next, a nitride insulating film 26 is formed on the oxide insulating film 25. As the nitride insulating film 26, a silicon nitride film having a thickness of 50 nm is formed. The plasma CVD method is performed to form a silicon nitride film under the following conditions: silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia with a flow rate of 100 sccm are used as raw material gases, the pressure of the processing chamber is set to 200 Pa, and the substrate temperature Set to 220°C, and supply high-frequency power of 2000W to the parallel plate electrodes.

The sample D1 was manufactured through the above steps. In addition, as the sample D2, a sample in which no electrode was formed was manufactured (refer to FIGS. 23A and 23B).

Perform pressure cooker test (PCT) on sample D1 and sample D2. In the PCT of this embodiment, the temperature is 130°C and the humidity is 85% (contained in The volume ratio of water vapor in the gas is H₂O (water): D₂O (heavy water) = 4: 1), the sample D1 and the sample D2 were maintained for 15 hours under the condition of 2.0 atmospheres (0.20 MPa).

In this embodiment, the "D atom" represented by heavy water etc. means a hydrogen atom with a mass number of 2 (²H).

As the SIMS analysis, SSDP (Substrate Side Depth Profile)-SIMS (SIMS measurement from the back) was used to measure the H atom and D atom concentration of the sample D1 and the sample D2 after the PCT test.

FIG. 24A shows the H atom and D atom concentration profile after the PCT test of the sample D1 obtained by SIMS, and FIG. 24B shows the H atom and D atom concentration profile after the PCT test of the sample D2 obtained by SIMS. In FIGS. 24A and 24B, the concentration profile of D atoms (natural density) refers to the concentration profile of D atoms existing in nature calculated from the concentration profile of H atoms assuming that the abundance ratio of D atoms is 0.015%. Therefore, the amount of D atom mixed into the sample by the PCT test is the difference between the actually measured D atom concentration and the D atom concentration of the natural density.

When the sample D1 and the sample D2 are compared, it can be seen from FIG. 24A that, since electrodes are provided on the oxide semiconductor film and voids are generated, the concentration profile of D atoms actually measured in the oxide semiconductor film is significantly increased, and a lot of D atoms are mixed into the oxide semiconductor film. From this, it can be confirmed that the sample D1 has an effect on the external water (H₂O, D₂O) has low barrier properties.