Standard cell architecture using double poly patterning for multi VT devices

Standard component architecture using double broken line patterning for multi-threshold voltage devices

The embodiments are related to semiconductor devices, and more specifically, to device groups with a structure designed using a standard cell library, and the device groups are configured to operate with different threshold voltages.

In semiconductor design, standard component methodology usually involves the use of standard components and interconnect structures to design integrated circuits with various functionalities. In the computer-aided design environment, these activities are usually promoted. The standard component methodology uses abstraction, in which low-level integrated circuit synthesis is replaced by more abstract and higher-level functional representations. The component-based methodology allows designers to focus on high-level design aspects. The standard element can be composed of a transistor structure, a passive structure, and a group of interconnect structures that constitute atomic functions (such as logic functions, storage functions, or the like). When the component design is completed, the production can be executed for physical implementation.

A polyline is a graphic object provided as part of a conventional computer-aided design package. Broken lines can be used during the design phase to define features associated with the device patterned onto the semiconductor. During fabrication, the fold line can be formed on the semiconductor, and then the fold line can be changed at various stages in the process of realizing the device.

The width of the broken line usually determines the channel length of the device in the component, and therefore affects the threshold voltage VT of the device. Partly due to the resolution problem associated with conventional photolithography equipment, when designing certain devices such as integrated transistor devices, it is customary to use uniformly sized polylines with the same channel length for devices in a specific pattern. Because the devices associated with the broken line are designed to operate under the same voltage VT, and because the resolution has historically been insufficient to allow deviation from the conventional approach, there is little doubt about the conventional standard component library.

In some instances, it may be advantageous to fabricate devices with different channel lengths (and therefore different threshold voltages) on a common semiconductor substrate. This requires patterning polylines with different line widths on the separation area. Existing patterning techniques can be used to realize these devices. However, these techniques can make the polyline tapered in the region where the channel length changes. This tapering can lead to undesirable process changes, and can increase the interval between the active areas to a value exceeding 170 nm, which can lead to inefficiency of manufacturing and reduced process yield.

Presents a device fabricated using a standard device architecture including devices with different voltage thresholds.

In one embodiment, the device may include a first set of fold lines associated with a first channel length, wherein each fold line in the first set of fold lines is separated by a substantially fixed interval. The device may further include a second set of fold lines associated with a second channel length and aligned with the first set of fold lines, wherein each fold line in the second set of fold lines is laterally separated by the substantially fixed pitch . The device may further include a first action area under the first fold line set, and a second action area under the second fold line set, wherein the first action area and the second action area are separated by less than A distance of 170 nm.

In another embodiment, a plurality of devices that are associated with a standard device architecture and manufactured by programming are presented. The procedure may include providing a plurality of fold lines on a first action area and a second action area, wherein each fold line is separated by a substantially fixed distance, and in addition, wherein the first action area and the second action area The zones are separated by a distance of less than 170 nm. The procedure may further include: forming the plurality of fold lines such that each fold line is associated with a first channel length and a second channel length; and separating the fold lines into a first fold line set and a second fold line set, The first fold line set is associated with the first channel length, and the second fold line set is associated with the second channel length.

The accompanying drawings are presented to assist the description of the embodiments. The drawings are provided only for the purpose of illustrating the embodiment and not limiting the embodiment.

The aspects are disclosed in the following description of specific embodiments and related drawings. Alternative embodiments can be designed without departing from the scope of the invention. In addition, well-known components will not be described in detail or will be omitted so as not to obscure relevant details.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." It is not necessary to interpret any embodiment described as "exemplary" herein as being better or advantageous than other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments include the discussed features, advantages, or modes of operation.

The terminology used herein is only for the purpose of describing specific embodiments and is not intended to limit the embodiments of the present invention. As used herein, the singular forms "one" and "the" are intended to also include the plural forms, unless the context clearly dictates otherwise. It should be further understood that the terms "including" and/or "including" when used herein designate the existence of the stated features, integers, steps, operations, components and/or components, but do not exclude one or more other features, integers The existence or addition of, steps, operations, parts, components, and/or groups thereof.

With regard to the present invention, the term "polyline" can refer to graphical objects (open polylines) that can be used to represent lines in a computer-aided design (CAD) system, and/or can be used for things such as transistor gates, circuit traces, and the like Graphical objects (closed polylines) of polygonal objects. The phrase "double polyline patterning" can refer to the use of continuous polyline patterning during production to specify the corresponding continuous patterning step to form irregular features or compared to the current production or lithography scale. The possible features have finer resolution features. Various components can be understood as components for specifying component libraries and generating output file formats as described in this article. These formats include (but are not limited to) free software design systems, such as Magic design system, Electric VLSI design system, and Commercial systems such as the following families: IC design systems provided by Mentor Graphics, such as Design Architect IC, IC Station, Quicksim II, Mach TA/Accusim II;<img file="TW201250996A_D0001.tif" /> Systems provided by Design Systems, such as Composer, Verilog-XL, Virtuoso, Silicon Ensemble, Spectre; and systems provided by Tanner Research, such as S-Edit, L-Edit, LVS, T-Spice.

FIG. 1 is a diagram illustrating a semiconductor device 100 that can be fabricated using a double-folding program based on a standard component library design. The device 100 may include a first active area 102, a second active area 104, a first set of fold lines 106, and a second set of fold lines 108. The first set of fold lines 106 and the second set of fold lines 108 have different widths, which are expressed as channel lengths Lc herein. As mentioned above, the channel length is usually related to the critical voltage (V_T) Is proportional. The first fold line set 106 has a first channel length (Lc1). The second set of fold lines 108 may have a second channel length (Lc2). As illustrated in FIG. 1, the broken line 106 may have a channel length Lc1 that is less than the channel length Lc2 of the broken line 108. Therefore, devices associated with active area 102 may have different threshold voltages than devices associated with active area 104.

Each fold line in the first fold line set 106 can be separated laterally by a fixed distance or pitch (Pc). Each fold line in the second fold line set 108 can also be separated laterally by the same pitch (Pc). In an embodiment, the second set of fold lines 108 may be aligned with the first set of fold lines 106 such that the centers of the fold lines from each set are aligned. However, other embodiments may contemplate different alignments between the two sets of fold lines, for example, where the fold lines may be aligned at the left or right edge. In addition, in other embodiments, the first part and the second part of the fold line may be aligned with each other on a per fold line basis.

The first active area 102 may be located under the first fold line set 106, and the second active area 104 may be located under the second fold line set 108. The distance between the first active area 102 and the second active area 104 (D_OD) Is less than 170 nm, and preferably 135 nm. Although it is not explicitly shown in FIG. 1, it should be understood that each active area may have components formed thereon, and these components correspond to the circuit implementation based on the standard component library.

In an embodiment, the first channel length (Lc1) may be in a range between 20 nm and 30 nm. The second channel length (Lc2) can be in the range between 30 nm and 40 nm. The distance between the edge of the first set of fold lines and the edge of the first active area may be 31.5 nm. The element pitch Pc may be about 140 nm.

2A to 2C are diagrams showing exemplary stages when the double patterning process is used to fabricate the semiconductor shown in FIG. 1. Figure 2A shows the stage 201 of the device prior to fold line patterning. At stage 201, all fold lines 210 can have a length L that can correspond to the thicker fold line set 108 shown in FIG. 1_c2The length of a single channel. However, in other embodiments, the initial channel length of the broken line can start to be thicker than L_c2. The fold line 210 can extend over both the active areas 202 and 204.

Figure 2B shows an exemplary stage 203 where the first fold line patterning of the semiconductor device occurs. Here, the upper part of the fold line 210 is patterned so that its channel length is reduced to L_c1. The lower part of the fold line can be patterned so that its channel length is reduced to L_c2. It should be noted that in the embodiment where the length of the fold line channel is already at the desired second length, the lower part of the fold line can remain unchanged at this stage. In one embodiment, a suitable step mask 212 can be used to form a step configuration (L_c1And L_c2), the appropriate step mask 212 will perform the first patterning.

FIG. 2C shows an exemplary stage 205 in which the second patterning separates the polyline into two distinct polyline sets 206 and 208. The second patterning can be implemented by the second mask 214 to perform the separation cleanly. Using the first mask 212 and the second mask 214 is an exemplary implementation of the double patterning process. The double patterning process may allow the edges of each of the polyline sets 206 and 208 near the space between the two active areas to remain sharp. In other words, masking can reduce the taper of the polyline. This situation allows the interval between the first active area 202 and the second active area 204 to be kept relatively close. And therefore, the manufacturing efficiency is improved (through better utilization of the area of the action zone), and the process variability is reduced at the same time. Therefore, the double patterning used to form standard components maximizes the area utilization of the active area. In some embodiments, the distance between the first active zone 202 and the second active zone 204 may be less than 170 nm.

FIG. 3 is a flowchart illustrating an exemplary process 300 for manufacturing the semiconductor shown in FIG. 1. In block 310, a photolithography process can be used to pattern the polyline. In other embodiments, any type of suitable semiconductor process can be used to perform the formation of the polyline. During the masking step, a single set of fold lines 210 may be formed on both the first active area 202 and the second active area 204. The final size can be set by the etching process. As shown in Figure 2A, each fold line can be separated by a substantially fixed pitch (P_c). In addition, the first active zone 202 and the second active zone 204 can be separated by a distance of less than 170 nm.

In the next block 320, a fold line 210 may be formed such that each fold line is associated with both the first channel length and the second channel length. In an embodiment, this formation may be performed in association with the mask 212. Then, the separation mask 214 can be used to separate the polyline 210 into a first polyline set 206 and a second polyline set 208 (block 330). The second mask can be specified in the standard component library, and can be an adjuster that improves the respective shapes of the overlapping area while separating the polylines 206 and 208 into distinct sets. Therefore, according to various exemplary embodiments, a component library that specifies double-line patterning can be advantageously used to specify different lengths and therefore different voltages in the same manufacturing and specifying process that further permits tighter spacing of the active regions 202 and 204. Construction of required devices.

It should be further noted that the standard component library disclosed above can be configured into a computer file with IC layout specifications according to output formats such as the following: Caltech Intermediary Format (CIF), Calma GDS Interchange Format (GDS II), Electronic Design Exchange Format (EDIF), Schematic User Environment (SUE), AutoCAD Mechanical Format (DXF), VHSIC Hardware Description Language (VHDL), Hardware Description Language (Verilog),<img file="TW201250996A_D0002.tif" />Circuit Description Language (CDL), EAGLE sketch extraction interface format, ECAD sketch extraction interface format, HPGL drawing language format, Postscript drawing language format, and the like. The specification file is stored on a computer readable medium. These files are provided to the manufacturing processor who makes devices based on these files. The resulting product is a semiconductor wafer, and then the semiconductor wafer is cut into semiconductor dies and packaged in the semiconductor wafer. The wafer is then used in the devices described above.

Figure 4 is a block diagram showing an exemplary wireless communication system 400 in which an embodiment of the present invention can be used. For illustrative purposes, FIG. 4 shows three remote units 420, 430, and 450, and two base stations 440. It should be noted that the conventional wireless communication system may have more remote units and base stations. The remote units 420, 430, and 450 may include devices 425A, 425B, and 425C that are an embodiment of the invention as discussed above. 4 further shows the forward link signal 480 from the base station 440 and the remote units 420, 440, and 450, and the reverse link signal 490 from the remote units 420, 430, and 450 to the base station 440.

In FIG. 4, the remote unit 420 is shown as a mobile phone, the remote unit 430 is shown as a portable computer, and the remote unit 450 is shown as a fixed location remote unit in the wireless zone loop system. For example, the remote unit can be a mobile phone, a handheld personal communication system (PCS) unit, a portable data unit such as a personal data assistant, a GPS enabled device, a navigation device, a set-top box, a music player, and a video player Devices, entertainment units, fixed-location data units such as meter reading equipment, or any other device that stores or retrieves data or computer commands, or any combination thereof. Although FIG. 4 illustrates a remote unit according to the teachings of the present invention, the present invention is not limited to these exemplary illustrated units. The embodiments of the present invention can be suitably used in any device including active integrated circuits (including memory and on-chip circuits for testing and characterization).

Although the foregoing disclosure shows illustrative embodiments of the present invention, it should be noted that various changes and modifications can be made herein without departing from the scope of the present invention as defined by the scope of additional patent applications. The functions, steps and/or actions of the method claims according to the embodiments of the present invention described herein do not need to be executed in any specific order. In addition, although the components of the present invention may be described or claimed in the singular form, the plural form is contemplated unless the limitation on the singular form is clearly stated.

<p>100. . . Semiconductor device</p><p>102. . . First action zone</p><p>104. . . Second area of action</p><p>106. . . First polyline set/polyline</p><p>108. . . Second polyline set/polyline</p><p>201. . . At the stage of the device before the line patterning</p><p>202. . . First action zone</p><p>203. . . Exemplary stage where the first broken line patterning of a semiconductor device occurs</p><p>204. . . Second area of action</p><p>205. . . The second patterning is an exemplary stage where the polyline is separated into two different polyline sets and</p><p>206. . . First polyline set/polyline</p><p>208. . . Second polyline set/polyline</p><p>210. . . Polyline/polyline collection</p><p>212. . . Appropriate step mask/first mask</p><p>214. . . Second mask/separation mask</p><p>400. . . Wireless communication system</p><p>420. . . Remote unit</p><p>425A. . . Device</p><p>425B. . . Device</p><p>425C. . . Device</p><p>430. . . Remote unit</p><p>440. . . Base station</p><p>450. . . Remote unit</p><p>480. . . Forward link signal</p><p>490. . . Reverse link signal</p>

FIG. 1 is a diagram illustrating a semiconductor designed using a standard component library with polylines separated by a fixed pitch with different channel lengths.

2A to 2C are diagrams showing different manufacturing stages of the semiconductor shown in FIG. 1.

FIG. 3 is a flowchart illustrating an exemplary procedure for manufacturing the semiconductor shown in FIG. 1. FIG.

Figure 4 is a block diagram showing an exemplary wireless communication system in which embodiments of the present invention can be used.