Package substrate having an embedded via hole medium layer and method of forming same

Package substrate with embedded through-hole interposer and its manufacturing method

The present invention relates to a packaging substrate and a manufacturing method thereof, in particular to a packaging substrate embedded with a through-hole interposer and a manufacturing method thereof.

With the vigorous development of the electronics industry, electronic products tend to be lighter, thinner, shorter and smaller in terms of function, and gradually enter the direction of high-performance, high-function, and high-speed research and development. Please refer to FIG. 1A, which is a schematic cross-sectional view of a conventional flip-chip package structure.

As shown in Figure 1A, the process of the package structure first provides a bismaleimide-triazine (Bismaleimide-Triazine, BT) package with a core board 102, a first surface 10a and a second surface 10b The substrate 10 has flip chip solder pads 100 on the first surface 10a of the package substrate 10; then the electrical connection pads 120 of the semiconductor chip 12 are electrically connected by solder bumps 11; A primer 17 is formed between a surface 10a and the semiconductor chip 12 to cover the solder bumps 11; and a second surface 10b of the packaging substrate 10 has a ball pad 101 to be electrically connected by solder balls 13 For example, another electronic device (not shown in the figure) such as a printed circuit board.

However, since the semiconductor chip 12 is a process with a size of 45nm or less, in the back-end process (Back-End Of Line, BEOL), ultra-low-k dielectric (ELK) or ultra-low-k dielectric will be used. Low dielectric constant (Ultra low-k, ULK) dielectric material, but the low-k dielectric material is porous and fragile, so that after flip chip packaging, the reliability thermal cycle test will be affected by The thermal expansion coefficient (CTE) difference between the packaging substrate 10 and the semiconductor chip 12 is too large, causing the solder bump 11 to be easily cracked due to uneven thermal stress, causing the semiconductor chip 12 to crack, resulting in a product Poor reliability.

Furthermore, as electronic products become more lightweight, thinner, shorter, and more functional, the wiring density of the semiconductor chip 12 is getting higher and higher, and the unit is nanometer size. Therefore, the spacing between the electrical connection pads 120 However, the distance between the flip chip pads 100 of the conventional package substrate 10 is measured in micrometers, and cannot be effectively reduced to the size corresponding to the distance between the electrical connection pads 120, resulting in a semiconductor with high circuit density The chip 12 does not have a compatible packaging substrate, so that it is impossible to effectively produce electronic products.

Please refer to Fig. 1B. In order to overcome the above-mentioned problem, a silicon interposer 14 is added between the package substrate 10 and the semiconductor chip 12'. The silicon interposer 14 has a Through-silicon via. TSV) 140 and a redistribution layer (RDL) 141 arranged on the top of the silicon via 140, so that the bottom of the silicon via 140 is electrically connected to the package substrate 10 with a larger pitch through the conductive bumps 142 Flip-chip soldering pad 100, and the uppermost circuit of the circuit redistribution layer 141 has electrode pads 1410 to electrically connect the electrical connection pads 120' of the semiconductor chip 12' with a smaller pitch through solder bumps 11', and then The packaging compound 18 is formed so that the packaging substrate 10 can be combined with the semiconductor chip 12' with high wiring density electrical connection pads 120', so as to achieve the purpose of integrating the semiconductor chip 12' with high wiring density. Therefore, the silicon interposer 14 not only solves the problem of lack of compatible packaging substrates, but also does not change the original supply chain and infrastructure of the IC industry.

Furthermore, by providing the semiconductor chip 12' on the silicon interposer 14, and the thermal expansion coefficient of the silicon interposer 14 is the same as the thermal expansion coefficient of the semiconductor chip 12' (CET is 2.6 ppm), the semiconductor The solder bump 11' between the chip 12' and the silicon interposer 14 is broken, which effectively improves the reliability of the product.

However, although the silicon interposer 14 solves the matching problem between the semiconductor chip 12 and the package substrate 10, the increase in the thickness of the silicon interposer 14 results in an increase in the thickness of the overall structure, which cannot meet the thinning requirements. The demand.

Furthermore, after the silicon interposer 14 is completed, conductive bumps 142 need to be fabricated to bond with the package substrate 10. Because the conductive bumps 142 need to be polished to a thickness of less than 100 microns, the conductive bumps 142 must be polished. , And the equipment and materials using thin wafers are very expensive, resulting in a substantial increase in cost, which is not conducive to mass production.

Therefore, how to overcome the various problems in the conventional technology has become an urgent problem to be solved at present.

In view of the various deficiencies of the above-mentioned conventional technologies, the present invention discloses a package substrate embedded with a through-hole interposer, which includes: a mold sealing layer having opposite first and second surfaces; and a through-hole interposer embedded in the The molding layer has a first side and a second side opposite to each other, and a plurality of conductive through holes penetrating the first side and the second side, and the conductive through holes respectively have first end surfaces on the first side and the second side And the second end surface, and the second side and the second end surface of the conductive through hole are flush with the second surface of the mold sealing layer; the circuit redistribution layer is embedded in the mold sealing layer and arranged in the through hole medium The first side of the layer and the first end surface of the conductive through hole are electrically connected to the first end surface of the conductive through hole, and the outermost layer of the circuit redistribution layer has an electrode pad, and the electrode pad is exposed on the mold sealing layer The first surface; and the build-up structure are provided on the second surface of the mold sealing layer, the second side of the perforated interposer and the second end surface of the conductive through hole, and have a plurality of conductive blind holes, and part of The conductive blind hole corresponds to the second end surface of the conductive through hole which is electrically connected.

In the aforementioned packaging substrate, the first surface of the mold sealing layer has a first opening, so that the electrode pad is correspondingly exposed in the first opening, so as to be used as a connection point for a flip chip connection chip.

The present invention further discloses a manufacturing method of a package substrate embedded with a through-hole interposer. The method includes: providing a carrier board; providing a through-hole interposer and a circuit redistribution layer disposed thereon. The through-hole interposer has opposite first sides and The second side and a plurality of conductive through holes penetrating the first side and the second side, the conductive through holes respectively have a first end surface and a second end surface on the first side and the second side, and the circuit redistribution layer is disposed on the The first side of the through-hole interposer and the first end surface of the conductive through hole, and the line redistribution layer is electrically connected to the first end surface of the conductive through hole, and the second end surface of the conductive through hole is flush with the second side, The second side and the second end surface of the conductive through hole are combined on the carrier board, and the outermost layer of the circuit redistribution layer has electrode pads; a mold sealing layer is formed on the carrier board and the circuit redistribution layer to make The perforated interposer is embedded in the mold seal layer, and the mold seal layer has an exposed first surface and a second surface bonded to the carrier board; a metal layer is formed on the first surface of the mold seal layer; Remove the carrier board to expose the second surface of the mold sealing layer, the second side of the perforated interposer and the second end surface of the conductive through hole; on the second surface of the mold seal and the first of the perforated interposer A build-up structure is formed on both sides and the second end surface of the conductive through hole, the build-up structure has a plurality of conductive blind holes, and part of the conductive blind holes are correspondingly electrically connected to the second end surface of the conductive through hole; remove the metal layer , Exposing the first surface of the mold sealing layer; and forming a first opening on the first surface of the mold sealing layer, so that the electrode pad is correspondingly exposed from the first opening.

In the aforementioned packaging substrate and its manufacturing method, the build-up structure has at least one dielectric layer and a circuit layer provided on the dielectric layer, and each of the conductive blind holes is provided in the dielectric layer and electrically connected The circuit layer and the second end surface of the conductive through hole. The compound includes an insulating protective layer, which is arranged on the build-up structure, and the insulating protective layer has a plurality of second openings, and the exposed part of the circuit layer is used as an electrical contact pad.

According to the above-mentioned structure and manufacturing method, an antenna structure or a heat sink is formed on the first surface of the mold sealing layer, and the heat sink has an opening to expose the electrode pads of the circuit redistribution layer for storing electronics element.

According to the above-mentioned structure and manufacturing method, the electronic component is combined on the carrier board, and the electronic component is embedded in the mold sealing layer and electrically connected to the build-up structure or the chip. In addition, the electronic component is, for example, an active component, a passive component, or an integrated passive component.

In the aforementioned package substrate and its manufacturing method, the material for forming the through-hole interposer is monocrystalline silicon or polysilicon, the sidewall of the conductive through-hole is provided with an insulating layer, and the manufacturing process of the through-hole interposer and the circuit redistribution layer includes : Provide a substrate, and form a plurality of cavities on the substrate; form an insulating layer on the sidewall of each cavity and the substrate, and the insulating layer on the substrate is defined as the first side; in the cavity A metal material is formed on the insulating layer to form the conductive through hole, and the first end surface of the conductive through hole is exposed on and flush with the first side; formed on the first side and the first end surface of the conductive through hole The circuit redistribution layer, the circuit redistribution layer is electrically connected to the first end surface of the conductive through hole, and the outermost layer of the circuit redistribution layer has the electrode pad; and the substrate material under the cavity is removed to form the The through-hole interposer and the second side are penetrated, and the second end surface of the conductive through hole is exposed on the second side.

In the aforementioned package substrate and its manufacturing method, the material for forming the through-hole interposer is glass or ceramic, and the process of the through-hole interposer and the circuit redistribution layer includes: providing a substrate and placing it on one of the surfaces of the substrate Defined as the first side, and a plurality of cavities are formed on the first side; a metal material is formed in the cavities to form the conductive through hole, and the first end surface of the conductive through hole is exposed on the first side and Flush with it; the circuit redistribution layer is formed on the first side and the first end surface of the conductive through hole, the circuit redistribution layer is electrically connected to the first end surface of the conductive through hole, and the most of the circuit redistribution layer The outer layer has the electrode pad; and the substrate material under the cavity is removed to form the through-hole interposer and the second side, and the second end surface of the conductive through hole is exposed on the second side.

In the aforementioned package substrate and its manufacturing method, the thickness of the through-hole interposer is preferably 75 to 150 microns.

It can be seen from the above that the packaging substrate with embedded through-hole interposer and its manufacturing method of the present invention mainly embed the through-hole interposer in the mold sealing layer to avoid stacking the through-hole interposer on the outside, thereby reducing the overall structure Thickness, and because the build-up structure is formed on the second surface of the mold sealing layer, the thickness of the overall structure can be reduced without using the core board of the conventional technology.

Furthermore, because the through-hole interposer is embedded in the mold sealing layer, the through-hole interposer can be electrically connected to the conductive blind holes of the build-up structure through the conductive through holes, so there is no need to make conductive bumps as in the conventional technology. Therefore, the production cost can be greatly reduced, which is conducive to mass production.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification.

Please refer to FIGS. 2A to 2F, which are schematic cross-sectional views of the manufacturing method of the package substrate embedded with the through-hole interposer disclosed in the present invention.

As shown in FIG. 2A, first, a carrier board 20, a perforated interposer 21 and a circuit redistribution layer 213 are provided.

The through-hole interposer 21 has a first side 21a and a second side 21b opposite to each other, and a plurality of conductive through holes 210 passing through the first side 21a and the second side 21b. The conductive through holes 210 are formed on the first side 21a and the second side 21b. The two sides 21b respectively have a first end surface 210a and a second end surface 210b, and the second end surface 210b of the conductive through hole 210 is flush with the second side 21b, so that the second side 21b is flush with the second side of the conductive through hole 210 The end surface 210b is combined with the supporting board 20. Furthermore, the thickness of the perforated interposer 21 is preferably 75 to 150 micrometers (μm).

The circuit redistribution layer 213 is disposed on the first side 21a of the through-hole interposer 21 and the first end surface 210a of the conductive through hole 210, and the innermost circuit of the circuit redistribution layer 213 is electrically connected to the conductive The first end surface 210 a of the through hole 210 and the outermost circuit of the circuit redistribution layer 213 have electrode pads 211.

As shown in Figure 2B, a mold sealing layer 22 is formed on the carrier board 20 and the circuit redistribution layer 213, so that the perforated interposer 21 is embedded in the mold sealing layer 22, and the mold sealing layer 22 has exposed The first surface 22a and the second surface 22b connected to the carrier board 20.

As shown in FIG. 2C, a metal layer 23 is formed on the first surface 22a of the molding layer 22.

As shown in FIG. 2D, the carrier board 20 is removed to expose the second surface 22b of the molding layer 22, the second side 21b of the through-hole interposer 21, and the second end surface 210b of the conductive through hole 210.

As shown in Figure 2E, using fan-out technology, on the second surface 22b of the molding layer 22, the second side 21b of the through-hole interposer 21, and the second end surface 210b of the conductive through hole 210 A build-up structure 24 is formed. The build-up structure 24 has a plurality of conductive blind holes 242, and part of the conductive blind holes 242 are correspondingly electrically connected to the second end surface 210b of the conductive through hole 210.

The build-up structure 24 has at least one dielectric layer 240 and a circuit layer 241 provided on the dielectric layer 240, and each of the conductive blind holes 242 is provided in the dielectric layer 240 and electrically connected to the dielectric layer 240. The circuit layer 241 and the second end surface 210 b of the conductive through hole 210. In addition, an insulating protective layer 25, such as a solder mask, is formed on the outermost dielectric layer 240 and the circuit layer 241 of the build-up structure 24, and the insulating protective layer 25 has a plurality of second openings 250 with exposed portions The outermost circuit layer 241 serves as an electrical contact pad 243.

As shown in Figure 2F, the metal layer 23 is removed to expose the first surface 22a of the mold sealing layer 22, and then a first opening 220 is formed on the first surface 22a of the mold sealing layer 22 to make the The electrode pad 211 is correspondingly exposed from the first opening 220.

In the package substrate of the present invention, by embedding the through-hole interposer 21 in the mold sealing layer 22, compared with the structure in which silicon interposers are stacked on the outside of the prior art, the present invention effectively reduces the thickness of the overall structure, and Since the build-up structure 24 is formed on the second surface 22b of the molding layer 22, it is not necessary to use the core board of the conventional technology, and the thickness of the overall structure is also reduced.

Furthermore, because the through-hole interposer 21 is embedded in the molding layer 22, the through-hole interposer 21 is electrically connected to the conductive blind hole 242 of the build-up structure 24 through the conductive through hole 210, so the through-hole intermediate layer The layer 21 does not need to fabricate conductive bumps as in the prior art on the second end surface 210b of the conductive via 210, thereby effectively reducing the manufacturing cost and facilitating mass production.

Please refer to Figure 2G, which is an application state of the package substrate of the present invention; as shown in Figure 2G, the chip 27 is electrically connected to the electrode pads of the circuit redistribution layer 213 by flip-chip through solder bumps 271 211, and then fill the bottom glue 270 between the electrode pad 211 and the chip 27, and use the electrical contact pad 243 as a bump pad and bond the solder balls 26 thereon to connect to, for example, a printed circuit Another electronic device of the board (not shown). Wherein, the chip 27 can also be multiple chips or passive components. The passive components can be capacitors, inductors, and resistors.

Combining the chip 27 with the through-hole interposer 21 of the package substrate can improve the reliability of the product compared to the flip-chip package substrate of the prior art.

Please refer to FIGS. 3A to 3D and FIGS. 4A to 4D, which show the different structures and manufacturing processes of the perforated interposer 21.

As shown in FIGS. 3A to 3D, the material of the through-hole interposer 21 is single crystal or poly silicon.

As shown in FIG. 3A, a substrate 21' is provided, and a plurality of cavities 210' are formed on the substrate 21'.

As shown in FIG. 3B, an insulating layer 212 is formed on the sidewall of each cavity 210' and on the substrate 21', and the surface of the insulating layer 212 on the substrate 21' is defined as the first side 21a; A metal material is formed on the insulating layer 212 in the cavity 210 to form the conductive through hole 210, and the first end surface 210 a of the conductive through hole 210 is exposed on the first side 21 a and is flush with it.

As shown in FIG. 3C, the circuit redistribution layer 213 is formed on the first side 21a and the first end surface 210a of the conductive via 210, and the innermost circuit of the circuit redistribution layer 213 is electrically connected to the conductive via 210 The first end surface 210a of the circuit redistribution layer 213 and the outermost circuit of the circuit redistribution layer 213 have the electrode pad 211.

As shown in FIG. 3D, a thinning process is performed to remove the substrate 21' material under the cavity 210' (below the imaginary line L shown in FIG. 3C) to form the through-hole interposer 21 and the second Side 21b, and the second end surface 210b of the conductive through hole 210 is exposed on the second side 21b.

In this manufacturing process, the insulating layer 212 is used to prevent the conductive via 210 and the silicon material of the via interposer 21 from being connected, thereby avoiding short circuits.

As shown in FIGS. 4A to 4D, the material of the perforated interposer 21 can be glass, or for example, Al₂O₃Or AlN ceramics, where the thermal expansion coefficient of ceramics (approximately 3 ppm/°C) is close to silicon, so it can be used.

As shown in FIG. 4A, a substrate 21' is provided, and one surface of the substrate 21' is defined as the first side 21a, and a plurality of cavities 210' are formed on the first side 21a.

As shown in FIG. 4B, a metal material is formed in the cavity 210' to form the conductive through hole 210, and the first end surface 210a of the conductive through hole 210 is exposed on and flush with the first side 21a.

As shown in FIG. 4C, the circuit redistribution layer 213 is formed on the first side 21a and the first end surface 210a of the conductive via 210, and the innermost circuit of the circuit redistribution layer 213 is electrically connected to the conductive via 210 The first end surface 210a of the circuit redistribution layer 213 and the outermost circuit of the circuit redistribution layer 213 have the electrode pad 211.

As shown in FIG. 4D, the substrate 21' material under the cavity 210' (below the imaginary line L shown in FIG. 4C) is removed to form the perforated interposer 21 and the second side 21b, and the The second end surface 210b of the conductive through hole 210 is exposed on the second side 21b.

In this manufacturing process, since the glass or ceramic silicon of the through-hole interposer 21 is an insulator, it is not necessary to form an insulating layer 212 on the sidewall of each cavity 210'.

In the above two manufacturing processes, since the through-hole interposer 21 is embedded in the molding layer 22, there is no need to fabricate conductive bumps on the second end surface 210b of the conductive through hole 210, thereby reducing the manufacturing cost.

Furthermore, the thermal expansion coefficient of the through-hole interposer 21 is close to or the same as that of the silicon wafer, which can improve the reliability of the thermal cycle test after packaging.

Please also refer to FIGS. 5A, 6A, and 7A and FIGS. 5B, 6B, and 7B, which are other embodiments and applications of the package substrate embedded in the through-hole interposer 21 of the present invention.

As shown in FIG. 5A, in the package substrate shown in FIG. 2F, an antenna structure 29 is formed on the first surface 22a of the molding layer 22, and the antenna structure 29 is embedded in a dielectric material. Furthermore, before the molding layer 22 is formed (before the process in Figure 2B), the first electronic component 30 with the electrical connection pad 300 can be combined on the carrier board 20, so that the first electronic component 30 is embedded in In the molding layer 22 and when the build-up structure 24 is formed, the first electronic component 30 can be electrically connected to the conductive blind via 242 of the build-up structure 24 through the electrical connection pad 300. Wherein, the first electronic component 30 is an active component (semiconductor chip, etc.), a passive component (capacitor, inductor, resistor) or an integrated passive device (IPD).

As shown in Fig. 5B, it is the application of the package substrate shown in Fig. 5A. The chip 27 is electrically connected to the electrode pad 211 of the circuit redistribution layer 213 by means of solder bumps 271 in a flip chip manner. A primer 270 is filled between the electrode pad 211 and the chip 27, and a solder ball 26 is bonded to the electrical contact pad 243 to connect to another electronic device such as a printed circuit board (not shown) .

As shown in FIG. 6A, in the package substrate shown in FIG. 2F, before the molding layer 22 is formed, a second electronic component 30' with an electrical connection pad 300' can also be combined on the carrier board 20 , The second electronic component 30' is embedded in the molding layer 22, and the electrical connection pad 300' of the second electronic component 30' can be correspondingly exposed in the third opening 221 of the molding layer 22 . Wherein, the second electronic component 30' is an active component (semiconductor chip, etc.), a passive component (capacitor, inductor, resistor) or an integrated passive component (IPD).

As shown in Figure 6B, it is an application of the package substrate shown in Figure 6A. Another chip 27' is electrically connected to the electrode pad 211 and the second electronic component by means of solder bumps 271 in a flip chip manner. On the electrical connection pad 300 of 30, a primer 270 is filled between the package substrate and the chip 27, and solder balls 26 are bonded to the electrical contact pad 243 to be connected to, for example, printing Another electronic device on the circuit board (not shown).

As shown in FIG. 7A, in the package substrate shown in FIG. 2F, the first electronic component 30 is embedded in the molding layer 22, and a heat sink is formed on the first surface 22a of the molding layer 22 31. The heat sink 31 has an opening 310 outside of which the electrode pad 211 of the circuit redistribution layer 213 is exposed, and is used for accommodating electronic components.

As shown in Fig. 7B, it is an application of the package substrate shown in Fig. 7A. On the electrode pad 211, two chips 28 are electrically connected by a flip chip method through solder bumps 271, so that each chip 28 is located the open port 310, and then to the opening 310, is formed on the heat sink 31 and the plurality of chip encapsulant 28, such as: thermal plastic 32 encapsulating the wafer 28.

In the description of the above embodiments and their applications, the components in the package substrate, such as the antenna structure 29, the first electronic component 30, the second electronic component 30' or the heat sink 31, can be added as required. It is not limited to the above type, and there is no particular limitation on the number of chips 27, 27', 28 in application.

The present invention further provides a package substrate embedded with a through-hole interposer 21, which includes: a mold sealing layer 22 having opposite first and second surfaces 22a and 22b, and a through-hole interposer 21 embedded in the mold sealing layer 22 , The circuit redistribution layer 213 embedded in the mold sealing layer 22 and arranged on the perforated interposer 21, and the build-up structure 24 arranged on the second surface 22b of the mold sealing layer 22.

The first surface 22 a of the mold sealing layer 22 has a first opening 220.

The through-hole interposer 21 has a first side 21a and a second side 21b opposite to each other, and a plurality of conductive through holes 210 passing through the first side 21a and the second side 21b. The conductive through holes 210 are formed on the first side 21a and the second side 21b. The two sides 21 b respectively have a first end surface 210 a and a second end surface 210 b, and the second side 21 b and the second end surface 210 b of the conductive through hole 210 are flush with the second surface 22 b of the molding layer 22. Furthermore, the material for forming the through-hole interposer 21 is glass, ceramic, monocrystalline silicon or polycrystalline silicon. If it is monocrystalline silicon or polycrystalline silicon, an insulating layer 212 is provided on the sidewall of the conductive through hole 210.

The circuit redistribution layer 213 is disposed on the first side 21a of the through-hole interposer 21 and the first end surface 210a of the conductive through hole 210, and the innermost circuit of the circuit redistribution layer 213 is electrically connected to the conductive The first end surface 210a of the through hole 210, and the outermost circuit of the circuit redistribution layer 213 has an electrode pad 211, and the electrode pad 211 corresponds to the first opening 220 exposed in the mold sealing layer 22 for use as a flip chip connection At least one chip 27, 27', 28 connection point.

The build-up structure 24 is multiplexed on the second side 21b of the through-hole interposer 21 and the second end surface 210b of the conductive through hole 210. The build-up structure 24 has at least one dielectric layer 240 and is disposed on the dielectric layer. The circuit layer 241 on the electric layer 240 and the plurality of conductive blind holes 242 disposed in the dielectric layer 240 and electrically connecting the circuit layer 241 and the second end surface 210b of the conductive through hole 210.

The packaging substrate includes an insulating protective layer 25, which is disposed on the build-up structure 24, and the insulating protective layer 25 has a plurality of second openings 250, and the exposed part of the circuit layer 241 is used as electrical power. The pad 243 is contacted, and the solder ball 26 is bonded.

The packaging substrate includes an antenna structure 29, which is disposed on the first surface 22 a of the molding layer 22.

The packaging substrate includes the first electronic component 30, which is embedded in the mold sealing layer 22 and electrically connected to the build-up structure 24.

The packaging substrate further includes a second electronic component 30' with an electrical connection pad 300', which is embedded in the mold sealing layer 22, and makes the electrical connection pad 300' of the second electronic component 30' correspond to Exposed in the mold sealing layer 22.

The packaging substrate further includes a heat sink 31, which is disposed on the first surface 22a of the mold sealing layer 22, and the heat sink 31 has an opening 310 to expose the electrode pads 211 of the circuit redistribution layer 213. And for storing electronic components.

In summary, the packaging substrate of the present invention embedded with a through-hole interposer and its manufacturing method are based on the technology of embedding the through-hole interposer in the mold sealing layer to avoid stacking the through-hole interposer and using the core board, so it is effective Reduce the thickness of the overall structure.

Furthermore, because the through-hole interposer is embedded in the mold sealing layer, the through-hole interposer is electrically connected to the conductive blind hole of the build-up structure through the conductive through hole, so the through-hole interposer does not need to be in the conductive through hole. Conductive bumps are made on the end surface to effectively reduce the production cost.

In addition, the reliability of the product can be improved by combining the chip with the through-hole interposer.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone who is familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

<p>10. . . Package substrate</p><p>10a, 22a. . . First surface</p><p>10b, 22b. . . Second surface</p><p>100. . . Flip chip pad</p><p>101. . . Ball planting pad</p><p>102. . . Core board</p><p>11,11',271. . . Solder bump</p><p>12,12'. . . Semiconductor wafer</p><p>120,120',300,300'. . . Electrical connection pad</p><p>13,26. . . Solder ball</p><p>14. . . Silicon interposer</p><p>140. . . Silicon perforation</p><p>141,213. . . Line re-layout</p><p>1410,211. . . Electrode pad</p><p>142. . . Conductive bump</p><p>17,270. . . Primer</p><p>18. . . Encapsulation colloid</p><p>20. . . Carrying board</p><p>twenty one. . . Perforated interposer</p><p>21a. . . First side</p><p>21b. . . Second side</p><p>210. . . Conductive perforation</p><p>210a. . . First end</p><p>210b. . . Second end</p><p>212. . . Insulation</p><p>twenty one'. . . Substrate</p><p>210'. . . Pit</p><p>twenty two. . . Molding layer</p><p>220. . . First opening</p><p>221. . . Third opening</p><p>twenty three. . . Metal layer</p><p>twenty four. . . Build-up structure</p><p>240. . . Dielectric layer</p><p>241. . . Circuit layer</p><p>242. . . Conductive blind hole</p><p>243. . . Electrical contact pad</p><p>25. . . Insulation protection layer</p><p>250. . . Second opening</p><p>27,27',28. . . Chip</p><p>29. . . Antenna structure</p><p>30. . . First electronic component</p><p>30'. . . Second electronic component</p><p>31. . . heat sink</p><p>310. . . Opening</p><p>32. . . Thermal glue</p><p>L. . . Imaginary line</p>

FIG. 1A is a schematic cross-sectional view of a conventional flip chip package structure;

Figure 1B is a schematic cross-sectional view of a conventional package substrate with a silicon interposer;

Figures 2A to 2F are schematic cross-sectional views of the manufacturing method of the package substrate embedded in the through-hole interposer of the present invention; Figure 2G is the application state of the package substrate embedded in the through-hole interposer of the present invention;

3A to 3D are schematic cross-sectional views of the manufacturing process of the embedded through-hole interposer according to the present invention;

4A to 4D are schematic cross-sectional views of another process aspect of the embedded through-hole interposer according to the present invention;

Figures 5A, 6A, and 7A are other embodiments of the package substrate with embedded through-hole interposer according to the present invention; and

Figures 5B, 6B, and 7B show different application aspects of the package substrate embedded with the through-hole interposer according to the present invention.