Method and apparatus for a LED driver with high power factor

Control method and control circuit of high power factor light emitting diode driver

The present invention is related to light emitting diode (LED) drivers. More specifically, the present invention relates to a control method and control circuit of a high power factor light emitting diode driver.

Offline LED drivers usually use flyback power conversion with primary side regulation to adjust the output current. FIG. 1 shows the prior art of an offline LED driver. The offline LED driver has an input electrolytic capacitor 40 for energy storage.

As shown in FIG. 1, the traditional offline LED driver includes a rectifier 12, and the rectifier 12 receives an input line voltage V_ACAnd for the input line voltage V_ACRectify. The input electrolytic capacitor 40 is coupled to an output terminal of the rectifier 12 for storing energy. A voltage V_DCProvided by the input electrolytic capacitor 40. A transformer 10 has a primary winding N_P, Primary and secondary winding N_SWith an auxiliary winding N_A。

Primary winding N_POne end is coupled to and receives the voltage V_DC. Primary winding N_PThe other end of is coupled to a transistor 20. The transistor 20 is used to switch the transformer 10. Secondary winding N_SOne end of is coupled to one end of a rectifier 60. An output capacitor 65 is connected to the secondary winding N_SBetween the other end of the rectifier 60 and the other end of the rectifier 60. The output capacitor 65 is used to provide an output voltage V_OGive multiple light-emitting diodes 70~79. The light emitting diodes 70 to 79 are connected to each other in series and connected in parallel with the output capacitor 65. Auxiliary winding N_AOne end of is coupled to the anode end of a diode 41. A capacitor 45 is coupled between the cathode terminal of the diode 41 and a ground terminal. Auxiliary winding N_AThe capacitor 45 is charged through the diode 41 to generate a supply power V_CCTo a switching controller 50.

Auxiliary winding N_AOne end of is further coupled to a voltage divider. The voltage divider is composed of resistors 51 and 52. The resistors 51 and 52 are connected in series with each other. The voltage divider generates a voltage detection signal V_S. The resistor 52 is further coupled to the ground terminal. The switching controller 50 is coupled to a connection point between the resistors 51 and 52 for receiving the voltage detection signal V_S。

The switching controller 50 generates a switching signal SW. The switching signal SW controls the transistor 20 to switch the transformer 10 to adjust an output of the LED driver (output current I_OAnd/or output voltage V_O). When the transistor 20 is turned on, a switching current I_PWill flow through the transformer 10. It is coupled to the transistor 20 through a resistor 30 to switch the current I_PIs used to generate a current detection signal V_CS. Current detection signal V_CSCoupled to the switching controller 50.

Input line voltage V_ACAnd voltage V_DCThe waveform is shown in Figure 2. Voltage V_DCIs the voltage on the input electrolytic capacitor 40. Voltage V_DCThe minimum value will maintain the normal operation of the power conversion. However, the input electrolytic capacitor 40 causes an input current I_DCDistortion and low power factor (Power Factor). Therefore, the capacitance value of the input electrolytic capacitor 40 must be reduced to improve the power factor. However, no input electrolytic capacitor 40 will cause a voltage V_DCToo low.

Voltage V_DCToo low may cause an open circuit in the feedback of the light emitting diode (LED) driver. The output voltage of the LED driver V_OIt can be expressed by the following equation (1):

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Among them, N is the turns ratio of the transformer 10 (N=N_S/N_P; N_PIs the primary winding, N_SIs the secondary winding); V_DCIs the input voltage of the transformer 10; T_ONIs the conduction time of the transistor 20; T is the switching period of the transistor 20.

In order to obtain a stable feedback loop and prevent transformer saturation, the maximum duty cycle "T_ON/T" is limited, for example, generally less than 80%. Assuming the voltage V_DCToo low, the maximum on-time T of the switching signal SW_ONWill not be able to maintain the output voltage V_O(Shown in equation (1)) and cause feedback open circuit. When the feedback loop corresponds to the input line voltage V_ACSignificant turn-on/off (close-loop and open-loop) due to the change of, an overshoot signal and/or undershoot signal may easily be generated on the LED The output of the body drive. In addition, the input electrolytic capacitor 40 is a bulky electrolytic capacitor with low reliability.

One of the objectives of the present invention is to improve the power factor of the LED driver.

One of the objectives of the present invention is to increase the reliability of the light-emitting diode driver without requiring an input electrolytic capacitor, while reducing the size and cost of the light-emitting diode driver.

One of the objectives of the present invention is to provide a control circuit and a control method of a light-emitting diode driver. The present invention can eliminate the need for input capacitance, and is used to increase the reliability of the light-emitting diode driver.

One of the objectives of the present invention is to provide a control circuit and a control method of a light-emitting diode driver. The present invention allows the LED driver to provide output adjustment without input capacitance, so as to improve the power factor and reduce the size and cost of the LED driver.

One of the objectives of the present invention is to provide a control circuit and a control method of a light-emitting diode driver. The invention controls the light-emitting diode driver to provide a certain current to drive the light-emitting diode.

One of the objectives of the present invention is to provide a control circuit and a control method for use in a light-emitting diode driver without an input electrolytic capacitor. According to the present invention, the control circuit includes: an output circuit, an input circuit, and an input voltage detection circuit.

The output circuit generates a switching signal according to a feedback signal to generate an output current to drive at least one light emitting diode. The switching signal is used to switch a transformer. The input circuit samples an input signal to generate a feedback signal. The input signal is related to the output current of the LED driver. The input voltage detection circuit generates an input voltage signal according to an input voltage of the LED driver. When the input voltage signal is lower than a critical value, the input circuit will stop sampling the input signal.

In order to enable your reviewer to have a better understanding and understanding of the technical features of the present invention and the achieved effects, I would like to provide a preferred embodiment diagram and detailed descriptions. The description is as follows:

Figure 3 is a preferred embodiment of the present invention. For a detailed description of the flyback power converter controlled by the primary side, please refer to U.S. Patent No.<b>6,977,824</b>No. "Control circuit for controlling output current at the primary side of a power converter", U.S. Patent No.<b>7,016,204</b>No. "Close-loop PWM controller for primary-side controlled power converters", U.S. Patent No.<b>7,349,229</b>No. "Causal sampling circuit for measuring reflected voltage and demagnetizing time of transformer", U.S. Patent No.<b>7,486,528</b>Known technologies such as "Linear-predict sampling for measuring demagnetized voltage of transformer". Regarding the power factor correction technology, please refer to the U.S. Patent No.<b>7,116,090</b>Known technology named "Switching control circuit for discontinuous mode PFC converters".

As shown in FIG. 3, this embodiment of the present invention is substantially the same as the conventional offline light emitting diode (LED) driver (as shown in FIG. 1), except for the switching controller 100. In addition, this embodiment does not require an input electrolytic capacitor 40 (as shown in FIG. 1). Transformer 10 includes: primary winding N_P, Auxiliary winding N_AWith secondary winding N_S. Primary winding N_PUsed to receive the input voltage V_IN. The rectifier 12 receives the input line voltage V_AC, And rectify the above-mentioned input line voltage V_ACUsed to generate input voltage V_IN. Resistors 51 and 52 are connected to the auxiliary winding N_A, Used to generate a voltage detection signal V coupled to the switching controller 100_S。

Voltage detection signal V_SIs the output voltage V_OAnd the input voltage V_INA voltage signal related to the level. The switching controller 100 is a control circuit that generates the switching signal SW. The switching signal SW is coupled to the transformer 10, and the transformer 10 is switched through the transistor 20 to adjust an output (output current I_OOr/and output voltage V_O). The switching controller 100 is a controller controlled by the primary side. The resistor 30 is connected between the transistor 20 and the ground terminal. When the transistor 20 is turned on, the switching current I_PWill flow through the transformer 10. Through resistor 30, switch current I_PIt is further used to generate the current detection signal V_CS. Current detection signal V_CSCoupled to the switching controller 100. Switching current I_PIs a current signal and is related to the output current I_OAnd input voltage V_IN. Therefore, the current detection signal V_CSRepresents the switching current I_PAnd output current I_ORelated. The diode 41 and the capacitor 45 are coupled to the auxiliary winding N_A, Used to generate supply power V_CCGo to the switching controller 100.

FIG. 4 is a schematic circuit diagram of a preferred embodiment of the switching controller 100 of the present invention. The switching controller 100 includes a first input circuit and a second input circuit. The first input circuit includes: a voltage detection circuit (V-DET) 150, a first error amplifier 160, and a first low-pass filter (LPF) 400. The second input circuit includes: a current detection circuit (I-DET) 200, an integrator 250, a second error amplifier 170, and a second low pass filter (LPF) 450. Voltage detection signal V_SAnd current detection signal V_CSEach is provided to the voltage detection circuit 150 and the current detection circuit 200 as a first input signal and a second input signal, respectively. The voltage detection circuit 150 receives and samples the voltage detection signal V_STo generate a first feedback signal and a degaussing time signal S_DS。

The first feedback signal is a voltage feedback signal V_V. Degaussing time signal S_DSIt is sent to the integrator 250. The first error amplifier 160 receives and compares the voltage feedback signal V_VAnd a first reference signal V_RVTo generate a first amplified signal E_V. The first error amplifier 160 is used to form a feedback loop. The first low-pass filter 400 is coupled to and receives the first amplified signal E_V, Used for loop compensation (frequency compensation of feedback loop) and generate a voltage loop signal COMV. The detailed description of the voltage detection circuit 150 can be found in the prior art, such as US Patent No.<b>7,016,204</b>Learned.

The current detection circuit 200 is coupled to and receives the current detection signal V_CS, And generate a second feedback signal through the integrator 250. The second feedback signal is a current feedback signal V_I. The current detection circuit 200 measures the current detection signal V_CSTo generate a current waveform signal. The integrator 250 controls the current waveform signal and the degaussing time signal S_DSIntegrate to generate current feedback signal V_I. This means that the current detection circuit 200 detects the sampling current detection signal V_CSTo generate current feedback signal V_I. The integrator 250 is used for constant current control. The detailed description of the current detection circuit 200 and the integrator 250 can be found in the prior art (e.g., U.S. Patent No.<b>7,016,204</b>).

The second error amplifier 170 receives and compares the current feedback signal V_IAnd a second reference signal V_RI, To generate a second amplified signal E_I. The second error amplifier 170 is used as another feedback loop. The second low-pass filter 450 is coupled to and receives the second amplified signal E_I, Used for additional compensation (frequency compensation of feedback loop), and generate a current loop signal COMI. The voltage loop signal COMV and the current loop signal COMI are both coupled and sent to a pulse width modulation circuit (PWM) 500 to generate the switching signal SW. The pulse width modulation circuit 500 is further coupled to and receives the degaussing time signal S_DS。

The pulse width modulation circuit 500 is an output circuit, which is used to generate the switching signal SW according to the feedback signal. Through the transistor 20, the switching signal SW is used to switch the transformer 10 to adjust the output of the light emitting diode (LED) driver. In other words, the pulse width modulation circuit 500 is based on the voltage feedback signal V_VAnd current feedback signal V_IA switching signal SW is generated to adjust the output of the light-emitting diode driver. The output of the LED driver is the output voltage V_OAnd/or output current I_O(As shown in Figure 3).

The output current I of the LED driver_OIt is a fixed current used to drive the light-emitting diodes 70~79 (as shown in Figure 3). Therefore, the switching signal SW is controlled by the current loop signal COMI to achieve a constant output current I under normal conditions._O. When driving the LED 70~79 open circuit, the voltage loop signal COMV is used to limit the maximum output voltage V_O. Therefore, in order to achieve a high PF (power factor), the second low-pass filter 450 is developed to provide a constant on-time for the switching signal SW during the linear frequency. Therefore, the bandwidth of the second low-pass filter 450 should be lower than the linear frequency, and the current feedback signal V_IIt is a low-bandwidth signal to provide a fixed on-time for the switching signal SW. In general, the linear frequency is 50 or 60 Hz, but the input line voltage V_AC(Shown in Figure 3) is rectified by the bridge rectifier 12, the input line voltage V_ACAfter rectification, the linear frequency will be twice, for example 120 Hz.

Voltage detection signal V_SIt is also coupled and sent to an input voltage detection circuit (V_IN-DET)110 to generate an input voltage signal E_IN. Voltage detection signal V_SRelated to the input voltage V of the LED driver_IN(As shown in Figure 3). Therefore, the input voltage detection circuit 110 detects the input voltage V of the LED driver through the resistors 51 and 52_IN, And according to the input voltage V of the LED driver_INVoltage level to generate the input voltage signal E_IN. Therefore, the input voltage signal E_INThe level of is related to the input voltage V of the LED driver_INThe voltage level. A comparator 120 is coupled to and receives the input voltage signal E_INWith a critical value V_TFor comparison. When the input voltage signal E_INBelow the critical value V_TAt this time, the comparator 120 will generate a blanking signal BLK, and the blanking signal BLK is a low-true signal. The blanking signal BLK is coupled and sent to the error amplifiers 160 and 170 to stop the sampling voltage feedback signal V_VAnd current feedback signal V_I. This is the same as when the input voltage signal E_INBelow the critical value V_TStop the input circuit from responding to the input signal (voltage detection signal V_SAnd/or current detection signal V_CS)sampling. The blanking signal BLK is further coupled to the low-pass filters 400 and 450 to inhibit the amplification of the signal E_VWith E_Isampling.

Figure 5 shows that the blanking signal BLK corresponds to the input voltage V_INAnd input voltage signal E_INofwaveform. The blanking signal BLK (low level is true signal) is at the input voltage signal E_INBelow the critical value V_TTime was produced. FIG. 6 shows a schematic circuit diagram of a preferred embodiment of the error amplifiers 160 and 170 of the present invention. Error amplifiers 160 and 170 are used for the feedback signal V_X(For example: voltage feedback signal V_VOr current feedback signal V_I) Carry out error amplification, and input voltage signal E_INBelow the critical value V_TWhen, stop the error amplification (as shown in Figure 5). An operational amplifier 165 is a transconductance amplifier, which is used to generate the amplified signal E_X(For example: the first amplified signal E_VOr the second amplified signal E_I)。

A switch 161 is coupled to and receives the feedback signal V_X(For example: voltage feedback signal V_VOr current feedback signal V_I) And connected to the negative input terminal of the operational amplifier 165. A reference signal V_RX(For example: the first reference signal V_RVOr the second reference signal V_RI) Is coupled to and transmitted to the positive input terminal of the operational amplifier 165. A switch 162 is coupled between the negative input terminal and the positive input terminal of the operational amplifier 165. The blanking signal BLK is coupled to and controls the switch 161. Through the inverter 163, the blind signal BLK is coupled to and controls the switch 162. Therefore, most of the time, the negative input terminal of the operational amplifier 165 is connected and receives the feedback signal V_X。

This is because when the two input terminals of the conductive amplifier are short-circuited, there will be no current output and high impedance. Therefore, when the blackout signal BLK is enabled (low logic level), the switch 161 is turned off and the switch 162 is turned on, and the negative input terminal and the positive input terminal of the operational amplifier 165 are short-circuited and connected and receive the reference signal V_RX. Therefore, the error amplifiers 160 and 170 are not connected and do not receive the feedback signal V_X. Just like when the input voltage signal E_INBelow the critical value V_TAt this time, the error amplifiers 160 and 170 stop performing error amplification.

FIG. 7 shows a schematic circuit diagram of a preferred embodiment of the low-pass filters 400 and 450 of the present invention. The low-pass filters 400 and 450 are used for low-pass filtering. Low-pass filtering is performed on the input voltage signal E_INBelow the critical value V_TWhen (as shown in Figure 5) to maintain the previous state. The switches 420 and 430 and the capacitors 425 and 435 constitute a low-pass switching filter for loop compensation and low-pass filtering. One end of the switch 420 is coupled to and receives the amplified signal E_X(For example: the first amplified signal E_VOr the second amplified signal E_I). The capacitor 425 is coupled between the other terminal of the switch 420 and the ground terminal. The switch 430 is coupled between the capacitors 425 and 435. The capacitor 435 generates a loop signal COMX (for example, a voltage loop signal COMV or a current loop signal COMI). Clock signal CK₁With CK₂Individually coupled and transmitted to an input terminal of AND gates 411 and 410. The blanking signal BLK is coupled and sent to the other input terminals of the gates 411 and 410. The output terminal of the gate 411 is used to control the switch 420, which is used to amplify the signal E_XSample to capacitor 425. The output terminal of the gate 410 is used to control the switch 430, which is used to transfer the amplified signal E stored in the capacitor 425_XThe capacitor 435 is sampled to generate the loop signal COMX.

Clock signal CK₁With CK₂The switches 420 and 430 are controlled through the gates 411 and 410. Among them, the blanking signal BLK passes through the gates 411 and 410 to turn off the switches 420 and 430. Therefore, when the blanking signal BLK is enabled, the signals on the capacitors 425 and 435 will remain in the previous state. According to the present invention, when the input voltage V_INBelow the critical value V_TWhen (as shown in Figure 5), the feedback loop of the LED driver will remain in the previous state. Therefore, the feedback loop will remain stable, and there will be no overshoot and undershoot phenomena.

FIG. 8 is a preferred circuit diagram of the pulse width modulation circuit 500 of the present invention. A signal generating circuit (OSC) 300 generates a pulse signal PLS for turning on the switching signal SW through the inverter 90. The inverter 90 is coupled between the output of the signal generating circuit 300 and the clock input terminal ck of a flip-flop 97. The input terminal D of the flip-flop 97 is coupled to and receives the supply power V_CC. The output terminal Q of the flip-flop 97 is coupled to an input terminal of an AND gate 98 for generating a switching signal SW at the output terminal of the AND gate 98. The other input terminal of the AND gate 98 is coupled to the output terminal of the inverter 90 for receiving the PLS for the pulse signal.

The signal generating circuit 300 further generates a ramp signal RMP. The negative input terminals of the comparators 91 and 92 are coupled to and receive the ramp signal RMP for comparison with the voltage loop signal COMV and the current loop signal COMI to be cut off by a gate 95 Switch signal SW. The voltage loop signal COMV and the current loop signal COMI are individually coupled and sent to the positive input terminals of the comparators 91 and 92. The input terminal of the AND gate 95 is coupled to the output terminals of the comparators 91 and 92, and the output terminal of the gate 95 is coupled to the reset input terminal R of the flip-flop 97, and is used to reset the flip-flop 97 and turn off the switching signal SW.

The signal generating circuit 300 is based on the unanimous energy signal S_ENBThe pulse signal PLS is generated to enable the power conversion to achieve "boundary current mode (BCM) operation". Enabling signal S_ENBAccording to the degaussing time signal S_DSAnd the switching signal SW is generated. Boundary current mode (BCM) operation will improve power factor. Degaussing time signal S_DSThe enabling signal S is generated through an inverter 82, a delay circuit (TDEY) 83 and an and gate 85_ENB. The switching signal SW generates an enabling signal S through an inverter 81 and a gate 85_ENB. Degaussing time signal S_DSEnabling means that the transformer 10 (as shown in FIG. 3) is completely demagnetized.

The input terminal of the inverter 82 receives the degaussing time signal S_DS, The output terminal of the inverter 82 is coupled to the input terminal of the delay circuit 83. The output terminal of the delay circuit 83 is coupled to the input terminal of the gate 85. The other input terminal of the AND gate 85 is coupled to the output terminal of the inverter 81. The input terminal of the inverter 81 is coupled to and receives the switching signal SW. The output terminal of the gate 85 generates the enable signal S_ENB。

FIG. 9 is a circuit diagram of a preferred embodiment of the signal generating circuit 300 in the present invention. A current source 350 is coupled to a capacitor 340 through a switch 351 for charging the capacitor 340. The current source 350 is coupled to the supply power V_CCAnd one end of the switch 351. The capacitor 340 is coupled between the other end of the switch 351 and the ground. A current source 355 is coupled to the capacitor 340 through a switch 354 for discharging the capacitor 340. The current source 355 is coupled between the ground terminal and one end of the switch 354. The other end of the switch 354 is coupled to the capacitor 340. The switch 351 is controlled by a charging signal. Switch 354 is controlled by a discharge signal S_DM. The capacitor 340 thus generates a ramp signal RMP, which is coupled to and sent to the comparators 361, 362, and 363.

The ramp signal RMP is coupled to the negative input terminal of the comparator 361. The ramp signal RMP is further coupled to the positive input terminals of the comparators 362 and 363. The positive input terminal of the comparator 361 is coupled to a critical value V_H, Used to compare with the ramp signal RMP. The negative input terminal of the comparator 362 is coupled to and receives a threshold value V_L, Used to compare with the ramp signal RMP. The negative input terminal of the comparator 363 is coupled to and receives a threshold value V_M, Used to compare with the ramp signal RMP. Among them, the critical value V_H&gt;Critical value V_M&gt;Critical value V_L。

The inverters 365 and 366 form a latch circuit and receive the output signals of the comparators 361 and 362. The latch circuit outputs a discharge signal S_D. Discharge signal S_DIt is a maximum frequency signal. An input terminal of the inverter 365 is coupled to the output terminal of the comparator 361. An input terminal of the inverter 366 is coupled to the output terminal of the comparator 362. The other input terminal of the inverter 365 is coupled to the output terminal of the inverter 366. The output terminal of the inverter 365 generates a discharge signal S_DAnd coupled to the other input terminal of the inverter 366. Discharge signal S_DThe output signal of the comparator 363 and the output signal of the comparator 363 are respectively connected to the input terminal of an and gate 367 to generate a discharge signal S_DM。

Discharge signal S_DAn inverter 375 is connected to generate a charging signal. The charging signal is connected and sent to an inverter 376 for generating the pulse signal PLS. The pulse signal PLS is generated during the discharge period of the capacitor 340 (as shown in FIG. 10). Discharge signal S_DIt is also coupled and sent to the input terminal of a gate 370 to generate a fast discharge signal S_FD. Fast discharge signal S_FDAnd enabling signal S_ENBThey are respectively connected to the input terminals of an OR gate 371. The output terminal of the OR gate 371 is connected to the other input terminal of the AND gate 370. Therefore, in the discharge signal S_DWhen enabling, enabling signal S_ENBWill trigger the fast discharge signal S_FD. Only when the discharge signal S_DWhen cut off, fast discharge signal S_FDCan be cut off.

A current source 359 is connected between the ground terminal and one end of a switch 358. The other end of the switch 358 is coupled to the capacitor 340 through the switch 354. Switch 358 is controlled by fast discharge signal S_FD. Since the current source 359 has a large current, when the rapid discharge signal S_FDWhen enabled, the capacitor 340 will be discharged immediately. During the discharge, the ramp signal RMP is maintained at the critical value V_MUntil the enabling signal S_ENBTrigger fast discharge signal S_FD. When the capacitor 340 is discharged and is lower than the critical value V_LWhen, the discharge signal S_DWill end. Degaussing time signal S_DS(As shown in Figure 8) Therefore, the discharge signal S_DWhen enabled, the pulse signal PLS can be triggered. Therefore, the switching control of power transition can be operated in Boundary Current Mode (BCM). The amount of current of the current source 350 and the capacitance of the capacitor 340 and the critical value V_H, V_MWith V_LDetermine the discharge signal S_DAnd determine the maximum frequency of the switching signal SW (as shown in Figure 8).

Figure 10 shows the switching signal SW operating in the Boundary Current Mode (BCM). The switching signal SW is turned on during the period T1. Period T_SThe demagnetization time of the transformer 10 (shown in FIG. 3) is displayed. Degaussing time and degaussing time signal S_DSRelated.

Therefore, the present invention is really novel, progressive, and available for industrial use. It should meet the patent application requirements of my country's patent law. Undoubtedly, I filed an invention patent application in accordance with the law. I pray that the office will grant the patent as soon as possible.

However, the foregoing is only a preferred embodiment of the present invention, and is not used to limit the scope of implementation of the present invention. Therefore, all the equivalent changes and changes in the shape, structure, characteristics and spirit described in the scope of the patent application of the present invention are mentioned. All modifications shall be included in the scope of the patent application of the present invention.

<p>10. . . transformer</p><p>12. . . Rectifier</p><p>20. . . Transistor</p><p>30. . . resistance</p><p>40. . . Input electrolytic capacitor</p><p>41. . . Diode</p><p>45. . . capacitance</p><p>50. . . Switch controller</p><p>51. . . resistance</p><p>52. . . resistance</p><p>60. . . Rectifier</p><p>65. . . Output capacitor</p><p>70~79. . . Light-emitting diode</p><p>81. . . inverter</p><p>82. . . inverter</p><p>83. . . Delay circuit</p><p>85. . . And gate</p><p>90. . . inverter</p><p>91. . . Comparators</p><p>92. . . Comparators</p><p>95. . . And gate</p><p>97. . . Flip-flop</p><p>98. . . And gate</p><p>100. . . Switch controller</p><p>110. . . Input voltage detection circuit</p><p>120. . . Comparators</p><p>150. . . Voltage detection circuit</p><p>160. . . First error amplifier</p><p>161. . . switch</p><p>162. . . switch</p><p>163. . . inverter</p><p>165. . . Operational Amplifier</p><p>170. . . Second error amplifier</p><p>200. . . Current detection circuit</p><p>250. . . Integrator</p><p>300. . . Signal generating circuit</p><p>340. . . capacitance</p><p>350. . . Battery</p><p>351. . . switch</p><p>354. . . switch</p><p>355. . . Battery</p><p>358. . . switch</p><p>359. . . Battery</p><p>361. . . Comparators</p><p>362. . . Comparators</p><p>363. . . Comparators</p><p>365. . . Reverse gate</p><p>366. . . Reverse gate</p><p>367. . . And gate</p><p>370. . . And gate</p><p>371. . . Or gate</p><p>375. . . inverter</p><p>376. . . inverter</p><p>400. . . First low pass filter</p><p>410. . . And gate</p><p>411. . . And gate</p><p>420. . . switch</p><p>425. . . capacitance</p><p>430. . . switch</p><p>435. . . capacitance</p><p>450. . . Second low pass filter</p><p>500. . . Pulse width modulation circuit</p><p>BLK. . . Obscured signal</p><p>CK₁. . . Clock signal</p><p>CK₂. . . Clock signal</p><p>COMI. . . Current loop signal</p><p>COMV. . . Voltage loop signal</p><p>E_I. . . Second amplified signal</p><p>E_IN. . . Input voltage signal</p><p>E_V. . . First amplified signal</p><p>E_X. . . Amplify the signal</p><p>I_DC. . . Input Current</p><p>I_O. . . Output current</p><p>I_P. . . Switching current</p><p>N_A. . . Auxiliary winding</p><p>N_P. . . Primary winding</p><p>N_S. . . Secondary winding</p><p>PLS. . . Pulse signal</p><p>RMP. . . Slope signal</p><p>S_D. . . Discharge signal</p><p>S_DM. . . Discharge signal</p><p>S_DS. . . Degaussing time signal</p><p>S_ENB. . . Enabling signal</p><p>S_FD. . . Fast discharge signal</p><p>SW. . . Switch signal</p><p>V_AC. . . Input line voltage</p><p>V_CC. . . Power supply</p><p>V_CS. . . Current detection signal</p><p>V_DC. . . Voltage</p><p>V_H. . . Critical value</p><p>V_I. . . Current feedback signal</p><p>V_IN. . . Input voltage</p><p>V_C. . . Critical value</p><p>V_M. . . Critical value</p><p>V_O. . . The output voltage</p><p>V_RI. . . Second reference signal</p><p>V_RV. . . First reference signal</p><p>V_RX. . . Reference signal</p><p>V_S. . . Voltage detection signal</p><p>V_T. . . Critical value</p><p>V_V. . . Voltage feedback signal</p><p>V_X. . . Feedback signal</p>

FIG. 1 is a schematic circuit diagram of a conventional offline light emitting diode (LED) driver with an input electrolytic capacitor.

Figure 2 shows the input line voltage V in the conventional off-line LED driver_AC, Voltage V_DCAnd input current I_DCSchematic diagram of the waveform.

FIG. 3 is a schematic circuit diagram of an embodiment of the light-emitting diode driver of the present invention.

Fig. 4 is a schematic circuit diagram of an embodiment of a switching controller in the present invention.

Figure 5 shows that the blanking signal BLK corresponds to the input voltage V in the present invention_INAnd input voltage signal E_INSchematic diagram of the waveform.

Fig. 6 is a circuit diagram of an embodiment of an error amplifier in the switching controller of the present invention.

Fig. 7 is a circuit diagram of an embodiment of a low-pass filter in the switching controller of the present invention.

FIG. 8 is a circuit diagram of an embodiment of a PWM circuit in the switching controller of the present invention.

FIG. 9 is a circuit diagram of an embodiment of a signal generating circuit in the PWM circuit of the present invention.

Figure 10 shows the ramp signal RMP and enable signal S in the PWM circuit of the present invention_ENB, The waveform diagram of the pulse signal PLS and the switching signal SW.