Method of programming data in a flash memory device

Method for programming data in flash memory element

This application claims the priority of Korean Patent Application No. 2007-7046 filed on January 23, 2007, and is hereby incorporated by reference in its entirety.

The present invention relates to a flash memory device with multi-layer cells. More particularly, the present invention relates to a method for performing a read operation on a set voltage level that is independent of the LSB or MSB programming operation of a specific cell.

Generally speaking, flash memory systems are classified as NAND or NOR flash memory. Here, because the memory cell is independently connected to the bit line and the word line, the NOR flash memory has good random access time characteristics. However, in the NAND flash memory, because the memory cells are connected in series and therefore the NAND flash memory has good characteristics in terms of the degree of integration, only one contact point is required for a cell string. Therefore, NAND flash memory is generally used for highly integrated flash memory.

In recent years, in order to increase the degree of integration of flash memory, multi-bit cells for storing complex data in one memory cell have been actively developed.

This memory cell system is called multi-layer cell (MLC). A memory cell used to store one bit is called a single-layer cell (SLC).

Generally, the MLC can be programmed with multiple levels.

Figure 1 is a diagram illustrating the threshold voltage distribution based on MLC flash memory programming.

Figure 1 shows the voltage distribution of the MLC for storing at least two bits programmed by various level methods.

As shown in Figure 1, when the least significant bit (LSB) is programmed, the erase cell 110 and the program cell 120 have a voltage distribution based on the voltage V1. An additional flag cell F is included in each character line of the flash memory to indicate whether only the LSB is programmed (for example, the first state 170) or whether both the LSB and MSB have been programmed ( For example, the second state 180).

When the programming of the most significant bit (MSB) is completed, the erase cell 110 is converted into erase cells 130 and 140, and the programming cell 120 is converted into programming cells 150 to 160. In addition, the flag cell F (ie, the second state 180) is programmed based on the voltage V5, and thus the flag cell F is used to indicate both the most significant bit and the least significant bit that have been programmed.

Figure 2A illustrates the representation of memory blocks in MLC flash memory.

Referring to FIG. 2A, the memory cell array 200 in the MLC flash memory includes a memory cell 210 and a flag cell 220. Each memory cell 212 of the memory cell array is structured to store two or more bits of data. In FIG. 2A, for the convenience of description, each memory cell 212 is marked as being capable of storing two-bit data. The flag cell 220 is used to indicate the memory cells connected to the same character line, that is, the programming status of the memory cells in the same page. Each character line is coupled to a plurality of memory cells and flag cells.

The flag cell 220 indicates whether the high programming operation has been processed for the corresponding page. If the flag cell 220 is in the second state 180 (refer to FIG. 1), a high programming operation has been performed, in which the least significant bit page and the most significant bit page have been programmed. For example, when the memory cell 212 is structured to store 2-bit data, each of the word lines WL<0> to WL<N> can perform the operation of programming the least significant bit page and programming the most significant bit Another operation of the meta page. If the word line WL<0> has programmed the least significant bit page and the most significant bit page, the flag cell F is programmed to the second state 180 to indicate that the high programming operation has been performed.

However, in the case where the (k-1)th word line WL<k> only programs the least significant bit page, the flag cell F related to the (k-1)th word line WL<k> <k> Keep the state where the erased cell 170 is not programmed to indicate that only the least significant bit page is programmed.

Figure 2B is a diagram of the programming sequence of the memory blocks in Figure 2A, where the programming is completed in page units. The memory block is connected to the word lines WL<0> to WL<N>. Each character line is connected to a plurality of memory cells and flag cells that together define a physical page.

The multi-layer cell 212 is structured to store N bits of data. Each multi-layer cell 212 can be programmed into N different states by corresponding character lines. Therefore, each physical page provides N logical pages.

According to the sequence set in response to the input data, the MLC flash memory executes programming in logical page units. Here, the MLC flash memory is programmed in the order of the first logical page to the Nth logical page in each of the word lines WL<0> to WL<N>, or according to borrowing By referring to the sequence set by the interference between the surrounding memory cells, programming and so on are performed in the logical page unit.

The generally used method involves controlling the programming so that when the programming is performed in logical page units, adjacent pages are not continuously programmed.

In addition, the address counter (not shown) counts the addresses according to the preset page sequence to execute the programming of the entered data.

In addition, during the programming operation, the flag cell F is programmed according to the programming state of the first to Nth logical pages. Therefore, in the programming state of the character line, the flag cell F displays information.

For example, if the first to Nth logical pages related to the first word line WL<0> in Figure 2B are all programmed, the programming flag cell F<0> is in the second state 180. Here, the commonly used flag cell F is SLC.

As explained above, if the memory cell stores N bits of data, the corresponding character line has N logical pages. Therefore, the programming operation has been programmed N times.

For example, if the memory cell stores four bits of data, the corresponding character line can have four logical pages. Therefore, the programming operation will need to be performed four times to complete programming all four logical pages associated with the word line. In this case, the flag F should have two SLCs to indicate four programming states.

In the read operation for the above-mentioned flash memory cell, the data of the flag cell F is first read to obtain programming status information. Use the programming state information of the flag cell to select the appropriate threshold voltage. The selected threshold voltage is then used to read the data stored in the memory cell.

In order to implement the above method, the number of SLCs contained in the flag cell F should be increased according to the number of bits, and the structure is configured to store memory cells. This reduces the number of memory cells that can be used to store data.

Therefore, since the voltage level used to read the data stored in the memory cell is determined after the programming state is confirmed by reading the flag cell F, if the data in the flag cell F has an error At this time, it will be difficult to read the data stored in the memory cell. In addition, the time required for the read operation will increase as the number of flag cells F increases.

The present invention relates to an MLC non-volatile memory element, which can be operated without a flag cell, wherein the flag cell indicates the programming state of the memory cell. The non-volatile memory device can be a NAND or NOR flash memory device.

In one embodiment, the flash memory device includes a memory cell array, and the structure has at least one block including a plurality of physical pages, and each physical page defines a plurality of logical pages. The structure of the controller is to start the data-simulating programming operation before allowing the read command to be executed to program any logical page of the block that has not been programmed. The controller has a storage part for storing dummy data used in the dummy data programming operation. The controller is structured to randomly generate imitation data used in the imitation data programming operation, and the block does not contain any flag cells. The memory cell array has at least one redundant page for storing dummy data during the dummy data programming operation.

An embodiment of a method for performing a read operation in a flash memory device, wherein the flash memory device has a memory cell array including at least one block, and the block has a plurality of pages. The method includes: receiving a read command to read data from a selected page in the block; determining whether the block has any pages that have not been programmed; executing simulation on at least one page that is determined to be unprogrammed Data programming operation; and execute the read command to read the data of the selected page after completing the imitated data programming operation.

In one embodiment, the imitation data programming operation programs imitation data for all pages that are determined not to be programmed. The block includes a plurality of physical pages, and each physical page defines a plurality of logical pages. The determining step includes determining whether all the logical pages in the block have been programmed. This imitating data programming operation programs imitated data on redundant pages.

Regarding another embodiment of a method for programming data in a flash memory device, the flash memory device has a memory cell array including at least one block, the block including a plurality of pages. The method includes: receiving a programming command to program a plurality of pages in the block; programming the plurality of pages in a predetermined order; and storing an address corresponding to the last programmed page in the plurality of pages. The plural pages are programmed in increasing order.

Regarding yet another embodiment of a method for performing a read operation in a flash memory device, the flash memory device has a memory cell array including at least one block, the block having a plurality of pages. The method includes: receiving a read command to read the selected page in the block; determining whether all pages in the block have been programmed; executing simulation on any page in the block that is determined to have not been programmed Data programming operation; and after executing the imitation data programming operation, execute the read command to read the selected page. The imitation data programming operation programs imitation data on the pages that are determined to be unprogrammed. Or, the imitation data programming operation programs imitation data on redundant pages in the block.

In yet another embodiment, the flash memory device includes a memory cell array, a controller, a page buffer, an X decoder, and a Y decoder. The memory cell array has at least one block containing a plurality of pages. The controller determines whether each page of the block is programmed according to a read command, executes imitation data programming without programming according to the discrimination result, and outputs a control signal for executing a read operation according to the read command. The page buffers program or read the data of the memory cell array under the control of the controller. The X decoder decodes the address of the page in response to the programming command or the read command of the controller, and outputs the programming voltage or the read voltage by activating the page selected according to the decoding result. The Y decoder decodes the row address in response to a programming command or a read command of the controller, and outputs a page buffer control signal and a data input/output control signal according to the decoding result.

As described above, in the flash memory device and the method for operating the flash memory device of the present invention, the flag cell is not used to perform a read operation to display the programming status. Therefore, the size of the chip related to the flash memory device can be reduced.

FIG. 3A is a flowchart illustrating a programming operation of a non-volatile memory device (for example, a flash memory device) according to an embodiment of the present invention. Figure 3B illustrates a memory block and controller according to one embodiment.

Referring to FIG. 3B, the flash memory device of this embodiment includes a memory cell array (not shown) having at least one block 320, and a controller 310, which controls the surrounding circuit 370 so that the area corresponds to the area by sending a response Block 320 presets the input data of the page address of the word line to perform the programming operation. The structure of the memory cell array (or block 320) is described in detail in US Patent No. 7,193,911, which is incorporated herein by reference. The memory cell array described in the 7,193,911 patent is related to NAND flash memory devices. However, the memory cell array (or memory block) in this embodiment is not limited to the NAND architecture and may include other architectures, for example, the NOR architecture.

The memory block 320 is connected to the complex number element lines WL<0> to WL<N>. Each character line is connected to a plurality of memory cells 312, which together define a physical page. The memory cell 312 is a multi-layer cell structured to store N bits of data. Each multi-layer cell 312 can be programmed to N different states by corresponding word lines. Therefore, each physical page can be defined up to N logical pages according to the number of times the physical page is programmed. The data in the memory cell 312 (or block 320) is read according to the received read command.

The controller 310 controls the programming operation according to the data transmitted from the peripheral circuit 370 and the sequence set by the programming command. In one embodiment, the controller 310 stores the address of the page that has been last programmed. The saved address can include information on both physical and logical pages. The programming operation usually starts from the first word line WL<0>. The programming operation is performed in the logic page unit, so that the selected logic page is programmed each time. The controller 310 can be configured to program logical pages in a predetermined order.

For example, the programming operation can sequentially program the logical page from the first logical page to the Nth logical page of a given word line (for example, WL<0>). Once the logical pages of all word lines have been programmed, the logical pages of the next word lines are programmed in sequence (for example, from the first page to the Nth page of the next word line WL<1>). Alternatively, the programming operation may be performed in a predetermined order without continuous progress.

Generally, the programming sequence is set in advance by using an algorithm that maximizes the efficiency of data storage. In this method, adjacent logical pages are not continuously programmed to reduce interference between the adjacent logical pages.

For example, program the first page of each word line of word lines WL<0> to WL<N> in sequence, and then program the first page of each word line of word lines WL<0> to WL<N> The second page. In other words, different physical pages are programmed each time, so that adjacent logical pages are not programmed sequentially.

The controller 310 controls how to perform programming operations with the assistance of the peripheral circuits 370 (such as page buffers, X decoders, Y decoders, and voltage supply circuits). In one embodiment, the controller 310 stores the address of the last page programmed in a given programming operation. In one embodiment, only physical page (ie, word line) addresses are stored. In another embodiment, both the physical and logical page addresses are stored. The controller 310 uses the stored page address to determine which page to program in the subsequent programming operation.

In this embodiment, the controller 310 is structured to process the read command as shown in FIG. 3A. If the peripheral circuit 370 receives a read command (step S301), the controller 310 accesses the page address stored in the controller to determine which is the next page to be programmed in the next programming operation (step S301). S303). Therefore, the stored page address can indicate the last programmed page or the next page to be programmed according to the implementation. In addition, the stored page can be represented as a physical page, a logical page, or both according to the implementation.

In step S305, it is determined whether all logical pages in the block have been programmed. One of the determination methods is to use the page address stored in the controller. For example, if the page address indicates that the last logical page of the last physical page in the block is the page that has been last programmed, it is determined that all logical pages in the block have been programmed.

In step S309, if it is determined that all pages in the block have been programmed, the controller 310 controls the peripheral circuit 370 to execute the read command. Here, since each page of the block 320 is programmed, the memory cell used to store N bits of data has 2^NTherefore, the controller 310 controls the reading operation so that the reading operation is performed by using the reading voltage consistent with the set voltage level.

In step S307, if it is determined that all pages in the block are not programmed, the controller 310 executes dummy data programming to "dummy program" the logical pages that have not been programmed. That is, the imitation data programming operation programs data on the remaining pages of the block 320 that has not been programmed. The simulated data programming operation sequentially programs the simulated data from the address corresponding to the address stored in the controller 310 to the last page of the block 320. When the imitation data programming is performed, all the word lines WL<0> to WL<N> are programmed, and therefore the word lines WL<0> to WL<N> are converted to the final voltage level, that is, the conversion It can be read.

This imitating programming operation transfers the threshold voltage of a memory cell that has not been programmed in advance. Therefore, the controller can select an appropriate set voltage level to perform the read operation without using the programming status information of the flag cell.

Hereinafter, the above operation will be described in detail with reference to FIG. 3B. When the controller 310 receives a programming command, it starts a programming operation. The programming operation is executed according to the programming command until the Kth logical page of the (N+1)th word line. Since the first word line is WL<0>, the (N+1)th word line is the last word line WL<N>. The programming operation ends after the Kth logical page has been programmed.

The controller 310 stores the information of the next logical page to be programmed in the subsequent programming operation of the (k+1)th logical page of WL<N>. This can be accomplished by storing the address of the (k+1)th page or the kth page according to the implementation. If the address of the k-th page is stored, the controller may need to be additionally structured so that it can be understood that the stored address indicates the last programmed page instead of the next page to be programmed.

In this example, the programming has been executed to the Kth logical page 330 of WL<N>. That is, all logical pages in the block 320 except for a group of logical pages 340 (from (K+1)th to Nth) have been programmed. If the read command used to read the data in the Kth logical page 350 of the first word line WL<0> is received by the peripheral circuit 370 in step S301, the controller 310 will finally program After the operation, access the stored data to determine the last programmed page. According to the implementation, the stored address can be the next page to be programmed. The controller can use the stored addresses to determine whether all logical pages in the block have been programmed.

In this case, the controller 310 determines the group of logical pages 340 that have not been programmed (ie, the (K+1)th to Nth logical pages of WL<N>). The controller 310 controls the peripheral circuit 370 to program the dummy data for redundant pages, so that the (K+1)th to Nth logical pages of WL<N> are executed according to the dummy data operation. Here, the imitation data is stored in the storage unit 360 included in the controller 310 in advance. In another embodiment, each data in the imitation data can be "1" or "0", that is, the imitation data is data with no specific meaning.

After the imitating data operation has completed the "imitation programming" of the Nth logical page of WL<N>, the controller 310 allows data from the Kth logical page of WL<0> to be read. Here, since all these pages have been programmed, the read operation corresponds to 2^NThe read voltage of the voltage level.

Any reference in this specification to "one embodiment", "embodiment", "exemplary embodiment", etc. means specific technical features, structures, and features related to the embodiments included in at least one embodiment of the present invention. Or description of characteristics. The presentation of these terms in various places in this specification does not necessarily all refer to the same embodiment. In addition, when describing specific technical features, structures, or characteristics related to any embodiment, it can be considered that it is within the scope of those skilled in the art to complete this related to other embodiments of these embodiments. Technical characteristics, structure, or characteristics.

Although it has been described with reference to many of its schematic embodiments, it should be understood that various other modifications and embodiments designed by those with ordinary knowledge in the technical field will still fall within the spirit of the principles of this disclosure. With scope. More particularly, various changes and modifications can be the configuration of the component parts and/or the main body combination configuration within the scope of the disclosure, the drawings, and the scope of the attached patent application. In addition, various changes and modifications of the component parts and/or configurations will also be obvious to those with ordinary knowledge in the technical field.

<p>110, 130, 140. . . Erase cells</p><p>120, 150, 160. . . Programming cell</p><p>170. . . First state</p><p>180. . . Second state</p><p>200. . . Memory cell array</p><p>210, 312. . . Complex memory cell</p><p>212. . . Memory cell</p><p>220. . . Flag cell</p><p>310. . . Controller</p><p>320. . . Memory block</p><p>330, 350. . . Kth logical page</p><p>340. . . Group of logical pages</p><p>360. . . Storage Department</p><p>370. . . Surrounding circuit</p><p>S301, S303, S305, S307, S309. . . step</p>

Figure 1 illustrates the threshold voltage distribution based on MLC flash memory programming;

Figure 2A illustrates the representation of memory blocks in MLC flash memory;

Figure 2B illustrates the programming sequence of the blocks in Figure 2A according to the page;

FIG. 3A is a flowchart of a programming operation of a flash memory device according to an embodiment of the present invention;

FIG. 3B illustrates the memory block and the controller according to an embodiment of the present invention.