Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same

Decoder circuit for providing forward and reverse mode of memory array operation and bias method thereof

The present invention relates to a programmable memory array, and in particular to a semiconductor integrated circuit memory array having passive component memory cells, and even more specifically, with such memory cells A three-dimensional memory array.

Some passive component memory cells exhibit rewritable characteristics. For example, in some memory cells, unit programming can be achieved by applying a forward bias to the memory cells with a voltage of approximately 6 V to 8 V (eg, based on the polarity of the diodes therein). The erase can be achieved by applying a reverse bias to the memory cells with a voltage of approximately 10 V to 14 V. These high voltages require the use of special high voltage CMOS transistors in word line and bit line decoders. These high voltage transistors are not scaled appropriately as the memory cell word lines and bit line spacing are reduced. This situation is particularly problematic for 3D memory technology. In 3D memory technology, the pure density of word lines and bit lines that lead to the array and must be interfaced with word lines and bit line drivers makes the supply more and more The ability of small array line spacing compatible decoder circuits (and in particular word lines and bit line driver circuits) to be able to apply a sufficiently high voltage across selected memory cells is even more important.

In one aspect, the present invention provides an integrated circuit including: a memory array of memory cells, each memory cell coupled to an associated array line of one of the first types and a Between the associated array lines of one of the second types; a first array line selection circuit comprising a first decoder circuit configured to generate a first plurality of decoded output nodes, the first plurality of The decoded output nodes are each coupled to a respective plurality of first type array line driver circuits, and each of the plurality of first type array line driver circuits includes respective ones each coupled to one of the first type of respective array lines a plurality of first array line driver circuits; and a second array line selection circuit including a second decoder circuit configured to generate a second plurality of decoded output nodes, a second plurality of decoded outputs The nodes are each coupled to a respective multi-head second type array line driver circuit, and each multi-head second type array line driver circuit includes a respective complex coupled to each of the second type of respective array lines A second array line driver circuits. The first decoder circuit maintains the same polarity and operating voltage in both the first mode of operation and a second mode of operation; the second decoder circuit maintains both the first mode of operation and the second mode of operation The same polarity; compared to the first mode of operation, the plurality of first type array line driver circuits have a reverse polarity in the second mode of operation; compared to in the first mode of operation, The multi-head second type array line driver circuit has a reverse polarity in the second mode of operation; and the first array line selection circuit and the second array are compared to the bias voltage applied in the second mode of operation The line selection circuit applies a bias voltage of one of the opposite polarities across a selected memory cell in the first mode of operation.

In one aspect, the present invention provides a method for decoding a memory array, the method comprising: providing a first decoder circuit with an operating voltage of a first magnitude until all of its decoded outputs are stable And a first voltage difference is established between a selected decoded output and an unselected decoded output, each decoded output being coupled to each of the plurality of array line driver circuits; and at a source Providing a first non-active voltage level on each bus line of the selection bus, the source selection bus is coupled to each of the plurality of array line driver circuits, and a plurality of array line drivers are given Each individual array line driver circuit in the circuit is responsive to a decoded output of the first decoder circuit coupled to the given plurality of array line driver circuits to one of the source select busses The respective bus bars are coupled to a respective one of the first types of array lines; then the operating voltage of the first decoder circuit is increased to be greater than a second amount of the first amount, thereby The differential voltage between the output decoded output and the unselected decoded output is increased to a second differential voltage greater than the first differential voltage; then one of the source selection bus bars is first busbar The line generates a pulse to a first applied voltage level, and then returns to the first inactive voltage level to thereby cause one of the first types corresponding to the selected decoded output of the first decoder circuit The first array line generates a pulse; then the operating voltage of the first decoder is reduced to the first magnitude before allowing any decoded output of the first decoder to change state.

In several aspects, the present invention is suitable for an integrated circuit having a memory array suitable for use in operating such integrated circuits and memory arrays, and is suitable for fabricating memory products having such arrays. Methods, all as described in more detail herein and as set forth in the appended claims. The described techniques, structures, and methods can be used alone or in combination with each other.

The foregoing is a summary of the invention, and thus is in the Therefore, it is to be understood that the invention is intended to be illustrative, and is not intended to limit the invention in any way. Other aspects, inventive features, and advantages of the invention will be apparent from the embodiments described herein.

The invention will be better understood, and the subject matter, features and advantages of the invention will be apparent to those skilled in the art.

The use of the same reference symbols in different figures indicates similar or identical items.

FIG. 1 is a schematic diagram of an exemplary passive component memory array 100. Two word lines 102, 104 and two bit lines 106, 108 are shown. Assume that word line 102 is the selected word line (SWL) and that word line 104 is assumed to be an unselected word line (UWL). Similarly, the fake positioning element line 106 is a selected positioning element line (SBL), and the false positioning element line 108 is an unselected positioning element line (UBL). Four passive component memory cells 101, 103, 105, 107 are shown, each coupled between an associated word line and an associated bit line.

The memory unit 101 is associated with the selected word line 102 and the selected location line 106 and can be considered an "S" unit (i.e., a "selected" unit). The memory unit 103 is associated with the unselected word line 104 and the selected location line 106 and can be considered an "F" unit (ie, a "off" unit). Memory unit 105 is associated with selected word line 102 and unselected location line 108 and can be considered an "H" unit (i.e., a "semi-selected" unit). Finally, memory unit 107 is associated with unselected word line 104 and unselected location line 108 and can be considered a "U" unit (ie, an "unselected" unit).

Exemplary bias conditions for the forward bias mode of operation are also illustrated in FIG. The forward bias mode can be used in stylized mode, erase mode, block erase mode, and/or read mode (but typically has different voltage levels or conditions for these different modes). As shown, the bias conditions can be considered as a stylized mode of operation for the selected array block and will be described as such.

The selected word line 102 is biased at a VSX voltage (eg, ground), and the selected bit line 106 is biased at a VSB voltage (eg, +11 volts) at a VUX voltage (eg, +10.3 volts) The unselected word line 104 is biased and the unselected locating element line 108 is biased at a VUB voltage (eg, +0.7 volts). The selected positioning element line bias voltage VSB can be considered as a stylized voltage VPP because the entire voltage is substantially applied across the selected memory unit 101 (because the selected word line is biased at ground), so Some resistor drops are added to the bus and the array line itself. The unselected locating element line bias voltage VUB is also preferably set to a value corresponding to the apparent "threshold voltage" in the forward biasing direction of each memory cell, and thus is shown as being added The voltage VT on the locating element line 108 is not selected. Similarly, the unselected word line bias voltage VUX is also preferably set to a value of VPP-VT.

Under such bias conditions, S unit 101 receives a forward bias voltage equal to VPP (eg, +11 volts), F unit 103 receives a forward bias voltage equal to VT (eg, +0.7 volts), and H unit 105 receives Equal to VT (eg, +0.7 volts) forward bias voltage, and U unit 107 receives a reverse bias voltage equal to VPP-2VT (eg, -9.6 volts). There are several exemplary memory cell techniques: when biased under these conditions, the selected cell will change to a lower resistance value, while the F, H, and U cells will not significantly change the resistance. Exemplary unit techniques are described below.

Referring now to Figure 2, an exemplary bias condition 200 is shown for a reverse bias mode of operation. This reverse bias mode can be used in stylized mode, erase mode, and/or block erase mode (but usually with different conditions for these different modes), one or more of which can be characterized as The second "write" mode of operation. As shown, the bias conditions can be considered as a stylized mode of operation or an erase mode of operation for the selected array block and will be described as such.

Each of the bias conditions VSX, VUX, VSB, and VUB is now redefined for values appropriate for this mode of operation. The selected word line 102 is biased at a VSX voltage of VWL (e.g., +6 volts) and the selected bit line 106 is biased at a VSB voltage of -VBL (e.g., -6 volts). Both the unselected word line voltage VUX and the unselected positioning element line voltage VUB are grounded.

Under such bias conditions, S unit 101 receives a reverse bias voltage (sometimes referred to as VRR) equal to VWL-(-VBL) (eg, -12 volts), and F unit 103 receives a voltage equal to VBL. A reverse bias voltage (eg, -6 volts), and H cell 105 receives a reverse bias voltage (eg, -6 volts) equal to VWL. It is worth noting that U unit 107 does not receive any bias across the unit.

There are several exemplary memory cell techniques (described below): when biased under these conditions, the selected cell changes from a lower value of the self-resistance to a higher value of the resistance, while the F, H, and U cells Will not significantly change the resistance. Also concerned is the memory cell technology that, when biased under these reverse mode conditions, the selected cell will change from high resistance to lower resistance. For example, the particular material of interest is a metal oxide memory device in which some asymmetry in the metal oxide metal layered structure, such as electrode selection, is used to set a preferred field direction for the reset. These materials can be used for reverse bias setting as described more fully below. It should also be noted that the U memory cell is not selected (which would otherwise support a significant amount of leakage current when biased by a few volts across the cell) without bias and therefore no leakage current. As will be described in further detail, many useful memory array embodiments include U cells that are much larger than the number of H cells of the F cell, and such arrays will be in the array as compared to other biasing schemes. There is significantly less leakage current in the unselected memory cells and therefore much less power dissipation.

By "split" the VRR voltage in this reverse mode and bias the SBL at a negative voltage equal to one-half of the programmed voltage (ie, -VBL), and at a positive voltage equal to one-half of the programmed voltage (ie, VWL) biases the SWL, significantly relaxing the voltage requirements of both the bit line decoder and the word line decoder. Thus, consistent with the small spacing of the array lines (eg, word lines and bit lines), the high voltage transistors in the array line driver circuit occupy a small area because they can be designed for relatively low " Split "voltage.

Other memory technologies have faced the problem of stylizing and erasing voltages (and the area required for such high voltage transistors) that are not scaled at the same rate with memory cell spacing. For example, the impact of this problem in FLASH memory is slightly reduced due to the large fanout of a typical FLASH based memory array. In some of the newer technologies, more space consumption design rules for high voltage transistors can be amortized by increasing the memory block size. However, in a passive body memory array based on a diode, the larger block size is at the expense of increased leakage through unselected memory cells within the selected array. By biasing such unselected memory cells as depicted in Figure 2, this leakage component can be reduced to almost zero and a larger block size is achieved with less harmful power dissipation. However, in some embodiments, the reverse bias mode of operation may utilize a completely non-negative voltage (ie, only positive voltage and ground) or only a completely non-positive voltage (ie, only negative voltage and ground), or a positive voltage Other combinations with negative voltages.

Referring now to Figure 3, an exemplary word line decoder circuit 150 is shown including exemplary bias conditions (as depicted in Figure 1) suitable for a forward bias mode of operation. Column decoder circuit 152 is shown on the left side of the figure, which shows two decoded outputs 158, 162, which may also be referred to as column select (ie, ROWSEL) outputs. The decoded output 158 corresponds to the selected decoded output, and the decoded output 162 corresponds to the unselected decoded output. Column decoder 152 can be implemented using any of a variety of well known techniques. For example, the decoder can respond to pre-decoded address signals generated by previous column decoding circuits (not shown) or can respond to the address signals themselves. For the purposes of this description, column decoder 152 can be considered to include one or more circuit blocks that cooperate to decode column address information and produce decoded column select signals. The decoder circuit 152 can include a "NAND" gate that responds to the pre-decoded address signal, followed by a large capacitive load on each of the column selection nodes to drive this A column selects the inverting buffer of the node. In this mode of operation, the voltage VHI is supplied over VPP equal to the power supply node 153 (also referred to herein as the "VDD node" or "VHI node" of the column decoder 152), and coupled to The column decoder 152 is operated by supplying a voltage VLO below the ground of the power supply node 154 (also referred to herein as the "VSS node" or "VLO node" of the column decoder 152). This column decoder 152 is a "high state active" decoder, meaning that the selected output (or outputs), such as column select node 158, is driven to the higher of the two available voltage states (which in this case is VPP) ). The unselected column select output, such as the decoded output node 162, is driven to the lower of the two available voltage states (which is grounded in this case). The following description will initially assume that only one such decoded output node (e.g., "high") is selected at a time.

Each decoded output is coupled to one or more word line driver circuits. For example, the decoded output node 158 is coupled to a word line driver circuit 170 that includes a PMOS transistor 171 and an NMOS transistor 172. The respective delta terminals of transistors 171, 172 are coupled to the word line representing the selected word line 102 in this condition. Although some embodiments may envision a decoder other than a multi-head decoder, FIG. 3 depicts a second word line driver circuit that is also coupled to the decoded output node 158, the second word line driver circuit representing this particular The decoded output node 158 is associated with one or more remaining word line driver circuits. The second word line driver circuit includes a PMOS transistor 173 and an NMOS transistor 174 whose output drives word lines 181 that collectively represent one or more semi-selected word lines. These semi-selected word lines may reside in the same array block as the selected word line, and/or may even reside in other array blocks that are not selected.

The respective source terminals of the NMOS transistors in each of the word line driver circuits are coupled to respective bus lines of the WL source select bus XSEL. In this mode of operation, the source select bus is decoded based on the address information such that one of the XSEL bus bars is biased in an active state for the mode of operation for the mode of operation, and is suitable for this mode of operation. The remaining XSEL bus lines are biased in the inactive state of the word line. In some embodiments, more than one of the source selection bus bars may be functional, but we should now assume that bus bar 167 is active and biased at ground and is commonly converged by XSEL One or more of the remaining XSEL bus bars represented by line 168 are inactive and are driven to an unselected word line voltage VUX (shown as VPP-VT).

Since the voltage on the decoded output node 158 (VPP) is higher than the voltage of the bus bars 167, 168, both of the NMOS transistors 172, 174 are turned "on", thereby driving the selected word line 102 to ground, and The half selected word line 181 is driven to the VPP-VT. These two conduction paths are indicated by the open arrow line.

The respective source terminals of the PMOS transistors in each of the word line driver circuits are coupled to an unselected WL bias line UXL, and the unselected WL bias line UXL is also labeled as node 164. In this mode of operation, UXL bias line 164 carries the unselected word line voltage VUX. Since the voltage (VPP) on the decoded output node 158 is higher than the voltage of the UXL bias line (VPP-VT), both PMOS transistors 171, 173 are turned off.

Turning now to the bottom of the figure, the decoded output node 162 is coupled to a word line driver circuit that includes a PMOS transistor 175 and an NMOS transistor 176. The respective delta terminals of the transistors 175, 176 are coupled to the word line representing the selected word line 104 in this condition. A second word line driver circuit, also coupled to the decoded output node 162, represents one or more remaining word line driver circuits associated with the decoded output node 162 and includes a PMOS transistor 177 and an NMOS transistor 178. The output drives the unselected word line 183.

As previously described, the respective source terminals of the NMOS transistors in each of the word line driver circuits are coupled to respective bus lines of the WL source select bus XSEL. Since the voltage on the decoded output node 162 (ground) is not selected to be at or below the voltage of the XSEL bus bars 167, 168, both of the NMOS transistors 176, 178 are turned off. The respective source terminals of the PMOS transistors in each of the word line driver circuits are coupled to an unselected WL bias line UXL node 164. Since the voltage on the decoded output node 162 (ground) is not lower than the voltage of the UXL bias line 164 (below the voltage of the UXL bias line 164 is above the PMOS threshold voltage), the PMOS transistors 175, 177 are The person is turned "on" to drive the unselected word lines 104, 183 to the VUX (e.g., VPP-VT). These two conduction paths are indicated by the open arrow line.

Referring now to Figure 4, an exemplary bit line decoder circuit 200 is shown including exemplary bias conditions (as depicted in Figure 1) suitable for a forward bias mode of operation. Row decoder circuit 202 is shown on the left side of the figure, which shows two decoded outputs 208, 212. The decoded output 208 corresponds to the selected decoded output, and the decoded output 212 corresponds to the unselected decoded output. Row decoder 202 may be implemented using any of a variety of well known techniques, and row decoder 202 generates a plurality of decoded outputs, such as (for this particular embodiment) nodes that are identical to row select nodes 208, 212 Outputs 205, 209. In the exemplary embodiment shown and different from the exemplary column decoder 152, there is no inverting buffer to drive the decoded output node after the NAND gate, due to the capacitive loading on node 208 ( That is, the COLSELi output) is much lower than the capacitive load of the column decoder (ie, ROWSELi) output. The row decoder 202 is operated in this mode of operation by equalizing the VPP supply voltage VHI coupled to the power supply node 203 and the ground supply voltage VLO coupled to the power supply node 204. Row decoder 202 is a "low state active" decoder. The unselected decoded output, such as decoded output node 212, is driven to the higher of the two available voltage states (which in this case is VPP). The following description will initially assume that only one such decoded output node 208 (e.g., "low") is selected at a time.

Each of the decoded outputs (ie, COLSELi outputs) is coupled to one or more bit line driver circuits. For example, the decoded output node 208 is coupled to the bit line driver circuit 220, and the bit line driver circuit 220 includes a PMOS transistor 221 and an NMOS transistor 222. The respective turns of the transistors 221, 222 are coupled to the bit lines representing the selected bit line 106 in this case. Although some embodiments may envision a decoder other than a multi-head decoder, FIG. 4 depicts a second bit line driver circuit coupled to the decoded output node 208, the second bit line driver circuit representation The particular row selects one or more remaining bit line driver circuits associated with node 208. The second bit line driver circuit includes a PMOS transistor 223 and an NMOS transistor 224, the output of which drives a bit line 231 representing one or more half-selected bit lines. In contrast to the word line decoder, the semi-selected positioning element line may represent a selected positioning element line that is being maintained in an inactive state, such as, depending on the data to be programmed, a bit line that does not require a programmed bias, or While one of the bit lines of the selected group of bit lines is being programmed, another bit line of the selected group that is waiting to be programmed is further described below.

The respective source terminals of the PMOS transistors in each of the bit line driver circuits are coupled to respective bus lines of the BL source select busses SELB. In this mode of operation, the source select bus SELB is data dependent and can be further decoded based on the address information such that one or more of the SELBs are active for the mode of operation for the bit line. The bus bar is biased and the remaining SELB bus bars are biased in an inactive state suitable for the bit line for this mode of operation. In some embodiments, more than one source selection bus bar may be active, but we should now assume that bus bar 217 is active and biased under VPP and commonly converged by SELB One or more of the remaining SELB bus bars represented by wire 218 are inactive and are driven to ground. In some embodiments, the inactive SELB bus bars 218 can be driven to an unselected location line voltage VUB (VT in this mode of operation) to actively couple the semi-selected location lines to The locating element line voltage, VUB, is described in more detail in U.S. Application Serial No. 11/461,352, filed on Jul. 31, 2006, which is hereby incorporated by reference. The manner is incorporated herein.

Since the voltage on the decoded output node 208 (ground) is lower than the voltage at the bus bar 217, the PMOS transistor 221 is turned "on", thereby driving the selected bit line 106 to VPP. This conduction path is indicated by the solid line arrow line. In contrast, the PMOS transistor 223 is turned off because it biases both its source and gate at ground.

The respective source terminals of the NMOS transistors in each of the bit line driver circuits are coupled to an unselected BL bias line UYL, and the unselected BL bias line UYL is also labeled as node 214. In this mode of operation, the UYL bias line carries the unselected positioning element line voltage VUB (eg, equal to VT). Since the voltage (ground) on the decoded output node 208 is lower than the voltage of the UYL bias line 214, both NMOS transistors 222, 224 are turned off. However, since all of the bit lines are actively driven to this unselected locating element line voltage VUB (eg, equal to VT) when not selected (as described below), the semi-selected locating element line 231 is attributed to passing through the transistor 224. The leak remains floating at approximately VT voltage. This conduction path is indicated by the dotted arrow line.

The unselected decoded output node 212 is coupled to the bit line driver circuit, and the bit line driver circuit includes a PMOS transistor 225 and an NMOS transistor 226. The respective delta terminals of the transistors 225, 226 are coupled to the bit line representing the unselected location line 108 in this condition. A second bit line driver circuit, also coupled to the decoded output node 212, represents one or more remaining bit line driver circuits associated with the decoded output node 212 and includes a PMOS transistor 227 and an NMOS device Crystal 228, whose output drives unselected positioning element line 233.

As previously described, the respective source terminals of the PMOS transistors in each of the bit line driver circuits are coupled to respective bus lines of the source select busses SELB. Since the voltage (VPP) on the decoded output node 212 is at or above the respective voltages of the bus bars 217, 218, both PMOS transistors 225, 227 are turned off. The respective source terminals of the NMOS transistors in each of the bit line driver circuits are coupled to an unselected BL bias line UYL node 214. Since the voltage on the unselected (i.e., inactive) decoded output node 212 is VPP, both NMOS transistors 226, 228 are turned "on", thereby driving the unselected positioning elements 108, 233 to VUB (eg, , VT). These two conduction paths are indicated by the open arrow line.

Exemplary bias conditions suitable for the reverse bias mode of operation will now be described. Referring now to Figure 5, exemplary word line decoder circuit 150 is shown to include exemplary bias conditions (e.g., as depicted in Figure 2) suitable for a reverse bias mode of operation. The decoded output 158 of the column decoder 152 still corresponds to the selected decoded output, and the decoded output 162 corresponds to the unselected decoded output. In this mode of operation, for example, by supplying VWL+VOD (eg, (+6 V)+(+5 V)=+11 V) coupled to power supply node 153, supply voltage VHI, and coupling The column decoder 152 is operated by supplying a voltage VLO to the ground below the power supply node 154. The voltage VOD represents the "overdrive" voltage as illustrated in the following description. In this mode of operation, column decoder 152 is a "high active" decoder, as described above, and drives (selected) decoded output 158 to the higher of the two available voltage states. (for example, +11 V). The unselected decoded output, such as decoded output node 162, is driven to the lower of the two available voltage states (eg, grounded). In other words, the polarity of the column decoder is the same for both the forward mode of operation and the reverse mode of operation. In addition, the magnitude of the operating voltage (eg, (VHI-VLO) = +11 volts) is the same in both the forward operating mode and the reverse operating mode, and the actual VHI supply voltage and the VLO supply voltage are themselves forward. The operation mode does not change in the reverse operation mode.

In this reverse mode of operation (as described above in the forward mode), the source select bus XSEL is decoded based on the address information so that one of the XSELs is converged in an active state for the mode of operation for the word line. The wire is biased and the remaining XSEL bus bars are biased in an inactive state suitable for the word line for this mode of operation. In some embodiments, more than one of the source selection bus bars can be active, but we should now assume that the XSEL bus bar 167 is active and biased at VWL (eg, +6 V) The one or more remaining XSEL bus bars, which are collectively represented by the XSEL bus bar 168, are inactive and are driven to an unselected word line voltage VUX (eg, ground).

Since the voltage on the decoded output node 158 (e.g., +11 V) is higher than the voltage of the XSEL bus bars 167, 168, both NMOS transistors 172, 174 are turned "on", thereby driving the selected word line 102 to VWL (eg, +6 V) and drives the semi-selected word line 181 to ground. These two conduction paths are indicated by the open arrow line. It should be noted that the NMOS transistor is biased to pull the selected word line above, rather than pulling down the selected word line.

The respective source terminals of the PMOS transistors in each of the word line driver circuits are coupled to an unselected WL bias line UXL node 164. In this mode of operation, the UXL bias line carries, for example, the unselected word line voltage VUX to ground (although other voltages can be used). Since the voltage on the decoded output node 158 (e.g., +11 V) is higher than the voltage of the UXL bias line (e.g., ground), both PMOS transistors 171, 173 are turned off.

Turning now to the bottom of the figure, since the voltage (e.g., ground) on the decoded output node 162 is not selected to be at or below the voltage of the XSEL bus bars 167, 168, both NMOS transistors 176, 178 are disconnect. Similarly, since the voltage on the unselected output node 162 (e.g., ground) is also the same as the voltage of the UXL bias line 164, both PMOS transistors 175, 177 are also turned off, thereby rendering the unselected word. Lines 104, 183 are in a floating condition. Leakage currents in these unselected word line drivers (i.e., drains to the source through the transistors 175, 177, and 178, and word line to substrate leakage in the transistors 176, 178) are used to The selected word line remains grounded (ie, "floating at ground"). In the exemplary circuit shown, NMOS pull-down transistors 176, 178 are larger than PMOS pull-up transistors 175, 177. This larger transistor has a larger amount of leakage to its substrate well (eg, tied to GND) than a smaller transistor. Thus, the leakage current to ground dominates the substrate leakage current to volts caused by PMOS transistors 175, 177, and this net current tends to maintain unselected word lines 104, 183 at or near ground potential.

Other voltage values can be used for the upper supply voltage VHI (as long as a sufficient overdrive voltage VOD is provided) and for the lower supply voltage VLO. For example, the lower supply voltage VLO can be a negative voltage (ie, a voltage lower than the unselected word line voltage VUX for at least the PMOS threshold voltage) such that the PMOS transistors 175, 177 will be turned on and the unselected word lines will be selected. Drive to ground. In this embodiment, a large number of unselected column select lines 162 will be driven to the VLO voltage instead of ground. This embodiment showing VLO = -1 V is disclosed in the aforementioned U.S. Patent No. 7,486,587.

In some embodiments, only one of the XSEL bus bars 167, 168 can be "selected" in the forward or reverse bias mode of operation (ie, one of the bus bars is decoded and one of the sinks is decoded) The individual word lines are selected by driving the wires to a selected word line voltage suitable for a given mode of operation and maintaining the remaining bus bars at an unselected word line voltage suitable for a given mode of operation. In some embodiments, more than one word line can be selected simultaneously by selecting one or more XSEL bus bars associated with the multi-head word line driver circuit, such as available for resetting the block, wherein the word lines are consecutive blocks Driven to a selected voltage, such as VWL (eg, +6 V).

Referring now to Figure 6, an exemplary bit line decoder circuit 200 is shown to include bias conditions suitable for a reverse bias mode of operation (e.g., as depicted in Figure 2). The decoded output 208 of row decoder 202 still corresponds to the selected decoded output, and the decoded output 212 corresponds to the unselected decoded output. In this mode of operation, in the "down to ground" mode of operation (for example) by supplying a voltage VHI equal to the GND coupled to the power supply node 203, and to the power supply node 204 being -VBL-VOD ( For example, the lower supply voltage VLO of (-6 V) - (+5 V) = -11 V) operates the row decoder 202. The voltage VOD again represents the "overdrive" voltage, as illustrated by the following description. In this mode of operation, as in the previous forward bias condition, the row decoder is still a "low active" decoder and drives the (selected) decoded output 208 to the lower of the two available voltage states. (for example, -11V). The unselected decoded output, such as decoded output node 212, is driven to the higher of the two available voltage states (eg, ground). In other words, the polarity of row decoder 202 is the same in both forward (eg, "ground up") and reverse (eg, "fall down to ground") modes of operation.

In this mode of operation, as in the forward mode, the source select bus SELB is data dependent and can be further decoded based on the address information so that it is appropriate for the mode of operation for the bit line. One or more of such bus bars are biased, and the remaining bus bars are biased in an inactive state suitable for the bit line for this mode of operation. In some embodiments, more than one of the source selection bus bars can be active, but we should now assume that the SELB bus bar 217 is active and is added at -VBL (eg, -6 V) The bias voltage, while the one or more remaining SELB bus bars represented by the SELB bus bar 218 are inactive and driven to ground.

Since the voltage on the decoded output node 208 (e.g., -11 V) is lower than the voltage at the bus bar 217, the PMOS transistor 221 is turned "on", thereby driving the selected bit line 106 to -VBL. This conduction path is indicated by the solid line arrow line. It should be noted that the PMOS transistor 221 is biased below to pull the positioning element line instead of pulling up the selected positioning element line (relative to the unselected voltage). In addition, the PMOS transistor 223 is also turned on, so the half-selected locating element line 231 is driven to GND. In this mode of operation, the UYL bias line 214 transmits an unselected locating element line voltage VUB (eg, GND). Since the voltage on the decoded output node 208 is lower than the voltage of the UYL bias line, both NMOS transistors 222, 224 are turned off.

Regarding the unselected row decoder output node, since the voltage (GND) on the decoded output node 212 is at or above the respective voltages of the SELB bus bars 217, 218, both of the PMOS transistors 225, 227 are disconnect. In addition, both NMOS transistors 226, 228 are also turned off, thus placing the unselected locating elements 108, 233 in a floating condition. The leakage currents in the unselected positioning line drivers (i.e., the drain to source leakage through the transistors 226, 227, 228, and the bit line to substrate leakage in the transistors 225, 227) are used Leave the unselected positioning element line at ground. In the exemplary circuit shown, PMOS transistors 225, 227 are larger than NMOS transistors 226, 228. Larger PMOS transistors have a larger amount of leakage to their substrate wells that are tied to GND than smaller NMOS transistors. Therefore, since the larger transistor 225 has a substrate that is grounded to ground, the substrate leakage current to ground dominates the substrate leakage current to the -VBL caused by the NMOS transistor 226, and this net current tends to unselect the positioning element. Lines 108, 233 are maintained at or near ground potential.

Other voltage values can be used for the lower supply voltage VLO (as long as a sufficient overdrive voltage VOD is provided) and for the upper supply voltage VHI. For example, the upper supply voltage VHI can be a small positive voltage (ie, a voltage higher than the unselected locating element line bias voltage VUB for at least the NMOS threshold voltage) such that the NMOS transistors 226, 228 will be turned on and Drive the unselected positioning element to ground. In this embodiment, a large number of unselected row select lines 212 will be driven to the VHI voltage instead of ground. This embodiment showing VHI = +1 V is disclosed in the aforementioned U.S. Patent No. 7,486,587.

In this embodiment, it should be noted that in the forward mode, the row decoder is active low and the bit lines are active high. In the reverse mode, the row decoder maintains its polarity (but shifts its voltage downward), but the bit line itself reverses polarity and becomes active low. Conversely, in forward mode, the column decoder is active high and the word line is active low. In the reverse mode, the column decoder maintains its polarity, but the word line itself reverses polarity and becomes active high. It should also be noted that the average voltage of the row decoder output level is in the "self-ground rising" forward mode (ie, GND to VPP) and the "down to ground" reverse mode (ie, -VBL-VOD to GND). Shift between.

When the decoder circuit is considered to be a non-multi-head decoder (in Figure 3, Figure 4, Figure 5 and Figure 6, the output of the decoder circuit can be described very simply when the decoded output is only a single array line driver circuit) . In the reverse mode, the word line decoder reverses its polarity and makes a selected word line high (~6 V) and keeps all other word lines at ground. The opposite occurs on the bit line selection side, where one bit line is selected and made -6 V, and all other bit lines are grounded. The end result is a reverse bias of 12 V across the selected memory cell and zero volts across all other memory cells. The transistors in the word line and bit line driver circuits must only withstand 6 V, or half the maximum voltage, not the entire voltage.

In certain materials, such as those described in the aforementioned U.S. Patent No. 7,486,587, the disclosure of which is incorporated herein by reference in its entirety, the in the s s s s s s s s s s s s s s s s s s s s And drive the selected positioning element line to -VRR/2. In the description herein, in a similar manner, but using the selected word line to +VWL (which corresponds to +VRR/2) and the selected positioning element line to -VBL (which corresponds to -VRR/2) Notation to describe the reverse mode of operation. This +VWL and -VBL notation removes any suggestion that the selected word line voltage must have the same magnitude as the negatively selected location line voltage.

When we consider the use of a multi-head decoder (as shown in Figures 3, 4, 5, and 6), it should be noted that the circuit described so far utilizes the decoded source selection bus in the forward direction. This allows a single one of the groups of array lines (ie, word lines, bit lines) to be selected, while the remaining half-selected array lines are driven to an unselected bias condition (or close to an unselected bias condition). In the reverse mode, the semi-selected array lines are actively driven to their respective inactive voltages by powering the column decoder and the row decoder with "overvoltage" such that the decoded output nodes are in the word line driver circuit It traverses the NMOS source voltage and traverses the PMOS source voltage in the bit line driver circuit. By doing so, the selected word line can be driven up to the +VWL voltage via the NMOS transistor and the selected bit line is driven down to the -VBL voltage via the PMOS transistor. This utilizes the same transistor in both the forward mode and the reverse mode to drive the selected word line and bit line. For example, NMOS transistor 172 (rather than PMOS transistor 171) drives selected word lines in both forward mode and reverse mode, which allows transistor 171 to be much smaller because it does not need to support stylization or Wipe off the current. Similarly, PMOS transistor 221 (rather than NMOS transistor 222) drives selected location lines in both forward mode and reverse mode, which allows transistor 222 to be much smaller because it does not need to support stylization or Wipe off the current. In addition, a second set of source selection busbars (i.e., so-called reverse source selection busbars) is not required, and the layout area that such busbars would require is avoided.

7 is a block diagram of an exemplary configuration 300 of a high voltage generator circuit and a high voltage switching circuit for a column decoder and a row decoder, and a bias circuit for word line and bit line driver circuits. This figure illustrates the use of several different high voltage generator circuits (eg, charge pump circuits), each of which produces a different voltage in different modes of operation. These voltages are coupled to various decoder circuits as described below.

The four charge pump circuits 310, 312, 314, 316 respond to the mode control signal 302, the reference voltage VREF and the pulse signal 304 on the node 306, and produce four respective outputs on the respective output nodes 311, 313, 315, 317. The output voltage. Row decoder charge pump 310 selectively produces a -4 V or -11 V output voltage on its output node 311. BL selects charge pump 312 to selectively generate an output voltage of -4 V or -6 V at its output node 313. Column/row decoder charge pump 314 selectively produces a +4 V or +11 V output voltage on its output node 315. Finally, WL selects charge pump 316 to selectively generate a +4 V, +6 V, or +10.3 V output voltage at its output node 317. Mode control signal 302 communicates to each charge pump circuit which voltage will be generated (depending on the choice of forward mode of operation or reverse mode of operation), as well as a timing sequence within a given mode of operation, as described in more detail below. An exemplary charge pump circuit is described in U.S. Patent No. 7,495,500, issued to A.K. In this article.

The high voltage switching circuits 320, 322 select the appropriate VHI and VLO voltages for the row decoder 202, and the high voltage switching circuits 324, 326 select the appropriate VHI and VLO voltages for the bit line selection control 330, each of which is The selection is made in response to the mode control 319 signal. Switching circuit 320 couples a positive voltage (e.g., +11 V), a 3.3 V voltage, or a 0 V voltage (i.e., ground) received at node 315 to its output node 321. Switching circuit 322 couples the negative or ground voltage received at node 311 to its output node 323. Switching circuit 324 couples the positive or ground voltage received at node 315 to its output node 325. Finally, switch circuit 326 couples the negative or ground voltage received at node 313 to its output node 327. (Switch circuit 326 can use the VT input for embodiments in which the unselected SELB bus bars are driven to VT instead of ground, as described with respect to FIG. 4).

Row decoder 202 receives address information 332 and decodes its row select line 210 such that the selected row select line is driven to the COLDECVLO voltage transmitted on node 323 coupled to its VLO input, and causes the unselected row select line to be driven The COLDECVHI voltage transmitted to node 321 coupled to its VHI input. The selected row select line corresponds to COLSEL 208, and the unselected row select line corresponds to COLSEL 212, and both COLSEL 208 and COLSEL 212 are shown in FIGS. 4, 6. In the forward mode of operation, the COLDECVHI voltage is sequenced between +3.3 V and +11 V in response to the dual voltage sequence generated by charge pump 314 (as described below), and the COLDECVLO voltage is grounded. In the reverse mode of operation, the COLDECVHI voltage is grounded and the COLDECVLO voltage is responsive to the dual voltage sequence generated by charge pump 310 at -4 V and -11 Sequencing between V (as described below). As mentioned in the earlier figures, the row select line 210 is a "low one of N strips valid" select lines for both the forward mode of operation and the reverse mode of operation. Therefore, reconfiguration of the internal circuitry within row decoder 202 is not required to switch between the forward mode of operation and the reverse mode of operation. The fact is that the row decoder 202 operates from the "self-ground rise" operation in the forward mode to the "down to ground" operation in the reverse mode by changing the VHI and VLO voltages of the row decoder 202.

Bit line select control circuit 330 receives the data status information on DATA_IN bus 336 and drives the bit line source select SELB bus line 216. In the forward mode of operation, the SELB bus bar 216 is a "one of the N (or more than one) active high" bus bars. Accordingly, one or more selected SELB bus bars are driven to the BLSEL VHI voltage transmitted on node 325 coupled to the VHI input, and the unselected SELB bus bars are driven to node 327 coupled to the VLO input. Transmit BLSEL VLO voltage. The selected SELB bus bar (for example) is labeled 217 in Figures 4 and 6, and the unselected SELB bus bar is represented in Figure 4, Figure 6 by the bus bar labeled 218. In forward mode of operation, the BLSEL VHI voltage is +11 V and the BLSEL VLO voltage is grounded. In the reverse mode of operation, the SELB bus 216 is "one of the N (or more than one) active low" bus. Thus, one or more selected SELB bus bars are driven to the BLSEL VLO voltage and the unselected SELB bus lines are driven to the BLSEL VHI voltage. The BLSEL VHI voltage is grounded and the BLSEL VLO voltage is responsive to the double voltage sequence generated by charge pump 312 at -4 V and -6 Sequencing between V (as described below). Bit line selection control circuit 330 responds to mode control 338 signal to achieve this polarity reversal.

The exemplary bit line selection control circuit 330 can also receive the timing pulse control signal 342 to cause one or more "active" SELB lines (ie, select the SELB bus line and have the appropriate data state to write/erase memory). The body unit) is driven to the appropriate voltage (-VBL in reverse mode, or VPP in forward mode) for the length of time required, as described in more detail below. Several DATA_IN The 336 bus bars (eg, from 1 to N) are driven to an active state as determined by the desired data state and control logic (not shown), and the control logic will be during forward or reverse stylized operation The associated bit line source select bus line (SELB) is controlled to a corresponding active state (eg, high during forward mode and low during reverse mode). In some embodiments, the SELB bus bar switching (eg, SELB bus bar switching 408 shown in FIG. 9; SELB bus bar switching 488 shown in FIG. 11) is at a fixed high voltage (eg, BLSELVHI=VPP). This occurs during the time that is applied to the BL select control 330 circuit and is controlled by changing the state of the data on the DATA_IN bus bar 336. Since the BL select control 330 does not need to be implemented on the array line spacing and is relatively small compared to the decoder and driver circuits, a non-dense circuit can be used as compared to the circuits used in the decoder and driver. Any of several known circuits, such as higher voltage transistors, longer channel length transistors, and series devices for avoiding snap back, can be used in the BL select control 330 circuit to safely switch voltages to Up to VPP.

Column decoder 152 receives address information 344 and decodes its column select line 160 such that the selected column select line is driven to the ROWDECVHI voltage transmitted on node 315 coupled to its VHI input, and causes the unselected column select line to be driven To the ROWDECVLO voltage coupled to its VLO input, the ROWDECVLO voltage is grounded. The selected column select line corresponds to ROWSEL 158, and the unselected column select line corresponds to ROWSEL 162, and both ROWSE L158 and ROWSEL 162 are shown in FIGS. 3, 5. As mentioned in the earlier figures, the column select line 160 is a "high one of the N strips valid" selection lines for the forward and reverse modes of operation. In both modes of operation, the ROWDECVHI voltage is sequenced between +4 V and +11 V in response to the double voltage sequence generated by charge pump 314 (as described below), and the ROWDECVLO voltage is grounded.

Word line select control circuit 602 receives address information 348 and decodes word line source selects XSEL bus line 166. In the forward mode of operation, the XSEL bus 166 is a "one of the N low active" busbars. Thus, the selected XSEL bus line is driven to the WLSELVLO voltage (ie, ground) and the unselected XSEL bus line is driven to the WLSELVHI voltage, which is responsive to the double voltage sequence generated by charge pump 316 at +4 Sequencing between V and +10.3 V (as described below). The selected XSEL bus bar (for example) is labeled 167 in Figures 3 and 5, and the unselected XSEL bus bar is represented in Figure 3, Figure 5 by the bus bar labeled 168. In the reverse mode of operation, the XSEL bus 166 is a "one of the N high active" bus bars. Thus, the selected XSEL bus line is driven to the BLSELVHI voltage and the unselected XSEL bus line is driven to the BLSELVLO voltage (ie, ground). Word line select control circuit 602 responds to mode control 350 signals to achieve this polarity reversal.

The address information 332, 344, 348 can each represent an actual address signal (e.g., a true and complement address signal for each address bit). Such address information 332, 344, 348 may each represent pre-decoded address information generated by an upstream decoder or pre-decoder circuit, as is well known in the art.

Figure 8 is a timing diagram of an exemplary column circuit operation in a forward bias mode of operation. During the column power on interval 362, the column circuit transitions from the inactive state to the power on state. Preferably, the column address inputs are all inactive to inhibit any of the "select" column select line 160 and the XSEL bus bar 166. The column/row decoder charge pump 314 is enabled to generate a +4 V output voltage, and the WL select charge pump 316 is also enabled to generate a +4 V output voltage. In response, all column select lines 160 are unselected and driven to ground, all XSEL bus bars 166 are unselected and driven to +4 V, and all word lines are unselected and driven to +4 V.

During the column decoder switch interval 364, the address input associated with the column decoder circuit is enabled to present the desired column address. The column select line and the XSEL bus line (when necessary) are switched in response to the column address and are finally stabilized to decode the column select line and the XSEL bus line associated with the column address. At this point, the selected column select line 158 is driven to +4 V, the unselected column select line 162 is driven to ground (or remains at ground), the selected XSEL bus bar 167 is driven to ground, and the unselected XSEL bus is Line 168 is driven to +4 V (or remains at +4 V). Thus, the selected word line 102 is driven to ground by a word line driver circuit (such as the word line driver circuit labeled 170 in Figure 3) and the unselected word line is driven to +4 V (or driven to +4) VT).

During the column high voltage turn-on interval 366, the column/row decoder charge pump 314 is enabled to increase the output voltage it produces to +11 V (VPP) and enable the WL select charge pump 316 to produce the output it produces. The voltage is increased to +10.3 V (VPP-VT). Suppress the address input to change the state. As a result, the selected column select line 158 follows the increased ROWDECVHI voltage to +11 V, and the unselected XSEL bus line 168 follows the increased WLSELVHI voltage to +10.3. The unselected column select line 162 remains at ground and the selected XSEL bus bar 167 remains grounded as well.

During interval 368, all of the decoded nodes in the column circuit remain in a steady state, with various nodes being biased at the appropriate voltage for the forward mode of operation. Both column select line 160 or XSEL bus bar 166 are not allowed to switch. The selected column select line 158 is biased at VPP (e.g., +11 V) and the unselected column select line 162 is biased at ground. The selected XSEL bus bar 167 is biased at ground and the unselected XSEL bus bar 168 is biased at VPP-VT (eg, +10.3 V). These exemplary bias conditions are consistent with their bias conditions as shown in Figures 1 and 3. During this interval 368, the power circuit is preferably turned on, and then the row circuit sequentially selects different memory cells for writing, and then power turns off the row circuitry, as described below.

During the column high voltage off interval 370, the column/row decoder charge pump 314 output voltage is reduced back to +4 V, and the WL select charge pump 316 output voltage is reduced back to +4 V. The address input change state is still suppressed. As a result, the selected column select line 158 follows the reduced ROWDECVHI voltage back down to +4 V, and the unselected XSEL bus line 168 follows the reduced WLSELVHI voltage back down to +4 V. The unselected column select line 162 remains at ground and the selected XSEL bus bar 167 remains grounded as well.

During the column decoder switching interval 372, a new column address is presented, and the column select line and the XSEL bus line (when necessary) are switched in response to the column address, and finally stabilized to decode with the new column The column select line associated with the address and the XSEL bus line. As at the end of the earlier interval 364, the selected column select line 158 is driven to +4 V, the unselected column select line 162 is driven to ground, the selected XSEL bus bar 167 is driven to ground, and will not be selected. The XSEL bus bar 168 is driven to +4 V. Thus, the newly selected word line 102 is driven to ground by the word line driver circuit and the unselected word line is driven to +4 V (or to +4-VT).

During intervals 374, 376, and 378, the column circuits operate in the same manner as corresponding intervals 366, 368, 370. Whenever a new column address is presented during this mode of operation, the column high voltage is first broken (i.e., column high voltage off interval 370), allowing column address switching (i.e., column decoder switching interval 372). ), and then return the column high voltage to ON (ie, column high voltage turn-on interval 374). When all of the column addresses to be programmed are completed, the column circuitry can be powered off (as shown in column power off interval 380) during which time column/row decoder charge pump 314 and WL select charge pump 316 Both are deactivated or disconnected so that their respective output voltages are returned to ground.

9 is a timing diagram of an exemplary row circuit operation in a forward bias mode of operation. Preferably, the entire sequence of operations is performed during stable high voltage column spacing, such as interval 368 (as shown in Figure 8) or corresponding interval 376.

During the row power on interval 402, the row circuit transitions from the inactive state to the power on state. Preferably, the row address inputs are inactive to inhibit either of the "select" row select line 210 and the SELB bus bar 216. Voltage regulator 308 is enabled to generate a +VT output voltage (e.g., 0.7 V) on node 309 and a +VT output voltage to unselected BL bias line 214 (see, for example, Figure 4). High voltage switch 320 couples its 3.3 V input to the COLDECVHI voltage, and high voltage switch 322 couples its GND input to the COLDECVLO voltage such that all row select lines 210 are unselected and driven to 3.3 V. High voltage switch 324 couples its VPOS input to the BLSELVHI voltage, and high voltage switch 326 couples its GND input to the BLSELVLO voltage. The pulse control signal 342 to the BL select control circuit 330 overrides the DATA_IN bus bar 336, and all of the SELB bus bars 216 are inactive and bias all of the SELB bus bars 216 under ground. Since all of the row select lines 210 are unselected and biased at 3.3 V, and the unselected bit line bias line 214 is biased at VT, all bit lines are unselected and driven to VT .

During the row decoder switch interval 404, the address input associated with the row decoder circuit is enabled to present the desired row address 332. Row select line 210 will switch (if necessary) in response to this row address and eventually stabilize to decode the row select line associated with the row address. Thus, the selected row select line 208 is driven to ground and the unselected row select line 212 is driven to +3.3V. All SELB bus bars 216 remain inactive at ground and all bit lines are unselected and remain at VT by the bit line driver circuit.

During the row high voltage turn-on interval 406, the high voltage switch 320 selects its VPOS input to pass the VPP voltage to the COLDECVHI voltage (recall that the column/row decoder charge pump 314 was previously enabled to produce an output voltage of +11 V ( VPP), and this voltage is maintained during interval 368). High voltage switch 324 also selects its VPOS input to pass the VPP voltage to the BLSELVHI voltage. Preferably, the row address input is suppressed from changing state. As a result, the selected row select line 208 remains at ground, but a large number of unselected row select lines 212 follow the increased COLDECVHI voltage to +11 V. All SELB bus bars 216 remain inactive under ground and all bit lines are unselected and remain at VT.

During the SELB switching interval 408, the row select line 210 does not change such that the selected row select line 208 is biased at GND and the unselected row select line 212 is biased at VPP (eg, +11 V). However, in response to mode control 338, pulse control signal 342, and DATA_IN bus bar 336, SELB bus bar 216 is now sequentially driven to active voltage VPP based on the state of the data to be programmed, and then returned to the inactive GND voltage. . As a result, the selected positioning element line 106 to be programmed is pulsed (i.e., driven for a period of time) to VPP, and then returned to the unselected positioning element line bias voltage VT. The location line that does not need to be programmed due to the state of the data remains at VT. These exemplary bias conditions are consistent with their bias conditions as shown in Figures 1 and 4.

During the row high voltage off interval 410, the high voltage switch 320 again selects its 3.3 V input to switch the COLDECVHI voltage back to +3.3 V. Suppress the address input to change the state. Mode control signal 338 and pulse control signal 342 together ensure that all SELB bus bars are inactive and remain grounded (even though the BLSELVHI voltage can still be coupled to the VPP voltage, regardless of DATA_IN bus bar 336). As a result, the selected row select line 208 remains at ground and the unselected row select line 212 follows the reduced COLDECVHI voltage back down to +3.3 volts. All bit lines remain unselected at VT voltage.

During the row decoder switch interval 412, a new row address is presented, and the row select line switches in response to the row address and is finally stabilized to decode the row select line associated with the new row address. As with the situation at the end of the earlier interval 404, the selected row select line 208 is driven to ground and the unselected row select line 212 is driven to +3.3V. All SELB bus bars 216 remain inactive at ground and all bit lines are unselected and remain at VT by the bit line driver circuit.

During intervals 414, 416, and 418, the row circuits operate in the same manner as corresponding intervals 406, 408, 410. Whenever a new "row select" address is presented during this mode of operation (i.e., corresponding to the address of the selected different row select line 210), the row high voltage is first turned off (i.e., the row high voltage) The break interval 410) allows row select address switching (i.e., row decoder switch interval 412) and then returns the row high voltage to turn "on" (i.e., row high voltage turn-on interval 414).

When all row addresses are completed, the row circuitry can be powered off (as shown in row power off interval 420) during which time high voltage switch 320 selects its GND input such that its COLDECVHI output voltage on node 321 is returned. To ground. Voltage regulator 308 can also be disabled such that the output of voltage regulator 308 returns to ground.

10 is a timing diagram of an exemplary column circuit operation in a reverse bias mode of operation. During the column power on interval 442, the column circuit transitions from the inactive state to the power on state. Preferably, the column address inputs are all inactive to inhibit any of the "select" column select line 160 and the XSEL bus bar 166. The column/row decoder charge pump 314 is enabled to generate a +4 V output voltage, and the WL select charge pump 316 is also enabled to generate a +4 V output voltage. In response, all column select lines 160 are unselected and driven to ground, all XSEL bus bars 166 are unselected and driven to ground, biasing unselected WL bias lines 164 under ground, and all words The line is unselected and driven to a voltage no higher than the PMOS threshold voltage above ground. As described earlier, the unselected word lines are due to drain-to-source leakage in the PMOS driver transistor and substrate leakage in the NMOS driver transistor and leakage through the unselected memory cells floating at ground or near Ground.

During the column decoder switching interval 444, the address input associated with the column decoder circuit is enabled to present the desired column address. The column select line and the XSEL bus line (when necessary) are switched in response to the column address and are finally stabilized to decode the column select line and the XSEL bus line associated with the column address. At this point, the selected column select line 158 is driven to +4 V, the unselected column select line 162 is driven to ground (or remains at ground), the selected XSEL bus line 167 is driven to +4 V, and the XSEL is not selected. Bus bar 168 is driven to ground (or remains grounded). Thus, the selected word line 102 is driven to +4 V by the word line driver circuit and the unselected word line is driven to ground (for half of the selected word line) or to a voltage no higher than +VTP (for unselected words) Line) (and then leak towards ground).

During the column high voltage turn-on interval 446, the column/row decoder charge pump 314 is enabled to increase the output voltage it produces to +11 V (VWL + VOD), and the WL select charge pump 316 is enabled to generate it. The output voltage is increased to +6 V (VWL). Suppress the address input to change the state. As a result, the selected column select line 158 follows the increased ROWDECVHI voltage to +11 V, and the selected XSEL bus line 167 follows the increased WLSELVHI voltage to +6 V. The unselected column select line 162 remains in ground and the unselected XSEL bus bar 168 remains in ground as well.

During interval 448, all of the decoded nodes in the column circuit remain in a steady state, with various nodes being biased at the appropriate voltage for the reverse mode of operation. Both column select line 160 or XSEL bus bar 166 are not allowed to switch. The selected column select line 158 is biased at VPP (e.g., +11 V) and the unselected column select line 162 is biased at ground. The selected XSEL bus bar 167 is biased at VWL (+6 V) and the unselected XSEL bus bar 168 is biased at ground. These exemplary bias conditions are consistent with their bias conditions as shown in Figures 2 and 5. During this interval 448, the power circuit is preferably turned on, and then the row circuit sequentially selects different memory cells for writing, and then power turns off the row circuitry, as described below.

During the column high voltage off interval 450, the column/row decoder charge pump 314 output voltage is reduced back to +4 V, and the WL select charge pump 316 output voltage is reduced back to +4 V. The address input change state is still suppressed. As a result, the selected column select line 158 follows the reduced ROWDECVHI voltage back down to +4 V, and the selected XSEL bus bar line 167 follows the reduced WLSELVHI voltage back down to +4 V. The unselected column select line 162 remains in ground and the unselected XSEL bus bar 168 remains in ground as well.

During the column decoder switch interval 452, a new column address is presented, and the column select line and the XSEL bus line (when necessary) are switched in response to the column address, and finally stabilized to decode with the new column The column select line associated with the address and the XSEL bus line. As at the end of the earlier interval 444, the selected column select line 158 is driven to +4 V, the unselected column select line 162 is driven to ground, and the selected XSEL bus line 167 is driven to +4 V, and The XSEL bus bar 168 is not selected to drive to ground. Thus, the newly selected word line 102 is driven to +4 V by the word line driver circuit, and the unselected word line is driven to ground (for half of the selected word line) or to a voltage no higher than +VTP (for unselected Word line) (and then leaks towards ground and is biased at ground).

During intervals 454, 456, and 458, the column circuits operate in the same manner as corresponding intervals 446, 448, 450. Whenever a new column address is presented during this mode of operation, the column high voltage is first turned off (ie, column high voltage off interval 450), allowing column address switching (ie, column decoder switching interval 452). And then return the column high voltage to ON (ie, column high voltage turn-on interval 454). When all of the column addresses to be programmed are completed, the column circuitry can be powered off (as shown in column power off interval 460) during which time column/row decoder charge pump 314 and WL select charge pump 316 Both are deactivated or disconnected so that their respective output voltages are returned to ground.

Figure 11 is a timing diagram of an exemplary row circuit operation in a reverse bias mode of operation. Preferably, the entire sequence of operations is performed during periods of stable high voltage column spacing, such as interval 448 (as shown in FIG. 10) or corresponding interval 456.

During the row power on interval 482, the row circuit transitions from the inactive state to the power on state. Preferably, the row address inputs are inactive to inhibit either of the "select" row select line 210 and the SELB bus bar 216. In some embodiments, the control inputs to row decoder 202 and BL select control 330 are provided by level shifting circuits that provide ground rise or fall to ground signals, respectively, for forward mode or reverse mode operation. Voltage regulator 308 is enabled to generate a GND output voltage on node 309 and a GND output voltage to unselected BL bias line 214 (see, for example, Figure 6). The row decoder charge pump 310 is enabled to produce a -4 V output voltage. High voltage switch 320 couples its GND input to the COLDECVHI voltage, and high voltage switch 322 couples its VNEG input to the COLDECVLO voltage such that all row select lines 210 are unselected and driven to GND.

The BL select charge pump 312 is also enabled to generate a -4 V output voltage. High voltage switch 324 couples its GND input to the BLSELVHI voltage, and high voltage switch 326 couples its VNEG input to the BLSELVLO voltage. The pulse control signal 342 to the BL select control circuit 330 takes precedence over the DATA_IN bus bar 336, and all of the SELB bus bars 216 are inactive and all SELB bus bars 216 are biased at GND. Since all of the row select lines 210 are unselected and biased at GND and the unselected bit line bias line 214 is biased at GND, all bit lines are unselected and driven to The voltage within the VT that is grounded (ie, not less than the NMOS threshold voltage below ground and not higher than the PMOS threshold above ground). Leakage currents within the bit line driver circuit will tend to push each unselected bit line to ground.

During the row decoder switch interval 484, the address input associated with the row decoder circuit is enabled (if this has not been done) to present the desired row address. Row select line 210 will switch (if necessary) in response to this row address and eventually stabilize to decode the row select line associated with the row address. Thus, the selected row select line 208 is driven to the COLDECVLO voltage (which is currently -4 V) and the unselected row select line 212 is driven to the COLDECVHI voltage (which is currently GND). All of the SELB bus bars 216 remain inactive at ground, and the bit lines are half-selected and remain at GND by the bit line driver circuit that responds to the selected COLSEL line 208, or are unselected and The conduction and/or leakage current in the bit line driver circuit in response to the unselected COLSEL line 212 remains at or near ground.

During the row high voltage turn-on interval 486, the row decoder charge pump 310 is enabled to increase the magnitude of the output voltage it produces to -11 V (-VBL-VOD) and enable the BL select charge pump 312 to The magnitude of the resulting output voltage is increased to -6 V (ie, -VBL). As a result, the COLDECVLO voltage is driven to -11 V and the BLSELVLO voltage is driven to -6 V. Preferably, the row address input is suppressed from changing state. As a result, the selected row select line 208 follows the COLDECVLO voltage to -11 V, but a large number of unselected row select lines 212 remain at GND. All of the SELB bus bars 216 remain inactive at GND, and the bit lines are half-selected and remain at GND by the bit line driver circuit that responds to the selected COLSEL line 208, or are unselected and The conduction and/or leakage current in the bit line driver circuit in response to the unselected COLSEL line 212 remains at or near ground.

During the SELB switching interval 488, the row select line 210 does not change such that the selected row select line 208 is biased at -VBL-VOD (eg, -11 V) and the unselected row select line 212 is added at GND bias. However, in response to mode control 338, pulse control signal 342, and DATA_IN bus bar 336, SELB bus bar 216 is now sequentially driven to the applied voltage -VBL (eg, -6 V) depending on the state of the data to be programmed, and then Return it to the inactive GND voltage. As a result, the selected positioning bit line 106 to be programmed is pulsed (i.e., driven for a period of time) to generate a pulse to -VBL, which is then returned to the unselected positioning element line bias voltage GND. The selected positioning element line, which does not need to be programmed due to the state of the data, remains at GND. These exemplary bias conditions are consistent with their bias conditions as shown in Figures 2 and 6.

During the row high voltage off interval 490, the address input change state is suppressed. Mode control signal 338 and pulse control signal 342 together ensure that all SELB bus bars are inactive and remain grounded regardless of DATA_IN bus bar 336. The row decoder charge pump 310 is enabled to reduce the magnitude of the output voltage it produces to -4 V, and the BL select charge pump 312 is enabled to reduce the magnitude of the output voltage it produces to -4 V. As a result, the COLDECVLO voltage is driven to -4 V and the BLSELVLO voltage is driven to -4 V. As a result, the selected row select line 208 follows the COLDECVLO voltage of -4 V and the unselected row select line 212 remains at GND. All bit lines are held (or near) GND by the bit line driver circuit as described above.

During the row decoder switch interval 492, a new row address is presented, and the row select line switches in response to the row address and is eventually stabilized to decode the row select line associated with the new row address. As with the situation at the end of the earlier interval 484, the selected row select line 208 is driven to -4 V and the unselected row select line 212 is driven to GND. All SELB bus bars 216 remain inactive at ground and all bit lines are unselected and held at or near GND by the bit line driver circuit.

During intervals 494, 496, and 498, the row circuits operate in the same manner as corresponding intervals 486, 488, 490. Whenever a new "row select" address is presented during this mode of operation (i.e., corresponding to the address of the selected different row select line 210), the row high voltage is first turned off (i.e., the row high voltage) Break interval 490) allows row select address switching (i.e., row decoder switch interval 492) and then returns the row high voltage to turn "on" (i.e., row high voltage turn-on interval 494). The row decoder 202 is switched only when the row decoder 202 is powered at a lower voltage (eg, 4 V operating voltage) and does not switch when the row decoder 202 is powered at a higher voltage (eg, 11 V operating voltage) The decoder 202 will improve the voltage margin of the row decoder. However, if the voltage margin allows higher voltage switching of row decoder 202, then all of the unselected COLSEL lines can be discharged and charged whenever the row address changes (eg, from -11 V to -4 V and from - 4 V to -11 V) Additional power required.

When all row addresses are completed, the row circuitry can be powered off (as shown in row power off interval 500) during which time high voltage switch 322 can select its GND input such that its COLDECVLO output voltage on node 323 Return to ground. Alternatively, the high voltage switch 322 may remain unchanged and the row decoder charge pump 310 may be deactivated to return its output to GND such that the COLDECVLO output voltage on node 323 returns to ground.

Additionally, high voltage switch 326 can select its GND input such that its BLSELVLO output voltage on node 327 returns to ground. Alternatively, high voltage switch 326 may remain unchanged and BL select charge pump 312 may be deactivated to return its output to GND such that the BLSELVLO output voltage on node 327 returns to ground.

As can be seen from the above description, the column circuit uses the same control sequence as the control sequence used in the reverse bias mode of operation in the forward bias mode of operation. The column source select bus does not switch when it is at a high voltage, but allows it to switch only when the column source selects the bus at a lower voltage. The polarity of the column decoder does not change between the forward mode and the reverse mode (eg, the high state is active), and the operating voltage does not change (eg, +11 V). However, the source select bus XSEL control logic activates one of the N low states in the forward mode (and changes to enable one of the N states in the reverse mode to be active). Therefore, the word line is active low in the forward bias mode and active high in the reverse mode.

As can be seen from the above description, the row decoder output (i.e., COLSEL line 210) switches only at a low voltage of about 4 V, so there is no risk of a snapback. The row source select bus (ie, SELB) switches at a higher voltage (eg, 11 V in forward mode, 6 V in reverse mode), and the SELB control circuit preferably uses stacked devices and is known DS voltage limiting technology to avoid snapback. The source select bus SELB control logic 330 provides an appropriate data state for one or more simultaneously selected location lines (eg, the high state in the forward mode is active, and the low state in the reverse mode is active).

It should be noted that this figure shows that the SELB line switches at high voltage to program all of the "waiting" bit lines. In some embodiments, all bit lines for a given row address can be programmed with the same pulse time, so there is no wait bit line and only one SELB pulse is needed (ie, based on the corresponding data to be written) All SELB bus bars that generate pulses simultaneously generate pulses).

The above description of the timing diagrams depicted in Figures 8 through 11 provides a useful background to better understand some of the subtle differences and useful configurations in the transition between forward mode and reverse mode.

12 is a timing diagram of an exemplary transition of a column decoder circuit to a reverse bias mode of operation. During interval 522, all column decoder outputs (i.e., column select line 160) are deselected and all column decoder outputs are driven to ground. As a result, all word lines are unselected and driven to the VUX voltage delivered on UXL bias line 164 (eg, +4 V during this interval). Next, during interval 524, UXL bias line 164 is discharged to ground. With all column decoder outputs deselected (ie, at ground) and UXL bias line 164 at ground, the PMOS transistors in each word line driver circuit discharge each word line down to PMOS Pro The voltage limit (ie, VTP), in this regard, the PMOS transistor is turned off. The leakage current through the U-shaped memory cell (see Figure 2) and in the unselected wordline driver circuit (see Figure 5) will continue to discharge the word line towards ground. Thus, all word lines are discharged to VTP and leaked to ground through the U-shaped cell and well interface (as described above). The unselected word line remains floating near ground during reverse bias operation.

The remaining intervals 442, 444, 446, 448, 450, and 460 are the same as the spacings 442, 444, 446, 448, 450, and 460 depicted in FIG. 10, and need not be described again here. The unselected output of column decoder 152 (i.e., unselected ROWSELj line 162) is at ground in all modes of operation and also inactive. The unselected WL (UXL) bias line 164 is discharged to ground while inactive, as shown in time interval 524.

13 is a timing diagram of an exemplary transition of a row decoder circuit to a reverse bias mode of operation. During interval 542, the "unselected location line bias" UBL line 214 is also reduced from its normal VUB bias level (e.g., VT) to ground. This discharges all unselected locating elements via NMOS transistors 226, 228 in each of the bit line driver circuits that are connected to unselected locating cell line bias lines 214. During interval 544, all remaining row decoder outputs (i.e., row select line 210) are deselected and driven high. As a result, during interval 546, all of the remaining bit lines are unselected and driven to the VUB voltage, at which point the VUB voltage is now GND. In this way, all bit lines are discharged to ground before the reverse bias mode of operation is initiated. Although this description is for the "previous word line" timing (ie, the bit line pulse is within the pre-established word line bias), the opposite is also known, where the given word line is pulsed in a given line. The SELB voltage and the bit line voltage of all the bit lines in a given row are established under the bias of all of the bit lines. In this case, a sequence of intervals 444, 446, 448, 450 occurs within a single row high voltage interval 488. If the same data is stylized into more than one column for a given row (eg, the background pattern is written to the memory array), the spacing 444, 446, 448, 450 can occur within a single row high voltage interval 488. Sequence of 452, 454, 456, 458.

Next, during interval 548, both VHI and VLO of row decoder 202 are ramped down to a "down to ground" configuration (ie, operating at a supply voltage equal to above GND and a negative supply voltage). . Specifically, the VHI of the row decoder 202 and the VHI of the source select bus SELB control circuit are ramped from V33 to ground. The VLO of the row decoder 202 and the VLO of the source select bus SELB control circuit are ramped from GND (for this example) to a negative low voltage of about -4 V.

During interval 550, row decoder 202 is enabled to decode selected COLSEL line 208 and drive selected COLSEL line 208 to a VLO voltage (eg, -4 V) with unselected COLSELj line 212 remaining at GND. The next three intervals 486, 488, and 490 are the same as the spacings 486, 488, and 490 described in FIG. 11, and need not be described again here.

At the end of the reverse bias mode of operation, the row decoder is disabled such that all COLSEL lines 210 are unselected during interval 552. Next, during interval 544, both the VHI and VLO of the row decoder circuit ramp up to the "self-ground rise" configuration. The VHI of the row decoder 202 and the VHI of the source select bus SELB control circuit are ramped up from ground to V33, and the VLO of the row decoder 202 and the VLO of the source select bus SELB control circuit are self-negative. Ramp to ground.

The exemplary decoder circuit described above advantageously utilizes only a single decoded source select bus. Moreover, in array line drivers for both word lines and bit lines, the same device provides a stylized current in both the forward mode of operation and the reverse mode of operation. As a result, it is only necessary to size one device within the array line driver circuit to be large enough to carry the programmed current, thereby providing a smaller array line driver circuit.

The exemplary decoder circuit described above is used to implement a memory array that includes a reversible resistor plus a diode. The memory cells can be reset using a reverse bias applied across the cells, and providing semi-selected word lines and bit lines allows individual word lines and bit lines to be placed under reset bias conditions, thus Provides the ability to reset individual memory cells without having to reset the entire block.

The forward mode is described above in the context of stylized conditions, where the voltage applied to the selected location line is VPP. The forward mode is also applicable to the read mode in which the selected bit line is driven to the read voltage VRD and the selected word line is driven again to ground. The read voltage can be a much lower voltage than the programmed voltage VPP, and the unselected word line bias voltage VUX and the unselected bit line bias voltage VUB are correspondingly reduced compared to their values for the stylized mode. . In some embodiments, this read mode can be a forward only mode and a reverse mode for staging memory.

Some memory cells can be "programmed" using the forward bias mode and can be erased using the reverse mode. Other units may be pre-conditioned using initial forward bias staging techniques (such as during manufacturing), but then "inverted" using reverse mode and "erase" using forward mode. To avoid confusion with historical usage in programmable technology and to understand the different memory technologies that are expected to be used by the decoder circuits described so far, three different modes of operation are used to describe: read, set, and reset. In the read mode, the read voltage VRD is applied across the selected memory cells. In the set mode, the set voltage VPP is applied across the selected memory cells. In the exemplary embodiment described so far, both the read voltage VRD and the set voltage VPP are positive voltages, and these modes are performed using the decoder to operate the forward mode. In the reset mode, the reset voltage VRR is applied across the selected memory cells. In the exemplary embodiment described so far, the reset voltage VRR is applied as a reverse bias voltage, and the reverse mode of the decoder operation is used to generate the reset voltage VRR. As indicated above, reverse setting and forward reset operations are also contemplated, while the pre-conditioning and read modes are still forward biased. Preconditioning can be a two-step process: a pre-biasing step to achieve an intermediate resistance state followed by a reverse setting operation.

The reset mode described above uses split voltage techniques to limit the voltage requirements of the decoder circuit and drive selected bit lines to a negative voltage (ie, using a triple well semiconductor structure).

Many types of memory cells (described below) can be programmed using the reset mode. In some of these memory cell technologies, an antifuse is initially placed in each memory cell in the forward direction. Next, the resistance of each memory cell is "tuned" in the reverse bias direction to achieve stylization. This will be the case for a single programmable unit. For rewritable cells, the cell is erased using the forward direction (which can be executed in blocks of various sizes) and then the cell is programmed using the reverse mode.

A reverse bias can be used to reset the selected memory unit. The stylized current is supplied by a diode collapse. In addition, the bias conditions associated with this stylization can be carefully controlled, including controlling the voltage ramps of selected word lines and/or bit lines. Additional insight into useful stylization techniques can be found in U.S. Patent No. 6,952,030, which is incorporated herein by reference. A number of stylized operations can be used to program various resistance states, as described in the 023-0049 and 023-0055 applications cited below, and as described in more detail in the MA-163-1 application cited below. . The use of tilted stylized pulses is described in the SAND-01114US0 and SAND-01114US1 applications cited below, and the techniques for trimming the resistance of a plurality of cells are described in the SAND-01117US0 and SAND-01117US1 applications cited below. .

The use of reset programming for passive component memory cells for stylized and trimmable resistive elements as described above is particularly useful for providing great flexibility to allow for larger array block sizes. Even in the selected array block (as all of the above description has assumed), in the reset mode, there is no bias across the unselected memory cells, and thus no wasted power dissipation. For block size, the reverse current through the cell (Irev) is not a concern. Therefore, many blocks can be selected to increase the write bandwidth. In addition, the voltage across each half of the selected memory cell is only one-half of the programmed voltage and is safe for such cells.

It should be noted that in the above description, the reset mode describes selected and semi-selected word lines and bit lines. For example, in the case of column selection, the semi-selected word line may actually be "not" selected by the given address, and the term is a human term for a multi-word line driver structure. However, in the case of a bit line, in the case of a row address, the half-selected bit line may actually be selected, but may be biased to an inactive state rather than an active state (for a bit line), It is because the specific data of the bit line does not need to "stylize" the unit, or because the bit line is "waiting" for stylization. This situation occurs when the number of bit lines that are less than the number of bit line decoder headers is simultaneously programmed. However, it is worth noting that the stylized bandwidth problem suggests configuring the memory array to program as many bit lines as possible at the same time.

Triple well processing allows the selected location line to be taken as a negative voltage and the selected word line to be taken as a positive voltage. In the reset stylization (ie, reverse mode), the reference levels of all unselected array lines (bit lines and word lines) are grounded, which allows fast decoding and selection of both word lines and bit lines. . Referring back to the description of the unselected word line and the bit line floating at ground (due to the leakage current to the larger of the two driver transistors), the resistance properties of the memory cell are actively kept unselected Additional leakage current between these unselected array lines and semi-selected array lines at the bias level. This situation further causes the unselected array lines to remain floating at or near the unselected bias potential.

Two-dimensional memory arrays are contemplated, but it is believed that the decoder configuration is particularly useful for 3D memory arrays having multiple memory planes. In some preferred embodiments, the memory array is configured, wherein each word line includes word line segments on each of more than one word line layer, as described below.

In some contemplated embodiments, the operation of the column circuit and the row circuit can be interchanged such that the column decoder is "self-grounded up" in one mode and the column decoder is "down to ground" in another mode of operation. operating. In such embodiments, the selected bit line can be driven to a non-negative voltage in two modes of operation, and the selected word line can be driven to a positive voltage in one mode and the selected word line in another mode of operation. Drive to a negative voltage.

Referring now to Figure 14, a block diagram of a useful multi-headline decoder configuration 600 is depicted. The UXL bias line and the XSELN line traverse perpendicular to the word line segment, and the RSEL column select line traverses parallel to the word line segment. Column decoder 152 generates a plurality of decoded RSEL lines, two of which are labeled 606 and 608. These RSEL lines can also be described herein as "ROWSEL" lines. Array block select decoder and bias generator circuit 602 generates four decoded source select bus lines XSELN(0), XSELN(1), XSELN(2), labeled 620, 622, 624, and 626, respectively. , XSELN (3), and also produces a UXL bias line 610. These XSELN bus bars can also be described herein as XSEL bus bars.

The four (i.e., four) word line driver circuit 638 includes four separate word line driver circuits 630 that each couple respective word lines (e.g., word lines 636) to associated XSELN bus lines (eg, In the set mode, when RSEL 606 is selected) or coupled to UXL bias line 610 (when RSEL 606 is not selected in the set mode). As described above, in the set mode of operation, one selected XSELN can transmit the selected bias level and the other XSELN lines carry the unselected bias level.

Similarly, a second quad word line driver circuit is shown, the second quad word line driver circuit including four separate word line driver circuits 640 that each couple respective word lines (eg, word line 646) to the associated XSELN The line is either coupled to the UXL bias line 610. A similar array block organization is disclosed in U.S. Patent No. 6,879,505 to RoyE. Scheuerlein (with particular reference to FIG. 9), the entire disclosure of which is hereby incorporated by reference.

Referring now to Figure 15, a block diagram showing a multi-headline line decoder 600 having a plurality of four-head driver circuits (such as the driver circuit depicted in Figure 14) across a memory array is shown. At least partially separated. As previously described, the global column decoder 152 generates a plurality of decoded column select (RSEL) lines, which are labeled as RSEL[0], RSEL[1], .. ., RSEL[n], one of which (for example, RSEL[i]) is labeled 606. Array block select decoder and bias generator circuit 602 generates four decoded source select bus lines XSELN and one UXL bias line for each vertical group 612 of multi-word line driver circuits. Each multi-word line driver circuit (e.g., 638) responds to each of the RSEL lines generated by global column decoder 152. A similar array of block structures is disclosed in the aforementioned U.S. Patent No. 6,879,505 to Roy E. Scheuerlein (particularly with respect to Figure 10).

Referring now to Figure 16, a schematic diagram showing a useful three dimensional memory array having a segmented word line configuration is shown. Each word line is formed by one or more word line segments on at least one (and advantageously one or more) word line layers of the memory array. For example, the first word line is formed by word line segments 660 disposed on one of the word line layers of the memory array and by word line segments 662 disposed on another word line layer. Word line segments 660, 662 are connected by vertical connections 658 to form a first word line. Vertical connection 658 also provides a connection path to word line driver devices 634, 632 that are typically disposed in another layer (e.g., within a semiconductor substrate). RSEL output 606 from a global column decoder (not shown) substantially traverses parallel to word line segments 660, 662, and sometimes couples word line segments 660, 662 to decoded source select bus via device 634 Line XSELN 626, source select bus line XSELN 626 substantially traverses perpendicular to the word line segment, and sometimes couples word line segments 660, 662 to UXL bias line 610 via device 632.

Word line segments 661, 663 are also shown. Word line segments 661, 663 are connected by vertical connections 659 to form a second word line and provide a connection path to word line driver circuits 642, 644. Word line driver circuits 642, 644 are coupled to Two RSEL outputs 608. Although this figure depicts an exemplary array configuration, other embodiments are contemplated for use with the decoder circuits described herein. For example, a memory array with a single memory plane can advantageously utilize the concepts described herein. In other embodiments having a fully mirrored 3D configuration of memory layers (ie, word lines are shared vertically by two memory planes and bit lines are shared by two memory planes), word line segments 661 and 663 may only An additional word line segment disposed on the odd digital line layer and driven by a separate word line driver (not shown) is controlled by the same RSEL line 608 but connected to the source select bus (XSELN) Different bus lines. Separate drive connections ensure the only choice of unit, regardless of the total mirror sharing of the word lines and bit lines. This fully mirrored memory array is more fully disclosed in the aforementioned U.S. Patent No. 6,879,505 to Roy E. Scheuerlein (with particular reference to Figure 4).

In some preferred embodiments, a six-word line driver is utilized. The six word lines associated with the six-word line driver circuit are common to two adjacent memory blocks, as described in U.S. Patent No. 7,054,219, the disclosure of which is incorporated herein. In other words, a given six-word line driver decodes and drives six word lines in each of two adjacent blocks. These neighboring blocks can be considered to be on the left and right sides of the associated word line driver, respectively. However, in the preferred embodiment, the multi-head word line drivers are disposed substantially below the array block and only the vertical connections to the word lines are between the blocks.

Certain embodiments are contemplated having a non-mirror array (e.g., a word line layer is associated with only a single bit line layer), such as described by Luca G. U.S. Patent Application Serial No. 11/095,907, filed on March 31, 2005, entitled,,,,,,,,,,,,,,,,,,,,,,,,,, The entire disclosure is hereby incorporated by reference. In particular, Figure 15 of this application shows a 4-bit line layer, a 16-head row decoder on both the top and bottom sides of the array block. This figure shows four bit lines on each of the four bit line layers (depicting four I/O layers) that are coupled by a single 16-head row decoder to the top data bus, and also in A single 16-head row decoder is coupled to the four bit lines on each of the same four bit line layers of the bottom data bus (but in the description, six of the six selected positioning lines) Groups are located in the same array block). Other semi-mirror embodiments are contemplated, such as two semi-mirror embodiments in which two bit line layers share a word line layer to form two memory planes. Other fully mirrored embodiments are also contemplated, such as two bit line layers sharing a word line layer to form two memory planes and two word line layers sharing one bit line layer to form two memory planes such that N The +1 array line layers (each being a word line layer or a bit line layer) form their complete mirror embodiment of N memory planes.

17 is a top plan view showing a word line layer and a bit line layer of a three-dimensional memory array in accordance with some embodiments of the present invention. Other wordline layers and bitline layers can be implemented by their wordline layers and bitline layers as shown, and will (in some embodiments) share the same vertical connection. Memory blocks 732, 734 are shown to include a plurality of bit lines 733, 735, respectively, and have word line segments interleaved by 2:1. The vertical connection to one of the half word line segments of the block is to the left of the block (eg, word line segment 737 and vertical connection 739), and the vertical connection to the other half of the word line segment of the block is to the right of the block (eg, Word line segment 736 and vertical connection 740). Additionally, each vertical connection servos a word line segment in each of two adjacent blocks. For example, vertical connection 740 is connected to word line segment 736 in array block 732 and to word line segment 738 in array block 734. In other words, each vertical connection, such as vertical connection 740, is shared by word line segments in each of two adjacent blocks. However, as would be expected, the respective "external" vertical connections of the first array block and the last array block may only serve the word line segments in the first array block and the last array block. For example, if block 734 is the last block of a plurality of blocks forming a memory array (or memory bay), then its external vertical connection (eg, vertical connection 744) may only serve block 734. The inner word line segment 742, and therefore is not shared by two word line segments as the remainder of the array.

By staggering the word segments as shown, the vertical connections are twice the distance between the individual word segments themselves. This situation is particularly advantageous since the word line spacing achievable for many passive element memory cell arrays is significantly smaller than the word line spacing achievable for many via structures that may be used to form vertical connections. In addition, this situation can also reduce the complexity of the word line driver circuit to be implemented in the semiconductor substrate below the memory array.

FIG. 18 is a block diagram of an exemplary memory array 700. The dual global column decoders 702, 704 generate column select lines for the array, each of which spans the array 700. In this embodiment, word line driver circuits (not shown) are spatially interspersed under the memory array and by alternating sides of individual memory array blocks (both of which are labeled 706, 708) The upper vertical connection (one of which is labeled 710) is connected to the word line. The memory array shown includes two memory "strips" 718, 720 and further includes four row decoder and bit line circuit blocks 712, 714 at the top, middle, bottom, and bottom of the array, respectively. , 715, 716. There may also be additional strips, and each strip may include one or more memory partitions. The bit lines in each block are also preferably interleaved by 2:1 to relax the spacing between the rows associated circuits. As an example, bit line 722 is associated with upper row circuit block 712 (i.e., driven and sensed by upper row circuit block 712), while bit line 724 is associated with upper middle row circuit block 714.

In the exemplary embodiment, memory array 700 is a three-dimensional memory array of passive element memory cells formed on each of four memory planes (or other number of memory planes). These memory cells can be combined with a trimmable resistor component (as described herein) and can also include an antifuse. These memory cells can have a breakdown diode or a bidirectional switching device instead of a junction diode. Each logical word line can be connected to a word line segment on each of the four word line layers (each associated with a respective memory plane).

Each of the memory arrays 700 is divided into a plurality of array blocks, such as array block 708. In some exemplary embodiments described herein, each memory partition includes 16 array blocks, although other numbers of blocks may be implemented. In an exemplary embodiment, each block may include 288 bit lines on each of the four bit line layers of each of the four memory planes, thus each block includes a total of 1,152 bits. Yuan line. The bit lines are interleaved by 2:1 such that each of the row decoder and data I/O circuits at the top and bottom of the array block are interfaced to 576 bit lines. Other numbers and configurations (including higher numbers) of such bit lines and array blocks are also contemplated.

Decoding one of the source select bus lines XSELN in the selected memory array block and driving it to the active bias condition by the column bias circuit, and the remaining bus lines (also referred to as The "bias line" is driven to an inactive condition (ie, a voltage suitable for unselected word lines). Thus, a single selected RSEL line (i.e., a column select line, which corresponds to the decoded output node 158 of Figure 3) preferably drives one of the selected memory blocks to function and selects the selected region. The other N-1 word lines in the block are driven to the unselected bias level. In other non-selected memory blocks, the individual bus lines of the source select bus are not driven to function, so that no word lines are selected by the active RSEL line. Alternatively, the source select bus and the UXL bias line in the unselected array block can be made floating (especially in forward mode). For example, the selected block can be adjacent to a second block that does not share the selected word line, and the second block can be floating. The unselected interleaved word line can extend into the block and cause the block to float to an unselected word line bias. Similarly, there may be blocks adjacent to the selected block that share only the unselected interleaved bit lines with the selected block, and the block may be floated and all array lines will float to approximately unselected location line voltages .

Each column select line spans all of the memory blocks in the entire memory strip and drives each of the pair of blocks (and more than two, each of which is located "outside" of the first and last blocks) "Four" four word line drivers. The RSEL line may also be referred to as a ROWSEL line and may also be referred to as a "global column line" and may also correspond to the column decoder output node mentioned herein. Additional details that may be useful for illustrative circuits, operations, bias conditions, floating conditions, modes of operation including reading and stylizing modes, and the like, are further described in the aforementioned U.S. Patent No. 6,879,505, and additionally to Christopher. J. Petti et al., U.S. Patent No. 7,054,219, the entire disclosure of which is incorporated herein by reference in its entirety, in In U.S. Patent Application Serial No. 11/146,952, the entire disclosure of which is hereby incorporated by Into this article.

To speed up the selection of global column lines, these RSEL lines can be driven at their two ends by two hierarchical column select decoders 702, 704 (also referred to as "global column decoders 702, 704"), each decoding. The devices are located outside the array on the left and right sides of the array strip. By using a hierarchical decoder structure, the size of the global column decoder 702 is reduced, thus improving array efficiency. In addition, in order to improve the test capability, a reverse decoding mode can be conveniently provided, as described in "Dual-Mode Decoder Circuit, Integrated Circuit Memory Array Incorporating Same" filed by Kenneth K. So et al. on December 30, 2004. , and Related Methods of Operation (U.S. Application Serial No. 11/026,493), the entire disclosure of which is incorporated herein by reference. An exemplary circuit for such hierarchical decoders can be found in Luca G. In the "Apparatus and Method for Hierarchical Decoding of Dense Memory Arrays Using Multiple Levels of Multiple-Headed Decoders" by Fasoli et al., the entire disclosure of which is incorporated herein by reference. Into this article.

In some of the text materials incorporated herein by reference, the exemplary four-head decoder circuit includes four "selected" bias lines and a single unselected bias line. The basic principle of this name is that if the input to a given decoder head is selected (i.e., driven to the active level), the decoder head couples its output to the "selected" bias line. However, this in no way implies that all four heads shown drive their respective outputs to reflect the level of the output being selected, since only one of the normally selected bias lines is actually suitable for the selected output. The bias is applied and the remaining three selected bias lines are biased under conditions suitable for the unselected output. Such "selected" bias lines for multi-head decoders are described herein as "source selection busses," but operate similarly except as noted. Some of these textual materials also describe an embodiment of a second such busbar that includes a "reverse source select bus" rather than a single unselected bias line, such as described in the aforementioned U.S. Patent No. 7,486,587.

Conversely, if the input nodes of the multi-head decoder are inactive or unselected, then all of these headers drive their respective outputs to the associated "unselected" bias line (or each of the reverse source select busses). Do not connect the bus line). For many useful embodiments, these unselected bias lines can be combined into a single bias line that is shared by all of the heads of the multi-head decoder.

The structure and technique of the associated word line decoder including the additional hierarchical level of the decoding, the biased circuit organization of the decoded bus and associated support circuits are further described in "Multi-Headed Decoder Structure" by Roy E. Scheuerlein et al. Utilizing Memory Array Line Driver with Dual Purpose Driver Device, U.S. Patent No. 6,856, 572, the entire disclosure of which is incorporated herein by reference in In U.S. Patent No. 6,859,410, the entire disclosure of which is hereby incorporated by reference in its entirety in In U.S. Patent No. 7,525,869, the disclosure of which is incorporated herein by reference.

Referring now to Figure 19, a triple well structure is depicted for providing certain source/drain nodes that can be driven above or below the potential of a bulk substrate 758 (e.g., VSS) for dual polarity The decoder output is necessary. A PMOS device (e.g., a representative PMOS device shown on the right side of the figure) is formed in a conventional N-well 756. An NMOS device (eg, a representative NMOS device shown on the left side of the figure) is enclosed in a triple well structure with an intermediate depth P-well 754 surrounded by a deep N-well 752. All N-wells 756 of the PMOS device share the most positive voltage in each mode of operation, and all P-wells 754 of the NMOS device share the most negative voltage in each mode of operation.

Referring now to Figure 20, a modified triple well structure is depicted. The PMOS device is enclosed in a deep N-well 802. The NMOS device is in a triple well configuration in which the intermediate depth P-well 804 is enclosed by the same deep N-well 802 for the PMOS device. The layout of the transfer gate is tight by combining the PMOS deep N-well with the NMOS triple well deep N-well. This may be because the source and drain voltages of the transfer gate circuit NMOS and the PMOS transistor are common voltages (that is, the NMOS and PMOS transistors of each coupling circuit in the decoder output driver circuit are connected in parallel).

As previously mentioned, in each mode of operation, all of the N-wells 806 of the PMOS device share the most positive voltage (coupled to the N+ region 812), and in each mode of operation, all of the P-wells 804 of the NMOS device share The most negative voltage (coupled to P+ region 808). Additionally, at the N-well 806 bias voltage, the entire decoder output driver circuit can use a common deep N-well 802. This merged structure avoids the spacing limitations of any deep N-well 752 to N-well 756 (as indicated in Figure 19).

As used herein, the term "setting" should be taken to mean forward biasing a single memory unit (or group of memory cells) to result in a lower resistance across each memory cell. The term "reset" should be considered to apply a reverse bias to the memory cells to cause a higher resistance across each of the cells.

In some embodiments, a memory array can be formed "above" the substrate, and various circuit blocks are described as "below" or "under" the memory array. As used herein, "in" memory array blocks (which are actual physical structures having general planar characteristics) are "above" or "below" or "below" relative to the substrate or memory plane. The direction of the surface.

As stated above, preferably, the memory array includes a segmented word line architecture (as depicted in Figure 14), and preferably includes a 3D array. In some embodiments, a word line on a given word line layer is associated with a bit line on a single bit line layer, and in some embodiments, in a so-called "semi-mirror" configuration, The word lines on the word line layer are shared between two bit line layers (i.e., a single word line layer defining two memory planes and two bit line layers). In some embodiments, in a so-called "completely mirrored" configuration, the word lines on a given word line layer are shared between two bit line layers, and the bit lines on the given element line layer are Shared between two word line layers. Such memory array structures are further described in the aforementioned U.S. Patent No. 6,879,505.

The description of the various decoder circuits to date has focused primarily on the description of a single array block. Recall that each decoder is described in the context of a source selection bus. The word line decoder hierarchy can be considered relatively straightforward. The source select bus and the unselected bias line are decoded based on the address information and driven according to which array block is active. Similar column decoder circuits have been mentioned elsewhere herein. If the unselected array block does not share the selected word line with the selected array block, then the respective source select bus and/or unselected bias lines of the word lines associated with the unselected array block may be floated. If the unselected array blocks share the selected word line with the selected array block, then the unselected word line bias is preferably supplied.

A useful row decoder configuration can be found in the aforementioned U.S. Patent Application Serial No. 11/095,907, the disclosure of which is incorporated herein by reference. A hierarchical bus configuration can be used to provide efficient delivery of read/write data and effective biasing of bit lines within selected and unselected array blocks. A useful hierarchical bus configuration is described in US Application No. 11/461,359 to Roy E. Scheuerlein, Luca G. Fasoli, and Christopher J. Petti entitled "Memory Array Incorporating Two Data Busses for Memory Array Block Selection" For US Open Case No. 2008-0025085) ("023-0052" application), and described in Roy E. Scheuerlein and Luca G. In the U.S. Application Serial No. 11/461,362 (issued to U.S. Patent Publication No. 2008-0025093), the entire disclosure of which is incorporated herein by reference. The applications are incorporated herein by reference.

In forward operation (read and set), the exemplary hierarchical bus configuration provides a suitable bias on the XSELN bus for the selected array block and is used for XSELN bus floating of unselected array blocks. This helps to reduce unwanted power dissipation in the array blocks adjacent to the selected array block. Unselected word lines in selected array blocks are biased at a relatively high voltage VUX (eg, VPP-VT), and in the case of a shared word line architecture, such unselected word lines also extend to adjacent non- The array block is selected (ie, the selected array block shares one half of the word line within the non-selected array block). Preferably, the unselected locating elements in the adjacent array blocks that also share the selected word line are biased at the unselected locating cell voltage VUB (eg, VT). This is due to the leakage of current through the unselected memory cells to consume power. The other half of the word lines adjacent to the non-selected array block are floating such that they leak up to the VUB voltage and minimize the leakage power of half of the unselected cells. In other neighboring blocks that share unselected word lines but do not share the selected word line, the bit line is floated and floats to the unselected word line voltage, thereby avoiding power dissipation of unselected cells.

With respect to the various embodiments described above, many types of memory cells can be programmed using reverse bias (e.g., the reset mode described above). These units include passive component units having metal oxides (e.g., transition metal oxides) and diodes. Other suitable units include those having a resistive material in a matrix of diodes. Examples include programmable metallization connections, phase change resistors such as GST materials, organic material variable resistors, composite metal oxides, carbon polymer films, doped chalcogenide glasses, and mobile atoms to change resistance Schottky barrier diode. The selected resistive material can provide a one-time programmable (OTP) memory cell or multiple writes to the memory cell. Additionally, a polycrystalline germanium diode having conduction modified by reverse bias stress can be used.

A useful memory unit for the reverse reset operation is described in U.S. Patent No. 6,952,030 to S. Brad Herner et al., entitled "High-Density Three-Dimensional Memory Cell"; and also described by Tanmay Kumar et al. U.S. Application Serial No. 11/237,167, filed on Sep. 28, 2005, entitled,,,,,,,,,,,,,,,,,,,,,,, A suitable metal oxide memory cell is shown in U.S. Application Serial No. 11/, filed on Mar. 31, 2006, entitled "Multilevel Nonvolatile Memory Cell Comprising a Resistivity-Switching Oxide or Nitride and an Antifuse, by S. Brad Herner. No. 394,903. Suitable memory cells using phase change materials that provide multiple resistance states are shown in Roy E. U.S. Patent Application Publication No. 2005-0158950 to Scheuerlein et al., entitled "Non-Volatile Memory Cell Comprising a Dielectric Layer and a Phase Change Material in Series". The entire contents of each of the above-referenced disclosures are hereby incorporated by reference. Exemplary units having a transition metal oxide (eg, including other transition memory oxides having cobalt) and a polycrystalline germanium material of the steering element itself comprising a switchable resistive material are described in the MA referenced below -163-1 application.

In addition, U.S. Patent Application Serial No. 11/125,939, filed on Sep. 9, 2005, which is incorporated herein by reference to the entire entire entire entire entire entire entire entire disclosure , nickel oxide) A useful rewritable memory cell of a series diode, wherein the resistance of the memory cell is repeatedly switched from a low resistance state to a high resistance state and from a high resistance state to a low resistance state. US Application No. 11/395,995, entitled "Nonvolatile Memory Cell Comprising a Diode and a Resistance Switching Material", filed on March 31, 2006 by S. Brad Herner et al. Reverse bias to reset the OTP multi-level memory cell. The entire contents of each of the above-referenced disclosures are hereby incorporated by reference.

In many of the embodiments described herein, the precise bias conditions imposed on each respective bus bar in the data path can be independently controlled. For each bit of the data path, the specific voltage and current settings for each of the set and reset drivers can be adjusted. As a result, a particular memory unit (i.e., a "multi-level" memory unit) having more than two states for use by many of the structures described herein is contemplated. Exemplary multi-level memory cells are described in the aforementioned U.S. Patent Application Serial No. 11/237,167, the disclosure of which is incorporated herein by reference.

Exemplary passive component memory cells and associated non-volatile memory structures that can be used in the practice of the present invention are described in the following documents, the entire contents of each of which are incorporated herein by reference: Mark G. Johnson et al. U.S. Patent No. 6,034,882, entitled "Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication"; U.S. Patent No. 6,420,215 to Johan Knall et al., entitled "Three Dimensional Memory Array and Method of Fabrication"; US Patent No. 6, "Market Johnson et al., "Vertically-Stacked, Field Programmable, Nonvolatile Memory and Method of Fabrication" by Mark Johnson et al. No. 6,525,953; U.S. Patent No. 6,490,218 to Michael Vyvoda et al., entitled "Digital Memory Method and System for Storing Multiple-Bit Digital Data"; U.S. Patent No. 6, "Electrically Isolated Pillars in Active Devices" by Michael Vyvoda et al. 6,952,043; and S. U.S. Patent Application Publication No. US 2005-0052915 to Brad Herner et al., entitled "Nonvolatile Memory Cell Without a Dielectric Antifuse Having High- and Low-Impedance States".

Memory cell structures, circuits, systems, and methods that can be used to practice the present invention are described in the following applications filed on July 31, 2006, each of which is incorporated by reference. Incorporating this article: U.S. Application Serial No. 11/496,985, entitled "Multi-Use Memory Cell and Memory Array" by Roy Scheuerlein and Tanmay Kumar, is currently filed in US Publication No. 2007-0069276 ("10519-141") US Patent Application No. 11/496,984 to Roy Scheuerlein and Tanmay Kumar entitled "Method for Using a Multi-Use Memory Cell and Memory Array", now US Publication No. 2007/0070690 ("10519-150") "Application"; Roy Scheuerlein, "Mixed-Use Memory Array", US Application No. 11/496,874, now US Publication No. 2008-0023790 ("10519-142" application); Roy Scheuerlein Titled "Method for Using a U.S. Application No. 11/496,983 to the Mixed-Use Memory Array, which is now filed in the US Publication No. 2008-0025118 ("10519-151"); Roy Scheuerlein and Christopher Petti entitled "Mixed-Use Memory Array" US Application No. 11/496,870, with Different Data States, is currently published in US Publication No. 2008-0025069 ("10519-149"); Roy Scheuerlein and Christopher Petti entitled "Method for Using a Mixed- US Patent Application No. 11/497,021 to Use Memory Array With Different Data States, now US Publication No. 2008-0025062 ("10519-152" application); Roy Scheuerlein entitled "Controlled Pulse Operations in Non- Volatile U.S. Patent Application Serial No. 11/461,393, issued to U.S. Patent Publication No. 2008-0025076 ("SAND-01114US0" application); and "Systems for Controlled Pulse Operations in Non-Volatile Memory" by Roy Scheuerlein US Application No. 11/461,399, now US Publication No. 2008-0025077 ("SAND-01114US1" application); Roy Scheuerlein and Christopher J. Petti entitled "High Bandwidth One-Time Field-Programmable Memory" U.S. Patent Application Serial No. 11/461,410, which is hereby incorporated by reference in its entirety in its entirety in the entire disclosure of the entire disclosures of Petti's U.S. Application Serial No. 11/461,419, entitled "Systems for High Bandwidth One-Time Field-Programmable Memory," is US Publication No. 2008-0025067 ("SAND-01115US1" application); Roy Scheuerlein and U.S. Application No. 11/461,424 to Tanmay Kumar, entitled "Reverse Bias Trim Operations in Non-Volatile Memory", now US Publication No. 2008-0025068 ("SAND-01117US0" application); Roy Scheuerlein and Tanmay U.S. Patent Application Serial No. 11/461,431 to Kumar, entitled "Systems for Reverse Bias Trim Operations in Non-Volatile Memory," US Publication No. 2008-0025078 ("SAND-01117US1" Application); Tanmay Kumar, S. Brad Herner, Roy E. Scheuerlein and Christopher J. U.S. Patent Application Serial No. 11/496,986, entitled "Method for Using a Memory Cell Comprising Switchable Semiconductor Memory Element with Trimmable Resistance," by Petti, US Patent Publication No. 2007-0072360 ("MA-163-1" Application U.S. Application No. 11/461,339 to "Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders" by Luca G. Fasoli, Christopher J. Petti, and Roy E. Scheuerlein, now US Publication No. 2008-0025066 ("023-0048" application); Luca G. Fasoli, Christopher J. Petti and Roy E. US Application No. 11/461,364 to Scheuerlein, entitled "Method for Using a Passive Element Memory Array Incorporating Reversible Polarity Word Line and Bit Line Decoders", is currently filed in US Publication No. 2008-0025132 ("023-0054") US Patent Application No. 11/461,343 to Roy E. Scheuerlein, Tyler Thorp, and Luca G. Fasoli entitled "Apparatus for Reading a Multi-Level Passive Element Memory Cell Array", now US Publication No. 2008- 0025088 ("023-0049" application); Roy E. Scheuerlein, Tyler Thorp and Luca G. U.S. Application Serial No. 11/461,367, entitled "Method for Reading a Multi-Level Passive Element Memory Cell Array" by Fasoli, now US Application No. 2008-0025089 ("023-0055" application); Roy E Scheuerlein and Luca G. Fasoli, U.S. Application Serial No. 11/461,352, entitled "Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array", now US Publication No. 2008-0025131 ("023 -0051"Application); US Application No. 11/461,369 to Roy E. Scheuerlein and Luca G. Fasoli entitled "Method for Using Dual Data-Dependent Busses for Coupling Read/Write Circuits to a Memory Array" For the US Open Case No. 2008-0025133 ("023-0056" application); Roy E. Scheuerlein, Luca G. Fasoli, and Christopher J. Petti, U.S. Application Serial No. 11/461,359, entitled "Memory Array Incorporating Two Data Busses for Memory Array Block Selection", now US Publication No. 2008-0025085 ("023 -0052, "Application"; Roy E. Scheuerlein, Luca G. Fasoli, and Christopher J. Petti, US Patent Application No. 11/461,372, entitled "Method for Using Two Data Busses for Memory Array Block Selection", now US Publication No. 2008-0025134 ("023-0057" application); Roy E. Scheuerlein and Luca G. U.S. Patent Application Serial No. 11/461,362, entitled,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, US Patent Application No. 11/461,376 to Scheuerlein and Luca G. Fasoli entitled "Method for Using a Hierarchical Bit Line Bias Bus for Block Selectable Memory Array", now US Publication No. 2008-0025094 ("023-0058" "Application".

As will be appreciated, the specific illustrative embodiments presented herein have been described in the context of specific numerical examples such as the specific voltages, the number of decoded outputs, the number of decoder heads, and the bus bars. The number, the number of data busses, the number of array blocks in the memory partition, and the number of memory banks. Other variations consistent with other design goals can be implemented using the teachings of the present invention. For the sake of clarity, all of the conventional features of the implementations described herein are not shown and described.

As used herein, "coupling a selected positioning element line to a first bus bar" means coupling each of the selected positioning element lines to a corresponding bus bar line of the first bus bar. As used herein, word lines (eg, including word line segments) and bit lines generally represent orthogonal array lines, and generally follow the common practice of driving word lines and sensing bit lines during at least read operations in the art. assumed. Moreover, as used herein, a "global line" (eg, a global selection line) is an array line that spans more than one memory block, but it should not be suggested that the global line must span the entire memory array or substance. A specific inference across the entire integrated circuit.

As used herein, a "data bus" or a data stream "segment" sometimes transmits data-dependent information at least, but does not need to always transmit data-dependent information. For example, for some modes of operation, this data bus can transmit the same bias information on each bus line of this data bus. The "data circuit" may include one or more of a read/write circuit, a setting circuit, a reset circuit, a read circuit, or a stylized circuit, or any combination, as appropriate.

As used herein, a "selected" line (such as a selected location line within an array block) corresponds to such bit lines that are simultaneously selected by the multi-head decoder circuit and each coupled to a corresponding bus bar. These bit lines may or may not be selected by the data or I/O circuitry to actually perform a given read, program, set, reset or erase operation. For example, if a 16-row row decoder simultaneously "selects" 16 bit lines and couples 16 bit lines to a given bus (eg, SELB bus), then 16 bit lines should be expected None of the bit lines of the group, one bit line of the group of 16 bit lines, one or more bit lines of the group of 16 bit lines or 16 pieces All of the bit lines in this group of bit lines can actually receive a selected (ie, active) bias condition suitable for a given mode of operation, while the remaining bit lines can be unselected (ie, non-active) Bias condition. This bus can be described as a "data dependent" bus. In other embodiments, such as when programming two simultaneously selected memory cells to different data states, there may be more than one "selected" bias condition transmitted on a given bus.

As used herein, a passive element memory array includes a plurality of 2-terminal memory cells each connected to an associated X-ray (eg, a word line) and an associated Y-line (eg, a bit line). between. The memory array can be a two-dimensional (planar) array or can be a three-dimensional array having more than one memory cell plane. Each of the memory cells has a non-linear conductivity in which the current in the reverse direction (i.e., from the cathode to the anode) is lower than the current in the forward direction. The passive component memory array can be a one-time programmable (ie, write-once) memory array or a read/write (ie, multiple write) memory array. These passive component memory cells are generally considered to be current steering components that direct current in one direction and another component (eg, fuses, anti-fuse, capacitors, resistive components, etc.) that can change their state. The stylized state of the memory component can be read by sensing the current flow or voltage drop as the memory component is selected.

The directionality of the various array lines in the various figures is only two groups that facilitate easy description of the intersecting lines in the array. As used herein, an integrated circuit memory array is a single-volume circuit structure, rather than one or more integrated circuit devices packaged together or in close proximity.

As used herein, an "array block" or "memory array block" is an contiguous array of adjacent memory cells that are typically not interrupted by a decoder, read/write circuit, bus, or other structure. The "polarity" of the decoder circuit refers to the selected decoder output being active high or active low regardless of any operating voltage shift (eg, having one of the selected outputs at +6 and one of the unselected outputs at ground) Has the same polarity as another decoder with a selected output at ground and an unselected output at -6 V. As used herein, a circuit that "powers to a first voltage" means applying a first voltage difference across the circuit regardless of the ground reference potential. The "operating voltage" of the circuit is the voltage difference between the upper supply voltage VHI and the lower supply voltage VLO (for example, "operating voltage" = VHI - VLO) regardless of the polarity of one or more of these voltages. For example, a circuit with VHI=+4 V and VLO=GND has an operating voltage of 4 volts, and a circuit with VHI=GND and VLO=-4 V also has an operating voltage of 4 volts.

As used in some of the descriptions herein, in a given mode of operation, the "selected" bus or bit line voltage or other is described as described with respect to the selected address for "writing" and the appropriate data state. Bias condition. For example, depending on the state of the data to be programmed, the selected source select bus coupled to the selected bit line can carry the write voltage to change the state of the selected memory cell associated with the selected bit line, Or conversely, the non-active voltage can be carried such that the state of the selected memory cell associated with the selected positioning element line does not change. In other words, the bit line can be selected (ie, "addressed") for writing, but the data state can be suppressed to the actual programmed voltage of the "selected" bus bar.

As used herein, each of the "first mode of operation" and the "second mode of operation" may refer to any of the described modes of operation, including standby, read, write, erase. Block erase, stylize, set, reset, and block reset. "Write mode of operation" may refer to any mode of operation used to change the state of one or more memory cells, whether or not described as setting, resetting, block resetting, erasing, block erasing or programming. Chemical.

The block diagrams herein may be described using the terminology of a single node that connects the blocks. However, it should be understood that when the context requires, this "node" may actually represent one of the nodes for transmitting the differential signal, or may be used to carry a number of related signals or to carry a digital word or other A plurality of individual wires (eg, bus bars) of a plurality of signals of the bit signal.

Although circuits and physical structures are generally assumed, it should be fully recognized that in modern semiconductor design and fabrication, physical structures and circuits may be in computer readable descriptive forms suitable for subsequent design, testing, or manufacturing stages, and in Manufactured in a semiconductor integrated circuit. Thus, the scope of the patent for a conventional circuit or structure can read (in accordance with its specific language) a computer readable code and its representation, whether embodied in the media or combined with a suitable reader facility to allow the corresponding circuitry and/or Manufacturing, testing, or design improvements to the structure. It is contemplated that the present invention includes circuits, packaged modules including such circuits, systems utilizing such circuits and/or modules and/or other memory devices, associated methods of operation, related methods of fabricating such circuits, and such circuits And computer readable medium code of the method, as described herein and as defined in the appended claims. As used herein, a computer readable storage medium includes at least a magnetic disk, magnetic tape, or other magnetic, optical semiconductor (eg, a flash memory card, ROM), or an electronic storage medium. The coding of the circuit may include circuit schematic information, physical layout information, behavioral simulation information, and/or may include any other code (from which the circuit may be represented or connected).

The foregoing embodiments have described only some of the many possible implementations of the invention. The reason for this reason is intended to be illustrative and not limiting. Variations and modifications of the embodiments disclosed herein can be made based on the description set forth herein. The scope of the invention is intended to be limited only by the following claims.

<p>100. . . Passive component memory array</p><p>101. . . Passive component memory unit / selected memory unit / S unit</p><p>102. . . Selected word line</p><p>103. . . Passive component memory unit / F unit</p><p>104. . . Unselected word line</p><p>105. . . Passive component memory unit / H unit</p><p>106. . . Selecting location line</p><p>107. . . Passive component memory unit / U unit</p><p>108. . . Unselected positioning line</p><p>150. . . Word line decoder circuit</p><p>152. . . Column decoder circuit / global column decoder</p><p>153. . . Power supply node</p><p>154. . . Power supply node</p><p>158. . . Decoded Output/Column Select Node/Decoded Output Node/Selected Column Select Line/ROWSEL</p><p>160. . . Column selection line</p><p>162. . . Decoded Output / Decoded Output Node / Unselected Column Select Line / ROWSEL</p><p>164. . . UXL bias line / unselected WL bias line UXL node / unselected WL (UXL) bias line</p><p>166. . . Word line source selects XSEL bus line</p><p>167. . . Selected XSEL bus line</p><p>168. . . XSEL bus line not selected</p><p>170. . . Word line driver circuit</p><p>171. . . PMOS transistor</p><p>172. . . NMOS transistor</p><p>173. . . PMOS transistor</p><p>174. . . NMOS transistor</p><p>175. . . PMOS pull-up transistor</p><p>176. . . NMOS pull-down transistor</p><p>177. . . PMOS pull-up transistor</p><p>178. . . NMOS pull-down transistor</p><p>181. . . Semi-selected word line</p><p>183. . . Unselected word line</p><p>200. . . Bit line decoder circuit / bias condition</p><p>202. . . Row decoder circuit/row decoder</p><p>203. . . Power supply node</p><p>204. . . Power supply node</p><p>205. . . Output</p><p>208. . . Decoded Output / Decoded Output Node / Row Select Node / COLSEL / Selected Row Select Line</p><p>209. . . Output</p><p>210. . . Row select line / COLSEL line</p><p>212. . . Decoded Output/Row Select Node/Unselected Decoded Output Node/Unselected Row Select Line/Unselected COLSEL Line</p><p>214. . . BL bias line UYL node/unselected BL bias line not selected</p><p>216. . . Bit line source selects SELB bus line</p><p>217. . . SELB bus line</p><p>218. . . Non-acting SELB busbar</p><p>220. . . Bit line driver circuit</p><p>221. . . PMOS transistor</p><p>222. . . NMOS transistor</p><p>223. . . PMOS transistor</p><p>224. . . NMOS transistor</p><p>225. . . PMOS transistor</p><p>226. . . NMOS transistor</p><p>227. . . PMOS transistor</p><p>228. . . NMOS transistor</p><p>231. . . Semi-selected positioning element</p><p>233. . . Unselected positioning line</p><p>300. . . Configuration of high voltage generator circuit and high voltage switching circuit for column and row decoder</p><p>302. . . Mode control signal</p><p>304. . . Clock signal</p><p>306. . . node</p><p>308. . . Voltage Regulator</p><p>309. . . node</p><p>310. . . Charge pump circuit / row decoder charge pump</p><p>311. . . Output node</p><p>312. . . Charge pump circuit / bit line select charge pump</p><p>313. . . Output node</p><p>314. . . Charge pump circuit / column / row decoder charge pump</p><p>315. . . Output node</p><p>316. . . Charge pump circuit / WL select charge pump</p><p>317. . . Output node</p><p>319. . . Mode control</p><p>320. . . High voltage switching circuit</p><p>321. . . Output node</p><p>322. . . High voltage switching circuit</p><p>323. . . Output node</p><p>324. . . High voltage switching circuit</p><p>325. . . Output node</p><p>326. . . High voltage switching circuit</p><p>327. . . Output node</p><p>330. . . Bit line selection control circuit / source selection bus SELB control logic</p><p>332. . . Address information/row address</p><p>336. . . DATA_IN bus line</p><p>338. . . Mode control signal</p><p>342. . . Timing pulse control signal</p><p>344. . . Address information</p><p>348. . . Address information</p><p>350. . . Mode control</p><p>362. . . Column power on interval</p><p>364. . . Column decoder switching interval</p><p>366. . . Column high voltage turn-on interval</p><p>368. . . interval</p><p>370. . . Column high voltage disconnect interval</p><p>372. . . Column decoder switching interval</p><p>374. . . Column high voltage turn-on interval</p><p>376. . . interval</p><p>378. . . interval</p><p>380. . . Column power off interval</p><p>402. . . Line power on interval</p><p>404. . . Row decoder switching interval</p><p>406. . . Line high voltage turn-on interval</p><p>408. . . SELB bus switch / SELB switch interval</p><p>410. . . Line high voltage disconnect interval</p><p>412. . . Row decoder switching interval</p><p>414. . . Line high voltage turn-on interval</p><p>416. . . interval</p><p>418. . . interval</p><p>420. . . Line power off interval</p><p>442. . . Column power on interval</p><p>444. . . Column decoder switching interval</p><p>446. . . Column high voltage turn-on interval</p><p>448. . . interval</p><p>450. . . Column high voltage disconnect interval</p><p>452. . . Column decoder switching interval</p><p>454. . . Column high voltage turn-on interval</p><p>456. . . interval</p><p>458. . . interval</p><p>460. . . Column power off interval</p><p>482. . . Line power on interval</p><p>484. . . Row decoder switching interval</p><p>486. . . Line high voltage turn-on interval</p><p>488. . . SELB bus switch / SELB switching interval / single line high voltage interval</p><p>490. . . Line high voltage disconnect interval</p><p>492. . . Row decoder switching interval</p><p>494. . . Line high voltage turn-on interval</p><p>496. . . interval</p><p>498. . . interval</p><p>500. . . Line power off interval</p><p>522. . . interval</p><p>524. . . time interval</p><p>542. . . interval</p><p>544. . . interval</p><p>546. . . interval</p><p>548. . . interval</p><p>550. . . interval</p><p>552. . . interval</p><p>600. . . Multi-head word line decoder configuration</p><p>602. . . Word line selection control circuit / array block selection decoder and bias generator circuit</p><p>606. . . Decoded RSEL line / RSEL[i] / RSEL output</p><p>608. . . Decoded RSEL line / second RSEL output</p><p>610. . . UXL bias line</p><p>612. . . Vertical group of multi-word line driver circuits</p><p>620. . . Decoded source select bus line XSELN(0)</p><p>622. . . Decoded source selection bus line XSELN(1)</p><p>624. . . Decoded source select bus line XSELN(2)</p><p>626. . . Decoded source selection bus line XSELN(3)</p><p>630. . . Word line driver circuit</p><p>632. . . Word line driver device</p><p>634. . . Word line driver device</p><p>636. . . Word line</p><p>638. . . Four (ie, four head) word line driver circuit</p><p>640. . . Word line driver circuit</p><p>642. . . Word line driver circuit</p><p>644. . . Word line driver circuit</p><p>646. . . Word line</p><p>658. . . Vertical connection</p><p>659. . . Vertical connection</p><p>660. . . Word line segment</p><p>661. . . Word line segment</p><p>662. . . Word line segment</p><p>663. . . Word line segment</p><p>700. . . Memory array</p><p>702. . . Dual global column decoder/hierarchical column selection decoder</p><p>704. . . Dual global column decoder/hierarchical column selection decoder</p><p>706. . . Memory array block</p><p>708. . . Memory array block</p><p>710. . . Vertical connection</p><p>712. . . Row decoder and bit line circuit block/upper row circuit block</p><p>714. . . Row decoder and bit line circuit block/middle upper row circuit block</p><p>715. . . Row decoder and bit line circuit block</p><p>716. . . Row decoder and bit line circuit block</p><p>718. . . Memory strip</p><p>720. . . Memory strip</p><p>722. . . Bit line</p><p>724. . . Bit line</p><p>732. . . Memory block/array block</p><p>733. . . Bit line</p><p>734. . . Memory block/array block</p><p>735. . . Bit line</p><p>736. . . Word line segment</p><p>737. . . Word line segment</p><p>738. . . Word line segment</p><p>739. . . Vertical connection</p><p>740. . . Vertical connection</p><p>742. . . Word line segment</p><p>744. . . Vertical connection</p><p>752. . . Deep N well</p><p>754. . . Intermediate depth P-well</p><p>756. . . N-type well</p><p>758. . . Bulk substrate</p><p>802. . . Deep N well</p><p>804. . . Intermediate depth P-well</p><p>806. . . N-type well</p><p>808. . . P+ area</p><p>812. . . N+ area</p>

1 is a schematic diagram of a memory array illustrating selected and unselected word lines and bit lines, and exemplary bias conditions in a forward bias mode of operation.

2 is a schematic diagram of the memory array depicted in FIG. 1, but illustrating exemplary bias conditions in a reverse bias mode of operation.

3 is a schematic diagram of an exemplary column decoder and word line driver circuit including exemplary conditions in a forward biased mode of operation.

4 is a schematic diagram of an exemplary row decoder and bit line driver circuit including exemplary conditions in a forward bias mode of operation.

5 is a schematic diagram of an exemplary column decoder and word line driver circuit including exemplary conditions in a reverse bias mode of operation.

6 is a schematic diagram of an exemplary row decoder and bit line driver circuit including exemplary conditions in a reverse bias mode of operation.

7 is a block diagram of an exemplary high voltage generator circuit and switching circuit for a column decoder and a row decoder, and a bias circuit for a word line and bit line driver circuit.

8 is a timing diagram of an exemplary column decoder operation in a forward bias mode of operation.

9 is a timing diagram of an exemplary row decoder operation in a forward bias mode of operation.

10 is a timing diagram of an exemplary column decoder operation in a reverse bias mode of operation.

11 is a timing diagram of an exemplary row decoder operation in a reverse bias mode of operation.

12 is a timing diagram of an exemplary transition of a column decoder to reverse bias mode of operation.

13 is a timing diagram of an exemplary transition from a row decoder to a reverse bias mode of operation.

14 is a block diagram/schematic diagram depicting a global column decoder configuration with a multi-head word line driver, each coupled to an unselected bias line and coupled to a respective line of a source select bus.

15 is a block diagram depicting a global column decoder configuration in which a column select line drives a multi-head wordline driver for each of a plurality of array blocks.

16 is a three-dimensional view depicting a portion of a three-dimensional memory array consistent with certain embodiments of the memory array illustrated in FIGS. 14 and 15 and illustrated by two adjacent array blocks A word line driver circuit coupled to each of the two or more word line layers for vertical connection to each of the word line segments.

17 is a top plan view showing a word line layer and a bit line layer of a three-dimensional memory array showing a word line segment interleaved by 2:1, wherein a vertical connection to one of the half word line segments of the block is in the block On the left side, and the vertical connection to the other half of the word line segment of the block is to the right of the block. In addition, word line segments from two adjacent blocks share each vertical connection.

18 is a block diagram depicting an exemplary integrated circuit including a three-dimensional memory array, the integrated circuit including a respective global column decoder on each side of each array and the top and bottom of each array A separate line decoder on the top.

Figure 19 is a cross-sectional view of a triple well structure with a deep n-well semiconductor structure.

Figure 20 is a cross-sectional view of a triple well structure incorporating a deep n-well semiconductor structure.